Vertical field effect transistor, method for manufacturing the same, and component having a vertical field effect transistor

Abstract

A vertical field effect transistor (10) is provided. The vertical field effect transistor has a first semiconductor layer (13) on or above a drift region (12), the first semiconductor layer having a p-conductivity type, a trench structure (50) penetrating the first semiconductor layer (13) vertically, wherein the trench structure (50) has at least one sidewall on which a field effect transistor (FET) channel region is configured, wherein the FET channel region has a III-V heterostructure (15 / 16) for configuring a two-dimensional electron gas on an interface of the III-V heterostructure (15 / 16), a source / drain electrode (21) which is in an electrically conductive connection with the III-V heterostructure (15 / 16), a contact structure (24, 25) at least partially on or above the drift region (12), the contact structure at least configuring a Schottky contact or a hetero contact with the drift region (12), wherein the contact structure (24, 25) is in an electrically conductive connection with the source / drain electrode (21), wherein a region at least vertically between the contact structure (24, 25) and the drift region (12) is free of the first semiconductor layer (13).

Description

Technical Field

[0001] A vertical field-effect transistor is provided, a method for manufacturing the same, and a component having the vertical field-effect transistor. Background Technology

[0002] Compared to similar devices based on silicon or silicon carbide, gallium nitride (GaN)-based transistors offer the possibility of achieving devices with lower on-resistance and higher breakdown voltage. One possible structural approach for such transistors is the so-called VHEMT (vertical trench high electron mobility transistor), where the channel is represented by a two-dimensional electron gas (2DEG) at the interface of the AlGaN / GaN heterostructure, grown in a V-shaped trench. Figure 1 An example of a conventional VHEMT transistor 100 is shown. Figure 1 The structure shown illustrates two transistor units. Each transistor unit comprises a conductive GaN substrate 111 on which a weakly n-doped GaN drift region 112 is applied. Above the drift region 112 lies a p-doped GaN region 113, above which lies an insulating GaN region or AlGaN region 114. The two regions 113 and 114 are penetrated by a V-shaped trench, above which an undoped GaN region 115 and an AlGaN region 116 extend. A two-dimensional electron gas (2DEG) is formed at the interface of the two regions 115 and 116—but within region 115. A p-doped GaN region 117 is introduced into the V-shaped trench to ensure normally-off operation of the transistor. A gate electrode 122 contacts the p-GaN region 117. A highly doped p-region 118 is introduced into the drift region 112 to shield the gate trench from the high electric field that occurs in the off state. The source contact 121 contacts not only the 2DEG but also the p-regions 113 and 118. A drain electrode 123 is present on the back side of the substrate 111.

[0003] Without a gate voltage applied, transistor 100 latches up because the 2DEG beneath p-GaN region 117 is depleted. By applying a positive voltage to gate electrode 122, the entire 2DEG is filled with electrons, and electrons flow from source electrode 121 through the sidewalls of the gate trench to the bottom of the gate trench and from there to drift region 112, through GaN substrate 111, and to drain electrode 123.

[0004] For the use of transistor 100, such as in inverter applications, the reverse conductivity of the component is absolutely essential. Figure 1In the structure shown, this reverse operation is achieved via a so-called body diode constructed between the p-region 118 and the n-type conductive drift region 112. During reverse operation, electrons do not flow through the 2DEG to the undoped GaN region 115, but instead flow from the drain electrode 123 through the substrate 111, drift region 112, and p-region 118 to the source electrode 121. In this sense, the body diode is connected in parallel with the transistor. The high bandgap of GaN creates an energy barrier at the pn junction, resulting in a high forward voltage of approximately 3V for the body diode. This forward voltage leads to high electrical losses during the transistor's reverse operation.

[0005] In addition, other power transistor architectures are known that provide additional Schottky contacts for low-loss reverse operation, see, for example, US 9,184,286 B2 or Zhu et al., “Vertical GaN Power Transistor With Intrinsic Reverse Conduction and Low Gate Charge for High-Performance Power Conversion” (IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 7, No. 3, DOI: 10.1109 / JESTPE.2019.2903828). Summary of the Invention

[0006] The objective of this invention is to provide a vertical field-effect transistor that achieves lower line loss during reverse operation and simultaneously achieves a lock-up vertical field-effect transistor with low sheet resistance, as well as a method for manufacturing the same and a component having the vertical field-effect transistor.

[0007] According to one aspect of the invention, this task is solved by a vertical field-effect transistor (VFET). The VFET comprises: a first semiconductor layer of p-conductivity type on or above a drift region; a trench structure perpendicularly penetrating the first semiconductor layer, wherein the trench structure has at least one sidewall on which a field-effect transistor (FET) channel region is formed, wherein the FET channel region has a III-V heterostructure for forming a two-dimensional carrier gas, such as an electron gas, at the interface of the III-V heterostructure; source / drain electrodes electrically connected to the III-V heterostructure; and a contact structure at least partially on or above the drift region, which forms a Schottky contact or heterostructure contact at least with the drift region, wherein the contact structure is electrically connected to the source / drain electrodes, and wherein the first semiconductor layer is absent at least vertically in the region between the contact structure and the drift region. This enables lower line losses during reverse operation and simultaneously enables a latching transistor with low sheet resistance. Intuitively, the high-loss conduction mechanism of the pn diode is replaced by a Schottky diode or heterojunction diode integrated into the vertical field-effect transistor (VFET). This enables a lower forward voltage than a traditional pn junction. This significantly reduces the conduction losses (Leitverluste) of the FET during reverse operation, thereby improving the efficiency of the VFET. During forward operation of the VFET, the Schottky diode or heterojunction diode is polarized in the cutoff direction and is therefore always off, ensuring that the switching performance of the VFET remains unaffected.

[0008] Optionally, an electrically insulating second semiconductor layer can be constructed on the first semiconductor layer. The trench structure can penetrate perpendicularly through the first and second semiconductor layers. The region perpendicularly between the contact structure and the drift region may not have the first and second semiconductor layers.

[0009] According to another aspect of the invention, this task is solved by a component. The component comprises: a first vertical field-effect transistor (VFET) and a second VFET, each having: a first semiconductor layer of p-conductivity type on or above the drift region; a trench structure perpendicularly penetrating the first semiconductor layer, wherein the trench structure has at least one sidewall on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure for constructing a two-dimensional electron gas at the interface of the III-V heterostructure; source / drain electrodes electrically connected to the III-V heterostructure; the component further comprises a contact structure at least partially on or above the drift region, wherein the contact structure is laterally constructed between the trench structure of the first VFET and the trench structure of the second VFET, and the contact structure is electrically connected to the source / drain electrode of at least one of the first and second VFETs, wherein at least vertically, there is no first semiconductor layer in the region between the contact structure and the drift region.

[0010] Optionally, the vertical field-effect transistor may have a second semiconductor layer, which is electrically insulating and constructed on the first semiconductor layer. The region vertically between the contact structure and the drift region may lack both the first and second semiconductor layers.

[0011] According to another aspect of the invention, this task is accomplished by a method for manufacturing a vertical field-effect transistor. The method comprises: constructing a first semiconductor layer having a p-conductivity type on or above a drift region; constructing a trench structure that vertically penetrates the first semiconductor layer, wherein the trench structure is configured to have at least one sidewall on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure for constructing a two-dimensional electron gas at the interface of the III-V heterostructure; constructing source / drain electrodes electrically connected to the III-V heterostructure; constructing a contact structure at least partially on or above the drift region, the contact structure forming a Schottky contact or heterostructure contact at least with the drift region, wherein the contact structure is electrically connected to the source / drain electrodes, and wherein at least vertically, the region between the contact structure and the drift region remains free of the first semiconductor layer.

[0012] Optionally, an electrically insulating second semiconductor layer can be constructed on the first semiconductor layer. The trench structure can penetrate perpendicularly through the first and second semiconductor layers. At least perpendicularly, the region between the contact structure and the drift region may lack both the first and second semiconductor layers. Attached Figure Description

[0013] Extensions to the described aspects are explained in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and described in more detail below. The drawings show:

[0014] Figure 1 A schematic cross-sectional view of a VEHMT transistor of the related technology is shown;

[0015] Figures 2 to 8 Schematic cross-sectional views of components having vertical field-effect transistors according to different embodiments are shown respectively;

[0016] Figure 9 and 10 Schematic top views of components having vertical field-effect transistors according to different embodiments are shown respectively;

[0017] Figure 11 Methods for manufacturing vertical field-effect transistors according to different embodiments are shown. Detailed Implementation

[0018] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification and illustrate specific embodiments in which the invention can be practiced. It will be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. It will be understood that features of the different embodiments described herein can be combined with each other unless specifically stated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined by the appended claims. In the drawings, the same or similar elements are given the same reference numerals, as is appropriate for the purpose.

[0019] Figures 2 to 8 Schematic cross-sectional views of components 51 having vertical field-effect transistors 10, 10a, and 10b according to different embodiments are shown respectively. Figure 9 and 10 Schematic top views of components 51 having vertical field-effect transistors 10, 10a, and 10b according to different embodiments are shown respectively. Figure 6 , Figure 9 and Figure 10 Field-effect transistor 10 is shown respectively. Figures 2 to 5 and Figures 7 to 8 A first vertical field-effect transistor 10a and a second vertical field-effect transistor 10b are shown. The shown vertical field-effect transistors 10, 10a, and 10b are individual units of a component having at least one vertical field-effect transistor (FET unit). A two-dimensional extended field of the FET unit is generated by combining multiple FET units. The vertical field-effect transistor can be a power semiconductor component.

[0020] Vertical field-effect transistors 10, 10a, and 10b have drift regions 12 on a semiconductor substrate 11, such as a GaN substrate 11, for example, an n-doped GaN drift region 12. A first semiconductor layer 13 having a p-conductivity type, such as a p-doped semiconductor layer 13, is present above the drift region 12. Optionally, a second semiconductor layer 14, such as an electrically insulating semiconductor layer 14, such as an electrically insulating GaN or AlGaN semiconductor layer 14, may be constructed on the first semiconductor layer 13. The first and (optionally) second semiconductor layers 13, 14 are penetrated by a V-shaped trench. A trench structure 50 is constructed in the V-shaped trench, which vertically penetrates the first semiconductor layer 13 and (optionally) the second semiconductor layer 14. The trench structure 50 has at least one sidewall on which a field-effect transistor (FET) channel region is constructed. The trench structure 50 may have a first sidewall and a second sidewall including a bottom. The FET channel region has a III-V heterostructure 15 / 16, which is used to construct a two-dimensional electron gas (2DEG) at the interface of the III-V heterostructure 15 / 16. The III-V heterostructure 15 / 16 has, for example, an undoped GaN layer 15 and an AlGaN layer 16. A two-dimensional electron gas (2DEG) is formed at the interface of the two layers 15, 16—but within layer 15. A p-doped GaN region 17 is also constructed in the V-shaped trench to ensure normally-off operation of the vertical field-effect transistors 10, 10a, 10b. The gate electrode 22 contacts the p-GaN region 17. A shielding structure 18 with p-conductivity, such as a highly doped p-doped layer 18, can be constructed in the drift region 112 to shield the trench from the high electric field that occurs in the off state. The shielding structure 18 can be electrically connected to the source / drain electrodes 21. Compared to the III-V heterostructure 15 / 16, the shielding structure 18 can extend further in the direction of the drift region 12 or into the drift region 12. The source electrode 21 is in contact with, and electrically connected to, not only the 2DEG, but also the first semiconductor layer 13 and (optionally) the shielding structure 18. A drain electrode 23 is present on the back side of the substrate 11.

[0021] Vertical field-effect transistors 10, 10a, and 10b also have a contact structure 24, at least partially on or above the drift region 12, which forms a Schottky contact or heterojunction contact with the drift region 12. In different embodiments, the contact structure 24 is part of a Schottky diode (see [link to relevant documentation]). Figures 2 to 6 Alternatively, contact structure 24 is part of a heterodiode (see [link]). Figure 7 and Figure 8It has, for example, polysilicon or is formed of polysilicon. The contact structure 24 is electrically connected to the source / drain electrode 21. At least vertically, there is no first semiconductor layer 13 and second semiconductor layer 14 in the region between the contact structure 24 and the drift region 12.

[0022] like Figures 2 to 4 , Figure 8 As shown, contact structure 24 can be constructed on the III-V heterostructure 15 / 16. Alternatively, contact structure 24 can be directly constructed on the drift region 12, as shown. Figures 5 to 7 As shown in the diagram, contact structure 24 can be constructed on the III-V heterostructure 15 / 16 and above the bottom (see Figure 1). Figure 2 and Figure 3 ) and / or above one of the first and second sidewalls (see above) Figure 3 ).

[0023] The vertical field-effect transistor 10 may also have an insulating layer 31 on or above the III-V heterostructure 15 / 16. The insulating layer 31 may be constructed between the contact structure 24 and the gate electrode 22 (see [link to documentation]). Figure 8 ).

[0024] Alternatively, the contact structure 24 may be constructed laterally alongside the trench structure 50. (See also) Figures 4 to 7 )

[0025] Contact structure 24 can, for example, be laterally constructed between trench structure 50 and shielding structure 18 (see...). Figure 6 ).

[0026] Alternatively, the contact structure 24 can be arranged outside the FET cell 10 (see [reference]). Figure 4 , Figure 5 or Figure 7For example, laterally between the shielding structures of adjacent vertical field-effect transistors 10a and 10b. In this case, component 51 has, for example, at least one first vertical field-effect transistor 10a and a second vertical field-effect transistor 10b. The first and second vertical field-effect transistors 10a and 10b each have: a first semiconductor layer 13 on or above the drift region 12, the first semiconductor layer having a p-conductivity type; a second semiconductor layer on the first semiconductor layer 13, the second semiconductor layer being electrically insulating; a trench structure 50 that vertically penetrates the first semiconductor layer 13 and the second semiconductor layer 14, wherein the trench structure 50 has at least one sidewall on which a field-effect transistor (FET) channel region is formed, wherein the FET channel region has a III-V heterostructure 15 / 16, the III-V heterostructure being used to form a two-dimensional electron gas at the interface of the III-V heterostructure 15 / 16; and a source / drain electrode 21 that is electrically connected to the III-V heterostructure 15 / 16. The component 51 also has a contact structure 24 at least partially on or above the drift region 12, wherein the contact structure 24 is laterally constructed between the trench structure 50 of the first vertical field-effect transistor 10a and the trench structure 50 of the second vertical field-effect transistor 10b, and the contact structure is electrically connected to the source / drain electrode 21 (e.g., to the source / drain electrode 21 of both) of at least one of the first and second vertical field-effect transistors 10a and 10b. At least vertically, there is no first semiconductor layer 13 and second semiconductor layer 14 in the region between the contact structure 24 and the drift region 12. The first and second vertical field-effect transistors 10a and 10b may also each have a shielding structure 18 having a p-conductivity type and being electrically connected to the source / drain electrode 21 of the corresponding vertical field-effect transistors 10a and 10b. Compared to the III-V heterostructure 15 / 16 of the corresponding vertical field-effect transistor 10, the shielding structure 18 can extend further in the direction of the drift region 12 or extend into the drift region 12. The contact structure 24 can be laterally constructed between the shielding structure 18 of the first vertical field-effect transistor 10a and the shielding structure 18 of the second vertical field-effect transistor 10b (see [reference]). Figure 4 , Figure 5 or Figure 7 ).

[0027] The groove structure 50 can have a strip shape or a hexagonal shape in the longitudinal direction perpendicular to the vertical direction. The contact structure 24 can have a columnar cross-sectional shape in the longitudinal direction (see...). Figure 9 Alternatively, the contact structure 24 may have a strip shape that extends laterally across the width of the vertical field-effect transistor 10 (see [link]). Figure 10 ).

[0028] Without applying a gate voltage and with the drain electrode having a positive polarity relative to the source electrode 21, the vertical field-effect transistors 10, 10a, and 10b are latched up because the 2DEG beneath the p-doped layer 17 is depleted. By applying a positive voltage to the gate electrode 22, the entire 2DEG is filled with electrons, and electrons flow from the source electrode 21 through the sidewalls of the gate trench to the bottom of the trench and from there to the drift region 12, through the substrate 11, and to the drain electrode 23.

[0029] Intuitively, in Figure 2 In the embodiment shown, the gate electrode 22 and the p-doped GaN layer 17 beneath it are interrupted at the bottom of the trench, and a contact structure 24 is introduced at the bottom, which forms a Schottky contact with the III-V heterostructures 15 / 16 and / or the drift region 12. In this case, electron flow in reverse operation proceeds from the drain electrode 23 through the substrate 11, the drift region 12, the III-V heterostructures 15+16, to the contact structure 24. The contact structure 24 is electrically connected to the source electrode 21. This connection can be made locally in each FET cell of component 51 or in a separate region within FETs 10, 10a, 10b. Alternatively, the III-V heterostructures 15+16 beneath the contact structure 24 can be removed. This can facilitate a Schottky contact (not shown). In this case, the contact structure 24 is located directly on the drift region 12.

[0030] exist Figure 3 In the embodiment shown, the contact structure 24 is implemented not only in the bottom of the trench but also above the sidewalls. This results in a significantly larger contact area and thus a reduction in the resistance of the body diode. Furthermore, the channel resistance increases because the channel is only constructed on the sidewalls of the trench structure. This embodiment is advantageous for applications requiring particularly low losses during reverse operation. Furthermore, this embodiment, for example, is similar to... Figure 2 Compared to the previous implementation, this method has lower requirements for photolithography because the contact structure 24 is no longer introduced into the break between layer 17 and gate electrode 22. The contact structure 24 only needs to be precisely adjusted in one direction. This can significantly reduce manufacturing overhead. In this implementation, the region beneath the contact structure 24 may also be free of the III-V heterostructure 15 / 16.

[0031] exist Figure 4In the embodiment shown, the contact structure 24 is arranged outside the FET cells 10a, 10b, for example, between two directly adjacent FET cells 10a and 10b. This can further reduce manufacturing overhead. In this embodiment, the shielding structure 18 also shields the contact structure 24 from the electric field in the off state. By positioning the contact structure 24 outside the FET cells 10a, 10b, photolithography requirements are lower. Furthermore, the grid size (Rastermaß) of the component 51 is increased, thereby increasing the maximum current density during forward operation. In this case, the first and second semiconductor layers 13, 14 are interrupted below the contact structure 24 to enable current flow through the contact structure 24, such as a Schottky contact, during reverse operation. This interruption can be achieved, for example, by applying the contact structure 24 in the bottom of a trench that penetrates the first and second semiconductor layers 13, 14 and the III-V heterostructure 15 / 16, as... Figure 5 As shown in the diagram. Alternatively, a trench including contact structure 24 may be introduced within the FET cell (see [reference]). Figure 6 The potential material for contact structure 24 can be applied by sputtering, thermal evaporation, and / or electron beam evaporation. As an alternative to a Schottky contact and corresponding to a Schottky diode as a body diode, contact structure 24 can realize a semiconductor heterojunction, for example, by means of contact structure 24 composed of or having polysilicon 25 (see...). Figure 7 The trench can be completely filled with polysilicon 25 through conformal deposition, such as by chemical vapor deposition. The polysilicon 25 can be easily connected to the source potential at the upper edge of the trench via the source electrode 21. An energy barrier can be constructed at the transition from the polysilicon 25 to the drift region 12, such as the n-GaN drift region, which is higher than the energy barrier of a typical Schottky contact but lower than that of a pn junction. In reverse operation of component 51, a forward voltage of approximately 1.2V to approximately 1.8V may thus be achieved. Alternatively, the body diode can also be implemented using polysilicon 25 within the gate trench, such as... Figure 8 As shown in the diagram. Here, the polysilicon contact structure 24 (25) is electrically insulated from the gate electrode 22 and the p-GaN layer 17 by means of an insulating layer 31. In component 51, Figures 2 to 8 The cross-sectional structure shown can continue as a strip or hexagonal shape in the longitudinal direction (within the drawing plane) perpendicular to the cross-sectional view. In this strip or hexagonal shape, optionally or not necessarily, each segment of each FET cell has a body diode contact structure 24 in the longitudinal direction. Providing corresponding body diode contact structures 24 in each segment may be sufficient. Figure 9The top view shows a strip-shaped embodiment in which the body diode contact structure 24 is introduced not only in the gate trench but also segmentally, replacing the shielding structure. Figure 10 As shown, the body diode contact structure 24 can also be implemented segment by segment in the longitudinal direction over the entire width of the FET cell. In this case, in the longitudinal direction, FET cells without the body diode contact structure 24 are alternated with FET cells that only have the body diode contact structure 24, and in which, for example, the first and second semiconductor layers 13, 14, the III-V heterostructure 15 / 16, and layer 17 have been at least partially or completely removed. This reduces the requirements for the photolithography process.

[0032] Figure 11 A flowchart of a method 200 for manufacturing a vertical field-effect transistor according to a different embodiment is shown. Method 200 includes: constructing a first semiconductor layer 13 210 on or above a drift region 12, the first semiconductor layer having a p-conductivity type; constructing a trench structure 230 perpendicularly penetrating the first semiconductor layer 13, wherein the trench structure is configured to have at least one sidewall, on which a field-effect transistor FET-channel region is constructed, wherein the FET-channel region has a III-V heterostructure 15 / 16, the III-V heterostructure being used to construct a field-effect transistor at the interface of the III-V heterostructure 15 / 16. A two-dimensional electron gas is created; a source / drain electrode 21 is constructed 240, which is electrically connected to a III-V heterostructure 15 / 16; a contact structure 250 is constructed at least partially on or above the drift region 12, the contact structure forming a Schottky contact or heterostructure contact with the drift region 12, wherein the contact structure 24 is electrically connected to the source / drain electrode 21, and wherein at least vertically, the region between the contact structure 24, 25 and the drift region 12 remains free of the first semiconductor layer 13.

[0033] Optionally, an electrically insulating second semiconductor layer 14 may be constructed on the first semiconductor layer 13. The trench structure 50 may penetrate perpendicularly through the first semiconductor layer 13 and the second semiconductor layer 14. At least perpendicularly, the region between the contact structures 24, 25 and the drift region 12 may be devoid of the first semiconductor layer 13 and the second semiconductor layer 14.

[0034] The embodiments described and shown in the accompanying drawings are selected only by way of example. Different embodiments can be combined with each other completely or with respect to various features. One embodiment can also be supplemented by features of another embodiment. Furthermore, the described method steps can be performed repeatedly and in a different order than described. In particular, the invention is not limited to the described method.

Claims

1. A component (51) having: A first vertical field-effect transistor (10a) and a second vertical field-effect transistor (10b), wherein the first vertical field-effect transistor and the second vertical field-effect transistor respectively have: A first semiconductor layer (13) on or above the drift region (12) has a p-conductivity type; A trench structure (50) that penetrates vertically through the first semiconductor layer (13). in, The trench structure (50) has at least one sidewall on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure (15 / 16) for constructing a two-dimensional electron gas at the interface of the III-V heterostructure (15 / 16); and Source / drain electrode (21), which is electrically connected to the III-V heterostructure (15 / 16); A shielding structure (18) having a p-conductivity type and conductively connected to the source / drain electrodes (21) of the corresponding vertical field-effect transistors (10a, 10b), wherein, compared to the III-V heterostructure (15 / 16) of the corresponding vertical field-effect transistor (10), the shielding structure (18) extends further in the direction of the drift region (12) or extends into the drift region (12); and The component (51) also has contact structures (24, 25) at least partially on or above the drift region (12), the contact structures forming a Schottky contact or heterogeneous contact with at least the drift region (12), wherein the contact structures (24, 25) are laterally configured between the shielding structure (18) of the first vertical field-effect transistor (10a) and the shielding structure (18) of the second vertical field-effect transistor (10b) and are electrically connected to the source / drain electrode (21) of at least one of the first vertical field-effect transistor (10a) and the second vertical field-effect transistor (10b), wherein the contact structures (24, 25) are spaced apart from the shielding structure (18), wherein the shielding structure (18) is configured to shield the trench structure (50) and the contact structures (24, 25) from the high electric field that occurs in the off state. Wherein, at least in the region between the contact structure (24, 25) and the drift region (12), there is no first semiconductor layer (13).

2. The component (51) according to claim 1, wherein, The contact structures (24, 25) are constructed on the III-V heterostructure (15 / 16).

3. The component (51) according to claim 1, wherein, The contact structures (24, 25) are directly constructed on the drift region (12).

4. The component (51) according to claim 1. in, The groove structure (50) has a strip shape or a hexagonal shape in the longitudinal direction, and the longitudinal direction is perpendicular to the vertical direction. The contact structures (24, 25) have a columnar cross-sectional shape in the longitudinal direction; The contact structures (24, 25) have a strip shape that extends laterally across the width of the vertical field-effect transistor (10).

5. The component (51) according to any one of claims 1 to 4. in, The contact structure is part of a Schottky diode. Alternatively, the contact structure may be part of a heterodiode.

6. The component (51) according to claim 5, wherein, The contact structure has polycrystalline silicon or is formed of polycrystalline silicon.

7. The component (51) according to any one of claims 1 to 4, wherein the first vertical field-effect transistor (10a) and the second vertical field-effect transistor (10b) further comprise: A second semiconductor layer (14) is placed on the first semiconductor layer (13), the second semiconductor layer being electrically insulating. in, The trench structure (50) penetrates vertically through the first semiconductor layer (13) and the second semiconductor layer (14), wherein at least vertically, there are no first semiconductor layer (13) and second semiconductor layer (14) in the region between the contact structure (24, 25) and the drift region (12).

8. A method (200) for manufacturing a component (51) having a first vertical field-effect transistor (10a) and a second vertical field-effect transistor (10b), wherein the first vertical field-effect transistor (10a) and the second vertical field-effect transistor (10b) are respectively constructed having: A first semiconductor layer of p-conductivity type is constructed on or above the drift region (12); A trench structure (50) is constructed, which perpendicularly penetrates the first semiconductor layer (13). in, The trench structure is configured to have at least one sidewall on which a field-effect transistor (FET) channel region is constructed, wherein the FET channel region has a III-V heterostructure (15 / 16) for constructing a two-dimensional electron gas at the interface of the III-V heterostructure (15 / 16). Construct source / drain electrodes (21), which are electrically connected to the III-V heterostructure (15 / 16); A contact structure (24, 25) is constructed at least partially on or above the drift region (12), the contact structure forming at least a Schottky contact or a heterogeneous contact with the drift region, wherein the contact structure (24, 25) is electrically connected to the source / drain electrode (21). The method also has the following characteristics: A shielding structure (18) is constructed, the shielding structure having a p-conductivity type and being conductively connected to the source / drain electrodes (21) of the corresponding vertical field-effect transistors (10a, 10b), wherein, compared to the III-V heterostructure (15 / 16) of the corresponding vertical field-effect transistor (10), the shielding structure (18) extends further in the direction of the drift region (12) or extends into the drift region (12), wherein the contact structures (24, 25) are laterally constructed on the shielding structure of the first vertical field-effect transistor (10a). 18) Conductively connected between the shielding structure (18) of the second vertical field-effect transistor (10b) and the source / drain electrodes (21) of at least one of the first vertical field-effect transistors (10a) and the second vertical field-effect transistor (10b), wherein the shielding structure (18) is configured to shield the trench structure (50) and the contact structures (24, 25) from the high electric field that occurs in the off state, wherein the contact structures (24, 25) are spaced apart from the shielding structure (18). The first semiconductor layer (13) is absent in the region between the contact structure (24, 25) and the drift region (12), at least vertically.

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