Graphic design method and system, mask combination, device and storage medium

Abstract

A graphic design method and system, mask assembly, device, and storage medium. The graphic design method includes: providing an initial graphic, including multiple main graphics; defining the distance between adjacent main graphics as a spacing; setting preset problem spacings, including a violation spacing and a weak point spacing, wherein the violation spacing is less than the lithography resolution limit, and the weak point spacing is greater than the lithography resolution limit; configuring preset problem graphics based on the preset problem spacings, including: a violation pattern pair consisting of a pair of adjacent main graphics with a violation spacing, and a weak point pattern combination consisting of a central main graphic located at a central position and at least two edge main graphics with a weak point spacing between the central main graphic and the violating pattern pair; and splitting the initial graphic, with the violation pattern pair being prioritized over the weak point pattern combination, to obtain multiple sub-graphic layers. Embodiments of the present invention facilitate increasing the lithography process window of the sub-graphic layers and improving the imaging quality of the lithography process.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a graphic design method and system, a mask assembly, a device, and a storage medium. Background Art

[0002] As circuit integration increases and scale grows, the size of unit devices in the circuit continues to shrink, and the requirements for integrated circuit manufacturing processes continue to increase. For example, critical dimensions continue to decrease, and chip manufacturing requires increasingly higher lithography resolution.

[0003] To address the resolution limitations of traditional photolithography, multiple patterning (MP) technology was proposed to achieve technology node scaling. The core of MP technology is to split the original single-layer lithography pattern onto two or more masks, thereby breaking down a high-density pattern into two or more discrete, lower-density patterns. Multiple photolithography and etching steps are then used to recreate the original single-layer design.

[0004] Multi-patterning technology typically defines a series of splitting rules based on design rules when splitting patterns. These rules are then used to decompose the pattern to meet the requirements of the multiple exposure process. Multi-patterning pattern splitting can affect the accuracy and quality of subsequent lithography processes, and thus the smooth progress of the entire semiconductor process.

[0005] However, in the current multiple patterning technology, after the initial pattern is split, there is still the problem of a small photolithography process window. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a graphic design method and system, a mask assembly, a device and a storage medium, which are conducive to increasing the photolithography process window of the sub-graphic layer and improving the imaging quality of the photolithography process.

[0007] To solve the above problems, an embodiment of the present invention provides a graphic design method, including: providing an initial graphic, including multiple main graphics; defining the distance between adjacent main graphics as a spacing; setting a preset problem spacing, including a violation spacing and a weakness spacing, wherein the violation spacing is less than the lithography resolution limit, and the weakness spacing is greater than the lithography resolution limit; based on the preset problem spacing, configuring a preset problem graphic, including: a violation graphic pair consisting of a pair of adjacent main graphics with the violation spacing, and a weakness graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the weakness spacing between the central main graphic and the edge main graphics; splitting the initial graphic, and the splitting priority of the violation graphic pair is higher than the splitting priority of the weakness graphic combination, to obtain multiple sub-graphic layers.

[0008] Optionally, the weak point spacing includes a first weak point spacing within a prohibited period.

[0009] Optionally, the weakness pattern combination includes: a central main pattern and four edge main patterns having the first weakness point spacing between the central main pattern and the edge main patterns.

[0010] Optionally, the weak point spacing includes a second weak point spacing; the second weak point spacing is greater than the photolithography resolution limit and less than or equal to 103% of the photolithography resolution limit.

[0011] Optionally, in the process of setting a preset problem spacing, the preset problem spacing also includes a secondary problem spacing, and the secondary problem spacing is greater than the lithography resolution limit; based on the preset problem spacing, in the process of configuring a preset problem graphic, the preset problem graphic also includes: a secondary problem graphic pair consisting of a pair of adjacent main graphics with the secondary problem spacing; in the process of splitting the initial graphic, the splitting priority of the secondary problem graphic pair is lower than the splitting priority of the weakness graphic combination.

[0012] Optionally, splitting the initial graphics includes: splitting the main graphics of each of the violation graphics pairs into different sub-graphic layers, and splitting the multiple main graphics in each of the weak graphics combination into at least two different sub-graphic layers.

[0013] Optionally, the main graphic is a rectangular graphic.

[0014] Optionally, the main pattern is used to form a conductive through hole, a contact hole or a metal line.

[0015] Optionally, in the process of splitting the initial graphic, the number of the sub-graphic layers is 2 to 5.

[0016] Correspondingly, an embodiment of the present invention also provides a graphic design system, including: a providing unit for providing an initial graphic, including multiple main graphics; defining the distance between adjacent main graphics as a spacing; a problem graphic configuration unit for setting a preset problem spacing, including a violation spacing and a weakness spacing, wherein the violation spacing is less than the lithography resolution limit, and the weakness spacing is greater than the lithography resolution limit; and further for configuring a preset problem graphic based on the preset problem spacing, including: a violation graphic pair consisting of a pair of adjacent main graphics with the violation spacing, and a weakness graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the weakness spacing between the central main graphic and the central main graphic; a graphic splitting unit for splitting the initial graphic, and the splitting priority of the violation graphic pair is higher than the splitting priority of the weakness graphic combination, to obtain multiple sub-graphic layers.

[0017] Correspondingly, an embodiment of the present invention further provides a mask assembly, comprising: a plurality of sub-masks, each of the sub-masks having a corresponding sub-pattern layer, wherein the sub-pattern layer is formed using any of the aforementioned pattern design methods.

[0018] Accordingly, an embodiment of the present invention also provides a device comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement any of the aforementioned graphic design methods.

[0019] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement any of the aforementioned graphic design methods.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] In the graphic design method provided by an embodiment of the present invention, the preset problem spacing configured also includes a weak point spacing, and the weak point spacing is greater than the lithography resolution limit. When configuring the preset problem graphic, the preset problem graphic also includes a weak point graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the weak point spacing between the central main graphic and the central main graphic. In addition, in the process of splitting the initial graphic, the splitting priority of the violation graphic pair is higher than the splitting priority of the weak point graphic group, thereby ensuring that while the main graphics of each violation graphic pair are split into different sub-graphic layers, the weak point graphics are The multiple main graphics in the combination can be split into at least two sub-graphic layers, so that the weak graphic combination can be avoided in the same sub-graphic layer. Accordingly, when splitting the initial graphics, the embodiment of the present invention not only considers whether the spacing between the two main graphics is greater than the lithography resolution limit, but also considers the weak graphic combination composed of multiple main graphics with weak point spacing, so as to ensure that in the sub-graphic layer after splitting, the spacing between adjacent main graphics is greater than the resolution limit, and there is no graphic combination that is prone to weak points in the sub-graphic layer, which is beneficial to increasing the lithography process window of the sub-graphic layer and improving the imaging quality of the lithography process.

[0022] In an optional solution, the weak point spacing includes a first weak point spacing within a prohibited period. When the spacing between adjacent main patterns is within the prohibited period, the resolution and imaging quality of the lithography process are reduced and the process window is small. By making the weak point spacing include the first weak point spacing, while the main patterns of each violating pattern pair are split into different sub-pattern layers, it is also ensured that the weak point pattern combination can be avoided in the same sub-pattern layer, thereby preventing the occurrence of a central main pattern and multiple edge main patterns with a spacing within the prohibited period between the central main pattern and the sub-pattern layer. Correspondingly, it prevents the generation of a bad spot (hot spot) at the position of the central main pattern, which is beneficial to significantly increase the lithography process window of the sub-pattern layer. Moreover, it can also provide more setting space for setting auxiliary patterns around the main pattern, which is beneficial to increase the number of auxiliary patterns that can be set, and correspondingly enhance the resolution of the lithography process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of a graphic design method;

[0024] Figures 2 to 3 yes Figure 1 Schematic diagram corresponding to each step of the graphic design method;

[0025] Figure 4 yes Figure 3 Schematic diagram of the lithography simulation outline of the sub-pattern layer 13(1);

[0026] Figure 5 It is a flow chart of an embodiment of a graphic design method of the present invention;

[0027] Figure 6 is a schematic diagram of an embodiment of an initial graphic provided by the graphic design method of the present invention;

[0028] Figure 7 The embodiment of the present invention is Figure 6 Schematic diagram of the sub-graphic layers obtained by splitting the initial graphic in;

[0029] Figure 8 is a functional block diagram of an embodiment of a graphic design system of the present invention;

[0030] Figure 9 It is a hardware structure diagram of an embodiment of the device of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, in current multi-patterning technology, after the initial pattern is split, the lithography process window is still small. Now, combined with a pattern design method, the reason why the lithography process window is still small after the initial pattern is split is analyzed.

[0032] Figure 1 It is a flowchart of a graphic design method. Figures 2 to 3 yes Figure 1 Schematic diagram corresponding to each step of the graphic design method.

[0033] like Figure 2 As shown, step s1: providing an initial graphic 10 including a plurality of main graphics 11.

[0034] like Figure 2 As shown, step s2: defining the spacing between adjacent main patterns 11 that is less than the resolution limit of the photolithography process as a violation spacing Sa; marking the initial pattern 10 to mark a pair of main patterns 11 having the violation spacing Sa as a violation pattern pair. Figure 2 As shown, the pairs of illegal patterns are connected by short straight lines.

[0035] like Figure 3 As shown in (a), step s3: split the initial pattern 10 to obtain multiple sub-pattern layers 13, which are used to split the main pattern 11 of each illegal pattern pair into different sub-pattern layers 13, so that each sub-pattern layer 13 meets the requirements of the multiple exposure process. For example: Figure 3 As shown in (a), the initial graph 10 is split into three sub-graphs 13(1), 13(2), and 13(3).

[0036] However, in the above method, after the initial pattern 10 is split, the individual sub-pattern layers 13 may still have the problem of a small photolithography process window.

[0037] According to the inventors' analysis, although the illegal spacing is eliminated in a single sub-pattern layer 13, so that the spacing between adjacent main patterns 11 can be greater than the resolution limit of the photolithography process, the method only considers whether the spacing between two main patterns 11 is a illegal spacing when splitting. It does not consider that when each illegal pattern pair is split into different sub-pattern layers 13, in each sub-pattern layer 13 after splitting, one of the main patterns 11 of the illegal pattern pair may form a weak pattern combination with other adjacent main patterns 11, for example, Figure 3 As shown in (b), in one of the sub-pattern layers 13(1), the main pattern 11 located at the center serves as the central main pattern 11(1), and the spacing Sf between the central main pattern 11(1) and the adjacent main pattern 11 is within the forbidden pitch range, resulting in poor imaging quality of the photolithography process and a reduced photolithography process window.

[0038] like Figure 4 As shown, Figure 4 The circle in the figure shows the range of the lithography simulation profile of the main pattern 11 of the sub-pattern layer 13 (1) under different process conditions, that is, the lithography process variation bandwidth (PV band). Figure 4 As shown, compared with other main graphics 11, the photolithography process variation bandwidth of the central main graphics 11 (1) is larger. A too large photolithography process variation bandwidth means that the instability of the equipment and process during exposure will lead to a larger exposure deviation, and the photolithography process window will be reduced. The central main graphics 11 (1) is correspondingly a problematic main graphics.

[0039] One current approach is to increase the size of the problematic main pattern to reduce the spacing between it and adjacent main patterns, so that the spacing does not fall within the prohibited period. However, this approach can easily result in the problematic main pattern being too close to other adjacent main patterns, or even bridging them.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a graphic design method, wherein the configured preset problem spacing also includes a weak point spacing, and the weak point spacing is greater than the lithography resolution limit. When configuring the preset problem graphic, the preset problem graphic also includes a weak point graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the central main graphic having the weak point spacing therebetween. In the process of splitting the initial graphic, the splitting priority of the violation graphic pair is higher than the splitting priority of the weak point graphic group, thereby ensuring that while the main graphics of each violation graphic pair are split into different sub-graphic layers, multiple main graphics in the weak point graphic combination can be split into at least two sub-graphic layers, so that the weak point graphic combination can be avoided in the same sub-graphic layer. Accordingly, when splitting the initial graphic, the embodiment of the present invention not only considers whether the spacing between each pair of main graphics is greater than the lithography resolution limit, but also considers the weak point graphic combination consisting of multiple main graphics with weak point spacing, so as to ensure that in the sub-graphic layer after splitting, the spacing between adjacent main graphics is greater than the resolution limit, and there is no weak point (Weak Point) in the sub-graphic layer. The pattern combination of the sub-pattern layer and the sub-pattern layer is beneficial to enlarging the photolithography process window of the sub-pattern layer and improving the imaging quality of the photolithography process.

[0041] Figure 5 1 is a flow chart of an embodiment of a graphic design method of the present invention. As an example, the graphic design method of this embodiment includes the following basic steps:

[0042] Step S1: providing an initial graphic, including a plurality of main graphics; defining the distance between adjacent main graphics as a spacing;

[0043] Step S2: setting a preset problem spacing, including a violation spacing SA and a weak point spacing, wherein the violation spacing SA is smaller than the lithography resolution limit, and the weak point spacing is larger than the lithography resolution limit;

[0044] Step S3: Based on the preset problem spacing, configuring a preset problem pattern, including: a violation pattern pair consisting of a pair of adjacent main patterns having the violation spacing, and a weakness pattern combination consisting of a central main pattern located at a central position and at least two edge main patterns having the weakness spacing between the central main pattern and the edge main pattern;

[0045] Step S4: splitting the initial graph, and giving a higher priority to splitting the violation graph pair than to splitting the weak graph combination, to obtain a plurality of sub-graph layers.

[0046] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] refer to Figure 5 and Figure 6 , Figure 6 1 is a schematic diagram of an initial graphic 100 provided in this embodiment. Step S1: providing an initial graphic 100 including a plurality of main graphics 110; defining the distance between adjacent main graphics 110 as a spacing.

[0048] The initial pattern 100 is an initial design pattern to be split into multiple patterns. In the initial pattern 100, a plurality of main patterns 110 are arranged at intervals.

[0049] It should be noted that, in this embodiment, the multiple patterning splitting may be double patterning splitting, triple patterning splitting, quadruple patterning splitting, etc., and the number of masks obtained by the multiple patterning splitting is greater than or equal to two.

[0050] Specifically, based on the rules of multiple pattern splitting, the multiple main patterns 110 in the initial pattern 100 are subsequently split into different sub-pattern layers, so that the sub-pattern layers meet the exposure process tolerance.

[0051] As an example, the main pattern 110 is a rectangular pattern. The initial pattern 100 includes a plurality of main patterns 110 of rectangular patterns, which is friendly to the mask manufacturing process and optical proximity effect correction, and the result is controllable.

[0052] As an embodiment, the main pattern 110 is used to form a conductive via. During the semiconductor manufacturing process, the conductive via is used to provide a space for forming a conductive plug, which is used to electrically connect the metal lines of the adjacent next layer and the adjacent previous layer.

[0053] In the semiconductor field, the probability of a conductive via pattern being split is high. Splitting a plurality of main patterns 110 for forming conductive vias is beneficial for significantly increasing the process window.

[0054] In other embodiments, based on actual process requirements, the main pattern may also be used to form other patterns such as contact holes or metal lines.

[0055] It should be noted that, for the convenience of illustration and description, Figure 6 Only a partial graph of the initial graph 100 is shown.

[0056] Step S2: setting a preset problem spacing, including a violation spacing SA and a weak point spacing, wherein the violation spacing SA is smaller than a photolithography resolution limit (Resolution Limit), and the weak point spacing is larger than the photolithography resolution limit.

[0057] The preset problem spacing is a preset spacing type that has the risk of violating design rules or reducing the photolithography process window. By setting the preset problem spacing, a preset problem graphic combination can be configured based on the preset problem spacing.

[0058] The violation spacing SA is smaller than the photolithography resolution limit. The adjacent main patterns 110 with the violation spacing SA violate the exposure process tolerance. Accordingly, the adjacent main patterns 110 with the violation spacing SA need to be split into different sub-pattern layers.

[0059] It should be noted that the photolithography resolution limit refers to the minimum spacing between patterns that can be distinguished during the exposure process during the photolithography process.

[0060] Accordingly, in a specific process, the photolithography resolution is determined based on actual photolithography process equipment and process conditions, and the specific value of the photolithography resolution limit is not limited in this embodiment.

[0061] The weak point spacing is greater than the photolithography resolution limit, and the weak point spacing is a preset spacing type that easily causes a reduction in the photolithography process window.

[0062] As an example, the weak point spacing includes a first weak point spacing SB within a forbidden period (Forbidden Pitch).

[0063] The forbidden period is larger than the lithography resolution limit. However, when the spacing between adjacent patterns falls within the forbidden period (or forbidden spacing), the lithography process image quality deteriorates significantly, the lithography process window narrows, and the error factor (MEEF) between the mask pattern and the wafer pattern increases. By including the first weak point spacing SB within the forbidden period in the preset problem spacing, subsequent configuration of the preset problem pattern based on the preset problem spacing can take into account pattern combinations with spacing within the forbidden period, further improving the lithography process window.

[0064] The prohibited period is related to the size between the main patterns and the spacing between adjacent main patterns. In patterns with different sizes and spacings, the corresponding prohibited periods are also different. Therefore, this embodiment does not limit the specific value of the first weak point spacing SB.

[0065] As an example, when the ratio of the size to the spacing of the main pattern is around 1:3, an inhibit period will be present.

[0066] It should be noted that, in an actual process, the weak point spacing may further include a second weak point spacing (not shown) that is close to the photolithography resolution limit.

[0067] Here, close to the lithography resolution limit means that it is greater than the lithography resolution limit, but the difference between it and the lithography resolution limit is very small.

[0068] In the semiconductor field, even if the spacing between adjacent main patterns 110 exceeds the lithography resolution limit, if the spacing is only slightly greater than the lithography resolution limit or the difference between the spacing and the lithography resolution limit is extremely small, there is still a risk of reducing the lithography process window. Therefore, by including the weak point spacing in the second weak point spacing, more situations that can easily reduce the lithography process window can be taken into account, thereby increasing the lithography process window of the sub-pattern layer when the initial pattern is split.

[0069] As an example, the second weak point spacing is greater than the photolithography resolution limit and less than or equal to 103% of the photolithography resolution limit.

[0070] It should be noted that the numerical relationship between the second weak point spacing and the photolithography resolution limit in this embodiment is only an example. In actual processes, the numerical range of the second weak point spacing can be reasonably set according to specific process requirements.

[0071] It should also be noted that the above description uses the weak point spacing including the first weak point spacing SB and the second weak point spacing as an example, and the spacing types included in the weak point spacing are not limited to this. In actual processes, those skilled in the art can set different weak point spacing types based on actual needs.

[0072] As an example, in the process of setting the preset problem spacing, the preset problem spacing may further include a secondary problem spacing (not shown), where the secondary problem spacing is greater than the photolithography resolution limit.

[0073] The minor problem spacing may be the same as or different from the weak point spacing. Compared with the violation spacing SA and the weak point spacing, the subsequent splitting priority of the minor problem graph pair configured based on the minor problem spacing is lower.

[0074] Specifically, as an embodiment, the secondary problem spacing can be set to 110%, 120%, 130%, etc. of the lithography resolution limit, so that the main graphic 110 can be evenly split into different sub-graphic layers, preventing the appearance of multiple main graphics 110 with high density and close distance in a single sub-graphic layer.

[0075] In other embodiments, based on actual needs, the preset question interval may not include the secondary question interval.

[0076] Step S3: Based on the preset problem spacing, a preset problem pattern is configured, including: a violation pattern pair consisting of a pair of adjacent main patterns 110 having the violation spacing SA, and a weakness pattern combination consisting of a central main pattern located at a central position and at least two edge main patterns having the weakness spacing between the central main pattern and the edge main pattern.

[0077] The preset problem pattern is configured so that when the initial pattern 100 is subsequently split, the preset problem pattern can be avoided in the sub-pattern layer, which is correspondingly beneficial to increase the photolithography process window.

[0078] The violation pattern pair consists of a pair of adjacent main patterns 110 with the violation spacing SA. That is, the spacing between the violation pattern pair violates the exposure process tolerance. Therefore, the violation pattern pair must be split into different sub-pattern layers.

[0079] In this embodiment, the first decomposition mark 120 (such as Figure 6 The adjacent main patterns 110 in the illegal pattern pair are marked.

[0080] In existing multi-patterning techniques, splitting is typically performed only on two adjacent main patterns. This allows adjacent main patterns with a spacing less than the lithography resolution limit to be split into different sub-pattern layers. However, within the split sub-pattern layers, the main pattern and other adjacent main patterns may form weak pattern combinations, resulting in a reduced lithography process window and lower lithography imaging quality.

[0081] In this embodiment, by making the preset problem pattern also include the weak pattern combination, the weak pattern combination can be avoided in each sub-pattern layer during the subsequent splitting of the initial pattern 100. Accordingly, when splitting the initial pattern 100, not only is it considered whether the spacing between the two main patterns 110 is greater than the lithography resolution limit, but also the weak pattern combination composed of multiple main patterns 110 with weak point spacing is considered, so as to ensure that in the sub-pattern layer after splitting, the spacing between adjacent main patterns is greater than the resolution limit, and there is no pattern combination that is prone to weak points in the sub-pattern layer, which is beneficial to increasing the lithography process window of the sub-pattern layer and improving the imaging quality of the lithography process.

[0082] The weak point pattern combination is composed of a central main pattern 110 (1) located at the center, and at least two edge main patterns 110 (2) having the weak point spacing between them and the central main pattern 110 (1). Therefore, when the initial pattern 100 is subsequently split, the situation between the central main pattern 110 (1) and the at least two main patterns 110 having the weak point spacing between them is taken into consideration to prevent the central main pattern 110 (1) from forming a weak point pattern combination with other main patterns in the sub-pattern layer obtained after the split.

[0083] In this embodiment, the second decomposition mark 130 (such as Figure 6 The adjacent main graphics 110 in the weakness graphic combination are marked.

[0084] As an example, the weakness spacing includes a first weakness spacing SA within a prohibited period, and the weakness pattern combination includes a central main pattern 110 (1) and at least two edge main patterns 110 (2) having the first weakness spacing SA between the central main pattern 110 (1). When the spacing between adjacent main patterns 110 is within the prohibited period, the resolution and imaging quality of the lithography process are reduced and the process window is small. By making the weak pattern combination include a central main pattern 110 (1) and at least two edge main patterns 110 (2) having the first weak point spacing SA with the central main pattern 110 (1), while splitting the main pattern 110 of each violating pattern pair into different sub-pattern layers, it is also ensured that the weak pattern combination can be avoided in the same sub-pattern layer, preventing the occurrence of a central main pattern and multiple edge main patterns with spacings within the prohibited period with the central main pattern in the sub-pattern layer, and preventing the generation of a hot spot at the position of the central main pattern 110 (1), thereby significantly increasing the lithography process window of the sub-pattern layer. In addition, it can also provide more setting space for setting auxiliary patterns around the main pattern 110, which is conducive to increasing the number of auxiliary patterns that can be set, and correspondingly enhancing the resolution of the lithography process.

[0085] As an example, the weakness pattern combination includes: a central main pattern 110 ( 1 ) and four edge main patterns 110 ( 2 ) having the first weakness interval SA between the central main pattern and the edge main patterns.

[0086] In this embodiment, the edge main pattern 110(2) surrounds the periphery of the central main pattern 110(1), and the edge main pattern 110(2) and the central main pattern 110(1) have the first weak point spacing SB, resulting in that the space around the central main pattern 110(1) is occupied by the edge main pattern 110(2), so that there is not enough space around the central main pattern 110(1) for adding auxiliary patterns, which correspondingly leads to a further reduction in the photolithography process window and a significant deterioration in imaging quality.

[0087] By setting a weak pattern combination consisting of the central main pattern 110 (1) and the four edge main patterns 110 (2), the weak pattern combination can be avoided when the initial pattern 100 is subsequently split, which is conducive to providing more space for setting auxiliary patterns, thereby significantly increasing the lithography process window and improving the imaging quality.

[0088] It should be noted that this embodiment is described by taking as an example a case where the weakness pattern combination includes a central main pattern 110(1) and four edge main patterns 110(2), and a first weakness spacing SB is provided between the edge main patterns 110(2) and the central main pattern 110(1). The types of the weakness pattern combination are not limited to this.

[0089] In other embodiments, according to actual process requirements and applicable scenarios, the number of edge main graphics included in the weakness graphic combination, the shape formed by the connection between the edge main graphics and the center main graphics, and the type of weakness spacing can also be set based on actual conditions.

[0090] For example, the weakness pattern combination includes a central main pattern and three edge main patterns having a second weakness spacing between the central main pattern and the edge main pattern. When the spacing between the edge main patterns and the central main pattern approaches the lithography resolution limit, a combination of a smaller number of main patterns can easily result in a reduction in the lithography process window. Therefore, by setting this type of weakness pattern combination, when the initial pattern is subsequently split to avoid the weakness pattern combination, the lithography process window can also be increased.

[0091] As an example, in the process of configuring the preset question graphic based on the preset question spacing, the preset question graphic may further include: a secondary question graphic pair consisting of a pair of adjacent main graphics having the secondary question spacing.

[0092] Compared to the offending pattern pairs and weak pattern groups, the secondary problematic pattern pairs are given a lower splitting priority when the initial pattern 100 is subsequently split. The multi-patterning splitting algorithm runs a limited number of times. By giving the offending pattern pairs and weak pattern groups a higher splitting priority, these offending pattern pairs and weak pattern groups are avoided first. This, in turn, ensures that the splitting algorithm runs within a limited number of times, shortening the process cycle and improving the efficiency of multi-patterning splitting while significantly expanding the lithography process window.

[0093] refer to Figure 7 Step S4: split the initial graph 100, and the splitting priority (Priority) of the violation graph pair is higher than the splitting priority of the weak graph combination, to obtain multiple sub-graph layers 140.

[0094] The initial graphic 100 is split into multiple sub-graphic layers 140 to produce multiple masks or photomasks. The initial graphic 100 is decomposed into multiple sets of discrete, lower-density graphics to meet the needs of multiple exposures and achieve contraction between technology nodes.

[0095] In this embodiment, the preset problem spacing configured also includes a weak point spacing, and the weak point spacing is greater than the lithography resolution limit. When configuring the preset problem pattern, the preset problem pattern also includes a weak point pattern combination consisting of a central main pattern 110 (1) located at the center, and at least two edge main patterns 110 (2) with the weak point spacing between the central main pattern 110 (1), and in the process of splitting the initial pattern 100, the splitting priority of the violation pattern pair is higher than the splitting priority of the weakness pattern group, thereby ensuring that the main pattern 110 of each violation pattern pair is split into different sub-patterns. At the same time, in the pattern layer 140, the multiple main patterns 110 in the weak pattern combination can be split into at least two sub-pattern layers 140, so that the weak pattern combination can be avoided in the same sub-pattern layer 140. Accordingly, when splitting the initial pattern 100, this embodiment not only considers whether the spacing between the two main patterns 110 is greater than the lithography resolution limit, but also considers the weak pattern combination composed of multiple main patterns 110 with weak point spacing, so as to ensure that in the sub-pattern layer 140 after splitting, the spacing between adjacent main patterns 110 is greater than the resolution limit, and there is no pattern combination that is prone to weak points in the sub-pattern layer 140, which is conducive to increasing the lithography process window of the sub-pattern layer 140 and improving the imaging quality of the lithography process.

[0096] As an example, by making the weak point pattern combination include a central main pattern 110 (1) and at least two edge main patterns 110 (2) having the first weak point spacing SA between them and the central main pattern 110 (1), while splitting the main pattern 110 of each violation pattern pair into different sub-pattern layers, it is also ensured that the weak point pattern combination can be avoided in the same sub-pattern layer, thereby preventing the occurrence of a central main pattern and multiple edge main patterns with spacings within a prohibited period between them and the central main pattern in the sub-pattern layer, and preventing the generation of a hot spot at the position of the central main pattern 110 (1), thereby significantly increasing the lithography process window of the sub-pattern layer 140, and providing more setting space for setting auxiliary patterns around the main pattern 110, thereby increasing the number of auxiliary patterns that can be set, and correspondingly enhancing the resolution of the lithography process.

[0097] In this embodiment, the process window and imaging quality of the photolithography process are increased, which is correspondingly beneficial to improving the matching degree between the pattern formed on the wafer and the target pattern.

[0098] In one embodiment, the main pattern 110 is used to form a conductive via. The conductive via provides a spatial location for forming a conductive plug, which is used to electrically connect metal lines in the adjacent lower layer and the adjacent upper layer. This embodiment increases the process window and imaging quality of the photolithography process, which in turn helps improve the matching between the conductive via and the target pattern, thereby improving the pattern quality of the conductive plug. This makes it less likely that the conductive plug will bridge with adjacent conductive plugs, thereby ensuring electrical isolation between the conductive plugs and, in turn, ensuring that the electrical connectivity of the circuit meets design requirements.

[0099] In this embodiment, splitting the initial pattern includes splitting the main pattern 110 of each illegal pattern pair into different sub-pattern layers 140 , and splitting the main patterns 110 in each weak pattern combination into at least two different sub-pattern layers 140 .

[0100] In which, the multiple main graphics 110 in each of the weakness graphic combinations are split into at least two different sub-graphic layers 140, thereby interrupting at least one of the second decomposition marks 130 in the weakness graphic combination. Accordingly, when the number of sub-graphic layers 140 obtained by splitting is limited, the weakness graphic combination is avoided.

[0101] In this embodiment, the priority of splitting the violation graphic pair is higher than the priority of splitting the weakness graphic combination, which means that the importance of splitting the violation graphic pair is higher than the importance of splitting the weakness graphic combination, the violation graphic pair is split first, and when splitting the weakness graphic group, no violation graphic pair can exist.

[0102] As an example, the priority of the violation pattern pair is set to 0, and the priority of the weak pattern combination is set to 0.5.

[0103] Specifically, during multi-pattern splitting, there are multiple splitting methods to split the main pattern 110 of the offending pattern pair into different sub-pattern layers 140. In this embodiment, one of these splitting methods is selected to ensure that the multiple main patterns 110 in the weak pattern combination are split into at least two different sub-pattern layers 140, while also ensuring that the main patterns 110 of the offending pattern pair are split into different sub-pattern layers 140.

[0104] As an example, during the splitting process of the initial graph 100, the splitting priority of the secondary problem graph pair is lower than the splitting priority of the weak point graph combination. As an embodiment, the priority of the secondary problem graph pair can be set to a positive integer greater than or equal to 1.

[0105] The multiple patterning splitting algorithm is run a limited number of times. By giving the splitting priority of violating pattern pairs and weak pattern groups a higher priority, it is ensured that the violating pattern pairs and weak pattern groups can be avoided first, thereby ensuring that the splitting algorithm is not run too many times, thereby shortening the process cycle, improving the efficiency of multiple patterning splitting, and significantly increasing the lithography process window.

[0106] As an example, during the process of splitting the initial pattern 100, the number of sub-pattern layers 140 is 2 to 5. The sub-pattern layers 140 are used to make masks, which are relatively expensive. By setting the number of sub-pattern layers 140 to 2 to 5, the illegal pattern pairs and weak pattern combinations are avoided in the sub-pattern layers, thereby increasing the lithography process window while keeping the process cost low.

[0107] Specifically, in this embodiment, the initial graphic 100 is split into three sub-graphic layers 140 (1), 140 (2), and 140 (3). Correspondingly, the main graphic 110 in the weak graphic combination is split into the three sub-graphic layers 140 (1), 140 (2), and 140 (3).

[0108] Accordingly, in this embodiment, triple patterning (or triple exposure) is performed during the semiconductor process.

[0109] In other embodiments, based on actual process requirements and cost requirements, the initial graphic may be split into other numbers of sub-graphic layers, which is not limited in this embodiment.

[0110] Correspondingly, the present invention also provides a graphic design system. Figure 8 It is a functional block diagram of an embodiment of the graphic design system of the present invention.

[0111] like Figure 8 As shown, in this embodiment, the graphic design system 20 includes: a providing unit 201, used to provide an initial graphic, including multiple main graphics; defining the distance between adjacent main graphics as a spacing; a problem graphic configuration unit 202, used to set a preset problem spacing, including a violation spacing and a weakness spacing, the violation spacing is smaller than the lithography resolution limit, and the weakness spacing is larger than the lithography resolution limit; and further used to configure a preset problem graphic based on the preset problem spacing, including: a violation graphic pair consisting of a pair of adjacent main graphics with the violation spacing, and a weakness graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the weakness spacing between the central main graphic and the edge main graphics, to obtain multiple sub-graphic layers.

[0112] The providing unit 201 is configured to provide an initial graphic.

[0113] The initial pattern is an initial design pattern (design layout pattern) to be subjected to multiple pattern splitting. In the initial pattern, a plurality of main patterns are arranged at intervals.

[0114] As an example, the main pattern is a rectangular pattern. The design pattern includes a plurality of rectangular patterns, which is friendly to the mask manufacturing process and optical proximity effect correction, and the result is controllable.

[0115] As an embodiment, the main pattern is used to form a conductive via. During the semiconductor manufacturing process, the conductive via is used to provide a space for forming a conductive plug, which is used to electrically connect the metal lines of the adjacent next layer and the adjacent previous layer.

[0116] In the semiconductor field, the probability of a conductive via pattern being split is high. Splitting a plurality of main patterns 110 for forming conductive vias is beneficial for significantly increasing the process window.

[0117] In other embodiments, based on actual process requirements, the main pattern may also be used to form other patterns such as contact holes or metal lines.

[0118] The problem pattern configuration unit 202 is used to set a preset problem spacing, including a violation spacing and a weak point spacing, wherein the violation spacing is smaller than a lithography resolution limit (Resolution Limit), and the weak point spacing is larger than the lithography resolution limit.

[0119] The preset problem spacing is a preset spacing type that has the risk of violating design rules or reducing the photolithography process window. By setting the preset problem spacing, a preset problem graphic combination can be configured based on the preset problem spacing.

[0120] The violation pitch is smaller than the photolithography resolution limit, so that adjacent main patterns with the violation pitch violate the exposure process tolerance. Accordingly, adjacent main patterns with the violation pitch need to be split into different sub-pattern layers.

[0121] It should be noted that the photolithography resolution limit refers to the minimum spacing between patterns that can be distinguished during the exposure process during the photolithography process.

[0122] Accordingly, in a specific process, the photolithography resolution is determined based on actual photolithography process equipment and process conditions, and the specific value of the photolithography resolution limit is not limited in this embodiment.

[0123] The weak point spacing is greater than the photolithography resolution limit, and the weak point spacing is a preset spacing type that easily causes a reduction in the photolithography process window.

[0124] As an example, the weak point spacing includes a first weak point spacing within a forbidden period (Forbidden Pitch).

[0125] The forbidden period is larger than the lithography resolution limit. However, when the spacing between adjacent patterns falls within the forbidden period (or forbidden spacing), the lithography process image quality deteriorates significantly, the lithography process window shrinks, and the error factor (MEEF) between the mask pattern and the wafer pattern increases. By including the first weak point spacing within the forbidden period in the preset problem spacing, subsequent configuration of the preset problem pattern based on the preset problem spacing can take into account pattern combinations with spacing within the forbidden period, further improving the lithography process window.

[0126] The forbidden period is related to the size between the main patterns and the spacing between adjacent main patterns. Under different process conditions and in different optical devices, the corresponding forbidden period is also different. Therefore, this embodiment does not limit the specific value of the first weak point spacing SB.

[0127] It should be noted that, in an actual process, the weak point spacing may further include a second weak point spacing (not shown) that is close to the photolithography resolution limit.

[0128] Here, close to the lithography resolution limit means that it is greater than the lithography resolution limit, but the difference between it and the lithography resolution limit is very small.

[0129] In the semiconductor field, even if the spacing between adjacent main patterns exceeds the lithography resolution limit, if the spacing is only slightly greater than the lithography resolution limit or the difference between the spacing and the lithography resolution limit is extremely small, there is still a risk of reducing the lithography process window. Therefore, by including the weak point spacing in the second weak point spacing, more situations that can easily reduce the lithography process window can be considered, thereby expanding the lithography process window of the sub-pattern layer when the initial pattern is split.

[0130] As an example, the second weak point spacing is greater than the photolithography resolution limit and less than or equal to 103% of the photolithography resolution limit.

[0131] It should be noted that the numerical relationship between the second weak point spacing and the photolithography resolution limit in this embodiment is only an example. In actual processes, the numerical range of the second weak point spacing can be reasonably set according to specific process requirements.

[0132] It should also be noted that the above description uses the weak point spacing including the first weak point spacing and the second weak point spacing as an example, and the spacing types included in the weak point spacing are not limited to this. In actual processes, those skilled in the art can set different weak point spacing types based on actual needs.

[0133] As an example, in the process of setting the preset problem spacing, the preset problem spacing may further include a secondary problem spacing (not shown), where the secondary problem spacing is greater than the photolithography resolution limit.

[0134] The minor problem spacing may be the same as or different from the weak point spacing. Compared with the violation spacing and the weak point spacing, the splitting priority of the minor problem graph pair configured based on the minor problem spacing is lower.

[0135] Specifically, as an embodiment, the secondary problem spacing can be set to 110%, 120%, 130%, etc. of the lithography resolution limit, so that the main graphic 110 can be evenly split into different sub-graphic layers, preventing the appearance of multiple main graphics 110 with high density and close distance in a single sub-graphic layer.

[0136] In other embodiments, based on actual needs, the preset question interval may not include the secondary question interval.

[0137] The problem graphic configuration unit 202 is further configured to configure a preset problem graphic based on the preset problem spacing, including: a violation graphic pair consisting of a pair of adjacent main graphics with the violation spacing, and a weakness graphic combination consisting of a central main graphic located at a central position and at least two edge main graphics with the central main graphic having the weakness spacing between the central main graphic and the edge main graphics.

[0138] The problem pattern configuration unit 202 configures a preset problem pattern so that the preset problem pattern can be avoided when the initial pattern is subsequently split, which is helpful to increase the photolithography process window accordingly.

[0139] The violation pattern pair consists of a pair of adjacent main patterns with the violation spacing SA. That is, the spacing between the violation pattern pair violates the exposure process tolerance. Therefore, the violation pattern pair must be split into different sub-pattern layers.

[0140] During multi-patterning, splitting is typically performed based on only two adjacent main patterns. This allows adjacent main patterns with a spacing less than the lithography resolution limit to be split into different sub-pattern layers. However, within the split sub-pattern layers, the main pattern and other adjacent main patterns may form weak pattern combinations, reducing the lithography process window and degrading the imaging quality of the lithography process.

[0141] In this embodiment, by making the preset problem pattern also include the weak pattern combination, the weak pattern combination can be avoided in each sub-pattern layer during the subsequent splitting of the initial pattern. Accordingly, when splitting the initial pattern, not only is it considered whether the spacing between the two main patterns is greater than the lithography resolution limit, but also the weak pattern combination composed of multiple main patterns with weak point spacing is considered, so as to ensure that in the sub-pattern layer after splitting, the spacing between adjacent main patterns is greater than the resolution limit, and there is no pattern combination that is prone to weak points in the sub-pattern layer, which is beneficial to increasing the lithography process window of the sub-pattern layer and improving the imaging quality of the lithography process.

[0142] The weak point pattern combination consists of a central main pattern located at the center and at least two edge main patterns separated from the central main pattern by the weak point spacing. Therefore, when the initial pattern is subsequently split, the relationship between the central main pattern and the at least two other main patterns separated by the weak point spacing is considered to prevent the formation of a weak point pattern combination between the central main pattern and other main patterns in the resulting sub-pattern layers.

[0143] As an example, the weak point spacing includes a first weak point spacing within a prohibited period, and the weak point pattern combination includes a central main pattern and at least two edge main patterns with the first weak point spacing from the central main pattern. When the spacing between adjacent main patterns is within the prohibited period, the resolution and imaging quality of the lithography process are reduced, and the process window is narrowed. By ensuring that the weak point pattern combination includes a central main pattern and at least two edge main patterns with the first weak point spacing from the central main pattern, the main pattern of each violating pattern pair is split into different sub-pattern layers while also avoiding the weak point pattern combination within the same sub-pattern layer. This prevents the occurrence of a central main pattern and multiple edge main patterns with spacings from the central main pattern within the prohibited period within the sub-pattern layer, and prevents the generation of hot spots at the location of the central main pattern. This significantly increases the lithography process window of the sub-pattern layer, and further provides more space for auxiliary patterns to be arranged around the main pattern, thereby increasing the number of auxiliary patterns that can be arranged and correspondingly enhancing the resolution of the lithography process.

[0144] As an example, the weakness pattern combination includes: a central main pattern and four edge main patterns with the first weakness interval SA between the central main pattern and the edge main patterns.

[0145] In this embodiment, the edge main pattern surrounds the periphery of the central main pattern, and the edge main pattern and the central main pattern have the first weak point spacing, resulting in the space around the central main pattern being occupied by the edge main pattern. As a result, there is insufficient space around the central main pattern for adding auxiliary patterns, which correspondingly leads to a further reduction in the lithography process window and a significant deterioration in imaging quality.

[0146] By setting a weak pattern combination consisting of the central main pattern and four edge main patterns, the weak pattern combination can be avoided when the initial pattern is subsequently split, which is correspondingly beneficial for providing more space for setting auxiliary patterns, thereby significantly increasing the lithography process window and improving imaging quality.

[0147] It should be noted that this embodiment is described by taking as an example the case where the weakness pattern combination includes a central main pattern and four edge main patterns, and a first weakness distance exists between the edge main patterns and the central main pattern.

[0148] In other embodiments, according to actual process requirements and applicable scenarios, the number of edge main graphics included in the weakness graphic combination, the shape formed by the connection between the edge main graphics and the center main graphics, and the type of weakness spacing can also be set based on actual conditions.

[0149] For example, the weakness pattern combination includes a central main pattern and three edge main patterns having a second weakness spacing between the central main pattern and the edge main pattern. When the spacing between the edge main patterns and the central main pattern approaches the lithography resolution limit, a combination of a smaller number of main patterns can easily result in a reduction in the lithography process window. Therefore, by setting this type of weakness pattern combination, when the initial pattern is subsequently split to avoid the weakness pattern combination, the lithography process window can also be increased.

[0150] As an example, in the process of configuring the preset question graphic based on the preset question spacing, the preset question graphic may further include: a secondary question graphic pair consisting of a pair of adjacent main graphics having the secondary question spacing.

[0151] When splitting the initial pattern, secondary problematic pattern pairs are given a lower splitting priority than those for violating pattern pairs and weak pattern groups. The multi-patterning splitting algorithm runs a limited number of times. By giving violating pattern pairs and weak pattern groups a higher splitting priority, these pairs are avoided first. This ensures that the splitting algorithm runs within a limited number of times while significantly expanding the lithography process window.

[0152] The graphic splitting unit 203 is used to split the initial graphic, and the splitting priority of the violation graphic pair is higher than the splitting priority of the weak graphic combination, to obtain multiple sub-graphic layers.

[0153] The initial graphic is split into multiple sub-graphic layers to produce multiple masks or photomasks, and the initial graphic is decomposed into multiple sets of discrete, lower-density graphics to meet the needs of multiple exposures and achieve contraction between technology nodes.

[0154] In this embodiment, the preset problem spacing configured by the problem pattern configuration unit 202 also includes a weak point spacing, and the weak point spacing is greater than the lithography resolution limit. When configuring the preset problem pattern, the preset problem pattern also includes a weak point pattern combination consisting of a central main pattern located at a central position and at least two edge main patterns with the central main pattern having the weak point spacing therebetween. In addition, in the process of splitting the initial pattern, the splitting priority of the violation pattern pair is higher than the splitting priority of the weak point pattern group, thereby ensuring that while the main pattern of each violation pattern pair is split into different sub-pattern layers, multiple main patterns in the weak point pattern combination can be split into at least two sub-pattern layers, so that the weak point pattern combination can be avoided in the same sub-pattern layer. Accordingly, when splitting the initial pattern, this embodiment not only considers whether the spacing between the two main patterns is greater than the lithography resolution limit, but also considers the weak point pattern combination consisting of multiple main patterns with the weak point spacing, so as to ensure that in the sub-pattern layer after splitting, the spacing between adjacent main patterns is greater than the resolution limit, and there is no weak point (Weak Point) in the sub-pattern layer. The pattern combination of the sub-pattern layer and the sub-pattern layer is beneficial to enlarging the photolithography process window of the sub-pattern layer and improving the imaging quality of the photolithography process.

[0155] As an example, by making the weakness pattern combination include a central main pattern and at least two edge main patterns with the first weakness distance between the central main pattern and the edge main patterns, while splitting the main patterns of each violation pattern pair into different sub-pattern layers, it is also ensured that the weakness pattern combination can be avoided in the same sub-pattern layer, thereby preventing the occurrence of a central main pattern and multiple edge main patterns with a distance from the central main pattern within a prohibited period in the sub-pattern layer, and preventing the generation of a bad spot (hot spot) at the position of the central main pattern, which is beneficial to significantly increase the lithography process window of the sub-pattern layer. Moreover, it can also provide more setting space for setting auxiliary patterns around the main pattern, which is beneficial to increase the number of auxiliary patterns that can be set, and correspondingly enhance the resolution of the lithography process.

[0156] In this embodiment, the process window and imaging quality of the photolithography process are increased, which is correspondingly beneficial to improving the matching degree between the pattern formed on the wafer and the target pattern.

[0157] In one embodiment, the main pattern is used to form a conductive via, which provides a spatial location for forming a conductive plug. The conductive plug is used to electrically connect metal lines in the adjacent lower layer and the adjacent upper layer. This embodiment increases the process window and imaging quality of the photolithography process, which in turn helps improve the matching between the conductive via and the target pattern, thereby improving the pattern quality of the conductive plug. This makes it less likely that the conductive plug will bridge with adjacent conductive plugs, thereby ensuring electrical isolation between the conductive plugs.

[0158] In this embodiment, splitting the initial graphics includes splitting the main graphics of each of the violation graphics pairs into different sub-graphic layers, and splitting the multiple main graphics in each of the weak graphics combination into at least two different sub-graphic layers.

[0159] Among them, multiple main graphics in each of the weakness graphic combinations are split into at least two different sub-graphic layers, thereby interrupting at least one of the second decomposition marks in the weakness graphic combination. Accordingly, when the number of split sub-graphic layers is limited, the weakness graphic combination is avoided.

[0160] In this embodiment, the priority of splitting the violation graphic pair is higher than the priority of splitting the weakness graphic combination, which means that the importance of splitting the violation graphic pair is higher than the importance of splitting the weakness graphic combination, and when splitting the weakness graphic group, no violation graphic pair can exist.

[0161] As an example, the priority of the violation pattern pair is set to 0, and the priority of the weak pattern combination is set to 0.5.

[0162] Specifically, during multi-pattern splitting, there are multiple splitting methods to split the main graphics of the offending graphic pair into different sub-graphic layers. In this embodiment, one of these splitting methods is selected to ensure that the multiple main graphics in the weak graphic combination are split into at least two different sub-graphic layers, and the main graphics of the offending graphic pair are also split into different sub-graphic layers.

[0163] As an example, the graphic splitting unit 203 has a lower splitting priority for the secondary problem graphic pair than for the weak graphic combination.

[0164] The multiple pattern splitting algorithm is run a limited number of times. By giving the splitting priority of violating pattern pairs and weak pattern groups a higher priority, it is ensured that the violating pattern pairs and weak pattern groups can be avoided first, thereby ensuring that the splitting algorithm is not run too many times while also significantly increasing the lithography process window.

[0165] As an example, the pattern splitting unit 203 splits the initial pattern into 2 to 5 sub-pattern layers. The sub-pattern layers are used to make masks (or photomasks), which are relatively expensive. By setting the number of sub-pattern layers to 5, it is ensured that while avoiding illegal pattern pairs and weak pattern combinations to expand the lithography process window, the process cost is not too high.

[0166] Specifically, the initial graphic is split into three sub-graphic layers, and correspondingly, the main graphic in the weakness graphic combination is split into the three sub-graphic layers.

[0167] Accordingly, triple patterning (or triple exposure) is performed during the semiconductor process.

[0168] In other embodiments, based on actual process requirements and cost requirements, the initial graphic may be split into other numbers of sub-graphic layers, which is not limited in this embodiment.

[0169] Correspondingly, the present invention further provides a mask assembly, comprising a plurality of masks, each of which has a corresponding sub-pattern layer, and the sub-pattern layer is formed using the aforementioned pattern design method.

[0170] It can be seen from the above records that by utilizing the graphic design method provided in the embodiment of the present invention, the weak graphic combination can be avoided in the same sub-graphic layer to ensure that in the sub-graphic layer after splitting, the spacing between adjacent main graphics is greater than the resolution limit, and there is no graphic combination that is prone to produce weak points (Weak points) in the sub-graphic layer, which is beneficial to increasing the lithography process window of the sub-graphic layer and improving the imaging quality of the lithography process.

[0171] In an optional solution, the weak point spacing includes a first weak point spacing within a prohibited period. When the spacing between adjacent main patterns is within the prohibited period, the resolution and imaging quality of the lithography process are reduced and the process window is small. By making the weak point spacing include the first weak point spacing, while the main patterns of each violating pattern pair are split into different sub-pattern layers, it is also ensured that the weak point pattern combination can be avoided in the same sub-pattern layer, thereby preventing the occurrence of a central main pattern and multiple edge main patterns with a spacing within the prohibited period between the central main pattern and the sub-pattern layer, and preventing the generation of a bad spot (hot spot) at the position of the central main pattern, which is beneficial to significantly increase the lithography process window of the sub-pattern layer. Moreover, it can also provide more setting space for setting auxiliary patterns around the main pattern, which is beneficial to increase the number of auxiliary patterns that can be set, and correspondingly enhance the resolution of the lithography process.

[0172] As an example, the mask combination includes 2 to 5 masks.

[0173] In other embodiments, the number of reticles in the mask combination may be other numbers.

[0174] An embodiment of the present invention further provides a device, which can implement the graphic design method provided by the embodiment of the present invention by loading the above-mentioned graphic design method in the form of a program.

[0175] An optional hardware structure of the terminal device provided by the embodiment of the present invention can be as follows Figure 9 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0176] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other through the communication bus 04. The communication interface 02 can be an interface of a communication module for network communication, such as an interface of a GSM module. The processor 01 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0177] The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the graphic design method provided by the embodiment of the present invention.

[0178] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic design method provided by the embodiment of the present invention.

[0179] The embodiments of the present invention may be implemented by various means such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0180] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. Software codes may be stored in a memory unit and executed by a processor. The memory unit may be located inside or outside the processor and may send and receive data to and from the processor via various known means.

[0181] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A graphic design method, characterized in that: include: Provide initial graphics, including multiple main graphics; define the distance between adjacent main graphics as spacing; Setting a preset problem spacing, including a violation spacing and a weak point spacing, wherein the violation spacing is smaller than the lithography resolution limit, and the weak point spacing is larger than the lithography resolution limit, wherein the lithography resolution limit indicates the minimum spacing between patterns that can be distinguished during the exposure process during the lithography process; Based on the preset problem spacing, a preset problem pattern is configured, comprising: a violation pattern pair consisting of a pair of adjacent main patterns having the violation spacing, and a weakness pattern combination consisting of a central main pattern located at a central position and at least two edge main patterns having the weakness spacing between the central main pattern and the edge main pattern; The initial graphic is split, and the splitting priority of the violation graphic pair is higher than the splitting priority of the weak graphic combination, to obtain multiple sub-graphic layers.

2. The graphic design method according to claim 1, wherein: The weak point spacing includes a first weak point spacing within a prohibited period.

3. The graphic design method according to claim 2, wherein: The weakness pattern combination includes a central main pattern and four edge main patterns with the first weakness distance between the edge main patterns and the central main pattern.

4. The graphic design method according to claim 1, wherein: The weak point spacing includes a second weak point spacing; the second weak point spacing is greater than the photolithography resolution limit and less than or equal to 103% of the photolithography resolution limit.

5. The graphic design method according to claim 1, wherein: In the process of setting the preset problem spacing, the preset problem spacing also includes a secondary problem spacing, and the secondary problem spacing is greater than the photolithography resolution limit; In the process of configuring the preset question graphics based on the preset question spacing, the preset question graphics further include: a secondary question graphic pair consisting of a pair of adjacent primary graphics having the secondary question spacing; In the process of splitting the initial graph, the splitting priority of the secondary problem graph pair is lower than the splitting priority of the weak point graph combination.

6. The graphic design method according to claim 1, wherein: Splitting the initial graphics includes splitting the main graphics of each of the violation graphics pairs into different sub-graphic layers, and splitting the multiple main graphics in each of the weak graphics combination into at least two different sub-graphic layers.

7. The graphic design method according to claim 1, wherein: The main graphic is a rectangular graphic.

8. The graphic design method according to claim 1, wherein: The main pattern is used to form a conductive through hole, a contact hole or a metal line.

9. The graphic design method according to claim 1, wherein: In the process of splitting the initial graphic, the number of the sub-graphic layers is 2 to 5.

10. A graphic design system, characterized in that: include: A unit is provided for providing an initial graphic, including a plurality of main graphics; and a distance between adjacent main graphics is defined as a spacing; a problem pattern configuration unit, configured to set a preset problem spacing, including a violation spacing and a weak point spacing, wherein the violation spacing is smaller than a photolithography resolution limit, and the weak point spacing is larger than the photolithography resolution limit; The method is further configured to configure preset problem patterns based on the preset problem spacing, including: a violation pattern pair consisting of a pair of adjacent main patterns having the violation spacing, and a weak point pattern combination consisting of a central main pattern located at a central position and at least two edge main patterns having the weak point spacing between the central main pattern and the edge main pattern; the lithography resolution limit represents the minimum spacing between patterns that can be distinguished during the exposure process during the lithography process; The graphic splitting unit is used to split the initial graphic, and the splitting priority of the violation graphic pair is higher than the splitting priority of the weak graphic combination, so as to obtain multiple sub-graphic layers.

11. A mask assembly, characterized in that: The invention comprises a plurality of mask plates, each of the mask plates has a corresponding sub-pattern layer, and the sub-pattern layer is formed by using the pattern design method according to any one of claims 1 to 9.

12. A device, characterized in that The system comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the graphic design method according to any one of claims 1 to 9.

13. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic design method according to any one of claims 1 to 9.

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