Reference current source

Abstract

A reference current source is provided. A reference current source (SCS) includes: a reference current path (P0) including a first transistor (M1), a second transistor (M2), and a first resistor (R1) connected in series between a first fixed potential (VDD) and a second fixed potential (GND), the first transistor (M1) and the second transistor (M2) being diode-connected transistors; a first output current path (P1) including a third transistor (M3) having a gate connected to a gate of the second transistor (M2) and constituting a current mirror with the second transistor (M2), and a second resistor (R2) between the third transistor (M3) and the first fixed potential (VDD); and a second output current path (P2) including a voltage-current conversion circuit (40) supplied with a potential of a third node (N3) between the third transistor (M3) and the second resistor (R2) in the first output current path (P1) and flowing a reference current (Is).

Description

Technical Field

[0001] This disclosure relates to a reference current source. Background Technology

[0002] Reference current sources are used in integrated circuits (ICs). A reference current source can generate one or more reference currents. A current mirror is used to supply the reference current to multiple circuits within the semiconductor chip. The reference current can be used to determine the operating point of each circuit within the IC. The reference current source preferably has a structure that is not easily affected by variations in PVT (process / voltage / temperature).

[0003] Non-Patent Document 1 discloses a current source utilizing a Band-Gap Reference (BGR), that is, a current source utilizing the band gap of a semiconductor. This current source has high tolerance to variations such as temperature. In principle, a bipolar transistor is used in the BGR method. When a semiconductor chip includes bipolar transistors in addition to complementary metal-oxide-semiconductor (CMOS) circuitry, the manufacturing cost of the semiconductor chip increases.

[0004] Non-patent document 2 discloses a β-multiplier reference circuit (BMR). Conventional reference current sources can generate a reference current with practical stability even when the power supply potential changes. However, in its theoretical circuit configuration, the BMR cannot compensate for temperature characteristics.

[0005] Non-Patent Document 3 discloses a Widlar current source (a BMR circuit with CMOS circuitry) having multiple field-effect transistors. Complex circuitry is required for temperature compensation.

[0006] Patent document 1 discloses a reference current source equipped with a current mirror. It is believed that this reference current source requires a startup circuit.

[0007] Existing technical documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2002-244748

[0009] Non-patent literature 1: Behzad Razavi, “The Bandgap Reference,” IEEE Solid-State Circuit Magazine, Vol. 8, Issue 3, pp. 9-12, Summer 2016.

[0010] Non-patent literature 2: R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation, Fourth Edition,” John Wiley & Sons, Chapter 23, July 2019.

[0011] Non-patent document 3: Yen-Ting Wang, Degang Chen, Randall L.Geiger, "A CMOSSupply-Insensitive with 13ppm / ℃Temperature Coefficient Current Reference," 2014IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), pp.475-478, August 2014). Summary of the Invention

[0012] However, as semiconductor structures are miniaturized, the power supply voltage variation rejection ratio (hereinafter referred to as PSRR) of the reference current supplied to internal circuits decreases. Therefore, a reference current source capable of stably supplying a reference current with a simple structure is needed.

[0013] The first reference current source comprises: a reference current path including a first transistor, a second transistor, and a first resistor connected in series between a first fixed potential and a second fixed potential, wherein the first transistor and the second transistor are both diode-connected transistors; a first output current path including a third transistor and a second resistor between the third transistor and the first fixed potential, wherein the third transistor has a gate connected to the gate of the second transistor and together with the second transistor forms a current mirror; and a second output current path including a voltage-to-current conversion circuit, wherein the voltage-to-current conversion circuit is provided with the potential of the node between the third transistor and the second resistor in the first output current path, and a reference current flows through the voltage-to-current conversion circuit.

[0014] In the second reference current source, the size of the second transistor is larger than the size of the third transistor.

[0015] In the third reference current source, the second transistor consists of N transistors, where 1 ≤ N.

[0016] The third transistor is composed of M transistors, where 1 ≤ M. The total gate width of the N transistors constituting the second transistor is K times the total gate width of the M transistors constituting the third transistor, where 1 < K.

[0017] In the fourth reference current source, the voltage-to-current conversion circuit includes: a fourth transistor having a gate connected to the node; and an output resistor connected between the fourth transistor and the second fixed potential.

[0018] In the fifth reference current source, the fourth transistor is larger than the first transistor.

[0019] In the sixth reference current source, the gate length of one transistor constituting the third transistor is less than 100 nm and more than 5 nm.

[0020] The reference current source according to the present invention can improve the stability of the reference current. Attached Figure Description

[0021] Figure 1 This is the circuit diagram of the reference current source for the comparative example.

[0022] Figure 2 This is a circuit diagram illustrating the reference current source used in the implementation method.

[0023] Figure 3 This is a circuit diagram of multiple identical transistors connected in parallel, forming the reference current source SCS for each transistor M2, M4, and M5.

[0024] Figure 4 It is a graph showing the relationship between the first fixed potential VDD (V) and the reference current Is (μA).

[0025] Figure 5 It is a graph showing the relationship between the gate-source voltage Vgs (mV) and the drain current Id (μA) of a transistor.

[0026] Figure 6 It is a graph showing the relationship between the first fixed potential VDD (V) and the reference current Ia (μA) and the first output current Ib (μA).

[0027] Figure 7 It is a conceptual graph that shows the relationship between the voltage V supplied to a circuit element and the current I.

[0028] Figure 8 It is a circuit diagram of a device that includes a circuit that draws a reference current Is from a reference current source SCS.

[0029] Figure 9 This is a circuit diagram of a reference current source in another embodiment. Detailed Implementation

[0030] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. Furthermore, in each drawing, the same or equivalent parts are labeled with the same reference numerals, and repeated descriptions are omitted.

[0031] Figure 1 This is the circuit diagram of the reference current source for the comparative example.

[0032] Figure 1 The reference current source shown is a β-multiplier reference circuit (BMR) with CMOS circuitry (Widlar current mirror current source). This reference current source includes a first upstream transistor M11, a second upstream transistor M12, a first downstream transistor M21, and a second downstream transistor M22. Furthermore, the transistors shown in the figures are metal-oxide-semiconductor (MOS) field-effect transistors.

[0033] The first upstream transistor M11 is a P-type MOS transistor, with its source connected to a first fixed potential VDD. The first downstream transistor M21 is an N-type MOS transistor, with its drain connected to the drain of the first upstream transistor M11 and its source connected to a second fixed potential GND. The gate and drain of the first downstream transistor M21 are connected, thus forming a diode-connected transistor.

[0034] The second upstream transistor M12 is a P-type MOS transistor, with its source connected to the first fixed potential VDD. The second downstream transistor M22 is an N-type MOS transistor, with its drain connected to the drain of the second upstream transistor M12, and its source connected to the second fixed potential GND via a resistor R. The gate and drain of the second upstream transistor M12 are connected, thus forming a diode-connected transistor.

[0035] The gate of the first upstream transistor M11 is connected to the gate of the second upstream transistor M12, and these transistor pairs form the upper current mirror. The gate of the first downstream transistor M21 is connected to the gate of the second downstream transistor M22, and these transistor pairs, together with the resistor R, form the lower current mirror. Furthermore, in the Widlar current source, the resistor R is not connected to the first downstream transistor M21, but is connected to the second downstream transistor M22 (which is not connected to a diode).

[0036] Here, the gate width W21 of the first downstream transistor M21 and the gate width W22 of the second downstream transistor M22 have a relationship of W22 = K × W21. Furthermore, K > 1, and the size of the second downstream transistor M22 is larger than the size of the first downstream transistor M21. The transistor gain coefficient β is given by β = μ × C. OX×(W / L) is given. Additionally, μ represents the carrier mobility, and C... OX Let W represent the capacitance per unit area of ​​the gate oxide, W represent the gate width, and L represent the gate length. If all the illustrated transistors have the same gate length L, then the value of the gain coefficient β, or (W / L), is proportional to the gate width W. The second downstream transistor M22 has a gain coefficient β that is K times that of the first downstream transistor M21. The gain coefficient β is proportional to the width of the channel through which charge carriers flow (gate width W).

[0037] On the other hand, the upstream current mirror carries a first reference current Iref1 and a second reference current Iref2 of the same magnitude in the left and right lines. Therefore, the first reference current Iref1 flowing through the first downstream transistor M21 is equal to the second reference current Iref2 flowing through the second downstream transistor M22.

[0038] Furthermore, to make the drain current Id of the transistor with a large gain coefficient β equal to that of the transistor with a small gain coefficient β, the gate-source voltage Vgs of the transistor with the large gain coefficient β can be reduced. That is, the gate-source voltage Vgs(M22) of the second downstream transistor M22 with a large gain coefficient β is smaller than the gate-source voltage Vgs(M21) of the first downstream transistor M21 with a small gain coefficient β. If the difference between these gate-source voltages is denoted as δVgs, then Vgs(M22) + δVgs = Vgs(M21) satisfies the condition.

[0039] Furthermore, regarding the gate-source voltage Vgs(M21) of the first downstream transistor M21, the gate-source voltage Vgs(M22) of the second downstream transistor M22, and the voltage V(R) between the two ends of the resistor R, according to the voltage rule of the closed loop that includes these circuit elements, Vgs(M21)-Vgs(M22)-V(R)=0.

[0040] Therefore, the voltage applied across resistor R is V(R) = Vgs(M21) - Vgs(M22) = δVgs. Thus, the voltage V(R) = δVgs across resistor R depends on the parameter K representing the transistor's size, but not on the first fixed potential VDD. When the resistance value of resistor R is set to r, the second reference current Iref2 = V(R) / r = δVgs / r. Thus, according to the reference current source of the comparative example, the second reference current Iref2 does not change even if the first fixed potential VDD changes. However, especially when the semiconductor structure is miniaturized, there is room for improvement in the reference current source of the comparative example. That is, the BMR circuit cannot compensate for temperature dependence alone. Furthermore, due to miniaturization, the Early voltage decreases, and the reference current becomes more dependent on the supply voltage (first fixed potential VDD). Additionally, the PSRR of the reference current supplied to the internal circuitry decreases. Therefore, a reference current source that can stably supply reference current with a simple structure, even when the power supply potential and temperature change, is required.

[0041] Figure 2 This is a circuit diagram of the reference current source according to the embodiment. The reference current source SCS according to the embodiment has the following structure.

[0042] First, in the reference current source SCS, not only is the variation of the reference current Is relative to changes in the power supply potential (or ground potential) suppressed, but the variation of the reference current relative to temperature changes is also small, and it has a simple construction. The comparative example's reference current source uses a BMR circuit to suppress the variation of the second reference current Iref2 relative to changes in the power supply potential, but the BMR circuit alone is highly temperature-dependent. In the comparative example's reference current source, the second reference current Iref2 varies significantly with temperature changes. In the comparative example's reference current source, to reduce temperature dependence, it is considered necessary to add a temperature compensation circuit with a complex structure. On the other hand, the reference current source SCS according to the embodiment can perform temperature compensation with a simple construction.

[0043] Second, the reference current source SCS has a structure that allows it to operate even without a startup circuit. That is, in the reference current source of the comparative example, a steady state exists even when the second reference current Iref2 = 0, so a startup circuit is required to exit this steady state. On the other hand, the reference current source of the embodiment operates even without a startup circuit.

[0044] The reference current source SCS involved in the implementation method will be described in detail below.

[0045] The reference current source SCS involved in the implementation has a reference current path P0, a first output current path P1, and a second output current path P2 between a power supply line providing a first fixed potential VDD and a ground line providing a second fixed potential GND.

[0046] The reference current path P0 includes a first transistor M1, a second transistor M2, and a first resistor R1 connected in series between a first fixed potential VDD and a second fixed potential GND. Furthermore, the reference current path P0 includes a third resistor R3 connected between the first fixed potential VDD and the first transistor M1. Additionally, the positions of the third resistor R3 and the first transistor M1 can be interchanged.

[0047] The third resistor R3 is located between the first fixed potential VDD and the drain of the first transistor M1. The first transistor M1 is an N-type MOS transistor, with its drain connected to the third resistor R3 and its source connected to the drain of the second transistor M2. The gate and drain of the first transistor M1 are connected, forming a diode-connected transistor. Alternatively, the first transistor M1 can also be a diode-connected P-type MOS transistor, in which case its source is connected to the third resistor R3. When the positions of the third resistor R3 and the first transistor M1 are interchanged, and the first transistor M1 is a diode-connected P-type MOS transistor, the source of the first transistor M1 is connected to the first fixed potential VDD, and its drain and gate are connected to the third resistor R3.

[0048] The second transistor M2 is an N-type MOS transistor, with its drain connected to the source of the first transistor M1, and its source connected to the first resistor R1. The gate and drain of the second transistor M2 are connected, forming a diode-connected transistor. The first resistor R1 is connected between the source of the second transistor M2 and the second fixed potential GND.

[0049] The first output current path P1 includes a second resistor R2 and a third transistor M3 connected in series between the first fixed potential VDD and the second fixed potential GND.

[0050] The second resistor R2 is located between the first fixed potential VDD and the drain of the third transistor M3. The third transistor M3 has a gate connected to the gate of the second transistor M2, forming a current mirror together with the second transistor M2. The source of the third transistor M3 is connected to the second fixed potential GND. The reference current source SCS includes an inverse Widlar current source. In the inverse Widlar current source, the first resistor R1 is not connected to the third transistor M3, which forms the current mirror, but is connected to the second transistor M2, which forms the diode.

[0051] The second output current path P2 includes a fifth transistor M5, a fourth transistor M4, and a fourth resistor R4 connected in series between the first fixed potential VDD and the second fixed potential GND. Furthermore, the fifth transistor M5 is less a component of the reference current source SCS and more a load carrying the drain current (reference current) of the fourth transistor M4. In other words, in the second output current path P2, the circuit belonging to the reference current source SCS is the voltage-to-current conversion circuit 40.

[0052] The fifth transistor M5 is a P-type MOS transistor, with its source connected to the first fixed potential VDD and its drain connected to the drain of the fourth transistor M4. The gate and drain of the fifth transistor M5 are connected, forming a diode-connected transistor. The fourth transistor M4 is an N-type MOS transistor, with its drain connected to the drain of the fifth transistor M5 and its source connected to the fourth resistor R4. The gate of the fourth transistor M4 is connected to the third node N3 in the first output current path P1, between the third transistor M3 and the second resistor R2. The fourth resistor R4 (output resistor) is connected between the source of the fourth transistor M4 and the second fixed potential GND.

[0053] The voltage-to-current conversion circuit 40 is composed of a fourth transistor M4 and a fourth resistor R4. Specifically, the voltage-to-current conversion circuit 40 includes: a fourth transistor M4 having a gate connected to a third node N3; and a fourth resistor R4 connected between the fourth transistor M4 and a second fixed potential GND. The potential of the third node N3 in the first output current path P1 is provided to the voltage-to-current conversion circuit 40 via the gate of the fourth transistor M4, through which a reference current Is flows.

[0054] Here, an example of the relationship between transistor dimensions is described, but the invention is not limited to these relationships. The size (gate width W2) of the second transistor M2 is larger than the size (gate width W1) of the first transistor M1. Furthermore, the size (gate width W2) of the second transistor M2 is larger than the size (gate width W3) of the third transistor M3. The size (gate width W4) of the fourth transistor M4 is the same as the size (gate width W2) of the second transistor M2, but larger than the size (gate width W1) of the first transistor M1. The size (gate width W5) of the fifth transistor M5, which serves as a load, is larger than the size (gate width W3) of the third transistor M3. Furthermore, if the gate lengths of all transistors are equal, then the size of each transistor is proportional to the size of its gate width.

[0055] In this example, W1 = 1 μm, W2 = 4 μm, W3 = 1 μm, W4 = 4 μm, and W5 = 5 μm, satisfying the relationship W1 = W3 < W2 = W4 < W5. When K = 4, W2 = K × W3 = K × W1, and W4 = K × W3 = K × W1. Among these transistors, the smallest transistor is either the first transistor M1 or the third transistor M3. Sometimes, transistors M1 through M5 are composed of multiple identical transistors. When transistors M1 through M5 are composed of multiple identical transistors, the sum of the gate widths of the identical transistors included in each transistor M1 through M5 is taken as the gate width of each transistor M1 through M5. The individual gain coefficient β of each transistor also has the same relationship as the gate width.

[0056] The gate length L of the single transistor constituting the smallest third transistor M3 is 5 nm to 100 nm. That is, due to transistor miniaturization, the Early voltage decreases, significantly affecting the generated reference current Is. When the gate length L is miniaturized to 100 nm or less, especially to 50 nm or less, the generated reference current Is is significantly affected. The purpose of the reference current source SCS is to improve the stability of the reference current under miniaturized conditions. Therefore, when the gate length L is 100 nm or less, the improvement in the reference current's PSRR becomes significant. When the gate length L is 50 nm or less, the improvement in the reference current's PSRR is even more significant. When the gate length L is 30 nm or less, the improvement in the reference current's PSRR is even more significant.

[0057] Typically, transistors with a gate length L of 5 nm or more are known, therefore this method can be applied to transistors with a gate length L of 5 nm or more. Of course, even when applying the circuit of this method to transistors with a gate length L of less than 5 nm, an improvement in the stability of the reference current Is can theoretically be expected. When the gate length L is equal to or less than 20 nm, transistors with a FinFET structure can be used. In transistors with a gate length L of 3 nm or less, transistors with structures different from the current FinFET structure (improved FinFET, Nanosheet FET, Forksheet FET, CFET, etc.) can also be used. Furthermore, as an example, each transistor M1 to M5 is used in the saturation region, but can also operate in the non-saturation region as the supply voltage decreases.

[0058] The parameters of each circuit element are obtained by using the short channel models disclosed in Non-Patent Document 2 as a basis, based on the values ​​designed as described later.

[0059] An example of the parameters for each circuit element is shown below.

[0060] The gate width W1 of the first transistor M1 is 1 μm.

[0061] The gate length of the first transistor M1 is L1 = 100 nm.

[0062] The gate width W2 of the second transistor M2 is 4μm.

[0063] The gate length of the second transistor M2 is L2 = 100 nm.

[0064] The gate width W3 of the third transistor M3 is 1 μm.

[0065] The gate length of the third transistor M3 is L3 = 100 nm.

[0066] The gate width W4 of the fourth transistor M4 is 4μm.

[0067] The gate length of the fourth transistor M4 is L4 = 100 nm

[0068] The gate width W5 of the fifth transistor M5 is 5μm.

[0069] The gate length of the fifth transistor M5 is L5 = 100 nm

[0070] The resistance value of the first resistor R1 is r1 = 5kΩ

[0071] The resistance of the second resistor R2 is r2 = 15kΩ.

[0072] The resistance of the third resistor R3 is r3 = 15kΩ

[0073] The resistance of the fourth resistor R4 is r4 = 17kΩ

[0074] First fixed potential VDD = 1.2V

[0075] Second fixed potential GND = 0V

[0076] In the above, 1.2V was used as the first fixed potential VDD (supply voltage), but even using 1.0V can stabilize the reference current Is. In setting the parameters, firstly, the characteristics of the transistors in this process must be understood. Within a reasonable range for resistance values ​​and transistor mounting area, parameters that yield the target current are selected. Furthermore, in practical design, it is considered that the deviation in transistor size will not become excessive.

[0077] If the voltage drop in the first transistor M1 is set to Vf1, and the voltage drop in the second transistor M2 is set to Vf2, then the relationship in the path from the second fixed potential GND to the first fixed potential VDD is 0V + (Ia × r1) + Vf2 + Vf1 + (Ia × r3) = VDD. That is, if this equation is modified, the reference current Ia is given by Ia = (VDD - Vf1 - Vf2) / (r1 + r3). ​​The reference current source SCS involved in the embodiment is different from the conventional β-multiplier, and does not have different equilibrium points, so a startup circuit is not required. The reference current Ia increases monotonically relative to the first fixed potential VDD, but the voltage drops Vf (= Vf1, Vf2) in each transistor do not change as much relative to the reference current Ia, so the rate of increase of the reference current Ia is greater than the rate of increase of the first fixed potential VDD.

[0078] As an example, the potential variation of the first node N1 is designed to be approximately half the variation of the first fixed potential VDD. For instance, suppose the potential variation of the first fixed potential VDD is ΔV(VDD) = 10mV. In this case, if the reference current Ia remains constant, the voltage drop caused by the third resistor R3 remains constant, therefore the potential of the first node N1 also rises by 10mV. To make the potential variation of the first node N1 half of 10mV (= 5mV), the voltage drop caused by the third resistor R3 needs to increase by 5mV. At this time, the reference current Ia increases by ΔIa = 5mV / 15kΩ = 1 / 3μA. If we assume the reference current Ia is approximately 15μA, then the rate of change of the reference current Ia is ΔIa / Ia = approximately 2%. With the first fixed potential VDD at 1.2V, the rate of change of the first fixed potential VDD is ΔV(VDD) / VDD = 10mV / 1.2V = 0.8%.

[0079] On the other hand, through a current mirror composed of the second transistor M2 and the third transistor M3, the variation of the first output current Ib is designed to be twice the variation of the reference current Ia. If the resistance values ​​of the third resistor R3 and the second resistor R2 are made the same (r3 = r2), then the potential of the third node N3 does not depend on the first fixed potential VDD. For example, as described above, when the first fixed potential VDD rises by 10mV, the reference current Ia increases, and the voltage drop in the third resistor R3 increases by 5mV, the potential of the first node N1 rises by 5mV. On the other hand, the increase in the first output current Ib is twice the increase in the reference current Ia, so the increase in the voltage drop in the second resistor R2 is 10mV. That is, when the first fixed potential VDD rises by 10mV, the voltage drop in the second resistor R2 increases by 10mV, so these voltage changes cancel each other out, and the potential of the third node N3 does not change.

[0080] The voltage fluctuation compensation conditions are summarized as follows.

[0081] (Condition 1)

[0082] The potential variation ΔV(N1) of the first node N1 at the lower end of the third resistor R3 is preferably set to 1 / 2 of the potential variation ΔV(VDD) of the first fixed potential VDD (ΔV(N1) = ΔV(VDD) / 2). In this case, the change in the reference current Ia ΔIa is the value obtained by dividing the voltage across the third resistor R3 by the resistance value r3, and the following relationship holds. To satisfy condition 1, the parameters of the circuit elements in the reference current path P0 are adjusted.

[0083] ΔIa=(ΔV(VDD) / 2)÷r3…(Formula 1)

[0084] (Condition 2)

[0085] Set the resistance value r3 of the third resistor R3 to be the same as the resistance value r2 of the second resistor R2. In this case, the following relationship holds.

[0086] r2 = r3…(Equation 2)

[0087] (Condition 3)

[0088] The change in the first output current Ib, ΔIb, is set to twice the change in the reference current Ia, ΔIa. In this case, using Equation 1, the following relationship holds.

[0089] ΔIb=2×ΔIa=2×(ΔV(VDD) / 2)÷r3=ΔV(VDD) / r3

[0090] …(Equation 3)

[0091] Under the conditions (1) to (3), the change in potential of the third node N3 becomes zero. That is, the change in potential ΔV(N3) of the third node N3 is given by (the increase in the first fixed potential VDD) - (the voltage drop caused by the second resistor R2), and is therefore expressed as ΔV(N3) = ΔV(VDD) - (r2 × ΔIb). In this formula, if we substitute the values ​​of (Equation 3) (ΔIb = ΔV(VDD) / r3) and (Equation 2) (r2 = r3), then ΔV(N3) = ΔV(VDD) - (r3 × ΔV(VDD) / r3) = 0.

[0092] Of course, based on this design philosophy, it is preferable to further fine-tune the parameters of each circuit element. Furthermore, other ratios can be set for each parameter. In the reference current source SCS of this example, by setting each parameter, it is possible not only to compensate for variations in the reference current Is based on power supply voltage changes, but also to compensate for variations in the reference current Is due to temperature changes. It should be noted that these conditions are an example of circuit design used to stabilize the reference current Is. Sometimes, parameters are optimized using a simulator to meet these conditions, thereby setting parameters that slightly deviate from them.

[0093] exist Figure 4 In the example shown, the reference current Is is designed for an operating range of 25μA or more. Furthermore, the resistance values ​​of the first resistor R1 (r1 = 5kΩ), the second resistor R2 (r2 = 15kΩ), and the third resistor R3 (r3 = 15kΩ) are each set to three times the resistance value of the first resistor R1. Additionally, the parameter (K ​​times) representing the size of the second transistor M2 is set to K = 4. This value deviates from the condition Ia = Ib, but it can suppress variations in the reference current Is relative to the first fixed potential VDD.

[0094] Figure 3 This is a circuit diagram of multiple identical transistors connected in parallel, forming the reference current source SCS for each transistor M2, M4, and M5.

[0095] In this example, Figure 2 Each transistor M1 to M5 shown is composed of one or multiple identical transistors connected in parallel. All transistors are of the same size. The remaining structure is similar to... Figure 2 The structures shown are the same. Therefore, Figure 3 The reference current source SCS shown is related to Figure 2 The circuit shown is equivalent to the reference current source SCS.

[0096] When each transistor M1 to M5 is composed of one or more identical transistors, the total gate width of the identical transistors included in each transistor M1 to M5 is taken as the gate width of each transistor M1 to M5. By comparing their total gate widths, the dimensions of each transistor M1 to M5 can be compared. That is, when the second transistor M2 is composed of N transistors (1≤N) and the third transistor M3 is composed of M transistors (1≤M), the total gate width of the N identical transistors constituting the second transistor M2 is K times (1<K) the total gate width of the M identical transistors constituting the third transistor M3 (N=K×M, K=4 in this example). In this figure, the second transistor M2 is composed of 4 identical transistors, the fourth transistor M4 is composed of 4 identical transistors, and the fifth transistor M5 is composed of 5 identical transistors. The gate width of each identical transistor is, for example, 1μm.

[0097] Figure 4 It means in Figure 2 The graph shows the relationship between the first fixed potential VDD (V) and the reference current Is (μA) in the reference current source.

[0098] The first permissible reference current range ΔIs1 is defined as the range of the reference current Is from 25.4μA to 25.6μA. The second permissible reference current range ΔIs2 is defined as the range of the reference current Is from 25.2μA to 25.6μA.

[0099] At 0°C (solid line), with the first fixed potential VDD varying from 1.14V to 1.26V, the reference current Is is within the first permissible reference current range ΔIs1. At 0°C (solid line), with the first fixed potential VDD varying from 1.11V to 1.29V, the reference current Is is within the second permissible reference current range ΔIs2.

[0100] At 50°C (single-dot dashed line), with the first fixed potential VDD varying from 1.17V to 1.30V, the reference current Is is within the first permissible reference current range ΔIs1. At 50°C (single-dot dashed line), with the first fixed potential VDD varying from 1.13V to 1.35V, the reference current Is is within the second permissible reference current range ΔIs2.

[0101] At 100°C (dashed line), when the first fixed potential VDD varies from 1.20V to 1.34V, the reference current Is is within the first permissible reference current range ΔIs1. At 100°C (dashed line), even when the first fixed potential VDD varies from 1.16V to 1.39V, the reference current Is is within the second permissible reference current range ΔIs2.

[0102] Even when the first fixed potential VDD varies from 1.20V to 1.26V and the temperature varies from 0℃ to 100℃, the reference current Is remains within the first permissible reference current range ΔIs1. Even when the first fixed potential VDD varies from 1.16V to 1.29V and the temperature varies from 0℃ to 100℃, the reference current Is remains within the second permissible reference current range ΔIs2. Furthermore, within the temperature range of 0℃ to 100℃, even when the first fixed potential VDD varies from 1.00V to 1.4V, the reference current Is remains within the reference current range of 23.4μA to 25.6μA.

[0103] according to Figure 4 As a result, regarding power supply potential fluctuations, the fluctuations are suppressed within the range of 1.2V×(100-10)%≤VDD≤1.2V×(100+10)%, and within the temperature range of 0℃~100℃, the fluctuations of the reference current Is are suppressed within the range of ±2%.

[0104] Next, the target parameters of each circuit element that satisfy (condition 1) to (condition 3) above will be explained.

[0105] First, we examine the first transistor M1 that constitutes the reference current path P0 as specified in condition 1.

[0106] Figure 5 This is a graph showing the relationship between the gate-source voltage Vgs (mV) and the drain current Id (μA) of a diode-connected transistor. The graph displays data for 0°C (solid line), 50°C (dotted line), and 100°C (dashed line). Figure 5 This is a graph showing the characteristics of the first transistor M1, but it can also be used when considering the characteristics of the third transistor M3.

[0107] As the gate-source voltage Vgs increases, the drain current Id increases. In the reference current source of the embodiment, the gate-source voltage Vgs is designed to use a reference voltage Vgs0. The variation of the gate-source voltage Vgs relative to the reference voltage Vgs0 is defined as |ΔVgs|. A preferred example of the range A of the gate-source voltage Vgs when the transistor is turned on is (|Vgs0|-|ΔVgs|)≤|Vgs|≤(|Vgs0|+|ΔVgs|). For example, when the reference voltage Vgs0 is 440mV and the variation |ΔVgs| is 120mV, 320mV≤|Vgs|≤560mV. For example, when the reference voltage Vgs0 is 400mV, 280mV≤|Vgs|≤520mV. These utilization ranges A are an example, which, while reducing the processing current, can further reduce the reference voltage |Vgs0| and the variation range |ΔVgs|. In the case of an N-channel transistor, the gate-source voltage is positive, and in the case of a P-channel transistor, the gate-source voltage is negative. Therefore, the magnitude (absolute value) of the gate-source voltage is set as described above.

[0108] Within a gate-source voltage Vgs that is higher than the gate-source voltage Vgs within the utilization range A, there exists a stationary point X1 where the drain current Id does not change with temperature. In other words, in the reference current source SCS of the embodiment, a gate-source voltage Vgs smaller than the gate-source voltage Vgs that provides the stationary point X1 is utilized. In this case, the drain current Id varies with temperature, but as described above, as a whole, the reference current SCS can suppress changes in the reference current Is.

[0109] Further explanation is provided for the fixed point X1.

[0110] The drain current Id of a transistor approximately follows the rule: Id = β / 2 × (Vgs - VT) 2 VT is the threshold voltage of the transistor. It is known that the higher the temperature, the smaller the two constants β and VT. The higher the temperature, the lower the rising voltage and the smaller the slope of the IV curve. Therefore, when the source of the transistor is connected to a second fixed potential GND, the position of the IV curve reverses at each temperature when Vgs becomes above a specific voltage. The reversal point is approximately the fixed point X1.

[0111] At gate-source voltages Vgs below the fixed point X1, the higher the temperature, the greater the drain current Id. Conversely, at gate-source voltages Vgs above the fixed point X1, the higher the temperature, the smaller the drain current Id. A circuit utilizing the voltage at the fixed point X1, as shown in the diagram, could also be considered, but it is difficult to use due to the excessively high voltage.

[0112] exist Figure 5In the current-voltage characteristic data curves shown, when a tangent line is drawn near Vgs = 500mV, the tangent line intersects the horizontal axis near 350mV, with a slope of approximately 0.25ms. This is applicable to the current-voltage characteristics of the third transistor M3. To set the change in the first output current Ib ΔIb to twice the change in the reference current Ia ΔIa, at a specific operating point (e.g.: Figure 7 At the intersection point X0), it is appropriate to set the resistance value r1 of the first resistor R1 to be close to the reciprocal of the transconductance of the third transistor M3 (the slope of the aforementioned tangent (approximately 0.25 mS)). Therefore, it is appropriate to target the resistance value r1 of the first resistor R1 as the reciprocal of this slope, and it is set to approximately 4 kΩ as the initial value for matching. This value is the target value, in order to obtain Figure 4 The characteristic is not the final optimized value (e.g., 5kΩ), but it can be used as the target for optimization.

[0113] Next, consider the combined resistance of the second transistor M2 and the first resistor R1 in series. For example, the target value for the combined resistance (rM2 + r1) of the second transistor M2's on-resistance rM2 and the first resistor R1's resistance r1 is set to be approximately twice the on-resistance rM1 of the first transistor M1 (rM2 + r1 = rM1 × 2 = 8kΩ). The second transistor M2 can carry four times the current of the third transistor M3, so its on-resistance rM2 is set to, for example, 1kΩ. These are targets; in reality, the resistance r1 of the first resistor R1, optimized by the simulator, is 5kΩ.

[0114] Next, consider the third resistor R3. With the combined resistance of the second transistor M2 and the first resistor R1 being 8kΩ, in order to satisfy the above (condition 1), the target resistance value r3 of the third resistor R3 is set as r3 = rM1 + rM2 + r1 = 4kΩ + 8kΩ = 12kΩ.

[0115] Next, consider the second resistor R2. According to condition 2 above, the target resistance value r2 of the second resistor R2 is r2 = r3 = 12kΩ. These are targets; in reality, the optimized resistance values ​​r2 and r3, determined by the simulator, are both 15kΩ.

[0116] Furthermore, with these parameters in place, if the Vgs of the first transistor M1 and the third transistor M3 are both 0.5V, then with VDD = 1.2V, 0.2V is applied across the third resistor R3. In this case, the reference current Ia becomes 16.7μA according to Ohm's law. Figure 5The current value was slightly smaller than expected. Therefore, with these parameters as targets, the parameters of each circuit element were adjusted and combined. In practice, with this value as the target, simulators such as "LTspice" were used to optimize the parameters of each circuit element to minimize the variation of the reference current Is relative to voltage and temperature variations, thus determining the parameters of the aforementioned circuit elements. In order to determine... Figure 4 When the chart is obtained using optimized parameters, the following is achieved: Figure 6 Its characteristics.

[0117] Figure 6 It is a graph showing the relationship between the first fixed potential VDD (V) and the reference current Ia (μA) and the first output current Ib (μA).

[0118] At 0°C (thin solid line), the reference current Ia (μA) increases as the first fixed potential VDD (V) rises. At 0°C (thick solid line), the first output current Ib (μA) increases with a larger slope than the reference current Ia (μA), and the voltage drop across the second resistor R2 increases. The rise in the first fixed potential VDD and the voltage drop across the second resistor R2 tend to cancel each other out at the third node N3. Therefore, the potential variation at the third node N3 caused by the variation in the first fixed potential VDD is suppressed.

[0119] At 50°C (thin dashed line), the reference current Ia (μA) increases as the first fixed potential VDD (V) rises. At 50°C (thick dashed line), the first output current Ib (μA) increases with a larger slope than the reference current Ia (μA), and the voltage drop across the second resistor R2 increases. Therefore, at 50°C, as at 0°C, the potential variation of the third node N3 caused by the variation of the first fixed potential VDD can be suppressed.

[0120] At 100°C (thin dashed line), the reference current Ia (μA) increases as the first fixed potential VDD (V) rises. At 100°C (thick dashed line), the first output current Ib (μA) increases with a larger slope than the reference current Ia (μA), and the voltage drop across the second resistor R2 increases. Therefore, even at 100°C, as at 0°C, the potential variation of the third node N3 caused by the change in the first fixed potential VDD is suppressed.

[0121] If the potential variation of the third node N3 is suppressed, the potential variation applied to the gate of the fourth transistor M4 is suppressed, and therefore the variation of the reference current Is flowing through the fourth transistor M4 is suppressed.

[0122] Furthermore, in condition 3 above, the change in the first output current ΔIb is set to be twice the change in the reference current Ia ΔIa. To satisfy this condition, an inverse Widlar current mirror is used in the reference current source of this method. In the inverse Widlar current mirror, a first resistor R1 is arranged downstream of the second transistor M2, such that the dimensions of the second transistor M2 are different from those of the third transistor M3. Figure 2 In the example shown, the third transistor M3 is smaller than the second transistor M2, and can set approximately twice the change in the reference current Ia as the change in the first output current Ib. The operation of the reverse Widlar current mirror is explained below.

[0123] Figure 7 It is a conceptual diagram showing the relationship between the voltage V supplied to the circuit element and the current I, and it is a diagram used to illustrate the reverse Widlar current mirror.

[0124] Figure 7 The thick solid line (M3) represents the drain current Id characteristic relative to the gate-source voltage Vgs of the third transistor M3. If the size of the second transistor M2 is K times that of the third transistor M3, then Figure 7 The current shown by the dashed line (second transistor M2) becomes Figure 7 The thick line indicates a current (third transistor M3) that is K times greater. This is due to... Figure 7 The dashed line (M2) indicates this.

[0125] The current I flowing through the first resistor R1 increases linearly in proportion to the voltage V across the resistor. Figure 7 The thin solid line (R1). When the first resistor R1 and the second transistor M2 are connected in series, as in the case of a reference current source SCS, the same current flows through them, so the combined IV characteristic is obtained by adding the horizontal axis (V) at the same vertical axis (current). This is derived from... Figure 7 The dashed line (M2+R1) represents the gate-source voltage Vgs of the third transistor M3. Figure 7 The thick solid line (M3) and the gate of the second transistor M2 ( Figure 2 The voltage between the second node N2 and the second fixed potential GND ( Figure 7 The dashed line (M2+R1) coincides at the intersection point X0 (voltage V0). That is, at the common gate potential V0, the drain current Id flowing through the second transistor M2 is equal to the drain current Id flowing through the third transistor M3. When the size of the second transistor M2 is increased (by a factor of K), the position of the intersection point X0 shifts to the right on the thick solid line (M3), and the voltage V0 increases.

[0126] Starting by making the resistance value r1 of the first resistor R1 the same as the reciprocal rM3 of the transconductance of the third transistor M3, by adjusting K and r1, it is possible to make the slope of the tangent line of the dashed line (M2+R1) at the intersection point X0 approximately half the slope of the tangent line of the dashed line (M2). In this case, approximately twice the change in the reference current Ia becomes the change in the first output current Ib.

[0127] Under the condition of intersection point X0, let the ratio of the change in reference current Ia flowing through reference current path P0 (second transistor M2) to voltage change ΔV be ka = (ΔIa / ΔV). Let the ratio of the change in first output current Ib flowing through first output current path P1 (third transistor M3) to voltage change ΔV be kb = (ΔIb / ΔV). As an example, let their ratio be ka:kb = 1:2. In summary, when the first fixed potential VDD (power supply potential) rises, and the reference current Ia flowing through reference current path P0 increases, the first output current Ib increases by twice the reference current Ia. When the first fixed potential VDD rises, the drain of the third transistor M3 ( Figure 2 When the potential of the third node N3 rises, the first output current Ib flowing through the third transistor M3 increases, the voltage drop in the second resistor R2 increases, and the potential change of the third node N3 is suppressed.

[0128] In addition, if the voltage drop of a single transistor is set to Vf, then when it is set to 2×Vf+α≤ the first fixed potential VDD (α is the voltage effect of the resistor, etc.), the reference current source operates at this minimum voltage.

[0129] Furthermore, these are the design goals; in fact, in order to achieve... Figure 4 The diagrams were used to further adjust the parameters of the circuit elements using a circuit simulator.

[0130] In the reference current source described in the above embodiment, as a general operation, a current mirror consisting of a second transistor M2, a third transistor M3, and a first resistor R1 is used to shift the voltage of the first node N1, which has risen by 2×Vf from the second fixed potential GND through the second transistor M2 and the first transistor M1, to the third node N3, which is located downstream of the second resistor R2. The voltage after the potential of the third node N3 has dropped by Vf through the fourth transistor M4 is applied to the fourth resistor R4 (output resistor).

[0131] This section explains the compensation for variations in the reference current Is related to temperature changes. Compensation for power supply potential variations is also performed in this reference current source SCS. By fine-tuning the parameters of each circuit element using a simulator, as described above, this circuit is also capable of temperature compensation.

[0132] In addition, in order to obtain Figure 4 The resistor used is an ideal resistor whose resistance value hardly changes with temperature rise due to its characteristics. Furthermore, in the case of various resistors composed of the on-resistance of transistors, the resistance value increases with temperature rise. However, if the change in resistance value causes a change in the reference current Is, then as needed, the parameters of the circuit components can be recalculated and set using a simulator to suppress the change in the reference current Is with temperature rise.

[0133] As described above, the aforementioned reference current source SCS can suppress variations in the reference current Is with a simple construction relative to power supply potential variations (variations in the first fixed potential VDD). Furthermore, the reference current source SCS can reduce temperature dependence. That is, the reference current Ia in the reference current path P0 has a temperature characteristic related to the voltage drop of the two transistors (let's say 2 × Vf). The third node N3 in the first output current path P1 has a temperature characteristic related to the voltage drop of the one transistor (let's say 1 × Vf). When the fourth resistor R4 does not have a temperature characteristic, this circuit can eliminate the temperature characteristic of the source potential of the fourth transistor M4, resulting in a reference current Is with low temperature dependence. As described above, when the reference current Ia ≈ the first output current Ib and the resistance value r3 of the third resistor R3 = the resistance value r2 of the second resistor R2, the temperature characteristic of the potential of the second node N2 is approximately the same as the temperature characteristic of the potential of the third node N3. This temperature characteristic has the same voltage variation as Vf of one transistor. Therefore, in the fourth transistor M4, if the potential is reduced by Vf, the voltage applied across the fourth resistor R4 has almost no temperature dependence.

[0134] Figure 8 This is a circuit diagram of a device that includes a circuit that draws a reference current Is from a reference current source SCS. There are countless ways to use a reference current source SCS, but one example is shown here.

[0135] replace Figure 2 The fifth transistor M5 shown has a differential circuit DIF disposed between the first fixed potential VDD and the fourth transistor M4. The differential circuit DIF includes a positive input transistor M51, a negative input transistor M52, a reference transistor M53, and an output transistor M54.

[0136] The positive input transistor M51 is an N-type MOS transistor, with its gate supplied with a positive input signal and its source connected to the drain of the fourth transistor M4. The negative input transistor M52 is an N-type MOS transistor, with its gate supplied with a negative input signal and its source connected to the drain of the fourth transistor M4. The reference transistor M53 is a P-type MOS transistor, with its gate and drain connected to the drain of the positive input transistor M51, and its source connected to the first fixed potential VDD. The output transistor M54 is a P-type MOS transistor, with its gate connected to the gate of the reference transistor M53, its source connected to the first fixed potential VDD, and its drain connected to the drain of the negative input transistor M52. The drain of the output transistor M54 is connected to the output terminal Vout, and a capacitor Cout is provided between the output terminal Vout and the second fixed potential GND.

[0137] The reference current Is flows through the fourth transistor M4 and the fourth resistor R4. The reference current source SCS provides the reference current Is flowing through the differential circuit DIF, and outputs a differential signal from the output terminal Vout according to the differential input. Circuits that can be connected to the reference current source SCS are not limited to the differential circuit DIF, but can also be connected to other amplifiers, etc.

[0138] Figure 9 This is a circuit diagram of a reference current source in another embodiment.

[0139] Figure 9 The reference current source SCS shown is... Figure 2 The reference current source SCS shown is formed by replacing the N-type MOS transistor with the P-type MOS transistor. That is, by replacing the N-type MOS transistor with the P-type MOS transistor. Figure 2 The first fixed potential VDD shown is replaced with the fixed potential GND (ground potential). Figure 2 The second fixed potential GND shown is replaced with a fixed potential VDD (power supply potential). Other structures are the same as... Figure 2 The structures shown are identical. Thus, there are N-channel (NMOS) transistors and P-channel (PMOS) transistors, which can operate in the same way even if they are interchanged.

[0140] As explained above, the reference current source SCS according to the embodiment includes: a reference current path P0, which includes a first transistor M1, a second transistor M2, and a first resistor R1 connected in series between a first fixed potential VDD and a second fixed potential GND, wherein the first transistor M1 and the second transistor M2 are both diode-connected transistors; a first output current path P1, which includes a third transistor M3 having a gate connected to the gate of the second transistor M2 and forming a current mirror together with the second transistor M2, and includes a current path between the third transistor M3 and the first fixed potential VDD (in Figure 9The first fixed potential is ground potential) is a second resistor R2; and a second output current path P2, which has a voltage-to-current conversion circuit 40, which is provided with the potential of the third node N3 between the third transistor M3 in the first output current path P1 and the second resistor R2, and a reference current flows through the voltage-to-current conversion circuit 40.

[0141] By appropriately setting the parameters of the circuit elements based on the reference current source SCS, the stability of the reference current Is can be improved. That is, regardless of changes in power supply potential, ground potential, or temperature, the potential of the third node N3 is relatively suppressed, thus suppressing fluctuations in the reference current Is that depend on the potential of the third node N3. Furthermore, the reference current source SCS can perform temperature compensation even without a complex temperature compensation circuit, but this does not preclude the possibility of setting up a separate temperature compensation circuit.

[0142] In the reference current source SCS described in this embodiment, the second transistor M2 is larger than the third transistor M3. When the first fixed potential VDD changes, the first output current Ib flowing through the third transistor M3 changes significantly compared to the reference current Ia flowing through the second transistor M2. Therefore, the voltage drop across the second resistor R2 increases, and potential fluctuations at the third node N3 are further suppressed. Thus, the stability of the reference current Is can be improved.

[0143] In the reference current source SCS described in the implementation, the second transistor M2 is composed of N transistors (1≤N), and the third transistor M3 is composed of M transistors (1≤M). The total gate width of the N transistors constituting the second transistor M2 is K times (1<K) the total gate width of the M transistors constituting the third transistor M3. That is, a single transistor can also be formed by connecting multiple sub-transistors in parallel.

[0144] In the reference current source SCS according to the embodiment, the voltage-to-current conversion circuit 40 includes: a fourth transistor M4 having a gate connected to a third node N3; and a fourth resistor (output resistor) connected between the fourth transistor M4 and a second fixed potential GND. Various structures are known as the voltage-to-current conversion circuit 40, but this structure has the advantage of simplicity.

[0145] In the reference current source SCS according to the embodiment, the size of the fourth transistor M4 is larger than the size of the first transistor M1. When the size of the fourth transistor M4 is set to be larger than the size of the first transistor M1, and to the same extent as the size of the second transistor M2, there is a tendency for the temperature dependence of the reference current Is to decrease. Therefore, the stability of the reference current Is can be improved.

[0146] In the reference current source SCS described in the embodiment, the gate length of one transistor constituting the third transistor M3 is 5 nm or more and less than 100 nm. That is, when the semiconductor structure is miniaturized, the reference current Is tends to fluctuate more significantly due to external factors, so the reference current source SCS described in the embodiment performs more effectively under such conditions.

[0147] As described above, the reference current source according to the embodiment can provide a reference current that is insensitive to both power supply voltage fluctuations and temperature fluctuations with a simple circuit. The reference current source consists only of a resistor and a field-effect transistor, therefore, bipolar transistors, which are necessary in the BGR circuit, are not required. Therefore, the reference current source can be manufactured using conventional CMOS processes. Furthermore, while the aforementioned transistor is an enhancement-mode transistor, depletion-mode transistors can also be used. Additionally, the on-resistance of the transistors can be used to construct the first resistor R1, the second resistor R2, and the third resistor R3. Moreover, the connections between the circuit elements described above are direct electrical connections, but other components can be interposed between the circuit elements without substantially affecting circuit operation. Furthermore, the desired effect is achieved even if the aforementioned values ​​contain an error of at least ±10%.

Claims

1. A reference current source, comprising: Referring to the current path, it includes a first transistor, a second transistor, and a first resistor connected in series between a first fixed potential and a second fixed potential, wherein the first transistor and the second transistor are both diode-connected transistors. A first output current path includes a third transistor and a second resistor between the third transistor and the first fixed potential, wherein the third transistor has a gate connected to the gate of the second transistor and together with the second transistor forms a current mirror; as well as A second output current path includes a voltage-to-current conversion circuit, wherein the voltage-to-current conversion circuit is provided with the potential of the node between the third transistor and the second resistor in the first output current path, and a reference current flows through the voltage-to-current conversion circuit. The voltage-to-current conversion circuit includes: A fourth transistor having a gate connected to the node; as well as An output resistor is connected between the fourth transistor and the second fixed potential.

2. The reference current source according to claim 1, wherein, The size of the second transistor is larger than the size of the third transistor.

3. The reference current source according to claim 1, wherein, The second transistor consists of N transistors, where 1 ≤ N. The third transistor consists of M transistors, where 1 ≤ M. The total gate width of the N transistors constituting the second transistor is K times the total gate width of the M transistors constituting the third transistor, where 1 < K.

4. The reference current source according to claim 1, wherein, The fourth transistor is larger than the first transistor.

5. The reference current source according to claim 1, wherein, The gate length of one of the transistors constituting the third transistor is less than 100 nm and more than 5 nm.

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