Method for verifying compression function in SOC system and device thereof
By identifying the master and slave devices in the SOC system, calling test cases and performing multiple access operations to calculate bandwidth data, the problem of verifying compression and decompression efficiency in the SOC system was solved, achieving fast and accurate efficiency evaluation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN AIXIN YUANZHI TECH CO LTD
- Filing Date
- 2022-06-30
- Publication Date
- 2026-07-07
AI Technical Summary
In SOC systems, existing technologies struggle to effectively verify the efficiency of subsystem compression and decompression functions, resulting in suboptimal compression and decompression efficiencies.
By identifying the master and slave devices in the SOC system, test cases are invoked, and multiple access operations are performed based on the write/read data paths to obtain bandwidth data and calculate the compression and decompression efficiency of each path.
It achieves rapid and accurate acquisition of compression and decompression efficiency of SOC system, with fast simulation speed and simple and efficient modeling method.
Smart Images
Figure CN115145772B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a method and apparatus for verifying the compression function in a SOC system. Background Technology
[0002] Image data has a large compressibility. In the performance verification of subsystems in a system-on-a-chip (SoC) system, it is necessary to test whether the compression and decompression efficiency of the corresponding subsystem is ideal in the actual system after the compression and decompression functions are enabled. Summary of the Invention
[0003] This application aims to at least partially address one of the technical problems in the related art.
[0004] Therefore, one objective of this application is to propose a method for verifying compression functionality in a System-on-Chips (SOC) system. This method involves identifying the master device and its corresponding slave device within the SOC system; invoking test cases from the SOC system; and performing multiple access operations on the master and slave devices based on the write / read data paths between them to conduct compression / decompression tests, thereby obtaining bandwidth data corresponding to each access operation. These access operations include both write and read operations. For each write data path, the compression efficiency is determined based on the first bandwidth data corresponding to the write operation on that path. Similarly, for each read data path, the decompression efficiency is determined based on the second bandwidth data corresponding to the read operation on that path.
[0005] The working principle of the data compression / decompression method in this application is simple and efficient, with fast simulation speed, and can obtain accurate compression and decompression efficiencies of the SOC system.
[0006] The second objective of this application is to provide a verification device for compression functionality in a SOC system.
[0007] The third objective of this application is to propose an electronic device.
[0008] The fourth objective of this application is to provide a non-transitory computer-readable storage medium.
[0009] The fifth objective of this application is to provide a computer program product.
[0010] To achieve the above objectives, the first aspect of this application proposes a method for verifying compression functionality in a System-on-Chip (SOC) system. This method involves identifying the master device and its corresponding slave device within the SOC system; invoking test cases from the SOC system; and performing multiple access operations on the master and slave devices based on the write / read data paths between them to conduct compression / decompression tests, thereby obtaining bandwidth data corresponding to each access operation. The access operations include write and read operations. For each write data path, the compression efficiency is determined based on the first bandwidth data corresponding to the write operation on that path. For each read data path, the decompression efficiency is determined based on the second bandwidth data corresponding to the read operation on that path.
[0011] The modeling method of this application is simple, the principle of driving the data compression / decompression method is simple and efficient, the simulation speed is fast, and it can obtain accurate compression and decompression efficiency of the SOC system.
[0012] To achieve the above objectives, a second aspect of this application provides a verification device for compression functionality in a System-on-Chip (SOC) system, comprising: a determination module for determining a master device and a corresponding slave device in the SOC system; a test module for calling test cases of the SOC system and performing multiple access operations on the master device and slave device based on the write / read data path between the master device and the slave device to perform compression / decompression tests, thereby obtaining bandwidth data corresponding to each access operation, wherein the access operation includes write operations and read operations; a first acquisition module for determining the compression efficiency corresponding to each write data path based on the first bandwidth data corresponding to the write operation on that write data path; and a second acquisition module for determining the decompression efficiency corresponding to each read data path based on the second bandwidth data corresponding to the read operation on that read data path.
[0013] To achieve the above objectives, a third aspect of this application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to implement a verification method for compression functionality in a SOC system as described in the first aspect of this application.
[0014] To achieve the above objectives, a fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement a verification method for compression functionality in a SOC system as described in the first aspect of this application.
[0015] To achieve the above objectives, a fifth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements a verification method for compression functionality in a SOC system as described in the first aspect of this application. Attached Figure Description
[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0017] Figure 1 This is a schematic diagram illustrating a method for verifying the compression function in a SOC system according to one embodiment of this application.
[0018] Figure 2 This is a schematic diagram illustrating the FBC module and FBDC module in one embodiment of this application.
[0019] Figure 3 This is a schematic diagram illustrating a method for obtaining compression efficiency based on an FBC module, as shown in one embodiment of this application.
[0020] Figure 4 This is a schematic diagram illustrating a method for obtaining decompression efficiency based on an FBDC module, as shown in one embodiment of this application.
[0021] Figure 5 This is a schematic diagram illustrating a method for setting up a test environment corresponding to the master device and slave device in a SOC system, as shown in one embodiment of this application.
[0022] Figure 6 This is a flowchart illustrating the overall process of a method for verifying compression functionality in a SOC system, as shown in one embodiment of this application.
[0023] Figure 7 This is a schematic diagram of a verification device for compression function in a SOC system, as shown in one embodiment of this application.
[0024] Figure 8 This is a schematic diagram of an electronic device according to one embodiment of this application. Detailed Implementation
[0025] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0026] Figure 1 This application illustrates an exemplary implementation of a method for verifying compression functionality in a SOC system, such as... Figure 1As shown, the verification method for the compression function in this SOC system includes the following steps:
[0027] S101, determine the master device and the corresponding slave device in the SOC system.
[0028] A System on Chip (SOC) is also known as a system-on-a-chip. An SOC can contain multiple master devices. In this application, the master devices in the SOC system and at least one corresponding slave device are defined. In this embodiment, a Double Data Rate controller is used as an example to illustrate the slave device.
[0029] After identifying the master device and its corresponding slave device in the SOC system, a test environment needs to be established for both the master and slave devices to perform compression / decompression tests on access operations. The Design Under Test (DUT) module in the test environment consists of the bus fabric and all memory subsystems and slave paths within the SOC chip. Optionally, when establishing the test environment for the master and slave devices in the SOC system, a verification IP can be used to replace the master device, and this verification IP can be used as the master device.
[0030] S102 calls the test cases of the SOC system and performs multiple access operations on the master and slave devices based on the write / read data path between the master and slave devices to perform compression / decompression tests in order to obtain the bandwidth data corresponding to each access operation. The access operations include write operations and read operations.
[0031] In the SOC system described in this application, the read data path and the write data path are two data paths.
[0032] Figure 2 This is a schematic diagram of the frame buffer compression (FBC) module and the frame buffer decompression (FBDC) module in this application, as shown below. Figure 2 As shown, this application uses the FBC module to implement data compression on the write data path and the FBDC module to implement data decompression on the read data path. The FBC and FBDC modules are implementations within the DUT.
[0033] The master device in the SOC system is identified to test the compression performance of the image data. The compression test case corresponding to the write data path of the master device is called. Based on the compression test case, multiple write operations are performed on the write data path to perform compression testing based on the FBC module. A bandwidth detector is installed at the master device interface and the slave device interface of the image data compression performance to be tested. The first bandwidth data is used to obtain the first bandwidth data corresponding to the write operation on the write data path when performing compression testing based on the FBC module. The first bandwidth data includes the first master device bandwidth corresponding to the master device interface and the first slave device bandwidth corresponding to the slave device interface on the write data path.
[0034] The master device in the SOC system is identified to test the decompression performance of the image data. A decompression test case corresponding to the read data path of this master device is invoked. Based on this test case, multiple read operations are performed on the read data path to conduct a decompression test using the FBDC module. A bandwidth detector is installed at both the master device interface and the slave device interface to acquire the second bandwidth data corresponding to the read operations on the read data path during the decompression test using the FBDC module. This second bandwidth data includes the second master device bandwidth corresponding to the master device interface and the second slave device bandwidth corresponding to the slave device interface on the read data path.
[0035] S103, for each write data path, determine the compression efficiency corresponding to the write data path based on the first bandwidth data corresponding to the write operation on the write data path.
[0036] For each write data path, after obtaining the first bandwidth data corresponding to the write operation on that write data path, the compression efficiency of that write data path = first slave device bandwidth / first master device bandwidth.
[0037] For example, when verifying the compression performance of a certain write data path, if the first slave device bandwidth of the slave device interface is measured to be 4.907 GB / s and the first master device bandwidth of the master device interface is measured to be 9.63 GB / s, then the compression efficiency corresponding to the write data path is 4.907 / 9.63 = 50.96%.
[0038] S104, for each read data path, determine the decompression efficiency corresponding to that read data path based on the second bandwidth data corresponding to the read operation on that read data path.
[0039] For each read data path, after obtaining the second bandwidth data corresponding to the read operation on that read data path, the decompression efficiency of that read data path = second slave device bandwidth / second master device bandwidth.
[0040] For example, when verifying the decompression performance of a certain read data path, if the second slave device bandwidth of the slave device interface is measured to be 4.716 GB / s and the second master device bandwidth of the master device interface is measured to be 9.442 GB / s, then the compression efficiency corresponding to the write data path is 4.716 / 9.442 = 49.95%.
[0041] This application proposes a method for verifying compression functionality in a System-on-a-Chip (SOC) system. The method involves identifying the master device and its corresponding slave device within the SOC system; invoking test cases for the SOC system; and performing multiple access operations on the master and slave devices based on the write / read data paths between them to conduct compression / decompression tests. This obtains the bandwidth data corresponding to each access operation, which includes both write and read operations. For each write data path, the compression efficiency is determined based on the first bandwidth data corresponding to the write operation. For each read data path, the decompression efficiency is determined based on the second bandwidth data corresponding to the read operation. This application features a simple modeling method, a simple and efficient principle driving the data compression / decompression mechanism, fast simulation speed, and the ability to obtain accurate compression and decompression efficiencies for the SOC system.
[0042] Figure 3 This application illustrates an exemplary implementation of a method for verifying compression functionality in a SOC system, such as... Figure 3 As shown, the method for obtaining the compression efficiency based on the FBC module in this SOC system includes the following steps:
[0043] S301, determine the master device and the corresponding slave device in the SOC system.
[0044] A System-on-Chip (SoC) system may contain multiple master devices. In this application, the master device in the SoC system and at least one slave device corresponding to the master device are defined. In this embodiment, a double data rate controller is used as an example to illustrate the slave device.
[0045] S302, invoke the compressed test case of the SOC system and parse the first text information corresponding to the compressed test case.
[0046] The master device for compressing the image data to be tested in the SOC system is identified, and the compression test case corresponding to the write data path of the master device is called to obtain the text information corresponding to the compression test case as the first text information. The test environment is driven to parse the first text information to obtain the write command and write data corresponding to the first text information. The write command and write data corresponding to the obtained first text information are recorded as the first write command and the first write data, respectively.
[0047] For example, the format of the first text information in the compressed test case of the data path can be:
[0048] awuser[0]='h015050001400001; addr[0]='h00000a0600; wr_burst_len[0]='h004; awid[0]='h415;
[0049] wr_data[0]='h24242323242523232223222322222222212121222223232323232222201f1c1c;
[0050] wr_data[1]='h24242323242523232223222322222222212121222223232323232222201f1c1c;
[0051] wr_data[2]='h1c1d1e1f1e1f1f1f1f2020212122212221222223222322232223222323242425;
[0052] wr_data[3]='h1c1d1e1f1e1f1f1f1f2020212122212221222223222322232223222323242425.
[0053] For example, the set_data_info function can be used to parse the first text information to obtain the first write command and the first write data.
[0054] S303, based on the write data path, caches the first write command and the first write data obtained after parsing from the master device to the frame buffer compression (FBC) module for compression, and obtains the compressed second write command and the second write data.
[0055] After parsing the first text information, if the master device initiates a write operation, the parsed first write command and first write data are cached in the FBC module via the M port of the frame buffer compression FBC module through the write data path. This allows the FBC module to parse the image data features according to the input first write command, compress the first write command and first write data, and obtain the compressed second write command and second write data. Here, the M port of the FBC module refers to the port of the FBC module corresponding to the master device.
[0056] S304, transmits the second write command and the second write data to the slave device via the write data path.
[0057] After obtaining the compressed second write command and second write data based on the FBC module, the second write command and second write data are output from the S port of the FBC module, so that the second write command and second write data are transmitted to the slave device via the write data path. In this application, the slave device is a DDR controller, that is, the second write command and second write data are transmitted to the DDR controller via the write data path. Here, the S port of the FBC module refers to the port of the FBC module corresponding to the slave device.
[0058] S305, for each write data path, determine the compression efficiency corresponding to that write data path based on the first bandwidth data corresponding to the write operation on that write data path.
[0059] A bandwidth detector is installed at both the master device interface and the slave device interface to test the compression performance of the image data. This detector acquires the first bandwidth data corresponding to the write operation on the write data path during compression performance verification. The first bandwidth data includes the first master device bandwidth corresponding to the master device interface and the first slave device bandwidth corresponding to the slave device interface. After acquiring the first master device bandwidth and the first slave device bandwidth, the compression efficiency corresponding to this write data path is calculated as: First Slave Device Bandwidth / First Master Device Bandwidth.
[0060] For example, when verifying the compression performance of a certain write data path, if the first slave device bandwidth of the slave device interface is measured to be 4.907 GB / s and the first master device bandwidth of the master device interface is measured to be 9.63 GB / s, then the compression efficiency corresponding to the write data path is 4.907 / 9.63 = 50.96%.
[0061] This application's embodiments call compression test cases of the SOC system to calculate the compression efficiency corresponding to each write data path. The modeling method is simple, the principle of driving the data compression method is simple and efficient, the simulation speed is fast, and it can obtain accurate compression efficiency of the SOC system.
[0062] Figure 4This application illustrates an exemplary implementation of a method for verifying compression functionality in a SOC system, such as... Figure 4 As shown, the method for obtaining the decompression efficiency based on the FBDC module in this SOC system includes the following steps:
[0063] S401, determine the master device and the corresponding slave device in the SOC system.
[0064] A System-on-Chip (SoC) system may contain multiple master devices. In this application, the master device in the SoC system and at least one slave device corresponding to the master device are defined. In this embodiment, a double data rate controller is used as an example to illustrate the slave device.
[0065] S402 calls the decompression test case of the SOC system, parses the second text information corresponding to the decompression test case to obtain the first read command and the first read data after parsing, and stores the first read data in the slave device.
[0066] The system identifies the master device in the SOC system to test the decompression performance of the image data, and calls the decompression test case corresponding to the read data path of this master device to obtain the text information corresponding to the decompression test case. This text information is then used as the second text information. The test environment is driven to parse the second text information to obtain the read command and read data corresponding to the second text information. The obtained read command and read data corresponding to the second text information are recorded as the first read command and first read data, respectively, and the first read data is stored in the slave device. In this embodiment, the slave device is a DDR controller, meaning the first read data is stored in the DDR controller.
[0067] For example, the second text information corresponding to the decompression test case of the read data path includes a read operation command file and a read operation data file.
[0068] The following is an example of a read operation command file:
[0069]
[0070] For example, the set_data_info function can be used to parse the above read operation command file to obtain the first read command.
[0071] The following is an example of reading data files:
[0072] type, id, addr, burst_len, data
[0073] READ,15,40020600,5,0994e6e28a10b71aa4629a64e131540426821f4811f423333333433222013223_6 4080525b4c054228ca50410fa410fa19919991998999991199346a96e8ec419_073f0b003f100bf0664666 666662664246656c76a50380d2c75d9227375c91d6_0111a1089199999119098e2b111a84ee4b2c7bb70ce c048971a52295d4261258_00000000000140d0681611677c09ad8e1224bf0230cf2e453f10460bfb003fb0
[0074] READ,15,40020740,5,210aa7a5a9196321012004816062d8b7787f2007f60002412221322312223031_a 9c436a21a5611864925f35dd7e80c5a00802008008ccc448488884488404752_cadc4123332ad40c584961 2b033eb2e3a401004010009111110999990908008c_4a202a4d4b5cbb344a52b49496522664a9401003f90 018999111112191090018_00000000000000000000000000000000000000000000000000000000000a495
[0075] For example, the fbdc_data_preload function can be used to process the above-mentioned read operation data file, obtain the first read data, and store the first read data in the slave device.
[0076] S403, based on the read data path, caches the first read command obtained after parsing from the master device to the frame buffer decompression FBDC module, and obtains the second read command output by the FBDC module.
[0077] After parsing the second text information, if the master device initiates a read operation, the parsed first read command is decompressed from the frame buffer and cached in the FBDC module's M port based on the read data path. The FBDC module parses the image data features according to the input first read command, and converts the first read command into a second read command. The second read command is output through the FBDC module's S port.
[0078] In this context, the M port of the FBC module refers to the port of the FBC module on the master side, and the S port of the FBC module refers to the port of the FBC module on the slave side.
[0079] S404 transmits the second read command to the slave device based on the read data path.
[0080] The second read command output from the S port of the FBDC module is transmitted to the slave device via the read data path. In this application, the slave device is a DDR controller, which means that the second read command is transmitted to the DDR controller via the read data path.
[0081] S405, based on the read data path, caches the first read data from the slave device to the FBDC module for decompression, and sends the decompressed second read data to the master device.
[0082] Taking the DDR controller as an example, after receiving the second read command, the DDR controller will reply to the FBDC module with the first read data pre-stored in the DDR controller through the read data path. Correspondingly, the FBDC module receives the first read data replied by the slave device and caches the first read data in the FBDC module so that the FBDC module can decompress the first read data and send the decompressed second read data from the M port of the FBDC module to the master device.
[0083] S406, For each read data path, determine the decompression efficiency corresponding to that read data path based on the second bandwidth data corresponding to the read operation on that read data path.
[0084] A bandwidth detector is installed at both the master device interface and the slave device interface to test the decompression performance of the image data. This detector acquires the second bandwidth data corresponding to read operations on the read data path during decompression testing using the FBDC module. The second bandwidth data includes the second master device bandwidth corresponding to the master device interface and the second slave device bandwidth corresponding to the slave device interface on the read data path. After acquiring the second master device bandwidth and the second slave device bandwidth, the decompression efficiency of the read data path is calculated as: second slave device bandwidth / second master device bandwidth.
[0085] For example, when verifying the decompression performance of a certain read data path, if the second slave device bandwidth of the slave device interface is measured to be 4.716 GB / s and the second master device bandwidth of the master device interface is measured to be 9.442 GB / s, then the compression efficiency corresponding to the write data path is 4.716 / 9.442 = 49.95%.
[0086] This application embodiment calls the decompression test cases of the SOC system to calculate the decompression efficiency corresponding to each read data path. The modeling method is simple, the principle of driving the data decompression method is simple and efficient, the simulation speed is fast, and the accurate decompression efficiency of the SOC system can be obtained.
[0087] Furthermore, before performing multiple access operations on the master and slave devices for compression / decompression testing based on the write / read data path between the master and slave devices, it is also necessary to establish corresponding test environments for the master and slave devices in the SOC system. Figure 5 This application illustrates an exemplary implementation of a method for verifying compression functionality in a SOC system, such as... Figure 5 As shown, the test environment for the master and slave devices in the SOC system is established, including the following steps:
[0088] S501, obtain the interface type corresponding to the master device.
[0089] Determine the interface type corresponding to the master device. For example, an Advanced eXtensible Interface (AXI) master device can be referred to as AXI Master; an Advanced High-performance Bus (AHB) master device can be referred to as AHB Master.
[0090] S502, based on the interface type of the main device, determine the first modular verification component corresponding to the main device.
[0091] If the master device is AXI Master, determine the first AXI modular verification component corresponding to AXI Master, that is, the verification IP (AXI VIP) corresponding to AXI Master, and replace AXI Master based on AXI VIP. The replacement boundary should be the boundary of AXI Master instantiation in each subsystem.
[0092] If the master device is AHB Master, determine the AHB modular verification component corresponding to AHB Master, that is, the verification IP (AHB VIP) corresponding to AHB Master, and replace AHB Master based on AHB VIP. The replacement boundary requirement is to reach the boundary of AHB Master instantiation in each subsystem.
[0093] If there are asynchronous bridges or components that downsize / upsize, they must also be instantiated upstream of the components, meaning that all Masters in the system must be fully simulated.
[0094] S503 generates a test environment based on the chip instantiation of the slave device or the second modular verification component corresponding to the slave device, and the first modular verification component.
[0095] The memory subsystem is instantiated using real chips. The memory subsystem includes Double-Data-Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Instruction Random Access Memory (IRAM), On-chip Memory (OCM), etc. The DDR SDRAM part also needs to have a complete instantiation of the DDRPHY model and memory model. IRAM, OCM, etc. are also design components of real chips. Combining the above-mentioned replacement of AXI Master based on AXI VIP and replacement of AHB Master based on AHB VIP, a test environment is generated, which is the complete SOC test environment.
[0096] This application embodiment establishes a test environment for the SOC, enabling accurate acquisition of the SOC system's compression and decompression efficiency based on this test environment.
[0097] Figure 6 This application presents a general flowchart of a method for verifying compression functionality in a SOC system, as shown below. Figure 6 As shown, the verification method for the compression function in this SOC system includes the following steps:
[0098] S601, establish the test environment corresponding to the master and slave devices in the SOC system.
[0099] S602, determine the master device and the corresponding slave device in the SOC system.
[0100] The implementation methods of steps S601 to S602 can be referred to the descriptions of the relevant parts in the above embodiments, and will not be repeated here.
[0101] S603 calls the compressed test case of the SOC system and parses the first text information corresponding to the compressed test case.
[0102] S604, based on the write data path, caches the parsed first write command and first write data from the master device to the frame buffer compression (FBC) module for compression, and obtains the compressed second write command and second write data.
[0103] S605 transmits the second write command and the second write data to the slave device via the write data path.
[0104] S606, for each write data path, determine the compression efficiency corresponding to that write data path based on the first bandwidth data corresponding to the write operation on that write data path.
[0105] The implementation methods of steps S603 to S606 can be referred to the description of the relevant parts in the above embodiments, and will not be repeated here.
[0106] S607 calls the decompression test case of the SOC system, parses the second text information corresponding to the decompression test case to obtain the first read command and the first read data after parsing, and stores the first read data in the slave device.
[0107] S608, based on the read data path, caches the first read command obtained after parsing from the master device to the frame buffer decompression FBDC module, and obtains the second read command output by the FBDC module.
[0108] S609 transmits the second read command to the slave device based on the read data path.
[0109] S610, based on the read data path, caches the first read data from the slave device to the FBDC module for decompression, and sends the decompressed second read data to the master device.
[0110] S611, for each read data path, determine the decompression efficiency corresponding to that read data path based on the second bandwidth data corresponding to the read operation on that read data path.
[0111] The implementation methods of steps S607 to S611 can be referred to the description of the relevant parts in the above embodiments, and will not be repeated here.
[0112] This application proposes a method for verifying compression functionality in a System-on-a-Chip (SOC) system. The method involves identifying the master device and its corresponding slave device within the SOC system; invoking test cases for the SOC system; and performing multiple access operations on the master and slave devices based on the write / read data paths between them to conduct compression / decompression tests. This obtains the bandwidth data corresponding to each access operation, which includes both write and read operations. For each write data path, the compression efficiency is determined based on the first bandwidth data corresponding to the write operation. For each read data path, the decompression efficiency is determined based on the second bandwidth data corresponding to the read operation. This application features a simple modeling method, a simple and efficient principle driving the data compression / decompression mechanism, fast simulation speed, and the ability to obtain accurate compression and decompression efficiencies for the SOC system.
[0113] Figure 7 This is a schematic diagram of a verification device for compression function in a SOC system, as shown in this application. Figure 7 As shown, the verification device 700 for the compression function in the SOC system includes a determination module 71, a test module 72, a first acquisition module 73, and a second acquisition module 74, wherein:
[0114] The determination module 71 is used to determine the master device and the corresponding slave device in the SOC system.
[0115] Test module 72 is used to call the test cases of the SOC system and perform multiple access operations on the master and slave devices based on the write / read data path between the master and slave devices to perform compression / decompression tests, so as to obtain the bandwidth data corresponding to each access operation. The access operations include write operations and read operations.
[0116] The first acquisition module 73 is used to determine the compression efficiency of each write data path based on the first bandwidth data corresponding to the write operation on that write data path.
[0117] The second acquisition module 74 is used to determine the decompression efficiency of each read data path based on the second bandwidth data corresponding to the read operation on that read data path.
[0118] Furthermore, the test module 72 is also used to: parse the first text information corresponding to the compressed test case; based on the write data path, cache the parsed first write command and first write data from the master device to the frame buffer compression (FBC) module for compression to obtain the compressed second write command and second write data; and transmit the second write command and second write data to the slave device based on the write data path.
[0119] Furthermore, the test module 72 is also used to: parse the second text information corresponding to the decompression test case to obtain the parsed first read command and first read data, and store the first read data in the slave device; based on the read data path, cache the parsed first read command from the master device to the frame buffer decompression FBDC module, and obtain the second read command output by the FBDC module; transmit the second read command to the slave device based on the read data path; based on the read data path, cache the first read data from the slave device to the FBDC module for decompression, and send the decompressed second read data to the master device.
[0120] Furthermore, the bandwidth data in test module 72 includes the master device port bandwidth on the master device side and the slave device port bandwidth on the slave device side for each access operation.
[0121] Furthermore, the verification device 700 for the compression function in the SOC system also includes: an environment establishment module 75, used to establish test environments corresponding to the master device and slave device in the SOC system, so as to perform compression / decompression tests of access operations in the test environment.
[0122] Furthermore, the environment setup module 75 is also used to: obtain the interface type corresponding to the master device; determine the first modular verification component corresponding to the master device based on the interface type of the master device; and generate a test environment based on the chip instantiation of the slave device and the first modular verification component.
[0123] Furthermore, the environment setup module 75 is also used to: in response to the master device being an Advanced Extension Interface (AXI) master device, determine the first AXI modular verification component corresponding to the AXI master device, and replace the AXI master device based on the first AXI modular verification component; in response to the master device being an Advanced High Performance Bus (AHB) master device, determine the AHB modular verification component corresponding to the AHB master device, and replace the AHB master device based on the AHB modular verification component.
[0124] To implement the above embodiments, this application also proposes an electronic device 800, such as... Figure 8 As shown, the electronic device 800 includes a processor 801 and a memory 802 communicatively connected to the processor. The memory 802 stores instructions that can be executed by at least one processor. The instructions are executed by at least one processor 801 to implement the verification method of compression function in the SOC system as shown in the above embodiment.
[0125] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to implement a verification method for the compression function in the SOC system as shown in the above embodiments.
[0126] To implement the above embodiments, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements a verification method for the compression function in a SOC system as shown in the above embodiments.
[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0128] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0129] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A method for verifying compression functionality in a SOC system, characterized in that, include: Determine the master device in the SOC system and the corresponding slave device; The test cases of the SOC system are invoked, and based on the write / read data path between the master device and the slave device, multiple access operations are performed on the master device and the slave device to perform compression / decompression tests, so as to obtain the bandwidth data corresponding to each access operation. The access operation includes write operation and read operation. For each write data path, the compression efficiency corresponding to the write data path is determined based on the first bandwidth data corresponding to the write operation on the write data path. The first bandwidth data includes the first master device bandwidth corresponding to the master device interface and the first slave device bandwidth corresponding to the slave device interface on the write data path. The compression efficiency = first slave device bandwidth / first master device bandwidth. For each read data path, the decompression efficiency corresponding to that read data path is determined based on the second bandwidth data corresponding to the read operation on that read data path. The second bandwidth data includes the second master device bandwidth corresponding to the master device interface and the second slave device bandwidth corresponding to the slave device interface on that read data path. The decompression efficiency = second slave device bandwidth / second master device bandwidth.
2. The method according to claim 1, characterized in that, The test cases include compression test cases, wherein, based on the write data path between the master device and the slave device, multiple write operations are performed on the master device and the slave device to perform compression tests, including: The first text information corresponding to the compression test case is parsed; Based on the write data path, the parsed first write command and first write data are cached from the master device to the frame buffer compression (FBC) module for compression to obtain the compressed second write command and second write data. The second write command and the second write data are transmitted to the slave device via the write data path.
3. The method according to claim 1, characterized in that, The test cases include decompression test cases, wherein, based on the read data path between the master device and the slave device, multiple read operations are performed on the master device and the slave device to perform decompression tests, including: The second text information corresponding to the decompression test case is parsed to obtain the first read command and the first read data after parsing, and the first read data is stored in the slave device; Based on the read data path, the parsed first read command is cached from the master device to the frame buffer decompression FBDC module, and the second read command output by the FBDC module is obtained. The second read command is transmitted to the slave device based on the read data path; Based on the read data path, the first read data is cached from the slave device to the FBDC module for decompression, and the decompressed second read data is sent to the master device.
4. The method according to claim 1, characterized in that, Before invoking the test cases of the SOC system, the following are also included: Establish test environments corresponding to the master device and the slave device in the SOC system, and perform compression / decompression tests of the access operation in the test environments.
5. The method according to claim 4, characterized in that, The establishment of the test environment corresponding to the master device and the slave device in the SOC system includes: Obtain the interface type corresponding to the main device; Based on the interface type of the main device, determine the first modular verification component corresponding to the main device; The test environment is generated based on the chip instantiation of the slave device and the first modular verification component.
6. The method according to claim 5, characterized in that, The step of determining the first modular verification component corresponding to the main device based on the interface type of the main device includes: In response to the fact that the master device is an Advanced Extension Interface (AXI) master device, a first AXI Modular Verification Component corresponding to the AXI master device is determined, and the AXI master device is replaced based on the first AXI Modular Verification Component; In response to the master device being an Advanced High Performance Bus (AHB) master device, the AHB Modular Verification Component corresponding to the AHB master device is determined, and the AHB master device is replaced based on the AHB Modular Verification Component.
7. A verification device for compression function in a SOC system, characterized in that, include: The determination module is used to determine the master device in the SOC system and the slave device corresponding to the master device. The testing module is used to call the test cases of the SOC system and perform multiple access operations on the master device and the slave device based on the write / read data path between the master device and the slave device to perform compression / decompression tests, so as to obtain the bandwidth data corresponding to each access operation. The access operation includes write operation and read operation. The first acquisition module is used to determine the compression efficiency of each write data path based on the first bandwidth data corresponding to the write operation on the write data path. The first bandwidth data includes the first master device bandwidth corresponding to the master device interface and the first slave device bandwidth corresponding to the slave device interface on the write data path. The compression efficiency = first slave device bandwidth / first master device bandwidth. The second acquisition module is used to determine the decompression efficiency of each read data path based on the second bandwidth data corresponding to the read operation on the read data path. The second bandwidth data includes the second master device bandwidth corresponding to the master device interface and the second slave device bandwidth corresponding to the slave device interface on the read data path. The decompression efficiency is equal to the second slave device bandwidth and the second master device bandwidth.
8. The apparatus according to claim 7, characterized in that, The test module is also used for: Parse the first text information corresponding to the compressed test cases; Based on the write data path, the parsed first write command and first write data are cached from the master device to the frame buffer compression (FBC) module for compression to obtain the compressed second write command and second write data. The second write command and the second write data are transmitted to the slave device via the write data path.
9. The apparatus according to claim 7, characterized in that, The test module is also used for: The second text information corresponding to the decompression test case is parsed to obtain the first read command and the first read data after parsing, and the first read data is stored in the slave device; Based on the read data path, the parsed first read command is cached from the master device to the frame buffer decompression FBDC module, and the second read command output by the FBDC module is obtained. The second read command is transmitted to the slave device based on the read data path; Based on the read data path, the first read data is cached from the slave device to the FBDC module for decompression, and the decompressed second read data is sent to the master device.
10. The apparatus according to claim 7, characterized in that, The device further includes: The environment setup module is used to establish a test environment corresponding to the master device and the slave device in the SOC system, so as to perform compression / decompression tests of the access operation in the test environment.
11. The apparatus according to claim 10, characterized in that, The environment setup module is also used for: Obtain the interface type corresponding to the main device; Based on the interface type of the main device, determine the first modular verification component corresponding to the main device; The test environment is generated based on the chip instantiation of the slave device and the first modular verification component.
12. The apparatus according to claim 11, characterized in that, The environment setup module is also used for: In response to the fact that the master device is an Advanced Extension Interface (AXI) master device, a first AXI Modular Verification Component corresponding to the AXI master device is determined, and the AXI master device is replaced based on the first AXI Modular Verification Component; In response to the master device being an Advanced High Performance Bus (AHB) master device, the AHB Modular Verification Component corresponding to the AHB master device is determined, and the AHB master device is replaced based on the AHB Modular Verification Component.
13. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.
15. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.