Display panel driving signal phase offset compensation method, device and display panel

Abstract

The present invention provides a compensation method, device and display panel for the phase shift of a display panel driving signal, including: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on the original driving signal and the phase shift of the actual driving signal of each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, the timing of the original driving signal is adjusted according to the clock count compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and the display panel is driven to display according to the target driving signal. By pre-acquiring and storing the clock count compensation value corresponding to each pixel row of the display panel, when the driving chip outputs the display panel driving signal, the timing of the driving signal corresponding to each pixel row is adjusted according to the clock count compensation value to alleviate the delay phenomenon of some pixel rows receiving the driving signal, thereby improving the problem of poor display uniformity of the OLED display panel.

Description

Technical Field

[0001] The present invention relates to the field of display panel driving, and in particular to a method and device for compensating a phase shift of a display panel driving signal, and a display panel. Background Art

[0002] Each component in the pixel circuit of the OLED (Organic Light-Emitting Diode) module has RC-loading (resistance and capacitance load). When the chip of the display panel sends a driving signal, the timing of actually reaching each pixel point cannot reach the ideal state due to IR-Drop, and the timing of actually reaching the remote chip end of the display panel will be delayed. Under abnormal timing, the delay of the driving signal timing will cause the display effect of the remote chip end of the display panel to change, such as lower brightness, thereby affecting the display effect.

[0003] Although the uniformity of the display panel can be optimized through external compensation methods such as Demura (sub-pixel optical imaging technology and software algorithm), the peripheral driving circuit is highly complex and the actual essence of Demura is just to brighten the areas it considers to be dark, or darken the bright areas, or eliminate the areas with color cast. The ultimate goal is to make different areas of the panel have roughly the same color, and it does not fundamentally solve the problem. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a compensation method, device and display panel for the phase shift of a display panel driving signal. By pre-acquiring and storing a clock count compensation value corresponding to each pixel row of the display panel, when the driving chip outputs the display panel driving signal, the driving signal timing corresponding to each pixel row is adjusted according to the clock count compensation value, thereby alleviating the delay in some pixel rows receiving the driving signal (for example, the driving signal received by the pixel row at the far chip end may be delayed), so that different pixel rows receive the driving signal for display at the same time, thereby improving the problem of poor display uniformity of the OLED display panel.

[0005] In a first aspect, an embodiment of the present invention provides a method for compensating for a phase offset of a display panel drive signal, comprising: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on a phase offset of a theoretical phase of an original drive signal in each pixel row of the display panel and an actual phase of the original drive signal in each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the timing of the original drive signal according to the clock count compensation value corresponding to the pixel row, to obtain a target drive signal corresponding to the pixel row; and driving the display panel for display according to the target drive signal.

[0006] Furthermore, the clock count compensation value is calculated in the following manner: obtaining the theoretical phase of the original driving signal in each pixel row of the display panel; constructing a simulation circuit according to the impedance model of the display panel; inputting the original driving signal into the simulation circuit, and simulating and obtaining the actual phase of each pixel row of the display panel; determining the phase offset corresponding to each pixel row of the display panel based on the theoretical timing diagram of the original driving signal and the timing diagram of the original driving signal; and determining the clock count compensation value corresponding to each pixel row according to the phase offset corresponding to each pixel row of the display panel.

[0007] Furthermore, the step of determining the clock count compensation value corresponding to each pixel row according to the phase offset corresponding to each pixel row of the display panel includes: dividing the phase offset corresponding to each pixel row of the display panel by a preset clock period to obtain a ratio corresponding to each pixel row; rounding up the ratio to obtain a clock count compensation value corresponding to each pixel row.

[0008] Furthermore, for each pixel row of the display panel, the timing of the original drive signal is adjusted according to the clock count compensation value corresponding to the pixel row to obtain the target drive signal corresponding to the pixel row, including: for each pixel row of the display panel, the clock count compensation value corresponding to the pixel row is determined as the clock advance amount of the rising edge and the falling edge of the drive signal corresponding to the pixel row; according to the clock advance amount, the rising edge and the falling edge of the original drive signal are moved forward to obtain the target drive signal corresponding to the pixel row.

[0009] Furthermore, the step of obtaining the clock count compensation value corresponding to each pixel row of the display panel includes: grouping the pixel rows of the display panel in advance to obtain multiple pixel units; wherein the clock count compensation value corresponding to each pixel row in each pixel unit is the same; and obtaining the clock count compensation value corresponding to each pixel unit.

[0010] Furthermore, the effective level time of each pixel unit is the same.

[0011] Furthermore, each pixel unit in the plurality of pixel units includes the same number of pixel rows.

[0012] In a second aspect, an embodiment of the present invention provides a compensation device for a display panel drive signal, comprising: an acquisition unit, used to acquire a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on a phase offset between a theoretical phase of the original drive signal in each pixel row of the display panel and an actual phase of the original drive signal in each pixel row of the display panel obtained by simulation; an adjustment unit, used to adjust the timing of the original drive signal for each pixel row of the display panel according to the clock count compensation value corresponding to the pixel row, so as to obtain a target drive signal corresponding to the pixel row; and a driving unit, used to drive the display panel for display according to the target drive signal.

[0013] In a third aspect, an embodiment of the present invention provides a display panel, including the compensation device for the display panel driving signal.

[0014] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processing device, the steps of the image correction method of any embodiment of the first aspect are executed.

[0015] An embodiment of the present invention provides a compensation method, device and display panel for the phase offset of a display panel driving signal, comprising: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row, to obtain a target driving signal corresponding to the pixel row; and driving the display panel for display according to the target driving signal. In this method, the theoretical phase of each pixel row of the display panel is compared with the actual phase of each pixel row of the display panel obtained by pre-simulation, and the phase offset between the theoretical phase and the actual phase is calculated to obtain the driving signal delay of each pixel row of the display panel, and the delay is stored in the form of clock count compensation in advance. When the driver chip outputs the display panel driving signal, the clock count compensation value corresponding to each pixel row is directly obtained, and then the driving signal timing corresponding to each pixel row is adjusted, thereby alleviating the delay phenomenon of some pixel rows receiving the driving signal (for example, the driving signal received by the pixel row at the far chip end may be delayed), so that different pixel rows receive the driving signal for display at the same time, thereby improving the problem of poor display uniformity of the OLED display panel.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the display effect of a display panel when a driving signal has a phase offset provided in an embodiment of the present invention;

[0020] Figure 2 A flow chart of a method for compensating a phase shift of a display panel driving signal provided in Embodiment 1 of the present invention;

[0021] Figure 3 A flow chart of a method for calculating a display panel clock count compensation value provided in the first embodiment of the present invention;

[0022] Figure 4 A theoretical timing diagram of an original driving signal of a display panel provided in the first embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the phase offset between the theoretical phase and the actual phase of the original driving signal of the display panel provided in the first embodiment of the present invention;

[0024] Figure 6 A schematic diagram of phase offset data of a simulation circuit provided in Embodiment 2 of the present invention;

[0025] Figure 7 A schematic diagram of a phase offset compensation solution provided in Embodiment 2 of the present invention;

[0026] Figure 8 A schematic diagram of a compensation device for a display panel driving signal is provided for a third embodiment of the present invention.

[0027] Icons: 1-acquisition unit; 2-adjustment unit; 3-drive unit. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In the field of OLED driver chip development, the chip needs to input the driving signal to the input port of the display panel according to a customized timing, so that each pixel in the display panel can emit light normally according to the timing. Under ideal conditions, the driving signal output by the chip will be directly transmitted to the input port of the display panel according to the original driving signal, and the timing of reaching each pixel will also meet the requirements of the original driving signal.

[0030] However, since each component in the module pixel circuit has internal resistance, the ID-Drop generated by the internal resistance makes the actual timing of reaching each pixel point not reach the ideal state, and the actual timing of reaching the remote chip end of the display panel will be delayed. Under abnormal timing, the delay of the driving signal timing will cause the display effect of the remote chip end of the display panel to change, such as lower brightness, etc., refer to Figure 1 , where DDIC is the driver chip.

[0031] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0032] Embodiment 1:

[0033] Figure 2 This is a flow chart of a method for compensating a phase shift of a display panel driving signal provided in Embodiment 1 of the present invention.

[0034] Reference Figure 2 , the compensation method for the phase shift of the display panel driving signal includes:

[0035] Step S101, obtaining the clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation.

[0036] Here, when the OLED display panel is working, due to different RC-loading (resistance and capacitance load), the driving signals of different pixel rows will be delayed to different degrees.

[0037] In one embodiment, reference Figure 3 The clock count compensation value in step S101 is calculated by the following method:

[0038] Step S201, obtaining the theoretical phase of the original driving signal in each pixel row of the display panel.

[0039] Here, the theoretical phase of the original driving signal is the phase of the driving signal of the display panel when the display panel is in an ideal working state, that is, when RC-loading is not considered.

[0040] Step S202: constructing a simulation circuit according to the impedance model of the display panel.

[0041] Here, the RC-loading impedance model of the display panel is preset at the factory. The closer the distance to the driver chip, the smaller the RC-loading, and the farther the distance from the driver chip, the larger the RC-loading. The display panel may include at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, and a micro light emitting diode display panel. The driver chip may be a universal driver chip, which may be applicable to display panels with different sub-pixel arrangements, thereby reducing design costs and manufacturing costs.

[0042] Step S203: inputting the original driving signal into the simulation circuit to obtain the actual phase of each pixel row of the display panel through simulation.

[0043] Step S204 , determining the phase offset corresponding to each pixel row of the display panel based on the theoretical timing diagram of the original driving signal and the actual timing diagram of the original driving signal.

[0044] Here, refer to Figure 4 The theoretical timing diagram of the original driving signal of the display panel without considering RC-loading and the actual timing diagram of the display panel when considering RC-loading are obtained. Figure 5 Schematic diagram of the phase offset between the theoretical phase and the actual phase of the original driving signal. Figure 5 The solid line part is the theoretical phase, and the dotted line part is the actual phase. The phase offset between the theoretical phase and the actual phase of the original drive signal is the phase difference between the rising edge of the theoretical phase and the rising edge of the actual phase or the phase difference between the falling edge of the theoretical phase and the falling edge of the actual phase.

[0045] Step S205 , determining a clock count compensation value corresponding to each pixel row according to the phase offset corresponding to each pixel row of the display panel.

[0046] In one implementation, step S205 includes:

[0047] The phase offset corresponding to each pixel row of the display panel is divided by a preset clock cycle to obtain a ratio corresponding to each pixel row; the ratio is rounded up to obtain a clock count compensation value corresponding to each pixel row.

[0048] Here, the preset clock period can be set according to actual conditions, and can be 15.75ns (nanoseconds), and its corresponding reference clock is 63.5MHz.

[0049] Step S102 : for each pixel row of the display panel, adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row, so as to obtain a target driving signal corresponding to the pixel row.

[0050] Here, the target driving signal corresponding to each pixel row is processed forward compared with the original driving signal.

[0051] In one embodiment, the step of adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row for each pixel row of the display panel in step S102 to obtain the target driving signal corresponding to the pixel row includes:

[0052] For each pixel row of the display panel, the clock count compensation value corresponding to the pixel row is determined as the clock advance amount of the rising edge and the falling edge of the driving signal corresponding to the pixel row; the rising edge and the falling edge of the original driving signal are moved forward according to the clock advance amount to obtain the target driving signal corresponding to the pixel row.

[0053] Here, because the actual driving signal is delayed compared with the original driving signal, the actual driving signal is shifted forward according to the clock count compensation value to obtain the corresponding target driving signal.

[0054] Step S103 , driving the display panel to display according to the target driving signal.

[0055] Here, the display panel is driven according to the target driving signal so that the driving signal output by the driving chip can reach each pixel row at the same time, so that each pixel row of the display panel emits light normally in a time sequence.

[0056] The embodiment of the present invention provides a compensation method for the phase offset of a display panel driving signal, comprising: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated based on the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row, obtaining a target driving signal corresponding to the pixel row; and driving the display panel for display according to the target driving signal. In this method, by obtaining the clock count compensation value corresponding to each pixel row and adjusting the timing of the driving signal corresponding to each pixel row, the delay of the driving signal between different pixel rows is eliminated, so that different pixel rows drive the display panel at the same time, thereby improving the uniformity of the display of the display panel.

[0057] Embodiment 2:

[0058] In practical applications, for GCK / GCB / ECK / ECB drive signals, since there are too many oscillations in each frame (referring to the resolution of 1080x2340, each frame oscillates about 1000-2000 times), it is too wasteful to perform precise compensation for each falling edge and rising edge, which wastes the area of ​​the driver chip, and the phase difference does not require very high compensation accuracy. Therefore, this embodiment provides another compensation method for the phase offset of the display panel drive signal. In this embodiment, the step of obtaining the clock count compensation value corresponding to each pixel row of the display panel includes:

[0059] The pixel rows of the display panel are grouped in advance to obtain a plurality of pixel units, wherein the clock count compensation values ​​corresponding to the pixel rows in each pixel unit are the same, and the clock count compensation value corresponding to each pixel unit is obtained. The number of pixel rows contained in each pixel unit in the plurality of pixel units is the same.

[0060] Here, the pixel rows of the display panel are grouped in advance according to the resolution of the display panel to obtain a plurality of pixel units including the same number of pixel rows; and the clock count compensation value corresponding to each pixel unit is obtained as the clock count compensation value corresponding to each pixel row.

[0061] Specifically, refer to Figure 6 , the pixel rows of the display panel are grouped in advance according to the resolution of the display panel. In this embodiment, 300 pixel rows are taken as an example to divide the display panel into 8 pixel units. Among them, the first pixel unit includes the 1st to 300th pixel rows, the second pixel unit includes the 300th to 600th pixel rows, the third pixel unit includes the 600th to 900th pixel rows, the fourth pixel unit includes the 900th to 1200th pixel rows, the fifth pixel unit includes the 1200th to 1500th pixel rows, the sixth pixel unit includes the 1500th to 1800th pixel rows, the seventh pixel unit includes the 1800th to 2100th pixel rows, and the eighth pixel unit includes the 2100th to 2340th pixel rows. The first pixel unit is close to the driving chip, and the RC-loading of the first pixel unit is less than the RC-loading of the second pixel unit, and so on.

[0062] Furthermore, a simulation circuit is constructed based on the RC-loading model of the display panel and the driver chip, and the original driving signal of the display panel under the ideal state is input into the simulation circuit to simulate and obtain the actual phase of each pixel unit of the display panel. Based on the actual phase timing diagram of the original driving signal and the theoretical phase timing diagram, we can obtain Figure 6The phase offsets corresponding to the pixel units shown are shown in FIG. 1 , wherein the phase offset of the first pixel unit is 0 μs (microseconds), the phase offset of the second pixel unit is 0.02 μs, the phase offset of the third pixel unit is 0.05 μs, the phase offset of the fourth pixel unit is 0.08 μs, the phase offset of the fifth pixel unit is 0.1 μs, the phase offset of the sixth pixel unit is 0.14 μs, the phase offset of the seventh pixel unit is 0.17 μs, and the phase offset of the eighth pixel unit is 0.2 μs.

[0063] Further, see Figure 7 , according to the preset clock cycle 15.75ns and the reference clock 63.5MHz, the clock count compensation value is calculated, and the phase offset corresponding to each pixel unit of the display panel is divided by the preset clock cycle to obtain the ratio corresponding to each pixel unit; the ratio is rounded up to obtain the clock count compensation value corresponding to each pixel unit. Among them, the clock count compensation value of the first pixel unit is 0, the clock count compensation value of the second pixel unit is 1, the clock count compensation value of the third pixel unit is 3, the clock count compensation value of the fourth pixel unit is 5, the clock count compensation value of the fifth pixel unit is 6, the clock count compensation value of the sixth pixel unit is 9, the clock count compensation value of the seventh pixel unit is 11, and the clock count compensation value of the eighth pixel unit is 13.

[0064] Furthermore, for each pixel unit of the display panel, the clock count compensation value corresponding to the pixel unit is determined as the clock advance amount of the rising edge and the falling edge of the driving signal corresponding to the pixel unit; the rising edge and the falling edge of the original driving signal are moved forward according to the clock advance amount to obtain the target driving signal corresponding to the pixel unit.

[0065] Here, referring to the eighth pixel unit, if the original driving signal phase of the eighth pixel unit is 0.8μs, the original driving signal of the eighth pixel unit corresponds to 52 clock counts. When the phase offset of the eighth pixel unit is 0.2μs, the eighth pixel unit needs to be moved forward by 13 clock counts. Then, the target driving signal of the eighth pixel unit is 39 clock counts. The calculation method of the remaining pixel units refers to the eighth pixel unit and will not be elaborated here.

[0066] Furthermore, the effective level time of each pixel unit is the same.

[0067] The embodiment of the present invention provides a compensation method for the phase shift of a display panel driving signal, comprising: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated based on the phase shift of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row, and obtaining a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. In this method, the delay of the driving signal between different pixel rows is eliminated by dividing the display panel into multiple pixel units according to the resolution. This method does not need to accurately compensate for each falling edge and rising edge, saving the area of ​​the driving chip, thereby making the compensation more efficient.

[0068] Embodiment three:

[0069] Figure 8 A schematic diagram of a compensation device for a display panel driving signal is provided for a third embodiment of the present invention.

[0070] Reference Figure 8 , the display panel driving signal compensation device comprises:

[0071] An acquisition unit 1 is used to acquire a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on a phase offset between a theoretical phase of an original driving signal at each pixel row of the display panel and an actual phase of the original driving signal at each pixel row of the display panel obtained by simulation;

[0072] An adjustment unit 2 is used to adjust the timing of the original driving signal for each pixel row of the display panel according to the clock count compensation value corresponding to the pixel row, so as to obtain a target driving signal corresponding to the pixel row;

[0073] The driving unit 3 is used to drive the display panel to display according to the target driving signal.

[0074] An embodiment of the present invention provides a compensation device for a display panel drive signal, comprising: obtaining a clock count compensation value corresponding to each pixel row of the display panel; the clock count compensation value is calculated in advance based on a phase offset between a theoretical phase of an original drive signal at each pixel row of the display panel and an actual phase of the original drive signal at each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the timing of the original drive signal according to the clock count compensation value corresponding to the pixel row, to obtain a target drive signal corresponding to the pixel row; and driving the display panel to display according to the target drive signal. In this method, the theoretical phase of each pixel row of the display panel is compared with the actual phase of each pixel row of the display panel obtained by pre-simulation, and the phase offset between the theoretical phase and the actual phase is calculated to obtain the driving signal delay of each pixel row of the display panel, and the delay is stored in the form of clock count compensation in advance. When the driver chip outputs the display panel driving signal, the clock count compensation value corresponding to each pixel row is directly obtained, and then the driving signal timing corresponding to each pixel row is adjusted, thereby alleviating the delay phenomenon of some pixel rows receiving the driving signal (for example, the driving signal received by the pixel row at the far chip end may be delayed), so that different pixel rows receive the driving signal for display at the same time, thereby improving the problem of poor display uniformity of the OLED display panel.

[0075] An embodiment of the present invention further provides a display panel, comprising the above-mentioned compensation device for the display panel driving signal.

[0076] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processing device, the steps of the above-mentioned method for compensating the phase shift of the display panel driving signal are executed.

[0077] The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0078] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

[0079] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0080] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0081] Although the steps and the order of the steps of the embodiment of the present invention are given in the method and the method legend, the executable instructions for implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method legend, and can be adjusted at any time according to the needs of the function. For example, some of the steps can be executed in parallel or in reverse order.

[0082] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0083] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0084] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0085] The term "and / or" in the present invention is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent the three situations that A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" in the present invention represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

Claims

1. A method for compensating a phase shift of a display panel driving signal, characterized in that: include: Acquiring a clock count compensation value corresponding to each pixel row of the display panel; The clock count compensation value is calculated in advance based on the phase offset between the theoretical phase of the original driving signal at each pixel row of the display panel and the actual phase of the original driving signal at each pixel row of the display panel obtained by simulation; For each pixel row of the display panel, adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; driving the display panel to display according to the target driving signal; The clock count compensation value is calculated in the following way: Acquiring a theoretical phase of the original driving signal in each pixel row of the display panel; constructing a simulation circuit according to the impedance model of the display panel; Inputting the original driving signal into the simulation circuit to obtain the actual phase of each pixel row of the display panel through simulation; Determining a phase offset corresponding to each pixel row of the display panel based on a theoretical timing diagram of the original driving signal and an actual timing diagram of the original driving signal; Determining a clock count compensation value corresponding to each pixel row according to a phase offset corresponding to each pixel row of the display panel; The step of determining a clock count compensation value corresponding to each pixel row according to the phase offset corresponding to each pixel row of the display panel comprises: Dividing the phase offset corresponding to each pixel row of the display panel by a preset clock cycle to obtain a ratio corresponding to each pixel row; The ratio is rounded up to obtain a clock count compensation value corresponding to each pixel row.

2. The method for compensating the phase shift of a display panel driving signal according to claim 1, characterized in that: For each pixel row of the display panel, the step of adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row to obtain the target driving signal corresponding to the pixel row includes: For each pixel row of the display panel, the clock count compensation value corresponding to the pixel row is determined as the clock advance amount of the rising edge and the falling edge of the driving signal corresponding to the pixel row; The rising edge and the falling edge of the original driving signal are moved forward according to the clock advance amount to obtain a target driving signal corresponding to the pixel row.

3. The method for compensating the phase shift of a display panel driving signal according to claim 1, characterized in that: The step of obtaining a clock count compensation value corresponding to each pixel row of the display panel comprises: Pre-grouping the pixel rows of the display panel to obtain a plurality of pixel units; wherein the clock count compensation values ​​corresponding to the pixel rows in each pixel unit are the same; A clock count compensation value corresponding to each of the pixel units is obtained.

4. The method for compensating the phase shift of a display panel driving signal according to claim 3, characterized in that: The effective level time of each pixel unit is the same.

5. The method for compensating the phase shift of a display panel driving signal according to claim 3, characterized in that: Each pixel unit in the plurality of pixel units includes the same number of pixel rows.

6. A compensation device for a display panel driving signal, characterized in that: include: An acquisition unit, used for acquiring a clock count compensation value corresponding to each pixel row of the display panel; The clock count compensation value is calculated in advance based on the phase offset between the theoretical phase of the original driving signal at each pixel row of the display panel and the actual phase of the original driving signal at each pixel row of the display panel obtained by simulation; an adjusting unit, configured to adjust the timing of the original driving signal for each pixel row of the display panel according to the clock count compensation value corresponding to the pixel row, so as to obtain a target driving signal corresponding to the pixel row; A driving unit, configured to drive the display panel to display according to the target driving signal; The acquisition unit is further used to acquire the theoretical phase of the original driving signal in each pixel row of the display panel; construct a simulation circuit according to the impedance model of the display panel; input the original driving signal into the simulation circuit, and simulate to obtain the actual phase of each pixel row of the display panel; Based on the theoretical timing diagram of the original driving signal and the actual timing diagram of the original driving signal, determining the phase offset corresponding to each pixel row of the display panel; according to the phase offset corresponding to each pixel row of the display panel, determining the clock count compensation value corresponding to each pixel row; The acquisition unit is further configured to divide the phase offset corresponding to each pixel row of the display panel by a preset clock cycle to obtain a ratio corresponding to each pixel row; The ratio is rounded up to obtain a clock count compensation value corresponding to each pixel row.

7. A display panel, characterized in that: A compensation device for a display panel driving signal comprising the device described in claim 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processing device, the steps of the method according to any one of claims 1 to 5 are executed.

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