Display panel and manufacturing method thereof, and display device

Abstract

A display substrate has a display area and a peripheral area; the display substrate comprises: a substrate, a first retaining wall, a second retaining wall and a connecting portion. The first retaining wall and the second retaining wall are located on one side of the substrate and in the peripheral area; the second retaining wall is away from the display area relative to the first retaining wall; the height of the second retaining wall is greater than the height of the first retaining wall. The connecting portion is located between the first retaining wall and the second retaining wall, the connecting portion connects the first retaining wall and the second retaining wall, and the height of the connecting portion is less than the height of the first retaining wall. Among them, at least part of the first retaining wall, the connecting portion and the second retaining wall are an integrated structure.

Description

[0001] This application claims priority to Chinese patent application No. 202110121161.6, filed on January 28, 2021, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, for example, to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] With the continuous development of science and technology, users have an increasingly higher demand for the screen-to-body ratio of display devices (the ratio of the area of ​​the display screen to the area of ​​the front panel of the display device). Therefore, the concept of full screen has emerged. For example, optical devices such as image acquisition devices and cameras in the display device are arranged under the display screen to increase the ratio between the area of ​​the display screen and the area of ​​the front panel of the display device, and make the ratio approach 100%. Summary of the invention

[0004] On the one hand, a display substrate is provided. The display substrate has a display area and a peripheral area; the display substrate includes: a substrate, a first retaining wall, a second retaining wall and a connecting portion. The first retaining wall and the second retaining wall are located on one side of the substrate and in the peripheral area; the second retaining wall is away from the display area relative to the first retaining wall; the height of the second retaining wall is greater than the height of the first retaining wall. The connecting portion is located between the first retaining wall and the second retaining wall, the connecting portion connects the first retaining wall and the second retaining wall, and the height of the connecting portion is less than the height of the first retaining wall; wherein at least part of the first retaining wall, the connecting portion and the second retaining wall are an integrated structure.

[0005] In some embodiments, the first retaining wall includes multiple first barrier layers stacked in sequence, and the second retaining wall includes multiple second barrier layers stacked in sequence; the total number of second barrier layers is greater than the total number of first barrier layers; the connecting portion includes at least one connecting layer; the total number of connecting layers is less than the total number of first barrier layers.

[0006] In some embodiments, at least one first barrier layer in the plurality of first barrier layers close to the substrate and at least one second barrier layer in the plurality of second barrier layers close to the substrate are connected via at least one connecting layer.

[0007] In some embodiments, a layer of the connecting layer connects a layer of the first barrier layer and a layer of the second barrier layer.

[0008] In some embodiments, the side wall of the first retaining wall close to the display area gradually moves away from the display area in a direction away from the substrate and is sloped or stepped; the portion of the side wall of the first retaining wall away from the display area that is not connected to the connecting portion gradually moves closer to the display area in a direction away from the substrate and is sloped or stepped.

[0009] In some embodiments, a portion of the side wall of the second retaining wall on a side close to the display area that is not connected to the connecting portion gradually moves away from the display area in a direction away from the substrate and is sloped or stepped; the side wall of the second retaining wall on a side away from the display area gradually moves closer to the display area in a direction away from the substrate and is sloped or stepped.

[0010] In some embodiments, a slope of a portion of the side wall of the first retaining wall away from the display area that is not connected to the connecting portion is smaller than a slope of a portion of the side wall of the second retaining wall close to the display area that is not connected to the connecting portion.

[0011] In some embodiments, a slope of a side wall of the first retaining wall close to the display area is smaller than a slope of a side wall of the second retaining wall away from the display area.

[0012] In some embodiments, a portion of the side wall of the second retaining wall close to the display area that is not connected to the connecting portion gradually moves away from the display area in a direction away from the substrate; a portion of the side wall of the second retaining wall close to the display area that is not connected to the connecting portion is sloped or stepped.

[0013] In some embodiments, the display area includes a main display area and an auxiliary display area; the light transmittance of a portion of the display substrate located in the auxiliary display area is greater than the light transmittance of a portion of the display substrate located in the main display area.

[0014] In some embodiments, the display substrate further comprises: a plurality of first sub-pixels and a plurality of second sub-pixels arranged on one side of the substrate. The plurality of first sub-pixels are located in the main display area. The second sub-pixels comprise: a pixel driving circuit and a light-emitting device. The light-emitting device is arranged on a side of the pixel driving circuit away from the substrate, the light-emitting device is located in the auxiliary display area, and the light-emitting device is coupled to the pixel driving circuit. Among the plurality of second sub-pixels, at least one pixel driving circuit is located outside the auxiliary display area.

[0015] In some embodiments, the display substrate further comprises: a plurality of planar layers disposed between the pixel driving circuit and the light-emitting device and stacked in sequence, wherein the first barrier layers other than the first barrier layers farthest from the substrate in the plurality of first barrier layers are disposed in the same layer as some of the planar layers in the plurality of planar layers; and / or the second barrier layers other than the second barrier layers farthest from the substrate in the plurality of second barrier layers are disposed in the same layer as all of the planar layers in the plurality of planar layers.

[0016] In some embodiments, the display substrate further comprises: at least one wire layer, the wire layer comprising at least one light-transmitting wire; one of the pixel driving circuits located in the peripheral area is coupled to a corresponding one of the light-emitting devices via a light-transmitting wire. At least one flat layer is disposed between the at least one wire layer as a whole and the pixel driving circuit; at least one flat layer is disposed between the at least one wire layer as a whole and the light-emitting device.

[0017] In some embodiments, at least one layer of the planarization layer is disposed between two adjacent layers of the conductive line layers.

[0018] In some embodiments, the planar layer between the at least one conductive line layer as a whole and the pixel driving circuit is a first planar layer, and the number of layers of the first planar layer is one or two. When the number of layers of the first planar layer is one, the multiple first barrier layers include a first first barrier layer disposed on the same layer as the first planar layer, the multiple second barrier layers include a first second barrier layer disposed on the same layer as the first planar layer, and the at least one connecting layer includes a first connecting layer; the first connecting layer connects the first first barrier layer and the first second barrier layer.

[0019] In some embodiments, when the number of layers of the first flat layer is two, the multiple first barrier layers further include a second first barrier layer arranged on the same layer as another first flat layer, the multiple second barrier layers further include a second second barrier layer arranged on the same layer as another first flat layer, and the at least one connecting layer further includes a second connecting layer; the second connecting layer connects the second first barrier layer and the second second barrier layer.

[0020] In some embodiments, the flat layer between two adjacent wire layers is a second flat layer. The number of wire layers is three, the flat layer between two adjacent wire layers close to the substrate is the first second flat layer, and the flat layer between two adjacent wire layers far from the substrate is the second second flat layer. The multiple first barrier layers include a third first barrier layer arranged in the same layer as the first second flat layer, and a fourth first barrier layer arranged in the same layer as the second second flat layer. The multiple second barrier layers include a third second barrier layer arranged in the same layer as the first second flat layer, and a fourth second barrier layer arranged in the same layer as the second second flat layer.

[0021] In some embodiments, the at least one connecting layer includes a third connecting layer and a fourth connecting layer; the third connecting layer connects the third first barrier layer and the third second barrier layer, and the fourth connecting layer connects the fourth first barrier layer and the fourth second barrier layer.

[0022] In some embodiments, the at least one connecting layer includes a third connecting layer; the third connecting layer connects the third first barrier layer and the third second barrier layer; and the fourth first barrier layer is disconnected from the fourth second barrier layer.

[0023] In some embodiments, the display substrate further comprises: a pixel defining layer disposed on a side of the multi-layer flat layer away from the substrate; and a plurality of support pads disposed on a surface of the pixel defining layer away from the substrate. A first barrier layer of the multi-layer first barrier layer that is farthest from the substrate is disposed in the same layer as the pixel defining layer or the plurality of support pads; a second barrier layer of the multi-layer second barrier layer that is farthest from the substrate is disposed in the same layer as the pixel defining layer or the plurality of support pads.

[0024] In some embodiments, when a first barrier layer farthest from the substrate among the multiple layers of first barrier layers is arranged in the same layer as the multiple support pads, a first barrier layer farthest from the substrate among the multiple layers of first barrier layers is arranged in the same layer as the pixel defining layer; when a second barrier layer farthest from the substrate among the multiple layers of second barrier layers is arranged in the same layer as the multiple support pads, a second barrier layer farthest from the substrate among the multiple layers of second barrier layers is arranged in the same layer as the pixel defining layer.

[0025] In some embodiments, the multi-layer first barrier layer further includes a fifth first barrier layer disposed in the same layer as the pixel defining layer or the plurality of support pads. The flat layer between the at least one wire layer as a whole and the light-emitting device is a third flat layer, and the third flat layer has one layer; the multi-layer second barrier layer further includes a fifth second barrier layer disposed in the same layer as the third flat layer, and a sixth second barrier layer disposed in the same layer as the pixel defining layer or the plurality of support pads. The fifth second barrier layer and the sixth second barrier layer are both disconnected from the fifth first barrier layer.

[0026] In some embodiments, the display substrate further includes: a barrier layer, one end of the barrier layer extending between two adjacent first barrier layers, and the other end of the barrier layer extending between two adjacent flat layers; the first barrier layer overlapped by one end of the barrier layer and the flat layer overlapped by the other end of the barrier layer are arranged on the same layer.

[0027] In some embodiments, the orthographic projection of the first barrier layer overlapped by one end of the barrier layer on the substrate is tangent to or overlaps with the orthographic projection of the flat layer located on the other end of the barrier layer away from the substrate on the substrate.

[0028] In some embodiments, when the display substrate includes multiple wire layers, the barrier layer is disposed on the same layer as at least one layer of the multiple wire layers.

[0029] In some embodiments, the display substrate further comprises: an encapsulation layer disposed on a side of the plurality of first sub-pixels and the plurality of second sub-pixels away from the substrate; the encapsulation layer is configured to encapsulate the plurality of first sub-pixels and the plurality of second sub-pixels on the substrate. The encapsulation layer comprises: a first inorganic layer; an organic layer disposed on a side of the first inorganic layer away from the substrate; and a second inorganic layer disposed on a side of the organic layer away from the substrate. The first retaining wall and the second retaining wall are used to block the organic layer; the first inorganic layer covers the first retaining wall and the second retaining wall, and the second inorganic layer covers the first retaining wall and the second retaining wall.

[0030] In some embodiments, among the multiple first barrier layers, a first barrier layer closest to the substrate is connected to a second barrier layer closest to the substrate through a connection layer to form a first connection portion, and a first barrier layer second closest to the substrate is connected to a second barrier layer second closest to the substrate through a connection layer to form a second connection portion. The display substrate further includes: a voltage signal line disposed on one side of the substrate, the voltage signal line is located in the peripheral area and is disposed around the display area; a region of the voltage signal line away from the display area is located between the first connection portion and the second connection portion, and an orthographic projection of an edge of the voltage signal line away from the display area on the substrate is located between an orthographic projection of an edge of the first connection portion close to the display area on the substrate and an orthographic projection of an edge of the first connection portion away from the display area on the substrate.

[0031] In some embodiments, the multiple layers of first barrier layers are arranged in at least one of the following ways: a first barrier layer among the multiple layers of first barrier layers that is farthest from the substrate covers a side of a first barrier layer among the multiple layers of first barrier layers that is second farthest from the substrate and faces the second barrier wall; or, a first barrier layer among the multiple layers of first barrier layers that is second farthest from the substrate covers a side of a first barrier layer among the multiple layers of first barrier layers that is third farthest from the substrate and faces the second barrier wall.

[0032] In some embodiments, the multiple layers of second barrier layers are arranged in at least one of the following ways: a second barrier layer farthest from the substrate among the multiple layers of second barrier layers covers a side of a second barrier layer second farthest from the substrate among the multiple layers of second barrier layers facing the first barrier wall; or, a second barrier layer second farthest from the substrate among the multiple layers of second barrier layers covers a side of a second barrier layer third farthest from the substrate among the multiple layers of second barrier layers facing the first barrier wall; or, a second barrier layer third farthest from the substrate among the multiple layers of second barrier layers covers a side of a second barrier layer fourth farthest from the substrate among the multiple layers of second barrier layers facing the first barrier wall.

[0033] In some embodiments, the connecting layer and the first barrier layer and the second barrier layer connected thereto are arranged in the same layer.

[0034] On the other hand, a method for manufacturing a display substrate is provided. The display substrate has a display area and a peripheral area. The manufacturing method comprises: providing a substrate; forming a first retaining wall, a connecting portion, and a second retaining wall located in the peripheral area and sequentially away from the display area on one side of the substrate; wherein the height of the second retaining wall is greater than the height of the first retaining wall; the height of the connecting portion is less than the height of the first retaining wall; and at least part of the first retaining wall, the connecting portion, and the second retaining wall are an integrated structure.

[0035] In some embodiments, the first retaining wall includes a plurality of first barrier layers stacked in sequence, and the second retaining wall includes a plurality of second barrier layers stacked in sequence; the total number of the second barrier layers is greater than the total number of the first barrier layers; the connecting portion includes at least one connecting layer; the total number of the connecting layers is less than the total number of the first barrier layers; at least one first barrier layer close to the substrate in the plurality of first barrier layers and at least one second barrier layer close to the substrate in the plurality of second barrier layers are connected by at least one connecting layer. In particular, one connecting layer connects one first barrier layer and one second barrier layer, and the connecting layer and the first barrier layer and the second barrier layer connected thereto are formed by the same patterning process.

[0036] On the other hand, a display device is provided, comprising: a display substrate as described in any of the above embodiments.

[0037] In some embodiments, the peripheral area of ​​the display substrate includes a binding area, and the binding area is located on a side of the second retaining wall away from the display area. The display device also includes: a touch driver chip located in the binding area of ​​the display substrate; a touch grid structure located in the display area of ​​the display substrate; and a plurality of signal transmission lines connecting the touch driver chip and the touch grid structure. The plurality of signal transmission lines are located on a side of the first retaining wall and the second retaining wall away from the substrate as a whole, and the orthographic projections of the plurality of signal transmission lines on the substrate partially overlap with the orthographic projections of the connection layer on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0039] Figure 1A structural diagram of a display device provided in some embodiments of the present disclosure;

[0040] Figure 2 A structural diagram of another display device provided for some embodiments of the present disclosure;

[0041] Figure 3 A partial structural diagram of a display device provided in some embodiments of the present disclosure;

[0042] Figure 4 A structural diagram of a display substrate provided for some embodiments of the present disclosure;

[0043] Figure 5 A partial structural diagram of a display substrate provided for some embodiments of the present disclosure;

[0044] Figure 6 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0045] Figure 7 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0046] Figure 8 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0047] Fig. 9 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0048] Fig.10 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0049] Fig.11 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0050] Fig.12 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0051] Fig.13 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0052] Fig.14 A partial structural diagram of another display substrate provided for some embodiments of the present disclosure;

[0053] Fig.15 A flow chart of a method for manufacturing a display substrate provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0058] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0061] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0062] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0063] As used herein, "perpendicular" and "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, that the difference between the two equalities is less than or equal to 5% of either one of them.

[0064] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0065] Some embodiments of the present disclosure provide a display device 1000. Figure 1 to Figure 3 The display device 1000 includes a display substrate 100 , a touch grid structure 200 , a touch driving chip 300 , and a plurality of signal transmission lines 400 .

[0066] For some examples, see Figure 1 and Figure 3 , the display device 1000 also includes an optical device 500 .

[0067] It should be noted that the optical device 500 may be of various types and may be selected and configured according to actual needs. For example, the optical device 500 may be a camera, an infrared receiver or an infrared transmitter, and the like.

[0068] For some examples, see Figure 4 The display substrate 100 has a display area A and a peripheral area B. The portion of the display substrate 100 located in the display area A can display images.

[0069] It should be noted that the present disclosure does not limit the location of the peripheral area B. For example, the peripheral area B may be located on one side, two sides, or three sides of the display area A. For another example, the peripheral area B may also be located around the display area A.

[0070] For some examples, see Figure 4 , the display area A includes a main display area A1 and an auxiliary display area A2. For example, the area of ​​the main display area A1 may be larger than the area of ​​the auxiliary display area A2.

[0071] It should be noted that the number of the auxiliary display area A2 can be one or more, which can be set according to actual needs. The positional relationship between the main display area A1 and the auxiliary display area A2 includes various types, which can be set according to actual needs.

[0072] For example, please refer to Figure 4, the auxiliary display area A2 is located next to the main display area A1, that is, a portion of the boundary of the auxiliary display area A2 overlaps a portion of the boundary of the main display area A1. At this time, the shape of the auxiliary display area A2 can be, for example, a rectangle, a rounded rectangle, a teardrop shape, or a semicircle.

[0073] For example, the main display area A1 may be located around the auxiliary display area A2, that is, the main display area A1 surrounds the auxiliary display area A2. In this case, the auxiliary display area A2 may be in a circular, elliptical or rectangular shape.

[0074] In some examples, the light transmittance of the portion of the display substrate 100 located in the auxiliary display area A2 is greater than the light transmittance of the portion of the display substrate 100 located in the main display area A1. This design can reduce the shielding of external light when external light passes through the portion of the display substrate 100 located in the auxiliary display area A2 and enters the optical device 500 so that the optical device 500 works, thereby improving the working performance of the optical device 500.

[0075] For some examples, see Figure 4 , the peripheral area B includes at least one binding area B1. Exemplarily, there may be a gap between the display area A and the binding area B1.

[0076] Below, the structure of the display device 1000 is schematically described by taking the optical device 500 as a camera, the number of auxiliary display areas A2 is one, the number of binding areas B1 is one, and the auxiliary display area A2 is located next to the main display area A1 as an example.

[0077] For some examples, see Figure 3 The optical device 500 is disposed on the non-light-exiting side of the display substrate 100 and is located in the auxiliary display area A2 of the display substrate 100. External light can pass through the display substrate 100 and enter the optical device 500, so that the optical device 500 can work.

[0078] For some examples, see Figure 3 The touch grid structure 200 may be disposed on the light-emitting side of the display substrate 100 and located in the display area A of the display substrate 100 . That is, the optical device 500 and the touch grid structure 200 are located on opposite sides of the display substrate 100 .

[0079] With such a design, the user can utilize the touch grid structure 200 to control the image to be displayed on the display substrate 100 , so that the display device 1000 has both a display function and a touch function.

[0080] For some examples, see Figure 2The touch driving chip 300 can be arranged in the binding area B1 and located on the same side of the display substrate 100 as the touch grid structure 200. The touch driving chip 300 can transmit a touch driving signal to the touch grid structure 200, and can also receive a touch sensing signal transmitted by the touch grid structure 200, so that the user can control the image to be displayed on the display substrate 100 through the touch grid structure 200.

[0081] For some examples, see Figure 2 , a plurality of signal transmission lines 400, the touch grid structure 200, and the touch driver chip 300 are located on the same side of the display substrate 100. One end of each signal transmission line 400 extends into the display area A and is electrically connected to the touch grid structure 200; the other end of each signal transmission line 400 extends into the binding area B1 and is electrically connected to the touch driver chip 300. In this way, the touch driver chip 300 and the touch grid structure 200 can realize the transmission of touch drive signals and touch sensing signals through the signal transmission lines 400.

[0082] At this time, since the touch grid structure 200 is located in the display area A and the touch driver chip 300 is located in the binding area B1, this means that the signal transmission line 400 needs to pass through the peripheral area B to achieve electrical connection between the touch grid structure 200 and the touch driver chip 300.

[0083] In some examples, when the optical device 500 is not working, the portion of the display substrate 100 located in the display area A can display images.

[0084] In some examples, when the optical device 500 is working (for example, when a user takes a selfie), the portion of the display substrate 100 located in the main display area A1 can present the image of the user's selfie, and the portion of the display substrate 100 located in the auxiliary display area A2 can present a black image, thereby more clearly showing the location of the optical device 500.

[0085] In other examples, during the operation of the optical device 500 (eg, a user taking a selfie), the portion of the display substrate 100 located in the main display area A1 and the portion located in the auxiliary display area A2 can present the user's selfie picture as a whole.

[0086] The structure of the display substrate 100 provided in some embodiments of the present disclosure is schematically described below with reference to the accompanying drawings.

[0087] In some embodiments, see Figure 4 , the display substrate 100 includes a substrate 1 .

[0088] It should be noted that there are various types of substrate 1, which can be selected according to actual needs.

[0089] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0090] Exemplarily, the substrate 1 may be a flexible substrate, such as a PET (Polyethyleneterephthalate) substrate, a PI (Polyimide) substrate, or a PEN (Polyethylene naphthalate diformic acid glycol ester) substrate.

[0091] In some embodiments, please refer to Figure 4 The display substrate 100 further includes: a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2 disposed on one side of the substrate 1. The plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 can cooperate with each other, so that the display substrate 100 can display images.

[0092] In some examples, each first subpixel P1 includes a pixel driving circuit and a light emitting device. The light emitting device may be located on a side of the pixel driving circuit away from the substrate 1 and electrically connected to the pixel driving circuit, and the pixel driving circuit is configured to provide a driving voltage to the light emitting device to control the light emitting state of the light emitting device.

[0093] See also Figure 4 and Figure 5 , each second sub-pixel P2 includes a pixel driving circuit 21 and a light emitting device 22. The light emitting device 22 may be located on a side of the pixel driving circuit 21 away from the substrate 1, and is electrically connected to the pixel driving circuit 21. The pixel driving circuit 21 is configured to provide a driving voltage to the light emitting device 22 to control the light emitting state of the light emitting device 22.

[0094] It should be noted that the structure of the pixel driving circuit included in the first sub-pixel P1 may be the same as the structure of the pixel driving circuit 21 included in the second sub-pixel P2. Exemplarily, the structure of the light-emitting device included in the first sub-pixel P1 may be the same as the structure of the light-emitting device 22 included in the second sub-pixel P2.

[0095] Exemplarily, the structure of the pixel driving circuit 21 may include multiple structures, which are not limited by the present disclosure. For example, the structure of the pixel driving circuit 21 may be a structure such as "6T1C", "7T1C", "6T2C" or "7T2C", wherein "T" represents a thin film transistor, the number before "T" represents the number of thin film transistors, and "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors. For another example, the thin film transistor included in the pixel driving circuit 21 may be a thin film transistor with a bottom gate structure, or a thin film transistor with a top gate structure.

[0096] Exemplarily, the structure of the light emitting device 22 may include multiple types, and the present disclosure does not limit this. For example, the structure of the light emitting device 22 may be an OLED (Organic Light Emitting Diode) device, or a QLED (Quantum Dot Light Emitting Diodes) device. For another example, the light emitting mode of the light emitting device 22 may be top light emission or bottom light emission.

[0097] Some embodiments of the present disclosure are schematically described by taking as an example that the thin film transistor in the pixel driving circuit 21 is a thin film transistor with a top gate structure, the light emitting device 22 is an OLED light emitting device, and the light emitting mode of the light emitting device 22 is top emission.

[0098] For some examples, see Figure 5 The pixel driving circuit in the first sub-pixel P1 can be electrically connected to the corresponding light-emitting device through the connection structure, and the pixel driving circuit 21 in the second sub-pixel P2 can be electrically connected to the corresponding light-emitting device 22 through the connection structure 11. This design is conducive to reducing the difficulty of wiring.

[0099] For some examples, see Figure 4 The display substrate 100 includes a plurality of first sub-pixels P1 located in the main display area A1. The display substrate 100 includes a plurality of second sub-pixels P2, each light emitting device 22 located in the auxiliary display area A2, and at least one pixel driving circuit 21 located outside the auxiliary display area A2.

[0100] Exemplarily, only one pixel driving circuit 21 in the plurality of second sub-pixels P2 is located outside the auxiliary display area A2, or the pixel driving circuit 21 in each second sub-pixel P2 is located outside the auxiliary display area A2.

[0101] It should be noted that the aforementioned area outside the auxiliary display area A2 may be, for example, located in the peripheral area B and / or the main display area A1.

[0102] Exemplarily, when only one pixel driving circuit 21 among the plurality of second sub-pixels P2 is located outside the auxiliary display area A2, the one pixel driving circuit 21 located outside the auxiliary display area A2 may be located in the peripheral area B or the main display area A1.

[0103] Exemplarily, when the pixel driving circuit 21 in each second sub-pixel P2 is located outside the auxiliary display area A2, that is, multiple pixel driving circuits 21 are located outside the auxiliary display area A2, the multiple pixel driving circuits 21 located outside the auxiliary display area A2 may all be located in the peripheral area B, or all be located in the main display area A1, or part may be located in the peripheral area B and the other part may be located in the main display area A1.

[0104] Exemplarily, if the pixel driving circuits 21 in the multiple second sub-pixels P2 are arranged in the peripheral area B and / or the main display area A1, then the multiple pixel driving circuits 21 can be arranged on the side of the peripheral area B and / or the main display area A1 close to the auxiliary display area A2, and the multiple pixel driving circuits 21 are arranged in sequence or in an array.

[0105] Since the pixel driving circuit 21 is mainly composed of metal lines, the metal lines can form a strong blocking effect on light. In some of the above examples, by setting at least one pixel driving circuit 21 outside the auxiliary display area A2, the number of pixel driving circuits 21 set in the auxiliary display area A2 can be reduced, so that when external light passes through the portion of the display substrate 100 located in the auxiliary display area A2 and is incident on the optical device 500 so that the optical device 500 works, the blocking of external light can be reduced, the transmittance of light passing through the display substrate 100 is increased, and the working performance of the optical device 500 is improved.

[0106] In some embodiments, see Figures 4 to 6 The display substrate further includes: an encapsulation layer 3 disposed on a side of the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 away from the substrate 1; the encapsulation layer 3 is configured to encapsulate the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 on the substrate 1.

[0107] In some examples, the orthographic projections of the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 on the substrate 1 are located within the orthographic projection range of the encapsulation layer 3 on the substrate 1. With such a design, the encapsulation layer 3 can be used to form a good encapsulation effect on the light-emitting device included in the first sub-pixel P1 and the light-emitting device 22 included in the second sub-pixel P2, thereby preventing the light-emitting device included in the first sub-pixel P1 and the light-emitting device 22 included in the second sub-pixel P2 from being corroded by external water vapor and / or oxygen, thereby affecting the light-emitting efficiency and service life.

[0108] For some examples, see Figure 4 and Figure 7 to Figure 14The encapsulation layer 3 may include: a first inorganic layer 31, an organic layer 32 disposed on a side of the first inorganic layer 31 away from the substrate 1, and a second inorganic layer 33 disposed on a side of the organic layer 32 away from the substrate 1. The first inorganic layer 31 and / or the second inorganic layer 33 may be made of, for example, an inorganic insulating material and prepared by a deposition process; the organic layer 32 may be made of, for example, an organic insulating material and prepared by an inkjet printing process.

[0109] Based on this, in some embodiments, please continue to refer to Figure 4 and Figure 7 to Figure 14 The display substrate 100 further includes: a first blocking wall 4 and a second blocking wall 5. The first blocking wall 4 and the second blocking wall 5 are used to block a portion of the encapsulation layer 3.

[0110] In some examples, the second blocking wall 5 is away from the display area A relative to the first blocking wall 4, and the first blocking wall 4 is away from the display area A relative to at least one pixel driving circuit 21 disposed in the peripheral area B. That is, in the display substrate 100, the pixel driving circuit 21 disposed in the peripheral area B, the first blocking wall 4, and the second blocking wall 5 are away from the display area A in sequence.

[0111] For example, see Figure 4 The first retaining wall 4 and the second retaining wall 5 can be arranged at the edge of the display substrate 100 and are arranged in a ring shape. The first retaining wall 4 surrounds the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2, and the second retaining wall 5 surrounds the first retaining wall 4.

[0112] For example, the first inorganic layer 31 can cover the first blocking wall 4 and the second blocking wall 5 while covering the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 to form a better packaging effect.

[0113] The organic layer 32 may be located within the range defined by the first retaining wall 4, that is, the orthographic projection of the organic layer 32 on the substrate 1 is located within the orthographic projection range of the first retaining wall 4 on the substrate 1. This means that the first retaining wall 4 can block the organic layer 32 in the encapsulation layer 3 to ensure a good encapsulation effect.

[0114] Exemplarily, the height of the second retaining wall 5 is greater than the height of the first retaining wall 4. The height of the second retaining wall 5 may be the vertical distance between the end of the second retaining wall 5 away from the substrate 1 and the substrate 1. The height of the first retaining wall 4 may be the vertical distance between the end of the first retaining wall 4 away from the substrate 1 and the substrate 1.

[0115] It should be noted that, due to the process of preparing and forming the organic layer 32, there will inevitably be certain errors, which may cause the first retaining wall 4 to fail to form a good barrier for the organic layer 32. In the above example, by setting the height of the second retaining wall 5 to be greater than the height of the first retaining wall 4, the second retaining wall 5 is used to further block the organic layer 32, thereby improving the blocking effect on the organic layer 32, and further improving the encapsulation effect of the encapsulation layer 3.

[0116] Exemplarily, the second inorganic layer 33 may cover the organic layer 32 and the first inorganic layer 31 , and while covering the first inorganic layer 31 , also cover the first retaining wall 4 and the second retaining wall 5 to form a better encapsulation effect.

[0117] It should be noted that since the orthographic projection of the organic layer 32 on the substrate 1 is located within the orthographic projection range of the first retaining wall 4 on the substrate 1, and the first inorganic layer 31 and the second inorganic layer 33 cover the first retaining wall 4 and the second retaining wall 5, the portions of the first inorganic layer 31 and the second inorganic layer 33 that extend beyond the organic layer 32 can form contact.

[0118] For some examples, see Figure 7 to Figure 14 The display substrate 100 further includes a connecting portion 15 located between the first retaining wall 4 and the second retaining wall 5, wherein the connecting portion 15 connects the first retaining wall 4 and the second retaining wall 5; wherein at least a portion of the first retaining wall 4, the connecting portion 15 and the second retaining wall 5 are an integrated structure.

[0119] It should be noted that at least part of the first retaining wall 4 , the connecting portion 15 and the second retaining wall 5 are an integrated structure. For example, a part of the first retaining wall 4 , a part of the connecting portion 15 and a part of the second retaining wall 5 may be an integrated structure.

[0120] Exemplarily, the height of the connection portion 15 is less than the height of the first retaining wall 4. The height of the connection portion 15 may be the vertical distance between the end of the connection portion 15 away from the substrate 1 and the substrate 1, and the height of the first retaining wall 4 may be the vertical distance between the end of the first retaining wall 4 away from the substrate 1 and the substrate 1.

[0121] In some of the above examples, a gap is formed between the first retaining wall 4 and the second retaining wall 5. By connecting the first retaining wall 4 and the second retaining wall 5 through the connecting portion 15, the step difference between the first retaining wall 4 and the gap, and the step difference between the second retaining wall 5 and the gap can be reduced.

[0122] On this basis, the signal transmission line 400 in the display device 1000 can be prepared and formed by, for example, a photolithography process. That is, in the process of forming the signal transmission line 400 on the light-emitting side of the display substrate 100 (that is, the side of the encapsulation layer 3 away from the substrate 1), a deposition process can be used to form a conductive material film, and then a photoresist is coated on the side of the conductive material film away from the substrate 1, and then the photoresist is exposed and developed, and the conductive material film is patterned to obtain the signal transmission line 400. At this time, since the signal transmission line 400 needs to pass through the peripheral area B to achieve the connection between the touch grid structure 200 and the touch driver chip 300, the orthographic projection of the signal transmission line 400 on the substrate 1 will overlap with the orthographic projection of the connecting portion 15 on the substrate 1, that is, part of the signal transmission line 400 will cover the gap between the first retaining wall 4 and the second retaining wall 5 (such as Figure 7 to Figure 12 shown).

[0123] In some of the above examples, by reducing the step difference between the first retaining wall 4 and the gap and the step difference between the second retaining wall 5 and the gap, the thickness of the photoresist in the gap can be reduced during the process of preparing the signal transmission line 400 using a photolithography process. In this way, during the exposure and development of the photoresist, residual photoresist in the gap can be avoided, and further during the patterning of the conductive material film, the formation of conductive material residue can be avoided, ultimately avoiding a short circuit in the signal transmission line 400, thereby improving the yield of the display device 1000.

[0124] In some embodiments, see Figure 7 to Figure 13 The first retaining wall 4 includes a plurality of first barrier layers 41 stacked in sequence, and the second retaining wall 5 includes a plurality of second barrier layers 51 stacked in sequence.

[0125] It should be noted that there are many ways to set the multi-layer first barrier layer 41 included in the first retaining wall 4 and the multi-layer second barrier layer 51 included in the second retaining wall 5, and the setting can be selected according to actual needs.

[0126] In some examples, the total number of layers of the second barrier layer 51 is greater than the total number of layers of the first barrier layer 41 .

[0127] In some of the above examples, by setting multiple layers of first barrier layers 41 to form the first barrier wall 4 and setting multiple layers of second barrier layers 51 to form the second barrier wall 5, the height of the first barrier wall 4 and the second barrier wall 5 can be effectively increased, thereby facilitating the blocking and leveling effects on the organic layer 32 in the encapsulation layer 3 and ensuring a good encapsulation effect of the encapsulation layer 3.

[0128] For some examples, see Figure 7 to Figure 13 The connecting portion 15 includes at least one connecting layer 10 , and the total number of connecting layers 10 is less than the total number of first barrier layers 41 .

[0129] Exemplarily, at least one first barrier layer 41 close to the substrate among the multiple first barrier layers 41 and at least one second barrier layer 51 close to the substrate among the multiple second barrier layers 51 are connected by at least one connecting layer 10. For example, one connecting layer 10 connects one first barrier layer 41 and one second barrier layer 51.

[0130] For example, the connection layer 10 and the first barrier layer 41 and the second barrier layer 51 connected thereto are arranged in the same layer. The first barrier wall 4, the second barrier wall 5 and the connection layer 10 may be, for example, an integral structure.

[0131] For some examples, see Figure 7 to Figure 14 The side wall of the first retaining wall 4 close to the display area A gradually moves away from the display area A in the direction Z away from the substrate 1 .

[0132] For example, the side wall of the first retaining wall 4 close to the display area A may be, for example, Figure 7 to Figure 14 The slope shown may be in the form of a ramp, or may be in the form of steps.

[0133] For some examples, see Figure 7 to Figure 14 The portion of the side wall of the first retaining wall 4 that is not connected to the connecting portion 15 on the side away from the display area A gradually approaches the display area A in the direction Z away from the substrate 1 .

[0134] For example, the portion of the side wall of the first retaining wall 4 that is away from the display area A and is not connected to the connecting portion 15 may be, for example, Figure 7-Figure 8 and Figure 11 to Figure 14 The slope shown, or it may be, for example, Figure 9-10 The steps shown.

[0135] For some examples, see Figure 7 to Figure 14 The portion of the side wall of the second retaining wall 5 that is not connected to the connecting portion 15 on the side close to the display area A gradually moves away from the display area A in the direction Z away from the substrate 1 .

[0136] For example, the portion of the side wall of the second retaining wall 5 close to the display area A that is not connected to the connecting portion 15 may be, for example, Figure 8 to Figure 10 The slope shown, or it may be, for example, Figure 7 and Figure 11 to Figure 14 The steps shown.

[0137] For some examples, see Figure 7 to Figure 14 The side wall of the second retaining wall 5 away from the display area A gradually approaches the display area A in the direction away from the substrate 1.

[0138] For example, the side wall of the second retaining wall 5 away from the display area A may be, for example, Figure 7 to Figure 14The slope shown may be in the form of a ramp, or may be in the form of steps.

[0139] For some examples, see Fig.14 The slope of the portion of the side wall of the first retaining wall 4 that is away from the display area A and is not connected to the connecting portion 15 (that is, the ratio of the elevation difference h1 of the portion to the horizontal distance L1 of the portion) is smaller than the slope of the portion of the side wall of the second retaining wall 5 that is close to the display area A and is not connected to the connecting portion 15 (that is, the ratio of the elevation difference h2 of the portion to the horizontal distance L2 of the portion).

[0140] Some of the above examples can further ensure the blocking and leveling effect of the second retaining wall 5 on the organic layer 32 in the encapsulation layer 3 by relatively increasing the slope of the portion of the side wall of the second retaining wall 5 close to the display area A that is not connected to the connecting portion 15, thereby further ensuring a good encapsulation effect of the encapsulation layer 3.

[0141] For some examples, see Fig.14 The slope of the side wall of the first retaining wall 4 close to the display area A (that is, the ratio of the elevation difference h3 of the side wall to the horizontal distance L3 of the side wall) is smaller than the slope of the side wall of the second retaining wall 5 away from the display area A (that is, the ratio of the elevation difference h4 of the side wall to the horizontal distance L4 of the side wall).

[0142] In some of the above examples, the size of the display substrate 100 can be reduced by relatively increasing the slope of the side wall of the second retaining wall 5 away from the display area A, thereby saving materials and reducing manufacturing costs.

[0143] It is easy to understand that the method of calculating the slope is not only applicable to the case where at least one of the four parts, namely, the part of the side wall of the first retaining wall 4 away from the display area A that is not connected to the connecting portion 15, the part of the side wall of the second retaining wall 5 close to the display area A that is not connected to the connecting portion 15, the side wall of the first retaining wall 4 close to the display area A, and the side wall of the second retaining wall 5 away from the display area A, is in a slope shape. The method of calculating the slope is also equally applicable when at least one of the four parts, namely, the part of the side wall of the first retaining wall 4 away from the display area A that is not connected to the connecting portion 15, the part of the side wall of the second retaining wall 5 close to the display area A that is not connected to the connecting portion 15, the side wall of the first retaining wall 4 close to the display area A, and the side wall of the second retaining wall 5 away from the display area A, is in a stepped shape.

[0144] It should be noted that after increasing the height of the first retaining wall 4 and the second retaining wall 5, the depth of the gap formed between the first retaining wall 4 and the second retaining wall 5 in the direction Z away from the substrate 1 will also increase. By connecting the corresponding at least one first barrier layer 41 and at least one second barrier layer 51 through at least one connecting layer 10, the step difference between the first retaining wall 4 and the gap, and the step difference between the second retaining wall 5 and the gap can also be reduced.

[0145] Therefore, in the display substrate 100 provided in some embodiments of the present disclosure, after at least one pixel driving circuit 21 among the above-mentioned multiple second sub-pixels P2 is set in the peripheral area B, a first blocking wall 4 composed of multiple layers of first blocking layers 41 and a second blocking wall 5 composed of multiple layers of second blocking layers 51 can be set in the peripheral area B to achieve a blocking effect on a part of the encapsulation layer 3 and ensure the encapsulation effect of the encapsulation layer 3.

[0146] It should be noted that, in the case where the optical device 500 is arranged below the display substrate 100, the light-emitting device 22 and the pixel driving circuit 21 above the optical device 500 are separated, the electrical connection between the two is achieved through at least one layer of wire, and an insulating layer is arranged between the light-emitting device and the wire, between two adjacent layers of wire, and between the wire and the pixel driving circuit, the thickness of the portion of the display substrate 100 located in the display area A will increase. However, the first retaining wall 4 composed of multiple layers of first barrier layers 41 and the second retaining wall 5 composed of multiple layers of second barrier layers 51 in some embodiments of the present disclosure can still achieve a blocking effect on a portion of the encapsulation layer 3, thereby ensuring the encapsulation effect of the encapsulation layer 3.

[0147] Moreover, by providing at least one connection layer 10 to connect the corresponding at least one first barrier layer 41 and at least one second barrier layer 51, the orthographic projection of the gap between the first barrier wall 4 and the second barrier wall 5 on the substrate 1 overlaps with the orthographic projection of at least one connection layer 10 on the substrate 1, which can effectively reduce the step difference between the first barrier wall 4 and the gap, and reduce the step difference between the second barrier wall 5 and the gap. In this way, when the display substrate 100 is applied to the display device 1000, the conductive material residue of the signal transmission line 400 can be effectively avoided, thereby avoiding the short circuit of the signal transmission line 400, and improving the yield of the display device 1000.

[0148] In some embodiments, see Figure 5 and Figure 6 The display substrate 100 further includes a multi-layer planarization layer 7. The multi-layer planarization layer 7 is disposed between the pixel driving circuit 21 and the light emitting device 22 located in the peripheral area B, and is stacked in sequence.

[0149] Among them, the first barrier layers 41 except the one or two first barrier layers 41 farthest from the substrate 1 in the multi-layer first barrier layers 41 are respectively arranged in the same layer with part of the flat layers 7 in the multi-layer flat layers 7; and / or, the second barrier layers 51 except the one or two second barrier layers 51 farthest from the substrate 1 in the multi-layer second barrier layers 51 are respectively arranged in the same layer with all the flat layers 7 in the multi-layer flat layers 7.

[0150] It should be noted that the partial flat layers 7 in the multi-layer flat layers 7 may be some of the multi-layer flat layers 7 .

[0151] For some examples, see Figure 5 and Figure 6 The display substrate 100 further includes a pixel defining layer 8 disposed on a side of the multi-layer flat layer 7 that is away from the substrate 1 as a whole; and a plurality of support pads 16 disposed on a surface of the pixel defining layer 8 that is away from the substrate 1 .

[0152] Among them, the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 is arranged on the same layer as the pixel defining layer 8 or multiple support pads 16; and / or the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 is arranged on the same layer as the pixel defining layer 8 or multiple support pads 16.

[0153] Exemplarily, the pixel defining layer 8 has a plurality of openings, each of which is provided with at least a portion of a light emitting device 22. By configuring the pixel defining layer 8 in this way, the light emitting regions of the first sub-pixel P1 and the second sub-pixel P2 can be defined.

[0154] Exemplarily, when the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 is arranged in the same layer as the multiple support pads 16 , the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 is arranged in the same layer as the pixel defining layer 8 .

[0155] When the second barrier layer 51 farthest from the substrate 1 among the multiple second barrier layers 51 is arranged in the same layer as the plurality of support pads 16 , the second barrier layer 51 farthest from the substrate 1 among the multiple second barrier layers 51 is arranged in the same layer as the pixel defining layer 8 .

[0156] For some examples, see Figure 5 and Figure 6 , the display substrate 100 further includes at least one wire layer 6, each wire layer 6 includes at least one light-transmitting wire 61, and a pixel driving circuit 21 located in the peripheral area B is electrically connected to a corresponding light-emitting device 22 through a light-transmitting wire 61. That is, one end of the light-transmitting wire 61 can extend into the peripheral area B and be electrically connected to the pixel driving circuit 21 (for example, electrically connected to the pixel driving circuit 21 through the connecting structure 11); the other end of the light-transmitting wire 61 can extend into the auxiliary display area A2 and be electrically connected to the corresponding light-emitting device 22. The pixel driving circuit 21 located in the peripheral area B provides a driving voltage to the corresponding light-emitting device 22 through the light-transmitting wire 61 to control the light-emitting state of the corresponding light-emitting device 22.

[0157] For example, the number of the light-transmitting wires 61 may be equal to the number of the pixel driving circuits 21 located in the peripheral area B.

[0158] Exemplarily, the number of layers of the wire layer 6 can be two or three. For example, the number of layers of the wire layer 6 is three. This design can provide sufficient space for the routing of the light-transmitting wires 61, thereby preventing interference between each light-transmitting wire 61.

[0159] It should be noted that since the pixel driving circuit 21 is electrically connected to the corresponding light emitting device 22 via the light-transmitting wire 61 , an insulating layer needs to be provided between the pixel driving circuit 21 and the wire layer 6 , and an insulating layer needs to be provided between the wire layer 6 and the light emitting device 22 .

[0160] Exemplarily, at least one flat layer 7 (also the above-mentioned insulating layer) is disposed between the at least one wire layer 6 as a whole and the pixel driving circuit 21; at least one flat layer 7 (also the above-mentioned insulating layer) is disposed between the at least one wire layer 6 as a whole and the light-emitting device 22. This design can ensure the flatness and continuity of the wire layer 6.

[0161] It should be noted that, when the display substrate 100 includes multiple layers of wire layers 6 , an insulating layer needs to be provided between two adjacent wire layers 6 .

[0162] Exemplarily, at least one flat layer 7 (ie, the above-mentioned insulating layer) is disposed between two adjacent wire layers 6 .

[0163] It should be noted that the number of the above-mentioned planar layers 7 is related to the total number of the wire layers 6 .

[0164] For some examples, see Figure 5 , the total number of layers of the wire layer 6 is one layer, that is, the light-transmitting wires 61 are arranged in the same layer. On this basis, each light-transmitting wire 61 can be connected to the pixel driving circuit 21 located in the peripheral area B through the connecting structure 11, for example; and each light-transmitting wire 61 is also electrically connected to the corresponding light-emitting device 22 located in the auxiliary display area A2. At this time, for example, only one flat layer 7 can be arranged between the above-mentioned wire layer 6 and the connecting structure 11; for example, only one flat layer 7 can be arranged between the above-mentioned connecting structure 11 and the pixel driving circuit 21; for example, only one flat layer 7 can be arranged between the above-mentioned wire layer 6 and the light-emitting device 22. Therefore, the display substrate 100 may include three layers of flat layers 7 stacked in sequence.

[0165] For other examples, see Figure 6 The total number of conductor layers 6 is multiple layers, that is, multiple light-transmitting conductors 61 are located in multiple layers, each conductor layer 6 includes at least one light-transmitting conductor 61 , and at least one flat layer 7 is arranged between two adjacent conductor layers 6 .

[0166] Exemplarily, the total number of layers of the wire layer 6 is three. On this basis, each light-transmitting wire 61 can be connected to the corresponding pixel driving circuit 21 located in the peripheral area B, for example, through the connecting structure 11; and each light-transmitting wire 61 is also electrically connected to the corresponding light-emitting device 22 located in the auxiliary display area A2. At this time, among the above-mentioned three layers of wire layers 6, for example, only one flat layer 7 can be arranged between each two adjacent layers of wire layers 6; for example, only one flat layer 7 can be arranged between a layer of wire layer 6 closest to the pixel driving circuit 21 and the connecting structure 11; for example, only one flat layer 7 can be arranged between the connecting structure 11 and the pixel driving circuit 21; for example, only one flat layer 7 can be arranged between a layer of wire layer 6 closest to the light-emitting device 22 and the light-emitting device 22. Therefore, the display substrate 100 can include five layers of flat layers 7 stacked in sequence.

[0167] Exemplarily, when the total number of wire layers 6 is three, one of the wire layers 6 can be electrically connected to the light-emitting devices 22 that can emit red light, another layer of the wire layers 6 can be electrically connected to the light-emitting devices 22 that can emit green light, and the last layer of the wire layers 6 can be electrically connected to the light-emitting devices 22 that can emit blue light.

[0168] It is easy to understand that the "same layer" mentioned in each embodiment of the present disclosure refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the above-mentioned multiple light-transmitting wires 61 can be prepared and formed simultaneously in a single patterning process, which is conducive to simplifying the preparation process of the display substrate 100.

[0169] Exemplarily, the light-transmitting wire 61 may be formed of a conductive material with high light transmittance, such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).

[0170] In some of the above examples, by using a light-transmitting wire 61 to connect the corresponding pixel driving circuit 21 and the light-emitting device 22, it is beneficial to further improve the light transmittance of the portion of the display substrate 100 located in the auxiliary display area A2 and improve the working performance of the optical device 500.

[0171] In some examples, the planar layer 7 between at least one layer of conductive line layer 6 and the pixel driving circuit 21 is the first planar layer 71 ; among the multiple second barrier layers 51 , the second barrier layer 51 arranged on the same layer as the first planar layer 71 is connected to the corresponding first barrier layer 41 through a connecting layer 10 .

[0172] Exemplarily, at least one wire layer 6 is directly electrically connected to the pixel driving circuit 21 as a whole, and only one flat layer 7 is provided between at least one wire layer 6 as a whole and the pixel driving circuit 21 , and the number of layers of the first flat layer 71 is one.

[0173] For example, see Figure 5 and Figure 6 At least one layer of the conductive wire layer 6 is electrically connected to the pixel driving circuit 21 through the connecting structure 11. For example, only one layer of flat layer 7 is arranged between at least one layer of the conductive wire layer 6 and the connecting structure 11. For example, only one layer of flat layer 7 is arranged between the connecting structure 11 and the pixel driving circuit 21. Then, the number of layers of the above-mentioned first flat layer 71 is two.

[0174] For some examples, see Figure 6 The flat layer 7 between two adjacent wire layers 6 is a second flat layer 72 ; among the multiple second barrier layers 51 , at least one second barrier layer 51 disposed on the same layer as at least one second flat layer 72 is connected to the corresponding at least one first barrier layer 41 through at least one connecting layer 10 .

[0175] For some examples, see Figure 6 The flat layer 7 between at least one wire layer 6 and the light emitting device 22 is a third flat layer 73; the multiple second barrier layers 51 also include at least one second barrier layer 51 disposed on the same layer as the at least one third flat layer 73. Exemplarily, the third flat layer 73 may be one layer.

[0176] For example, please refer to Figure 6, the total number of layers of the wire layer 6 is three, and the wire layer 6 as a whole is electrically connected to the pixel driving circuit 21 through the connecting structure 11. A flat layer 7 is arranged between the wire layer 6 as a whole and the connecting structure 11, a flat layer 7 is arranged between the connecting structure 11 and the pixel driving circuit 21, a flat layer 7 is arranged between each two adjacent wire layers 6, and a flat layer 7 is arranged between the wire layer 6 as a whole and the light-emitting device 22. That is, the number of layers of the first flat layer 71 is two, the number of layers of the second flat layer 72 is two, and the number of layers of the third flat layer 73 is one. In addition, the number of layers of the pixel defining layer 8 is one, and the number of layers of the plurality of support pads 16 is one. Therefore, the first retaining wall 4 includes five layers of first barrier layers 41 stacked in sequence, and the five layers of first barrier layers 41 can, for example, be arranged in sequence along the direction Z away from the substrate 1 with two layers of first flat layers 71, two layers of second flat layers 72 and a pixel defining layer 8 (or a support pad 16); the second retaining wall 5 includes six layers of second barrier layers 51 stacked in sequence, and the six layers of second barrier layers 51 can, for example, be arranged in sequence along the direction Z away from the substrate 1 with two layers of first flat layers 71, two layers of second flat layers 72, one layer of third flat layer 73 and a pixel defining layer 8 (or a support pad 16).

[0177] On this basis, the display substrate 100 may include, for example Figure 7 The four connecting layers 10 shown in the figure can be respectively arranged in the same layer with the two first flat layers 71 and the two second flat layers 72 along the direction Z away from the substrate 1. At this time, along the direction Z perpendicular to the substrate 1 and away from the substrate 1, the first connecting layer 10 connects the first first barrier layer 41 and the first second barrier layer 51 to form an integral structure; the second connecting layer 10 connects the second first barrier layer 41 and the second second barrier layer 51 to form an integral structure; the third connecting layer 10 connects the third first barrier layer 41 and the third second barrier layer 51 to form an integral structure; the fourth connecting layer 10 connects the fourth first barrier layer 41 and the fourth second barrier layer 51 to form an integral structure; the fifth second barrier layer 51 and the sixth second barrier layer 51 are both disconnected from the fifth first barrier layer 41.

[0178] The fifth first barrier layer 41 in the first barrier wall 4 and the fifth and sixth second barrier layers 51 in the second barrier wall 5 form a gap between the first barrier wall 4 and the second barrier wall 5. The orthographic projection of the first connecting layer 10 on the substrate 1, the orthographic projection of the second connecting layer 10 on the substrate 1, the orthographic projection of the third connecting layer 10 on the substrate 1, the orthographic projection of the fourth connecting layer 10 on the substrate 1, and the orthographic projection of the above gap on the substrate 1 overlap. At this time, the step difference between the first barrier wall 4 and the gap is the thickness of the fifth first barrier layer 41, and the step difference between the second barrier wall 5 and the gap is the sum of the thickness of the fifth and sixth second barrier layers 51.

[0179] Alternatively, the display substrate 100 may also include, for example Figure 8 The three-layer connection layer 10 shown in the figure can be respectively arranged in the same layer with the two first flat layers 71 and the first second flat layer 72 along the direction Z away from the substrate 1. At this time, along the direction Z perpendicular to the substrate 1 and away from the substrate 1, the first connection layer 10 connects the first first barrier layer 41 and the first second barrier layer 51 to form an integral structure; the second connection layer 10 connects the second first barrier layer 41 and the second second barrier layer 51 to form an integral structure; the third connection layer 10 connects the third first barrier layer 41 and the third second barrier layer 51 to form an integral structure; the fourth second barrier layer 51, the fifth second barrier layer 51, and the sixth second barrier layer 51 are disconnected from the fourth first barrier layer 41 and the fifth first barrier layer 41 as a whole.

[0180] The fourth first barrier layer 41 and the fifth first barrier layer 41 in the first barrier wall 4 and the fourth second barrier layer 51, the fifth second barrier layer 51 and the sixth second barrier layer 51 in the second barrier wall 5 form a gap between the first barrier wall 4 and the second barrier wall 5. The orthographic projection of the first connecting layer 10 on the substrate 1, the orthographic projection of the second connecting layer 10 on the substrate 1, the orthographic projection of the third connecting layer 10 on the substrate 1 and the orthographic projection of the above gap on the substrate 1 overlap. At this time, the step difference between the first barrier wall 4 and the gap is the sum of the thickness of the fourth first barrier layer 41 and the fifth first barrier layer 41, and the step difference between the second barrier wall 5 and the gap is the sum of the thickness of the fourth second barrier layer 51, the fifth second barrier layer 51 and the sixth second barrier layer 51.

[0181] Alternatively, the display substrate 100 may also include, for example Fig. 9 The two connecting layers 10 shown in the figure can be respectively arranged in the same layer with the two first flat layers 71 along the direction Z away from the substrate 1. At this time, along the direction Z perpendicular to the substrate 1 and away from the substrate 1, the first connecting layer 10 connects the first first barrier layer 41 and the first second barrier layer 51 to form an integral structure; the second connecting layer 10 connects the second first barrier layer 41 and the second second barrier layer 51 to form an integral structure; the third second barrier layer 51, the fourth second barrier layer 51, the fifth second barrier layer 51, and the sixth second barrier layer 51 are disconnected from the third first barrier layer 41, the fourth first barrier layer 41, and the fifth first barrier layer 41 as a whole.

[0182] The third first barrier layer 41, the fourth first barrier layer 41, the fifth first barrier layer 41 in the first barrier wall 4 and the third second barrier layer 51, the fourth second barrier layer 51, the fifth second barrier layer 51, the sixth second barrier layer 51 in the second barrier wall 5 form a gap between the first barrier wall 4 and the second barrier wall 5. The orthographic projection of the first connection layer 10 on the substrate 1, the orthographic projection of the second connection layer 10 on the substrate 1 and the orthographic projection of the above gap on the substrate 1 overlap. At this time, the step difference between the first barrier wall 4 and the gap is the sum of the thicknesses of the third first barrier layer 41, the fourth first barrier layer 41, and the fifth first barrier layer 41, and the step difference between the second barrier wall 5 and the gap is the sum of the thicknesses of the third second barrier layer 51, the fourth second barrier layer 51, the fifth second barrier layer 51, and the sixth second barrier layer 51.

[0183] It should be noted that, when the first retaining wall 4 includes the fifth first blocking layer 41 arranged on the same layer as the pixel defining layer 8, and the second retaining wall 5 includes the sixth second blocking layer 51 arranged on the same layer as the pixel defining layer 8, the first retaining wall 4 may also include the sixth first blocking layer 41 arranged on the same layer as the support pad 16, and the second retaining wall 5 may also include the seventh second blocking layer 51 arranged on the same layer as the support pad 16, and the sixth first blocking layer 41 is disconnected from the seventh second blocking layer 51.

[0184] In some of the above examples, by controlling the overall thickness of at least one connecting layer 10, that is, controlling the vertical distances from the top of the first retaining wall 4 and the top of the second retaining wall 5 to the top of at least one connecting layer 10 as a whole, it is possible to effectively avoid residual conductive material of the signal transmission line 400 while increasing the depth of the gap formed between the first retaining wall 4 and the second retaining wall 5 as much as possible, so as to further improve the blocking and leveling effects of the first retaining wall 4 and the second retaining wall 5 on the organic layer 32, thereby further ensuring a good encapsulation effect of the encapsulation layer 3.

[0185] In some embodiments, the multi-layer first barrier layer 41 is arranged in at least one of the following ways:

[0186] The first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 covers the side of the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 facing the second barrier wall 5; or, the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 covers the side of the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 facing the second barrier wall 5.

[0187] It should be noted that the above configuration is performed in at least one manner, for example, it may be configured in only one manner, or it may be configured in a combination of two or more manners at the same time.

[0188] For some examples, see Figure 8 Only the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 covers the side of the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 facing the second barrier wall 5 .

[0189] For other examples, see Fig. 9 and Fig.10 Only the first barrier layer 41 which is the second farthest from the substrate 1 among the multiple first barrier layers 41 covers the side of the first barrier layer 41 which is the third farthest from the substrate 1 among the multiple first barrier layers 41 and faces the second barrier wall 5 .

[0190] For some more examples, see Fig.11 , the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 covers the side of the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 facing the second barrier wall 5; the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 covers the side of the first barrier layer 41 farthest from the substrate 1 among the multiple layers of first barrier layers 41 facing the second barrier wall 5.

[0191] In some embodiments, the multi-layer second barrier layer 51 is arranged in at least one of the following ways:

[0192] The second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4; or, the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4; or, the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4.

[0193] It should be noted that the above configuration is performed in at least one manner, for example, it may be configured in only one manner, or it may be configured in a combination of two or more manners at the same time.

[0194] For some examples, see Figure 7 Only the second barrier layer 51 farthest from the substrate 1 among the multiple second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple second barrier layers 51 facing the first barrier wall 4 .

[0195] For other examples, see Figure 8Only the second barrier layer 51 which is the second farthest from the substrate 1 among the multiple second barrier layers 51 covers the side of the second barrier layer 51 which is the third farthest from the substrate 1 among the multiple second barrier layers 51 and faces the first barrier wall 4 .

[0196] For some more examples, see Fig. 9 Only the second barrier layer 51 which is the third farthest from the substrate 1 among the multiple second barrier layers 51 covers the side of the second barrier layer 51 which is the fourth farthest from the substrate 1 among the multiple second barrier layers 51 and faces the first barrier wall 4 .

[0197] For some more examples, see Fig.10 , the second barrier layer 51 which is the second farthest from the substrate 1 among the multiple second barrier layers 51 covers the side of the second barrier layer 51 which is the third farthest from the substrate 1 among the multiple second barrier layers 51 and faces the first barrier wall 4; the second barrier layer 51 which is the third farthest from the substrate 1 among the multiple second barrier layers 51 covers the side of the second barrier layer 51 which is the fourth farthest from the substrate 1 among the multiple second barrier layers 51 and faces the first barrier wall 4.

[0198] For some more examples, see Fig.11 , the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4; the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4; the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 covers the side of the second barrier layer 51 farthest from the substrate 1 among the multiple layers of second barrier layers 51 facing the first barrier wall 4.

[0199] In some embodiments, see Fig.12 Among the multiple layers of first barrier layers 41, the first barrier layer 41 closest to the substrate 1 is connected to the second barrier layer 51 closest to the substrate 1 through a connecting layer 10 to form a first connecting portion 12, and the first barrier layer 41 second closest to the substrate 1 is connected to the second barrier layer 51 second closest to the substrate 1 through a connecting layer 10 to form a second connecting portion 13.

[0200] The display substrate 100 further includes a voltage signal line 14 disposed on one side of the substrate 1. The voltage signal line 14 is located in the peripheral area B and is disposed around the display area A.

[0201] The area of ​​the voltage signal line 14 away from the display area A is located between the first connecting portion 12 and the second connecting portion 13, and the orthographic projection of the edge of the voltage signal line 14 away from the display area A on the substrate 1 is located between the orthographic projection of the edge of the first connecting portion 12 close to the display area A on the substrate 1 and the orthographic projection of the edge of the first connecting portion 12 away from the display area A on the substrate 1.

[0202] It should be noted that since the first connecting part 12 is an organic insulating layer and the voltage signal line 14 is a metal layer, some of the above examples control the voltage signal line 14 to only cover part of the first connecting part 12, thereby avoiding the water vapor generated by the organic insulating layer from being blocked by the metal layer, so that it can be smoothly dissipated. On this basis, as time goes by, even if the amount of water vapor generated increases, the amount of water vapor accumulated will not increase significantly, thereby avoiding the voltage signal line 14 from being lifted up due to excessive accumulation of water vapor, that is, avoiding the problem of peeling of the display substrate 100.

[0203] In some embodiments, see Fig.13 , the display substrate also includes a barrier layer 9.

[0204] In some examples, one end of the barrier layer 9 extends between two adjacent first barrier layers 41, the other end of the barrier layer 9 extends between two adjacent flat layers 7, and the first barrier layer 41 overlapped by one end of the barrier layer 9 and the flat layer 7 overlapped by the other end of the barrier layer 9 are arranged in the same layer.

[0205] It should be noted that, in the process of preparing the display substrate 100, the thin films are formed in sequence, that is, the thin films formed earlier are close to the substrate 1, and the thin films formed later are away from the substrate 1. Therefore, the barrier layer 9 is formed later than the first barrier layer 41 and the planar layer 7 it overlaps.

[0206] In some of the above examples, by setting the barrier layer 9, not only can the barrier layer 9 be used to reduce the step difference between the first retaining wall 4 and the multi-layer flat layer 7 and reduce the step difference change rate, but the barrier layer 9 can also be used to block the first barrier layer 41 and the first flat layer 7 to avoid contact between the two and form a water-oxygen channel, thereby preventing water vapor from entering the display area A, which is beneficial to improving the water vapor blocking ability and avoiding packaging failure due to water vapor entering the display area A.

[0207] In some examples, the barrier layer 9 is disposed on the same layer as at least one of the conductive line layers 6 .

[0208] That is, when the number of the conductive line layer 6 is one, the barrier layer 9 can be disposed in the same layer as the conductive line layer 6. When the number of the conductive line layer 6 is multiple, the barrier layer 9 can be disposed in the same layer as one of the conductive line layers 6. This is conducive to simplifying the method for preparing the display substrate 100.

[0209] For some examples, see Fig.13 , the orthographic projection of the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 on the substrate 1 is located within the orthographic projection range of the first barrier layer 41 farthest from the substrate 1 among the multiple first barrier layers 41 on the substrate 1. At this time, the orthographic projection area of ​​the first barrier layer 41 farthest from the substrate 1 on the substrate 1 is smaller than the orthographic projection area of ​​the first barrier layer 41 farthest from the substrate 1 on the substrate 1, and the first barrier layer 41 farthest from the substrate 1 only covers a portion of the first barrier layer 41 farthest from the substrate 1 on the substrate 1.

[0210] In some examples, the orthographic projection of the first barrier layer 41 overlapped by one end of the barrier layer 9 on the substrate 1 is tangent to or overlaps with the orthographic projection of the flat layer 7 on the side of the other end of the barrier layer 9 away from the substrate 1 on the substrate 1. This design can make the step difference of the thin film included in the display substrate 100 in the transition area between the peripheral area B and the display area A smaller, ensuring the yield of the signal transmission line 400 formed subsequently.

[0211] In some embodiments, the touch grid structure 200 in the display device 1000 may include multiple structures, which can be selected and set according to actual needs.

[0212] For example, see Figure 2 The touch grid structure 200 may include: a plurality of conductive bridges arranged in an array, and a plurality of rows of first touch sub-electrodes. Each row of first touch sub-electrodes may include, for example, a plurality of first touch sub-electrodes arranged at intervals along a first direction X, and in each row of first touch sub-electrodes, every two adjacent first touch sub-electrodes are electrically connected to a conductive bridge through vias, so that the plurality of rows of first touch sub-electrodes and the plurality of conductive bridges constitute a plurality of first touch electrodes.

[0213] For example, please refer to Figure 2 The touch grid structure 200 may further include: a plurality of second touch electrodes extending along the second direction Y, each of which may include, for example, a plurality of second touch sub-electrodes connected in series. Exemplarily, each second touch electrode is an integrated structure.

[0214] For example, please refer to Figure 2 Each first touch electrode is electrically connected to the touch driving chip 500 through a signal transmission line 400 , and each second touch electrode is electrically connected to the touch driving chip 500 through a signal transmission line 400 .

[0215] For example, the signal transmission line 400 included in the display device 1000 can be disposed in the same layer as the conductive bridge. This design is conducive to simplifying the manufacturing process of the display device 1000.

[0216] It should be noted that the display device 1000 may be, for example, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0217] Some embodiments of the present disclosure also provide a method for manufacturing the display substrate 100 as described in any of the above embodiments. Fig.15 , the manufacturing method includes S1~S2.

[0218] S1. Provide a substrate 1.

[0219] S2. A first retaining wall 4, a connecting portion 15 and a second retaining wall 5 are formed on one side of the substrate 1, which are located in the peripheral area B and are sequentially away from the display area A; wherein the height of the second retaining wall 5 is greater than the height of the first retaining wall 4; the height of the connecting portion 15 is less than the height of the first retaining wall 4; and at least part of the first retaining wall 4, the connecting portion 15 and the second retaining wall 5 are an integrated structure.

[0220] In some examples, the first retaining wall 4 includes a plurality of first barrier layers 41 stacked sequentially, and the second retaining wall 5 includes a plurality of second barrier layers 51 stacked sequentially; the total number of the second barrier layers 51 is greater than the total number of the first barrier layers 41 .

[0221] The connecting portion 15 includes at least one connecting layer 10, and the total number of connecting layers 10 is less than the total number of first barrier layers 41; at least one first barrier layer 41 close to the substrate 1 in the multiple first barrier layers 41 and at least one second barrier layer 51 close to the substrate 1 in the multiple second barrier layers 51 are connected by at least one connecting layer 10.

[0222] Among them, a connecting layer 10 connects a first barrier layer 41 and a second barrier layer 52. The connecting layer 10 and the first barrier layer 41 and the second barrier layer 51 connected thereto can be formed by, for example, the same patterning process.

[0223] The manufacturing method of the display substrate 100 in some of the above embodiments is used to prepare the display substrate 100 provided in any of the above embodiments. The display substrate 100 manufactured by the manufacturing method can achieve the same beneficial effects as the display substrate 100 in any of the above embodiments, which will not be described in detail.

[0224] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: The display substrate has a display area and a peripheral area; the display substrate comprises: substrate; a first retaining wall and a second retaining wall located at one side of the substrate and located in the peripheral area; the second retaining wall is farther away from the display area than the first retaining wall; the height of the second retaining wall is greater than the height of the first retaining wall; and, a connecting portion located between the first retaining wall and the second retaining wall, the connecting portion connecting the first retaining wall and the second retaining wall, and the height of the connecting portion is less than the height of the first retaining wall; Wherein, at least part of the first retaining wall, the connecting portion and the second retaining wall are an integrated structure; the first retaining wall comprises a plurality of first barrier layers stacked in sequence, and the second retaining wall comprises a plurality of second barrier layers stacked in sequence; the total number of the second barrier layers is greater than the total number of the first barrier layers; The connecting portion includes at least one connecting layer; the total number of the connecting layers is less than the total number of the first barrier layers.

2. The display substrate according to claim 1, characterized in that: At least one first barrier layer close to the substrate among the multiple first barrier layers and at least one second barrier layer close to the substrate among the multiple second barrier layers are connected via at least one connecting layer.

3. The display substrate according to claim 1, characterized in that: A layer of the connecting layer connects a layer of the first barrier layer and a layer of the second barrier layer.

4. The display substrate according to claim 1, characterized in that: The side wall of the first retaining wall close to the display area gradually moves away from the display area in a direction away from the substrate and is in a slope or step shape; A portion of the side wall of the first retaining wall that is away from the display area and is not connected to the connecting portion gradually approaches the display area in a direction away from the substrate and is in a slope or step shape.

5. The display substrate according to any one of claims 1 to 4, characterized in that: A portion of the side wall of the second retaining wall close to the display area that is not connected to the connecting portion gradually moves away from the display area in a direction away from the substrate and is in a slope or step shape; The second retaining wall is located away from the side wall of the display area, gradually approaches the display area in a direction away from the substrate, and is in a slope or step shape.

6. The display substrate according to any one of claims 1 to 4, characterized in that: The slope of a portion of the side wall of the first retaining wall away from the display area that is not connected to the connecting portion is smaller than the slope of a portion of the side wall of the second retaining wall close to the display area that is not connected to the connecting portion.

7. The display substrate according to any one of claims 1 to 4, characterized in that: The slope of the side wall of the first retaining wall close to the display area is smaller than the slope of the side wall of the second retaining wall away from the display area.

8. The display substrate according to any one of claims 1 to 4, characterized in that: The display area includes a main display area and an auxiliary display area; The light transmittance of a portion of the display substrate located in the auxiliary display area is greater than the light transmittance of a portion of the display substrate located in the main display area.

9. The display substrate according to claim 8, characterized in that: Also includes: A plurality of first sub-pixels and a plurality of second sub-pixels are disposed on one side of the substrate; The plurality of first sub-pixels are located in the main display area; The second sub-pixel includes: a pixel driving circuit; and A light emitting device is arranged on a side of the pixel driving circuit away from the substrate, the light emitting device is located in the auxiliary display area, and the light emitting device is coupled to the pixel driving circuit; Among the plurality of second sub-pixels, at least one pixel driving circuit is located outside the auxiliary display area.

10. The display substrate according to claim 9, characterized in that: Also includes: A plurality of planar layers are disposed between the pixel driving circuit and the light emitting device and are stacked in sequence; Wherein, the first barrier layers other than the one or two first barrier layers farthest from the substrate in the multi-layer first barrier layers are arranged in the same layer as some of the planar layers in the multi-layer planar layers; and / or, The second barrier layers except for one or two second barrier layers farthest from the substrate in the plurality of second barrier layers are arranged on the same layer as all the planar layers in the plurality of planar layers.

11. The display substrate according to claim 10, characterized in that: Also includes: at least one conductor layer, the conductor layer comprising at least one light-transmitting conductor; One of the pixel driving circuits located in the peripheral area is coupled to a corresponding one of the light emitting devices via a light-transmitting wire; Among them, at least one layer of the planar layer is arranged between the at least one layer of the wire layer as a whole and the pixel driving circuit; at least one layer of the planar layer is arranged between the at least one layer of the wire layer as a whole and the light-emitting device.

12. The display substrate according to claim 11, characterized in that: At least one flat layer is arranged between two adjacent conductive line layers.

13. The display substrate according to claim 11, characterized in that: The planar layer between the at least one conductive line layer as a whole and the pixel driving circuit is a first planar layer, and the number of layers of the first planar layer is one or two; When the number of layers of the first flat layer is one, the multiple first barrier layers include a first first barrier layer arranged on the same layer as the first flat layer, the multiple second barrier layers include a first second barrier layer arranged on the same layer as the first flat layer, and the at least one connecting layer includes a first connecting layer; the first connecting layer connects the first first barrier layer and the first second barrier layer.

14. The display substrate according to claim 13, characterized in that: When the first flat layer has two layers, the multiple first barrier layers further include a second first barrier layer arranged on the same layer as another first flat layer, the multiple second barrier layers further include a second second barrier layer arranged on the same layer as another first flat layer, and the at least one connecting layer further includes a second connecting layer; the second connecting layer connects the second first barrier layer and the second second barrier layer.

15. The display substrate according to claim 13, characterized in that: The flat layer between two adjacent wire layers is a second flat layer; The number of the conductor layers is three, the flat layer between two adjacent conductor layers close to the substrate is a first second flat layer, and the flat layer between two adjacent conductor layers far from the substrate is a second second flat layer; The multi-layer first barrier layer includes a third first barrier layer disposed on the same layer as the first second flat layer, and a fourth first barrier layer disposed on the same layer as the second second flat layer; The multi-layer second barrier layer includes a third second barrier layer disposed on the same layer as the first second flat layer, and a fourth second barrier layer disposed on the same layer as the second second flat layer.

16. The display substrate according to claim 15, characterized in that: The at least one connecting layer includes a third connecting layer and a fourth connecting layer; the third connecting layer connects the third first barrier layer and the third second barrier layer, and the fourth connecting layer connects the fourth first barrier layer and the fourth second barrier layer.

17. The display substrate according to claim 15, characterized in that: The at least one connecting layer includes a third connecting layer; the third connecting layer connects the third first barrier layer and the third second barrier layer; and the fourth first barrier layer is disconnected from the fourth second barrier layer.

18. The display substrate according to claim 16, characterized in that: Also includes: A pixel defining layer disposed on a side of the multi-layer planar layer away from the substrate; as well as, A plurality of support pads disposed on a surface of the pixel defining layer away from the substrate; Wherein, a first barrier layer farthest from the substrate among the multiple first barrier layers is arranged in the same layer as the pixel defining layer or the plurality of support pads; A second barrier layer among the multiple layers of second barrier layers, which is farthest from the substrate, is disposed in the same layer as the pixel defining layer or the plurality of support pads.

19. The display substrate according to claim 18, characterized in that: When a first barrier layer of the plurality of first barrier layers that is farthest from the substrate is disposed in the same layer as the plurality of support pads, a first barrier layer of the plurality of first barrier layers that is second farthest from the substrate is disposed in the same layer as the pixel defining layer; When the second barrier layer farthest from the substrate among the multiple second barrier layers is arranged in the same layer as the multiple support pads, the second barrier layer farthest from the substrate among the multiple second barrier layers is arranged in the same layer as the pixel defining layer.

20. The display substrate according to claim 18, characterized in that: The multi-layer first barrier layer further includes a fifth first barrier layer disposed on the same layer as the pixel defining layer or the plurality of support pads; The flat layer between the at least one wire layer as a whole and the light-emitting device is a third flat layer, and the third flat layer has one layer; The multi-layer second barrier layer further includes a fifth second barrier layer disposed on the same layer as the third flat layer and a sixth second barrier layer disposed on the same layer as the pixel defining layer or the plurality of support pads; Wherein, the fifth second barrier layer and the sixth second barrier layer are both disconnected from the fifth first barrier layer.

21. The display substrate according to any one of claims 10 to 20, characterized in that: Also includes: a barrier layer, wherein one end of the barrier layer extends between two adjacent first barrier layers, and the other end of the barrier layer extends between two adjacent planar layers; The first barrier layer overlapped by one end of the barrier layer and the flat layer overlapped by the other end of the barrier layer are arranged in the same layer.

22. The display substrate according to claim 21, characterized in that: The orthographic projection of the first barrier layer overlapped by one end of the barrier layer on the substrate is tangent to or overlaps with the orthographic projection of the flat layer located on the other end of the barrier layer away from the substrate on the substrate.

23. The display substrate according to claim 21, characterized in that: When the display substrate includes a plurality of conductive line layers, the barrier layer is disposed on the same layer as at least one layer of the plurality of conductive line layers.

24. The display substrate according to any one of claims 9 to 20, characterized in that: Also includes: An encapsulation layer disposed on a side of the plurality of first sub-pixels and the plurality of second sub-pixels away from the substrate; The encapsulation layer is configured to encapsulate the plurality of first sub-pixels and the plurality of second sub-pixels on the substrate; The encapsulation layer comprises: a first inorganic layer; an organic layer disposed on a side of the first inorganic layer away from the substrate; and A second inorganic layer disposed on a side of the organic layer away from the substrate; Wherein, the first retaining wall and the second retaining wall are used to block the organic layer; The first inorganic layer covers the first retaining wall and the second retaining wall, and the second inorganic layer covers the first retaining wall and the second retaining wall.

25. The display substrate according to any one of claims 1 to 4 or claims 9 to 20, characterized in that: Among the multiple first barrier layers, a first barrier layer closest to the substrate is connected to a second barrier layer closest to the substrate through a connection layer to form a first connecting portion, and a first barrier layer second closest to the substrate is connected to a second barrier layer second closest to the substrate through a connection layer to form a second connecting portion; The display substrate further comprises: A voltage signal line is arranged on one side of the substrate, the voltage signal line is located in the peripheral area and is arranged around the display area; An area of ​​the voltage signal line away from the display area is located between the first connecting portion and the second connecting portion, and an orthographic projection of an edge of the voltage signal line away from the display area on the substrate is located between an orthographic projection of an edge of the first connecting portion close to the display area on the substrate and an orthographic projection of an edge of the first connecting portion away from the display area on the substrate.

26. The display substrate according to any one of claims 1 to 4 or claims 9 to 20, characterized in that: The multi-layer first barrier layer is arranged in at least one of the following ways: The first barrier layer farthest from the substrate among the multiple first barrier layers covers the side of the first barrier layer farthest from the substrate among the multiple first barrier layers facing the second barrier wall; or A first barrier layer among the multiple first barrier layers that is the second most distant from the substrate covers a side surface of a first barrier layer among the multiple first barrier layers that is the third most distant from the substrate and faces the second barrier wall.

27. The display substrate according to any one of claims 1 to 4 or claims 9 to 20, characterized in that: The multi-layer second barrier layer is arranged in at least one of the following ways: The second barrier layer farthest from the substrate among the multiple second barrier layers covers the side of the second barrier layer second farthest from the substrate among the multiple second barrier layers facing the first barrier wall; or A second barrier layer in the plurality of second barrier layers that is the second most distant from the substrate covers a side surface of a second barrier layer in the plurality of second barrier layers that is the third most distant from the substrate and faces the first barrier wall; or, A second barrier layer among the multiple second barrier layers that is the third most distant from the substrate covers a side surface of a second barrier layer among the multiple second barrier layers that is the fourth most distant from the substrate and faces the first barrier wall.

28. The display substrate according to any one of claims 1 to 4 or claims 9 to 20, characterized in that: The connecting layer and the first barrier layer and the second barrier layer connected thereto are arranged in the same layer.

29. A method for manufacturing a display substrate, wherein the display substrate has a display area and a peripheral area; characterized in that: The production method comprises: providing a substrate; Forming a first retaining wall, a connecting portion, and a second retaining wall located in the peripheral area and sequentially away from the display area on one side of the substrate; The height of the second retaining wall is greater than that of the first retaining wall; the height of the connecting portion is less than that of the first retaining wall; at least part of the first retaining wall, the connecting portion and the second retaining wall are an integrated structure; the first retaining wall comprises a plurality of first barrier layers stacked in sequence, and the second retaining wall comprises a plurality of second barrier layers stacked in sequence; the total number of the second barrier layers is greater than the total number of the first barrier layers; The connecting portion includes at least one connecting layer; the total number of the connecting layers is less than the total number of the first barrier layers.

30. The manufacturing method according to claim 29, characterized in that: At least one first barrier layer close to the substrate among the multiple first barrier layers and at least one second barrier layer close to the substrate among the multiple second barrier layers are connected by at least one connecting layer; Wherein, one connecting layer connects one first barrier layer and one second barrier layer, and the connecting layer and the first barrier layer and the second barrier layer connected thereto are formed by the same patterning process.

31. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 28.

32. The display device according to claim 31, characterized in that The peripheral area of ​​the display substrate includes a binding area, and the binding area is located on a side of the second barrier wall away from the display area; the display device further includes: A touch control driving chip located in the binding area of ​​the display substrate; A touch grid structure located in the display area of ​​the display substrate; and A plurality of signal transmission lines connecting the touch driver chip and the touch grid structure, the plurality of signal transmission lines being located on a side of the first retaining wall and the second retaining wall that are away from the substrate as a whole, and an orthographic projection of the plurality of signal transmission lines on the substrate partially overlapping with an orthographic projection of the connection layer on the substrate.

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