A histogram peak detection circuit and method for laser ranging system

Abstract

The present invention discloses a histogram peak detection circuit for a laser ranging system, comprising a selection circuit, a histogram circuit, a data screening circuit, and a peak readout circuit. The present invention is suitable for use in scenarios where the ambient light noise level is high. By using a reference voltage V ref Adjustment of the discharge current can cope with varying ambient light noise intensities. This invention uses MOS capacitor discharge to segment the TDC output and generate a histogram. The reuse of the histogram circuit significantly reduces the number of histogram cells, effectively reducing the layout area and improving circuit integration. Furthermore, the detection output of the histogram peak not only improves the reliability and accuracy of the detection results, but also saves large-scale storage components, further enhancing the feasibility of on-chip integration of the histogram algorithm.

Description

Technical Field

[0001] The present invention belongs to the technical fields of laser ranging, 3D imaging and fluorescence lifetime imaging, and in particular relates to a histogram peak detection circuit and method applied to a laser ranging system. Background Art

[0002] Time-of-Flight (TOF) detectors offer advantages such as high detection efficiency, wide dynamic range, and fast response speed, making them widely used in laser ranging, three-dimensional imaging, and fluorescence lifetime imaging. TOF detectors calculate the target's position by calculating the time of flight of a light signal between the detector and the target. Due to their high sensitivity, detection results can be significantly affected by background noise when ambient light is strong and the target is far away. To extract valid TOF information, the detector repeatedly measures the target. The time-to-digital converter (TDC) outputs multiple sets of TOF information, which are stored in a histogram. The target's position is then calculated based on the peak values ​​in the histogram. With the increasing demand for detection range and the expansion of imaging arrays, reducing circuit complexity and minimizing circuit layout area to enhance on-chip integration feasibility while ensuring accurate and efficient noise suppression has become a pressing issue. Summary of the Invention

[0003] Technical Problem Solved: This invention uses MOS capacitor discharge to segmentally count TDC output and generate a histogram. The reuse of histogram circuits significantly reduces the number of histogram cells, effectively reducing the layout area and improving circuit integration. Furthermore, the detection and output of histogram peaks not only improves the reliability and accuracy of detection results, but also saves large-scale storage components, further enhancing the feasibility of on-chip integration of histogram algorithms.

[0004] Technical solution:

[0005] A histogram peak detection circuit for a laser ranging system, comprising a selection circuit, a histogram circuit, a data screening circuit, and a peak readout circuit;

[0006] The histogram circuit includes 8 groups of histogram units U[n] in parallel, n=0, 1, ..., 7, and the 8 output terminals thereof are correspondingly connected to the 8 input terminals of the peak readout circuit;

[0007] The selection circuit includes 8 output terminals U0-U7, which are connected to 8 input terminals H[0]-H[7] of the histogram circuit, respectively controlling 8 groups of histogram units. The selection circuit processes 9-bit TDC data T[0]-T[8] according to the corresponding external segmentation control signal, decodes part of the bits of the TDC data to select the corresponding histogram unit for accumulation, and repeats this process until all TDC data are accumulated. The histogram unit U[n] with the largest number of accumulations outputs the corresponding peak signal Y[n] to the peak readout circuit, which stores the peak value of the corresponding bit of the TDC data. At the same time, the peak signal Y[n] resets the MOS capacitor gates of two adjacent histogram units to V ref ;

[0008] The input end of the data filtering circuit is connected to the output end of the peak readout circuit, and the output end is connected to the valid bit input end Valid of the eight groups of histogram units U[n]. The data filtering circuit is used to filter out valid TDC data from the peak value range of the corresponding bit output by the previous peak readout circuit based on the current external segmentation control signal. The histogram circuit executes the current histogram accumulation process until the peak readout circuit completes the peak detection of the 9-bit TDC data.

[0009] Furthermore, the selection circuit includes a first data selector (MUX_1), a second data selector (MUX_2), a third data selector (MUX_3) and a decoder (Decoder3_8);

[0010] The 9-bit TDC data is divided into three groups of high, medium and low in sequence, each group includes 3 bits of data, wherein the high three bits of data T[8]~T[6] are respectively used as the input signals of the data terminals C3_1, C2_1 and C1_1 of the third data selector (MUX_3), the second data selector (MUX_2) and the first data selector (MUX_1), and the middle three bits of data T[5]~T[3] are respectively used as the input signals of the data terminals C3_1, C2_1 and C1_1 of the third data selector (MUX_3), the second data selector (MUX_2) and the first data selector (MUX_1). The lower three bits of data T[2]~T[0] serve as the input signals of the data terminals C3_3, C2_3, and C1_3 of the third data selector (MUX_3), the second data selector (MUX_2), and the first data selector (MUX_1), respectively. The data terminals C3_4, C2_4, and C1_4 of the third data selector (MUX_3), the second data selector (MUX_2), and the first data selector (MUX_1) are grounded at the same time.

[0011] The external segment control signal includes control signals S1 and S0, which are simultaneously sent to the control ends of the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3), and select the corresponding bits of the 9-bit TDC data T[0] to T[8] received by the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3);

[0012] The three output ends of the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3) are correspondingly connected to the three input ends of the decoder (Decoder3_8). The decoder (Decoder3_8) decodes some bits of the selected TDC data and outputs the decoding results to the histogram circuit.

[0013] Furthermore, the histogram unit includes a delay unit (Delay), a monostable circuit (Monostable), a three-input OR gate (OR_1), a first two-input AND gate (AND2_1), a second two-input AND gate (AND2_2), a transmission gate (TG), a MOS capacitor (MOS_C), a first inverter (INV_1), a second inverter (INV_2), a third inverter (INV_3), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a PMOS transistor (MP1), and a current source (Is);

[0014] The input terminal EN of the histogram unit U[n] is connected to the input terminal of the delay unit (Delay), and the output terminal of the delay unit (Delay) is connected to the input terminal of the monostable circuit (Monostable); the valid bit input terminal Valid of the histogram unit U[n] is connected to one input terminal of the first two-input AND gate (AND2_1), and the other input terminal of the first two-input AND gate (AND2_1) is connected to the output terminal of the monostable circuit (Monostable); the input terminal RstC of the histogram unit U[n] is connected to the first input terminal of the three-input OR gate (OR_1), the second input terminal HO[n-1] of the three-input OR gate (OR_1) is connected to the output terminal Y[n-1] of the previous adjacent histogram unit U[n-1], and the third input terminal HO[n-1] of the three-input OR gate (OR_1) is connected to the output terminal Y[n-1] of the previous adjacent histogram unit U[n-1]. +1] is connected to the output end Y[n+1] of the next adjacent histogram unit U[n+1]; the input end H[n] of the histogram unit U[n] is connected to one input end of a second two-input AND gate (AND2_2); the other input end of the second two-input AND gate (AND2_2) is connected to the output end of the first two-input AND gate (AND2_1); the output end of the second two-input AND gate (AND2_2) is simultaneously connected to the input end of the second inverter (INV_2) and the control end T of the transmission gate (TG); the output end of the second inverter (INV_2) is connected to the reverse control end TN of the transmission gate (TG); the input end and the output end of the first inverter (INV_1) are respectively connected to the output end of the three-input OR gate (OR_1) and the gate of the PMOS tube (MP1); the source of the PMOS tube (MP1) is connected to the reference voltage V ref The drain of the PMOS tube (MP1) is simultaneously connected to the input end of the third inverter (INV_3), the input end A of the transmission gate (TG), and the gate of the MOS capacitor (MOS_C); the drain of the MOS capacitor (MOS_C) is simultaneously connected to its source and ground; the input end and output end of the current source (Is) are respectively connected to the output end B of the transmission gate and ground, and the output end of the third inverter (INV_3) outputs a peak signal Y[n]. Furthermore, the peak readout circuit includes an encoder (Encoder8_3), a first data distributor (DMUX_1), a second data distributor (DMUX_2), a third data distributor (DMUX_3), and a D-flip-flop storage unit;

[0015] The eight input terminals I0 to I7 of the encoder (Encoder8_3) are correspondingly connected to the eight output terminals Y[0] to Y[7] of the histogram circuit, and the three output terminals E0, E1, and E2 are respectively connected to the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3); the 9-bit input terminals included in the D flip-flop storage unit are divided into three groups corresponding to the TDC data, each group including 3 input bits, and the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3) each include 3 output terminals, and the three output terminals of each data distributor are respectively connected to one of the input bits in the three groups;

[0016] The encoder (Encoder8_3) encodes the corresponding peak signal Y[n] output by each histogram unit U[n], and the D-flip-flop storage unit stores the peak values ​​of the corresponding bits of the TDC data output by the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3).

[0017] Furthermore, the data screening circuit includes a fourth data selector (MUX_4), a third two-input AND gate (AND_3), nine two-input exclusive-OR gates (XOR_1, XOR_2, XOR_3, XOR_4, XOR_5, XOR_6, XOR_7, XOR_8, XOR_9), and three three-input AND gates (AND3_1, AND3_2, AND3_3);

[0018] The upper three bits T[8]~T[6] of the 9-bit TDC data and the peak data W[8]~W[6] output by the peak readout circuit are respectively used as input data of the first two-input exclusive OR gate (XOR_1), the second two-input exclusive OR gate (XOR_2), and the third two-input exclusive OR gate (XOR_3), and are also respectively used as input data of the fourth two-input exclusive OR gate (XOR_4), the fifth two-input exclusive OR gate (XOR_5), and the sixth two-input exclusive OR gate (XOR_6). The middle three bits T[8]~T[6] of the 9-bit TDC data and the peak data W[5]~W[3] output by the peak readout circuit are respectively used as input data of the seventh two-input exclusive OR gate (XOR_7), the eighth two-input exclusive OR gate (XOR_8), and the ninth two-input exclusive OR gate (XOR_9).

[0019] The output ends of the first two-input exclusive OR gate (XOR_1), the second two-input exclusive OR gate (XOR_2), and the third two-input exclusive OR gate (XOR_3) serve as input signals of the first three-input AND gate (AND3_1), the output ends of the fourth two-input exclusive OR gate (XOR_4), the fifth two-input exclusive OR gate (XOR_5), and the sixth two-input exclusive OR gate (XOR_6) serve as input signals of the second three-input AND gate (AND3_2), and the output ends of the seventh two-input exclusive OR gate (XOR_7), the eighth two-input exclusive OR gate (XOR_8), and the ninth two-input exclusive OR gate (XOR_9) serve as input signals of the third three-input AND gate ( The output signals of the second three-input AND gate (AND3_2) and the third three-input AND gate (AND3_3) serve as the input signals of the third two-input AND gate (AND_2). The output terminals of the first three-input AND gate (AND3_1) and the third two-input AND gate (AND_2) are respectively connected to two input terminals C2 and C3 of a fourth data selector (MUX_4). The other two input terminals C1 and C4 of the fourth data selector (MUX_4) are respectively connected to a high level and a low level. The output terminal Y of the fourth data selector (MUX_4) serves as the output terminal CO of the data filtering circuit.

[0020] Based on the aforementioned histogram peak detection circuit, the present invention proposes a histogram peak detection method applied to a laser ranging system, the histogram peak detection method comprising the following steps:

[0021] The workflow of the entire circuit is divided into three stages: the peak detection stage of the upper three bits, the peak detection stage of the middle three bits, and the peak detection stage of the lower three bits:

[0022] (1) Peak detection phase of the upper three bits: Before the detection begins, the external segment control signal S1S0 is 00, and the external MOS capacitor reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The arrival of the external enable signal EN inputs the first group of 9-bit TDC data into the selection circuit. The selection circuit decodes the upper three bits of the TDC data through the data selector and decoder to select the corresponding histogram unit for accumulation. The histogram accumulation is performed by discharging the MOS capacitor MOS_C. This process is repeated until all TDC data are accumulated. The corresponding histogram unit U[n] will output the peak signal Y[n] to the peak readout circuit. At the same time, the peak signal Y[n] will reset the MOS capacitor gates of the two adjacent histogram units to V ref , to avoid generating multiple peaks; the peak readout circuit outputs the high three peak values ​​Q[8:6] of the TDC data to the D flip-flop storage unit through the encoder and the data distributor;

[0023] (2) Peak detection stage of the middle three bits: After the peak detection of the upper three bits is completed, the external segment control signal S1S0 changes to 01, and the external MOS capacitor reset signal RstC recharges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit filters out valid TDC data within the range of the upper three-digit peak value Q[8:6] and repeats the histogram accumulation process until the peak readout circuit outputs the middle three-digit peak value Q[5:3];

[0024] (3) Peak detection phase of the lower three bits: After the peak detection of the middle three bits is completed, the external segment control signal S1S0 changes to 10, and the external MOS capacitor reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit selects valid TDC data within the range of the upper three and middle three peak values ​​Q[8:6] and Q[5:3] and repeats the histogram accumulation process until the peak readout circuit outputs the lower three peak values ​​Q[2:0], thereby completing the peak detection of the 9-bit TDC data; after the external segment control signal S1S0 becomes 11, the target position information is calculated based on the histogram peak value.

[0025] Beneficial effects:

[0026] 1. The histogram peak detection circuit proposed in this invention can accurately and efficiently suppress noise in photon time-of-flight ranging. Moreover, it can cope with different ambient light noise intensities by adjusting the reference voltage Vref and the discharge current.

[0027] 2. The present invention has a novel structure and is simple to implement. It uses MOS capacitor discharge to segmentally count the TDC output and generate a histogram. In addition, the multiplexing of the histogram circuit significantly reduces the number of histogram units, which can effectively reduce the layout area and improve the circuit integration.

[0028] 3. The histogram peak detection and output method adopted by the present invention not only improves the reliability and accuracy of the detection results, but also saves large-scale storage components and further improves the feasibility of on-chip integration of the histogram algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the overall structure of the histogram peak detection circuit proposed by the present invention;

[0030] Figure 2 This is a schematic diagram of the data screening circuit structure of the histogram peak detection circuit proposed by the present invention;

[0031] Figure 3 This is a schematic diagram of the histogram unit structure of the histogram peak detection circuit proposed by the present invention;

[0032] Figure 4 This is a working timing diagram of the histogram peak detection circuit proposed by the present invention;

[0033] Figure 5 This is a schematic diagram of the detection method of the histogram peak detection circuit proposed by the present invention;

[0034] Figure 6 This is a schematic diagram of simulation results of a specific embodiment of the histogram peak detection circuit proposed in the present invention. DETAILED DESCRIPTION

[0035] The following examples may enable those skilled in the art to more fully understand the present invention, but are not intended to limit the present invention in any way.

[0036] like Figure 1 As shown, the embodiment of the present invention mentions a histogram peak detection circuit applied to a laser ranging system. The histogram peak detection circuit is suitable for application scenarios with high ambient light noise levels. ref The adjustment of the discharge current can cope with different ambient light noise intensities. The histogram peak detection circuit includes a selection circuit, a histogram circuit, a data screening circuit and a peak readout circuit.

[0037] The histogram circuit includes 8 groups of histogram units U[n] in parallel, where n=0, 1, . . . , 7, and 8 output terminals thereof are correspondingly connected to 8 input terminals of the peak readout circuit.

[0038] The selection circuit includes 8 output terminals U0~U7, which are connected to the 8 input terminals H[0]~H[7] of the histogram circuit respectively to control the 8 groups of histogram units respectively; the selection circuit processes the 9-bit TDC data T[0]~T[8] according to the corresponding external segmentation control signal, decodes part of the bits of the TDC data to select the corresponding histogram unit for accumulation, and repeats this process until all TDC data are accumulated, so that each histogram unit U[n] outputs the corresponding peak signal Y[n] to the peak readout circuit, and the peak readout circuit stores the peak value of the corresponding bit of the TDC data; at the same time, the peak signal Y[n] resets the MOS capacitor gates of the two adjacent histogram units to V ref .

[0039] The input end of the data filtering circuit is connected to the output end of the peak readout circuit, and the output end is connected to the valid bit input end Valid of the eight groups of histogram units U[n]. The data filtering circuit is used to filter out valid TDC data from the peak value range of the corresponding bit output by the previous peak readout circuit based on the current external segmentation control signal. The histogram circuit executes the current histogram accumulation process until the peak readout circuit completes the peak detection of the 9-bit TDC data.

[0040] The input terminal T[8:0] of the selection circuit is connected to the external input signal TDC[8:0], which is the first 9 bits of the output signal of the time-to-digital converter (TDC); the input terminals S1 and S0 of the selection circuit are connected to the external segmentation control signals S1 and S0 respectively, so as to complete the detection of the histogram peak in three stages; the input terminal T[8:3] of the data filtering circuit is connected to the external input signal TDC[8:3]; the input terminal W[8:3] of the data filtering circuit is connected to the output signal Q[8:3] of the peak readout circuit; the input terminals S1 and S0 of the data filtering circuit are connected to the external segmentation control signals S1 and S0 respectively; the input terminal EN of the histogram circuit is connected to the external enable signal EN; the input terminal RstC of the histogram circuit is connected to the external MOS capacitor reset signal Rs tC; the valid bit input terminal Valid of the histogram circuit is connected to the output terminal CO of the data filtering circuit; the input terminals H[0], H[1], H[2], H[3], H[4], H[5], H[6] and H[7] of the histogram circuit are respectively connected to the output terminals U0, U1, U2, U3, U4, U5, U6 and U7 of the selection circuit; the input terminals I0, I1, I2, I3, I4, I5, I6 and I7 of the peak readout circuit are respectively connected to the output terminals Y[0], Y[1], Y[2], Y[3], Y[4], Y[5], Y[6] and Y[7] of the histogram circuit; the input terminals S1 and S0 of the peak readout circuit are connected to the external segment control signals S1 and S0; the output terminal OUT of the peak readout circuit outputs a 9-bit peak signal Q[8:0].

[0041] (1) Selection circuit

[0042] The selection circuit includes a data selector MUX_1 , a data selector MUX_2 , a data selector MUX_3 , and a decoder Decoder3_8 .

[0043] Among them: the input terminals T[8], T[5] and T[2] of the selection circuit are respectively connected to the input terminals C3_1, C3_2 and C3_3 of the data selector MUX_3; the input terminals T[7], T[4] and T[1] of the selection circuit are respectively connected to the input terminals C2_1, C2_2 and C2_3 of the data selector MUX_2; the input terminals T[6], T[3] and T[0] of the selection circuit are respectively connected to the input terminals C1_1, C1_2 and C1_3 of the data selector MUX_1. The input terminals S1 and S0 of the selection circuit are respectively connected to the input terminals S1 and S0 of the data selectors MUX_1, MUX_2 and MUX_3. The input terminal C4 of the data selectors MUX_1, MUX_2 and MUX_3 of the selection circuit is grounded at the same time. Input terminals A0, A1, and A2 of the decoder Decoder3_8 of the selection circuit are respectively connected to the output terminal M0 of the data selector MUX_1, the output terminal M1 of the data selector MUX_2, and the output terminal M2 of the data selector MUX_3; output terminals U0, U1, U2, U3, U4, U5, U6, and U7 of the decoder Decoder3_8 of the selection circuit are the output terminals of the selection circuit.

[0044] (2) Peak readout circuit

[0045] The peak readout circuit includes an encoder Encoder8_3, a data distributor DMUX_1, a data distributor DMUX_2, a data distributor DMUX_3 and a D flip-flop storage unit.

[0046] Among them: the input terminals I0, I1, I2, I3, I4, I5, I6 and I7 of the peak readout circuit are the input terminals of the encoder Encoder8_3; the input terminals S1 and S0 of the peak readout circuit are connected to the input terminals S1 and S0 of the data distributor DMUX_1, data distributor DMUX_2 and data distributor DMUX_3 respectively; the input terminal G2 of the data distributor DMUX_3 of the peak readout circuit is connected to the output terminal E2 of the encoder Encoder8_3, and its output terminals D3_1, D3_2 and D3_3 are connected to the input terminals D8, D5 and D2 of the D flip-flop unit respectively, and its output terminal D3_4 is vacant; the data of the peak readout circuit is ...3 respectively; the data of the peak readout circuit is connected to the output terminal E2 of the encoder Encoder8_3, and the data of the peak readout circuit is connected to the output terminal E2 of the encoder Encoder8_3 The input terminal G1 of the data distributor DMUX_2 is connected to the output terminal E1 of the encoder Encoder8_3, and its output terminals D2_1, D2_2, and D2_3 are respectively connected to the input terminals D7, D4, and D1 of the D-type flip-flop unit, and its output terminal D2_4 is left vacant; the input terminal G2 of the data distributor DMUX_1 of the peak readout circuit is connected to the output terminal E0 of the encoder Encoder8_3, and its output terminals D1_1, D1_2, and D1_3 are respectively connected to the input terminals D6, D3, and D0 of the D-type flip-flop unit, and its output terminal D1_4 is left vacant; the output terminal OUT of the D-type flip-flop unit of the peak readout circuit outputs a 9-bit histogram peak signal Q[8:0].

[0047] (3) Data screening circuit

[0048] refer to Figure 2 This is a schematic diagram of the data filtering circuit structure of the histogram peak detection circuit proposed in this embodiment. The data filtering circuit includes a data selector MUX_4, a two-input AND gate AND_2, nine two-input XOR gates XOR_1, XOR_2, XOR_3, XOR_4, XOR_5, XOR_6, XOR_7, XOR_8, and XOR_9, and three three-input AND gates AND3_1, AND3_2, and AND3_3.

[0049] Among them, the input terminal W[8] of the data filtering circuit is simultaneously connected to the first input terminals of the XOR gates XOR_1 and XOR_4; the input terminal T[8] of the data filtering circuit is simultaneously connected to the second input terminals of the XOR gates XOR_1 and XOR_4; the input terminal W[7] of the data filtering circuit is simultaneously connected to the first input terminals of the XOR gates XOR_2 and XOR_5; the input terminal T[7] of the data filtering circuit is simultaneously connected to the second input terminals of the XOR gates XOR_2 and XOR_5; the input terminal W[6] of the data filtering circuit is simultaneously connected to the first input terminals of the XOR gates XOR_3 and XOR_6; the input terminal T[6] of the data filtering circuit is simultaneously connected to the second input terminals of the XOR gates XOR_3 and XOR_6.

[0050] The input terminals W[5], W[4] and W[3] of the data filtering circuit are connected to the first input terminals of the XOR gate XOR_7, the XOR gate XOR_8 and the XOR gate XOR_9 respectively; the input terminals T[5], T[4] and T[3] of the data filtering circuit are connected to the second input terminals of the XOR gate XOR_7, the XOR gate XOR_8 and the XOR gate XOR_9 respectively.

[0051] The input terminals S1 and S0 of the data filtering circuit are connected to the input terminals S1 and S0 of the data selector MUX_4 respectively.

[0052] The inputs of the three-input AND gate AND3_1 of the data filtering circuit are connected to the outputs of the XOR gates XOR_1, XOR_2, and XOR_3, respectively. The inputs of the three-input AND gate AND3_2 of the data filtering circuit are connected to the outputs of the XOR gates XOR_4, XOR_5, and XOR_6, respectively. The inputs of the three-input AND gate AND3_3 of the data filtering circuit are connected to the outputs of the XOR gates XOR_7, XOR_8, and XOR_9, respectively. The inputs of the two-input AND gate AND_2 of the data filtering circuit are connected to the outputs of the three-input AND gates AND3_2 and AND3_3, respectively.

[0053] The input terminals C1 and C4 of the data selector MUX_4 of the data filtering circuit are connected to a high level and a low level, respectively. The input terminals C2 and C3 of the data selector MUX_4 of the data filtering circuit are connected to the output terminals AND3_1 and AND_2, respectively. The output terminal Y of the data selector MUX_4 of the data filtering circuit is connected to the output terminal CO of the data filtering circuit.

[0054] When the data filtering circuit is performing peak detection of the upper three digits, the external segment control signal S1S0 is 00, and the data selector MUX_4 selects C1 for output, which is always high. When the data filtering circuit is performing peak detection of the middle three digits, the external segment control signal S1S0 is 01, and the data selector MUX_4 selects C2 for output. The level of C2 is determined by whether the upper three digits of the TDC match the peak value of the upper three digits of the output. If they are, C2 is high; if they are different, it is low. When the data filtering circuit is performing peak detection of the lower three digits, the external segment control signal S1S0 is 10, and the data selector MUX_4 selects C3 for output. The level of C3 is determined by whether the upper and middle three digits of the TDC match the peak values ​​of the upper and middle three digits of the output. If they are, C2 is high; if they are different, it is low.

[0055] (4) Histogram circuit

[0056] refer to Figure 3The present invention provides a schematic diagram of the histogram unit structure of the histogram peak detection circuit. The histogram circuit includes eight histogram units, namely U[0], U[1], U[2], U[3], U[4], U[5], U[6], and U[7]. Each histogram unit has the same structure, including a delay unit, a monostable circuit, a three-input OR gate OR3_1, a two-input AND gate AND2_1, a two-input AND gate AND2_2, a transmission gate TG, a MOS capacitor MOS_C, an inverter INV_1, an inverter INV_2, an inverter INV_3, two NMOS transistors MN1 and MN2, a PMOS transistor MP1, and a current source Is.

[0057] The input terminal EN of the histogram circuit is simultaneously connected to the input terminals EN of the eight histogram units U[0], U[1], U[2], U[3], U[4], U[5], U[6] and U[7]. The input terminal RstC of the histogram circuit is simultaneously connected to the input terminals RstC of the eight histogram units U[0], U[1], U[2], U[3], U[4], U[5], U[6] and U[7]. The valid bit input terminal Valid of the histogram circuit is simultaneously connected to the input terminals Valid of the eight histogram units U[0], U[1], U[2], U[3], U[4], U[5], U[6] and U[7]. The input terminals H[0], H[1], H[2], H[3], H[4], H[5], H[6] and H[7] of the eight histogram units U[0], U[1], U[2], U[3], U[4], U[5], U[6] and U[7] are the input terminals of the histogram circuit.

[0058] The input terminal EN of the histogram unit U[n] (n=0,1,…,7) is connected to the input terminal of the delay unit Delay, and the output terminal of the delay unit Delay is connected to the input terminal of the monostable circuit Monostable; the valid bit input terminal Valid of the histogram unit U[n] is connected to one input terminal of the two-input AND gate AND2_1, and the other input terminal of the two-input AND gate AND2_1 is connected to the output terminal of the monostable circuit Monostable; the input terminal RstC of the histogram unit U[n] is connected to the first input terminal of the three-input OR gate OR_1, the second input terminal HO[n-1] of the three-input OR gate OR_1 is connected to the output terminal Y[n-1] of the previous adjacent histogram unit U[n-1], and the third input terminal HO[n+1] of the three-input OR gate OR_1 is connected to the output terminal Y[n+1] of the next adjacent histogram unit U[n+1]; the input terminal H[n] of the histogram unit U[n] is connected to the two One input terminal of an input AND gate AND2_2 is connected. The other input terminal of the two-input AND gate AND2_2 is connected to the output terminal of the two-input AND gate AND2_1. The output terminal of the two-input AND gate AND2_2 is connected to both the input terminal of the inverter INV_2 and the control terminal T of the transmission gate TG. The output terminal of the inverter INV_2 is connected to the reverse control terminal TN of the transmission gate TG. The input terminal and output terminal of the inverter INV_1 are connected to the output terminal of the three-input OR gate OR3_1 and the gate of the PMOS transistor MP1, respectively. The source of the MOS transistor MP1 is connected to the reference voltage Vref. The drain of the MOS transistor MP1 is connected to both the input terminal of the inverter INV_3, the input terminal A of the transmission gate TG, and the gate of the MOS capacitor MOS_C. The drain of the MOS capacitor MOS_C is connected to both its source and ground. The input terminal and output terminal of the current source Is are connected to the output terminal B of the transmission gate and ground, respectively. The output terminal of the inverter INV_3 outputs a peak signal Y[n].

[0059] refer to Figure 4 This is a working timing diagram of the histogram peak detection circuit proposed in an embodiment of the present invention. Figure 4 As described above, the workflow of the entire circuit includes three stages, namely, the peak detection stage of the upper three bits, the peak detection stage of the middle three bits, and the peak detection stage of the lower three bits:

[0060] (1) Peak detection phase of the upper three bits: Before the detection begins, the external segment control signal S1S0 is 00, and the external MOS capacitor reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V refThe arrival of the external enable signal EN inputs the first set of 9-bit TDC data into the selection circuit. The selection circuit decodes the upper three bits of the TDC data through the data selector and decoder and selects the corresponding histogram unit for accumulation (histogram accumulation is performed by discharging the MOS capacitor MOS_C). This process is repeated until all TDC data are accumulated. The corresponding histogram unit U[n] will output the peak signal Y[n] to the peak readout circuit. At the same time, the peak signal Y[n] will reset the MOS capacitor gates of the two adjacent histogram units to V ref The peak readout circuit outputs the peak values ​​of the upper three bits of TDC data, Q[8:6] (101 in this example), to the D-type flip-flop storage unit through the encoder and data distributor.

[0061] (2) Peak detection stage of the middle three bits: After the peak detection of the upper three bits is completed, the external segment control signal S1S0 changes to 01, and the external reset signal RstC recharges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit will filter out valid TDC data within the range of the upper three peak values ​​Q[8:6] and repeat the histogram accumulation process until the peak readout circuit outputs the middle three peak values ​​Q[5:3] (100 in the example).

[0062] (3) Peak detection phase of the lower three bits: After the peak detection of the middle three bits is completed, the external segment control signal S1S0 changes to 10, and the external reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit selects valid TDC data within the upper and middle three-bit peak values, Q[8:6] and Q[5:3], and repeats the histogram accumulation process until the peak readout circuit outputs the lower three-bit peak value, Q[2:0] (011 in this example). This completes peak detection of the 9-bit TDC data. After the external segment control signal S1S0 changes to 11, the subsequent algorithm circuit calculates the target's position based on the histogram peak value.

[0063] The following will be based on the reference Figure 5The detection method of the histogram peak detection circuit proposed in this embodiment is described, and the left side of the schematic diagram shows the three processes of the histogram peak detection. The first is the peak detection stage of the upper three digits. The upper three digits of all TDC data are counted in 8 bins (bin is used to store the number of each data), and the upper three digits peak value Peak1 (example is 101) is output through the histogram circuit and the peak readout circuit. Then, within the range of the upper three digits peak value Peak1, the valid TDC data is screened out for the peak detection of the middle three digits, and the middle three digits of the valid TDC data are counted in 8 bins, and the middle three digits peak value Peak2 (example is 100) is output through the histogram circuit and the peak readout circuit. Finally, within the range of the upper three digits and the middle three digits peak value Peak1 and Peak2, the valid TDC data is screened out for the peak detection of the lower three digits, and the lower three digits of the valid TDC data are counted in 8 bins, and the middle three digits peak value Peak3 (example is 011) is output through the histogram circuit and the peak readout circuit. From this, we get the histogram peak value of 512 bins of the 9-bit TDC (as shown on the right side of the figure, the peak value is 101100011). The target location information can be calculated based on the histogram peak value.

[0064] This embodiment simulates the above histogram unit circuit based on the standard 0.18μm CMOS process. The simulation parameters are as follows: the reference voltage Vref is 1.2V, the control signal Ctrl is set to a continuous square wave with a pulse width of 5ns, and the MOS capacitor is discharged with a constant current of 5nA. Based on the above simulation parameters, this embodiment performs a simulation for 7μs and obtains the following Figure 6 The simulation results are shown in Figure 1; the horizontal axis is simulation time, and the vertical axis is the output voltage. It can be seen that before detection, the MOS capacitor reset signal RstC charges the MOS capacitor gate potential VC to the reference potential of 1.2V. After the MOS capacitor discharges 30 times between 0 and 7μs, the gate potential reaches the flip threshold voltage of inverter INV_3, and the inverter outputs the peak signal Y.

[0065] It should be further noted that this embodiment can also adjust the amount of data that the histogram unit can process by varying the MOS capacitor size, discharge current, and reference voltage Vref. Furthermore, the histogram peak detection circuit design proposed in this embodiment is not limited to 9-bit TDCs. Based on actual application requirements, the digital logic circuits in the selection circuit and peak readout circuit can be adjusted to accommodate histogram peak extraction for TDC data with more bits.

Claims

1. A histogram peak detection circuit for a laser ranging system, characterized in that: The histogram peak detection circuit includes a selection circuit, a histogram circuit, a data screening circuit and a peak readout circuit; The histogram circuit includes 8 groups of histogram units U[n] in parallel, n=0, 1, ..., 7, and the 8 output terminals thereof are correspondingly connected to the 8 input terminals of the peak readout circuit; The selection circuit includes 8 output terminals U0-U7, which are connected to 8 input terminals H[0]-H[7] of the histogram circuit, respectively controlling 8 groups of histogram units. The selection circuit processes 9-bit TDC data T[0]-T[8] according to the corresponding external segmentation control signal, decodes part of the bits of the TDC data to select the corresponding histogram unit for accumulation, and repeats this process until all TDC data are accumulated. The histogram unit U[n] with the largest number of accumulations outputs the corresponding peak signal Y[n] to the peak readout circuit, which stores the peak value of the corresponding bit of the TDC data. At the same time, the peak signal Y[n] resets the MOS capacitor gates of two adjacent histogram units to V ref ; The input end of the data filtering circuit is connected to the output end of the peak readout circuit, and the output end is connected to the valid bit input end Valid of the eight groups of histogram units U[n]. The data filtering circuit is used to filter out valid TDC data from the peak value range of the corresponding bit output by the previous peak readout circuit based on the current external segmentation control signal. The histogram circuit executes the current histogram accumulation process until the peak readout circuit completes the peak detection of the 9-bit TDC data.

2. The histogram peak detection circuit for a laser ranging system according to claim 1, wherein: The selection circuit includes a first data selector (MUX_1), a second data selector (MUX_2), a third data selector (MUX_3) and a decoder (Decoder3_8); The 9-bit TDC data is divided into three groups of high, medium and low in sequence, each group includes 3 bits of data, wherein the high three bits of data T[8]~T[6] are respectively used as the input signals of the data terminals C3_1, C2_1 and C1_1 of the third data selector (MUX_3), the second data selector (MUX_2) and the first data selector (MUX_1), and the middle three bits of data T[5]~T[3] are respectively used as the input signals of the data terminals C3_1, C2_1 and C1_1 of the third data selector (MUX_3), the second data selector (MUX_2) and the first data selector (MUX_1). _1), the lower three bits of data T[2]~T[0] are used as the input signals of the data terminals C3_3, C2_3, and C1_3 of the third data selector (MUX_3), the second data selector (MUX_2), and the first data selector (MUX_1), respectively. The data terminals C3_4, C2_4, and C1_4 of the third data selector (MUX_3), the second data selector (MUX_2), and the first data selector (MUX_1) are grounded at the same time; The external segment control signal includes control signals S1 and S0, which are simultaneously sent to the control ends of the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3), and select the corresponding bits of the 9-bit TDC data T[0] to T[8] received by the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3); The three output ends of the first data selector (MUX_1), the second data selector (MUX_2), and the third data selector (MUX_3) are correspondingly connected to the three input ends of the decoder (Decoder3_8). The decoder (Decoder3_8) decodes some bits of the selected TDC data and outputs the decoding results to the histogram circuit.

3. The histogram peak detection circuit for a laser ranging system according to claim 1, wherein: The histogram unit includes a delay unit (Delay), a monostable circuit (Monostable), a three-input OR gate (OR_1), a first two-input AND gate (AND2_1), a second two-input AND gate (AND2_2), a transmission gate (TG), a MOS capacitor (MOS_C), a first inverter (INV_1), a second inverter (INV_2), a third inverter (INV_3), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a PMOS transistor (MP1), and a current source (Is); The input terminal EN of the histogram unit U[n] is connected to the input terminal of the delay unit (Delay), and the output terminal of the delay unit (Delay) is connected to the input terminal of the monostable circuit (Monostable); the valid bit input terminal Valid of the histogram unit U[n] is connected to one input terminal of the first two-input AND gate (AND2_1), and the other input terminal of the first two-input AND gate (AND2_1) is connected to the output terminal of the monostable circuit (Monostable); the input terminal RstC of the histogram unit U[n] is connected to the first input terminal of the three-input OR gate (OR_1), the second input terminal HO[n-1] of the three-input OR gate (OR_1) is connected to the output terminal Y[n-1] of the previous adjacent histogram unit U[n-1], and the third input terminal HO[n-1] of the three-input OR gate (OR_1) is connected to the output terminal Y[n-1] of the previous adjacent histogram unit U[n-1]. +1] is connected to the output end Y[n+1] of the next adjacent histogram unit U[n+1]; the input end H[n] of the histogram unit U[n] is connected to one input end of a second two-input AND gate (AND2_2); the other input end of the second two-input AND gate (AND2_2) is connected to the output end of the first two-input AND gate (AND2_1); the output end of the second two-input AND gate (AND2_2) is simultaneously connected to the input end of the second inverter (INV_2) and the control end T of the transmission gate (TG); the output end of the second inverter (INV_2) is connected to the reverse control end TN of the transmission gate (TG); the input end and the output end of the first inverter (INV_1) are respectively connected to the output end of the three-input OR gate (OR_1) and the gate of the PMOS tube (MP1); the source of the PMOS tube (MP1) is connected to the reference voltage V ref The drain of the PMOS transistor (MP1) is simultaneously connected to the input terminal of the third inverter (INV_3), the input terminal A of the transmission gate (TG), and the gate of the MOS capacitor (MOS_C); the drain of the MOS capacitor (MOS_C) is simultaneously connected to its source and ground; the input terminal and output terminal of the current source (Is) are respectively connected to the output terminal B of the transmission gate and ground, and the output terminal of the third inverter (INV_3) outputs a peak signal Y[n].

4. The histogram peak detection circuit for a laser ranging system according to claim 1, wherein: The peak readout circuit includes an encoder (Encoder8_3), a first data distributor (DMUX_1), a second data distributor (DMUX_2), a third data distributor (DMUX_3) and a D flip-flop storage unit; The eight input terminals I0 to I7 of the encoder (Encoder8_3) are correspondingly connected to the eight output terminals Y[0] to Y[7] of the histogram circuit, and the three output terminals E0, E1, and E2 are respectively connected to the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3); the 9-bit input terminals included in the D flip-flop storage unit are divided into three groups corresponding to the TDC data, each group including 3 input bits, and the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3) each include 3 output terminals, and the three output terminals of each data distributor are respectively connected to one of the input bits in the three groups; The encoder (Encoder8_3) encodes the corresponding peak signal Y[n] output by each histogram unit U[n], and the D-flip-flop storage unit stores the peak values ​​of the corresponding bits of the TDC data output by the first data distributor (DMUX_1), the second data distributor (DMUX_2), and the third data distributor (DMUX_3).

5. The histogram peak detection circuit for a laser ranging system according to claim 1, wherein: The data screening circuit includes a fourth data selector (MUX_4), a third two-input AND gate (AND_2), nine two-input exclusive-OR gates (XOR_1, XOR_2, XOR_3, XOR_4, XOR_5, XOR_6, XOR_7, XOR_8, XOR_9), and three three-input AND gates (AND3_1, AND3_2, AND3_3); The upper three bits T[8] to T[6] of the 9-bit TDC data and the peak data W[8] to W[6] output by the peak readout circuit are respectively used as input data of the first two-input exclusive OR gate (XOR_1), the second two-input exclusive OR gate (XOR_2), and the third two-input exclusive OR gate (XOR_3), and are also respectively used as input data of the fourth two-input exclusive OR gate (XOR_4), the fifth two-input exclusive OR gate (XOR_5), and the sixth two-input exclusive OR gate (XOR_6). The middle three bits T[8] to T[6] of the 9-bit TDC data and the peak data W[5] to W[3] output by the peak readout circuit are respectively used as input data of the seventh two-input exclusive OR gate (XOR_7), the eighth two-input exclusive OR gate (XOR_8), and the ninth two-input exclusive OR gate (XOR_9); The output ends of the first two-input exclusive OR gate (XOR_1), the second two-input exclusive OR gate (XOR_2), and the third two-input exclusive OR gate (XOR_3) serve as input signals of the first three-input AND gate (AND3_1), the output ends of the fourth two-input exclusive OR gate (XOR_4), the fifth two-input exclusive OR gate (XOR_5), and the sixth two-input exclusive OR gate (XOR_6) serve as input signals of the second three-input AND gate (AND3_2), and the output ends of the seventh two-input exclusive OR gate (XOR_7), the eighth two-input exclusive OR gate (XOR_8), and the ninth two-input exclusive OR gate (XOR_9) serve as input signals of the third three-input AND gate ( The output signals of the second three-input AND gate (AND3_2) and the third three-input AND gate (AND3_3) serve as the input signals of the third two-input AND gate (AND_2). The output terminals of the first three-input AND gate (AND3_1) and the third two-input AND gate (AND_2) are respectively connected to two input terminals C2 and C3 of a fourth data selector (MUX_4). The other two input terminals C1 and C4 of the fourth data selector (MUX_4) are respectively connected to a high level and a low level. The output terminal Y of the fourth data selector (MUX_4) serves as the output terminal CO of the data filtering circuit.

6. A histogram peak detection method for a laser ranging system based on the histogram peak detection circuit according to any one of claims 1 to 5, characterized in that: The histogram peak detection method comprises the following steps: The workflow of the entire circuit is divided into three stages: the peak detection stage of the upper three bits, the peak detection stage of the middle three bits, and the peak detection stage of the lower three bits: (1) Peak detection phase of the upper three bits: Before the detection begins, the external segment control signal S1S0 is 00, and the external MOS capacitor reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The arrival of the external enable signal EN inputs the first group of 9-bit TDC data into the selection circuit. The selection circuit decodes the upper three bits of the TDC data through the data selector and decoder to select the corresponding histogram unit for accumulation. The histogram accumulation is performed by discharging the MOS capacitor MOS_C. This process is repeated until all TDC data are accumulated. The corresponding histogram unit U[n] will output the peak signal Y[n] to the peak readout circuit. At the same time, the peak signal Y[n] will reset the MOS capacitor gates of the two adjacent histogram units to V ref , to avoid generating multiple peaks; the peak readout circuit outputs the high three peak values ​​Q[8:6] of the TDC data to the D flip-flop storage unit through the encoder and the data distributor; (2) Peak detection stage of the middle three bits: After the peak detection of the upper three bits is completed, the external segment control signal S1S0 changes to 01, and the external MOS capacitor reset signal RstC recharges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit filters out valid TDC data within the range of the upper three-digit peak value Q[8:6] and repeats the histogram accumulation process until the peak readout circuit outputs the middle three-digit peak value Q[5:3]; (3) Peak detection phase of the lower three bits: After the peak detection of the middle three bits is completed, the external segment control signal S1S0 changes to 10, and the external MOS capacitor reset signal RstC charges the gate potential of the MOS capacitor MOS_C to the reference potential V ref The data filtering circuit selects valid TDC data within the range of the upper three and middle three peak values ​​Q[8:6] and Q[5:3] and repeats the histogram accumulation process until the peak readout circuit outputs the lower three peak values ​​Q[2:0], thereby completing the peak detection of the 9-bit TDC data. After the external segment control signal S1S0 becomes 11, the target position information is calculated based on the histogram peak value.

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