Method of manufacturing a semiconductor device

Abstract

The present disclosure provides methods of fabricating semiconductor devices. A semiconductor device includes a lower structure including a lower conductor, an upper structure on the lower structure having an opening exposing the lower conductor, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recessed region in the opening, and a second tungsten layer filling the recessed region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Description

[0001] This application is a divisional application of Samsung Electronics Co., Ltd.'s invention patent application filed on August 29, 2016, entitled "Semiconductor Device and Manufacturing Method Thereof", with application number 201610756035.7. Technical Field

[0002] The exemplary embodiments of the subject matter disclosed herein relate to semiconductor devices and methods of manufacturing the same. More specifically, the exemplary embodiments relate to three-dimensional (3D) semiconductor devices with improved reliability and methods of manufacturing the same. Background Technology

[0003] Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include a variety of tiny electronic components (e.g., MOS transistors, resistors, capacitors, and / or interconnects). These tiny electronic components can be electrically connected to each other via interconnects and / or contact plugs.

[0004] However, the need for highly integrated and / or high-speed semiconductor devices has led to a reduction in the distance between interconnects and an increase in the aspect ratio of contact plugs. Therefore, processes capable of manufacturing highly integrated semiconductor devices have been investigated. Summary of the Invention

[0005] Exemplary implementations of publicly available topics can provide semiconductor devices that can improve reliability.

[0006] The demonstrative implementation of the disclosed subject matter can also provide methods for manufacturing semiconductor devices that can improve reliability.

[0007] In one exemplary embodiment, a semiconductor device may include: a lower structure including a lower conductor, an upper structure disposed on the lower structure and having an opening exposing the lower conductor, and a connection structure filling the opening and connected to the lower conductor. The connection structure may include a first tungsten layer covering the inner surface of the opening and defining a recessed region within the opening, and a second tungsten layer filling the recessed region on the first tungsten layer. The grain size of the second tungsten layer in the upper portion of the connection structure may be larger than the grain size of the second tungsten layer in the lower portion of the connection structure.

[0008] In some exemplary implementations, the average grain size of the second tungsten layer can be larger than the average grain size of the first tungsten layer.

[0009] In other exemplary embodiments, the connection structure may include a first interface formed by grains of a first tungsten layer and grains of a second tungsten layer, and a second interface formed by grains of a second tungsten layer in the central region of the connection structure.

[0010] In other exemplary implementations, the connecting structure may have a linear shape extending in one direction, and the first and second interfaces may extend parallel to the connecting structure.

[0011] In another exemplary embodiment, the semiconductor device may include a stack of layers extending in one direction and spaced apart from each other on a substrate. Each stack includes vertically stacked electrodes, a vertical structure penetrating the stack, a common source line structure disposed between adjacent stacks and spaced apart from the vertical structures, and an insulating spacer disposed between the common source line structure and the stack. The common source line structure may extend parallel to the electrodes. The common source line structure may include a first tungsten layer covering the insulating spacer and defining a recessed region, and a second tungsten layer filling the recessed region on the first tungsten layer. The grain size of the second tungsten layer in the upper part of the common source line structure may be larger than the grain size of the second tungsten layer in the lower part of the common source line structure.

[0012] In another exemplary embodiment, a method of manufacturing a semiconductor device may include: forming an upper structure having an opening that exposes a lower conductor; depositing a first tungsten layer covering an inner surface of the opening and defining a recessed region in the opening; performing a surface treatment process on a portion of the first tungsten layer, the first tungsten layer having a first surface treated by the surface treatment process in an upper region of the opening and a second surface not treated by the surface treatment process in a lower region of the opening; and depositing a second tungsten layer filling the recessed region. The size of the tungsten grains grown from the first surface of the first tungsten layer may be larger than the size of the tungsten grains grown from the second surface of the first tungsten layer. Attached Figure Description

[0013] The exemplary implementation will become clearer thanks to the accompanying drawings and detailed descriptions.

[0014] Figures 1 to 7 This is a view illustrating some exemplary implementations of methods for manufacturing semiconductor devices based on the disclosed subject matter.

[0015] Figure 8A yes Figure 7 A magnified view of part 'A'.

[0016] Figure 8B and 8C yes Figure 7 A magnified view of part 'B'.

[0017] Figure 9 This is a cross-sectional view illustrating methods for manufacturing semiconductor devices according to some exemplary implementations of the disclosed subject matter.

[0018] Figure 10 and 11 This is a cross-sectional view illustrating methods for manufacturing semiconductor devices according to some exemplary implementations of the disclosed subject matter.

[0019] Figure 12 This is a schematic block diagram illustrating some exemplary implementations of three-dimensional (3D) semiconductor memory devices based on the disclosed subject matter.

[0020] Figure 13 This is a schematic circuit diagram showing a cell array of 3D semiconductor memory devices according to some exemplary implementations of the disclosed subject matter.

[0021] Figure 14 This is a plan view showing some exemplary implementations of 3D semiconductor memory devices based on the disclosed subject matter.

[0022] Figures 15 to 24 It is along Figure 14 The cross-sectional view obtained by line I-I' is used to illustrate some exemplary implementations of methods for manufacturing 3D semiconductor memory devices according to the disclosed subject matter.

[0023] Figure 25A and 25B yes Figure 22 A magnified view of part 'A'.

[0024] Figure 26A , 26B 26C and 26D are Figure 22 A magnified view of part 'B'.

[0025] Figure 27 This is a plan view showing some exemplary implementations of 3D semiconductor memory devices based on the disclosed subject matter.

[0026] Figure 28 and 29 It is along Figure 27 The cross-sectional views obtained along lines I-I' and II-II' illustrate methods for manufacturing 3D semiconductor memory devices according to some exemplary implementations of the disclosed subject matter.

[0027] Figure 30 and 31 It is shown in detail Figure 29 An enlarged cross-sectional view of the manufacturing method of 3D semiconductor memory devices.

[0028] Figure 32 This is a schematic block diagram illustrating some exemplary implementations of 3D semiconductor memory devices based on the disclosed subject matter.

[0029] Figure 33 This is a plan view showing some exemplary implementations of 3D semiconductor memory devices based on the disclosed subject matter.

[0030] Figure 34 For along Figure 33 The cross-sectional view obtained by line I-I'.

[0031] Figure 35 It is shown Figure 34 Enlarged cross-sectional view of the connector plug.

[0032] Figure 36 This is a cross-sectional view showing some exemplary implementations of semiconductor memory devices based on the disclosed subject matter. Detailed Implementation

[0033] Exemplary embodiments of the disclosed subject matter will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosed subject matter are shown. The advantages and features of the exemplary embodiments, as well as methods of implementing them, will become apparent from the following description with reference to the accompanying drawings. However, it should be noted that the exemplary embodiments are not limited to the examples described below, but can be implemented in various forms. Therefore, the exemplary embodiments are provided only to disclose the subject matter described herein and to allow those skilled in the art to understand the scope of the subject matter. In the accompanying drawings, the exemplary embodiments are not limited to the specific examples provided herein and are exaggerated for clarity. Throughout the specification, the same reference numerals or reference indicators refer to the same elements.

[0034] The terminology used herein is used only to describe specific exemplary implementations and is not intended to limit the exemplary implementations. As used herein, the singular terms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. It will be further understood that, when used herein, the terms “comprising” and / or “including” describe the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, element components, and / or groups thereof. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being “on” another element, it may be directly on the other element or intermediate elements may be present. Conversely, the term “directly” implies the absence of intermediate elements.

[0035] Furthermore, the exemplary embodiments are described herein with reference to cross-sectional and / or planar views as idealized exemplary views. In the figures, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be interpreted as limited to the shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0036] The exemplary implementation will be described in detail below with reference to the accompanying drawings.

[0037] Figures 1 to 7 This is a view illustrating a method for manufacturing a semiconductor device according to some exemplary implementations. Figure 8A yes Figure 7 A magnified view of part 'A'. Figure 8B and 8C yes Figure 7 A magnified view of part 'B'. Figure 9 This is a cross-sectional view illustrating a method for manufacturing semiconductor devices according to some exemplary implementations.

[0038] like Figure 1 As shown, an upper structure 20 with an opening 25 can be formed on a lower structure 10 including a lower conductor 15.

[0039] The lower structure 10 may include a semiconductor substrate, semiconductor components (not shown, such as memory elements, MOS transistors, capacitors, and / or resistors) formed on the semiconductor substrate, and one or more insulating layers covering the semiconductor components. The semiconductor components may be electrically connected to the lower conductor 15. For example, the lower conductor 15 may be a doped region, an interconnect, or a contact plug.

[0040] The upper structure 20 may include a semiconductor layer, multiple insulating layers, and / or multiple conductive layers. An opening 25 may penetrate the upper structure 20 to expose the lower conductor 15. The opening 25 may be a hole or trench extending in one direction. The opening 25 may have a large aspect ratio of approximately 5:1 to approximately 30:1.

[0041] Forming the opening 25 may include forming a mask pattern MP with an opening on the upper structure 20, and using the mask pattern MP as an etching mask to anisotropically etch the upper structure 20 to expose a portion of the lower conductor 15.

[0042] The upper end of the opening 25 may have a first width W1. The first width W1 may be substantially equal to the width of the opening of the mask pattern MP. The lower end of the opening 25 may have a second width W2, which is smaller than the first width W1.

[0043] The opening 25 may include an upper region 25U with negatively inclined sidewalls and a lower region 25L with positively inclined sidewalls, or vice versa. Thus, the opposing sidewall surfaces have sidewall surfaces with negative to positive slopes and sidewall surfaces with positive to negative slopes, respectively. A curved region 25B may be provided between the upper region 25U and the lower region 25L. The opening 25 may have a third width W3 in the curved region 25B. The third width W3 may be greater than the first width W1 and the second width W2. The third width W3 may correspond to the maximum width of the opening 25. The sidewalls of the opening 25 may be rounded in the curved region 25B. The vertical length of the lower region 25L with positively inclined sidewalls may be greater than approximately half the vertical length of the opening 25. Here, the vertical length of the opening 25 may correspond to the vertical distance from the top surface of the lower structure 10 to the top surface of the upper structure 20 (i.e., the thickness of the upper structure 20).

[0044] After the opening 25 is formed, the mask pattern MP can be removed to expose the top surface of the upper structure 20.

[0045] like Figure 2 As shown, the barrier metal layer 30 and the first tungsten layer 40 can be sequentially formed in the opening 25.

[0046] The barrier metal layer 30 can be uniformly deposited on the inner surface of the opening 25 and the top surface of the upper structure 20. In other words, the barrier metal layer 30 can have a substantially uniform thickness. The barrier metal layer 30 can be formed of a material capable of preventing the diffusion of metallic material formed in the opening 25 into the upper structure 20. For example, the barrier metal layer 30 can include at least one of tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), or tungsten nitride (WN). The barrier metal layer 30 can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). In some exemplary embodiments, the barrier metal layer 30 can be formed of titanium nitride (TiN).

[0047] The barrier metal layer 30 may have uniform nucleation sites on its surface from which tungsten grains can grow. As the number of nucleation sites increases, the size of the tungsten grains can be reduced.

[0048] The first tungsten layer 40 can be deposited on the surface of the barrier metal layer 30. The first tungsten layer 40 can be deposited using a thermal CVD method, a plasma-enhanced CVD method, a physical CVD method, or an ALD method. In some exemplary embodiments, the first tungsten layer 40 can be formed by a CVD method using process gases including tungsten hexafluoride (WF6) and silane (SiH4; or hydrogen (H2)).

[0049] When the first tungsten layer 40 is deposited on the surface of the barrier metal layer 30, tungsten grains can grow from the surface of the barrier metal layer 30. The tungsten grains can grow in a direction substantially perpendicular to the sidewalls of the opening 25. In other words, the tungsten grains can grow laterally.

[0050] The first tungsten layer 40 may define a recessed region 45 when deposited on the surface of the barrier metal layer 30. The recessed region 45 may have sidewalls facing each other and a bottom surface connecting the lower ends of the sidewalls. In some exemplary embodiments, the depth of the recessed region 45 may be greater than about half the vertical length of the opening 25 (i.e., about half the thickness of the superstructure 20).

[0051] In some exemplary implementations, the thickness of the first tungsten layer 40 may be less than the minimum width of the opening 25 (e.g., Figure 1 The width W2) is half of the width of the opening. In this case, the first tungsten layer 40 may have a substantially uniform thickness on the sidewalls and bottom surface of the opening 25.

[0052] In some exemplary implementations, such as Figure 9 As shown, the thickness of the first tungsten layer 40 can be less than the width of the upper end of the opening 25. Figure 1 Approximately half the width of W1 and greater than the width of the lower end of opening 25. Figure 1 Approximately half of W2). In this case, a portion of the lower region 25L of the opening 25 can be filled with the first tungsten layer 40, such as Figure 9 As shown. In other words, the first tungsten layer 40 may be thicker on the bottom surface of the opening 25 than on the sidewall of the opening 25.

[0053] like Figure 3 and 4 As shown, the surface treatment process can be performed on a portion of the first tungsten layer 40. The surface treatment process can be performed using at least one of plasma treatment, nitriding treatment, or ultraviolet (UV) treatment.

[0054] In some exemplary embodiments, the surface treatment process can be performed on a portion of the sidewall of the recessed region 45. In other words, the surface treatment process can be performed on the surface of the first tungsten layer 40 formed in the upper region 25U and the curved region 25B of the opening 25. Alternatively, the surface treatment process can be performed on a portion of the first tungsten layer 40 formed in the lower region 25L of the opening 25. In some exemplary embodiments, the surface treatment process can be performed on the entire sidewall of the recessed region 45, such as... Figure 4 As shown.

[0055] The surface of the defined recessed region 45 of the first tungsten layer 40 can be in an unstable energy state, thus allowing for the existence of numerous dangling bonds. These dangling bonds can serve as nucleation sites, which can be reduced through surface treatment processes.

[0056] In some exemplary embodiments, the first tungsten layer 40 may have a first surface S1 treated by a surface treatment process and a second surface S2 not treated by a surface treatment process. The first surface S1 of the first tungsten layer 40 may be formed in the upper region 25U, the curved region 25B, and a portion of the lower region 25L of the opening 25. The second surface S2 of the first tungsten layer 40 may be formed in another portion of the lower region 25L of the opening 25. In some exemplary embodiments, because the surface of the first tungsten layer 40 is locally treated by a surface treatment process, the tungsten growth rate (e.g., deposition rate) on the first surface S1 of the opening 25 during the subsequent tungsten deposition process may be lower than the tungsten growth rate on the second surface S2 of the opening 25.

[0057] In some exemplary embodiments, a plasma treatment process, as a surface treatment process, can be performed on the first tungsten layer 40. A process gas including at least one of Ar, H2, N2, O2, or NH3 can be used during the plasma treatment process. Atoms or ions activated by the plasma can combine with a portion of the surface of the first tungsten layer 40 (i.e., the first surface S1), thus allowing the first surface S1 to be in a stable energy state. Therefore, the surface morphology of the first surface S1 treated by plasma can be improved compared to the surface morphology of the second surface S2 without plasma treatment. In other words, the number of dangling bonds on the first surface S1 treated by plasma can be less than the number of dangling bonds on the second surface S2 without plasma treatment. As a result, the number of nucleation sites on the first surface S1 of the first tungsten layer 40 can be reduced.

[0058] According to an exemplary embodiment, since plasma is supplied downwards to the opening 25 during the plasma processing process, the intensity of the plasma in the upper region 25U of the opening 25 can be greater than the intensity of the plasma in the lower region 25L of the opening 25. Therefore, a portion of the first tungsten layer 40 disposed in the lower region 25L of the opening 25 may not be plasma-treated. In other words, the area of ​​the first surface S1 that is plasma-treated during the plasma processing process can vary depending on the intensity of the plasma. In some exemplary embodiments, the first surface S1 of the first tungsten layer 40 can be formed in the upper region 25U, the curved region 25B, and a portion of the lower region 25L of the opening 25, such as... Figure 3 As shown. In some exemplary embodiments, the entire sidewall of the recessed area 45 may correspond to the first surface S1, such as... Figure 4 As shown.

[0059] like Figure 5 As shown, a second tungsten layer 50 can be deposited to fill the recessed region 45 of the first tungsten layer 40. The second tungsten layer 50 can be deposited using thermal CVD, plasma-enhanced CVD, physical CVD, or ALD methods. For example, the second tungsten layer 50 can be formed using a CVD method employing process gases including tungsten hexafluoride (WF6) and silane (SiH4; or hydrogen (H2)). As described above, since the second tungsten layer 50 is deposited after a surface treatment process, the first interface IF1 can be formed by the bonding of the grains of the first tungsten layer 40 and the grains of the second tungsten layer 50, as shown in... Figure 8A , 8B Similar to that shown in 8C (although) Figure 7 (Use reference numerals 31, 41, and 51 in the attached figures).

[0060] The grain growth rate and grain size of the second tungsten layer 50 can be varied depending on the surface condition of the first tungsten layer 40. According to some exemplary embodiments, the grain growth rate of the second tungsten layer 50 on the first surface S1 of the first tungsten layer 40 can be lower than the grain growth rate of the second tungsten layer 50 on the second surface S2 of the first tungsten layer 40. Therefore, the second tungsten layer 50 can be deposited in the lower region 25L of the opening 25 faster than it is deposited in the upper region 25U and the curved region 25B of the opening 25. In other words, the second tungsten layer 50 can fill the opening 25 from the lower region 25L. Furthermore, the deposition rate (or growth rate) of the second tungsten layer 50 on the top surface of the upper structure 20 can be lower than the deposition rate of the second tungsten layer 50 in the upper region 25U of the opening 25. Therefore, the thickness of the second tungsten layer 50 on the top surface of the upper structure 20 can be less than the thickness of the second tungsten layer 50 deposited on the sidewall of the opening 25.

[0061] Because the second surface S2 of the first tungsten layer 40 has more nucleation sites than the first surface S1 of the first tungsten layer 40 when the second tungsten layer 50 is formed, large tungsten grains can grow on the first surface S1 of the first tungsten layer 40, and small tungsten grains can grow on the second surface S2 of the first tungsten layer 40. In other words, when the second tungsten layer 50 is deposited, the size of the grains on the first surface S1 can be larger than the size of the grains on the second surface S2. Furthermore, the grains of the second tungsten layer 50 grown on the first surface S1 can be larger than the grains of the first tungsten layer 40.

[0062] The grains of the second tungsten layer 50 grown from the first surface S1 and the second surface S2 can grow laterally until they contact each other. In other words, the grains of the second tungsten layer 50 grown from the sidewalls of the recessed region 45 can meet each other in the central region of the recessed region 45, so that the second interface IF2 can be formed by the grains of the second tungsten layer 50 in the central region of the recessed region 45.

[0063] In some exemplary implementations, due to the surface treatment process, the growth rate of tungsten grains gradually decreases from the lower region 25L of the opening 25 toward the upper region 25U. Therefore, the second tungsten layer 50 can fill the opening 25 from the lower region 25L. As a result, the opening 25 can be completely filled using tungsten layers 40 and 50 without gaps or seams.

[0064] like Figure 6 As shown, the third tungsten layer 60 can be deposited on top of the second tungsten layer 50, which completely fills the recessed region 45. In other words, the third tungsten layer 60 can be deposited on the top surface of the upper structure 20. The deposition rate of the third tungsten layer 60 can be higher than that of the second tungsten layer 50. The third tungsten layer 60 can be deposited rapidly for a predetermined time, so the third tungsten layer 60 can be thicker than the second tungsten layer 50. Furthermore, the grain size of the third tungsten layer 60 can be larger than that of the second tungsten layer 50, and the third tungsten layer 60 can have a rough surface. During the subsequent planarization process, the third tungsten layer 60 can act as a buffer. In some exemplary embodiments, the third tungsten layer 60 can be omitted.

[0065] like Figure 7 As shown, the planarization process can be performed on the first to third tungsten layers 41, 51, and 60 and the barrier metal layer 31 until the top surface of the upper structure 20 is exposed. The planarization process can be performed using a blanket anisotropic etching process (e.g., an etch-back process) and / or a chemical mechanical polishing (CMP) process.

[0066] The connection structure 70 can be formed in the opening 25 by a planarization process. The connection structure 70 can completely fill the opening 25. The connection structure 70 may include a blocking metal pattern 31, a first tungsten pattern 41, and a second tungsten pattern 51. In some exemplary embodiments, the connection structure 70 may have a linear shape extending in one direction and may contact the lower conductor 15. In some exemplary embodiments, the connection structure 70 may have a cylindrical shape.

[0067] The vertical length of the connecting structure 70 can be substantially equal to the thickness of the upper structure 20. The vertical length of the connecting structure 70 can refer to the length from the top surface of the lower structure 10 to the top surface of the connecting structure 70. The sidewall profile of the filling opening 25 of the connecting structure 70 can be substantially the same as the sidewall profile of the opening 25. Therefore, the connecting structure 70 can include an upper portion with negatively inclined sidewalls and a lower portion with positively inclined sidewalls, or vice versa. Thus, the opposing sidewall surfaces have a negative-to-positive slope sidewall surface and a positive-to-negative slope sidewall surface, respectively. A curved portion is provided between the upper and lower portions. The curved portion of the connecting structure 70 can be positioned at a level higher than half the thickness of the upper structure 20 from the top surface of the lower structure 10. In other words, the vertical length of the lower portion of the connecting structure 70 can be greater than the sum of the vertical lengths of the upper portion and the curved portion of the connecting structure 70. The curved portion of the connecting structure 70 can have a third width ( Figure 1 W3), the third width ( Figure 1 W3) can be larger than the width of the upper and lower parts of the connecting structure 70. Figure 1 W1 and W2). In some exemplary implementations, the third width ( Figure 1 W3) can be the maximum width of the connection structure 70.

[0068] like Figure 8A , 8B As shown in 8C, the grains of the first tungsten pattern 41 can contact the grains of the second tungsten pattern 51 to form a first interface IF1 in the connection structure 70. Additionally, the grains of the second tungsten pattern 51 can contact each other to form a second interface IF2 in the central region of the connection structure 70. In some exemplary embodiments, the connection structure 70 may have a line shape extending in one direction, so that the first and second interfaces IF1 and IF2 can extend in said one direction. Furthermore, the vertical length of the second interface IF2 formed in the second tungsten pattern 51 may be greater than half the vertical length of the connection structure 70.

[0069] In some exemplary embodiments, the average grain size in the second tungsten pattern 51 can be larger than the average grain size in the first tungsten pattern 41. The grain size of the second tungsten pattern 51 grown from the first surface of the first tungsten pattern 41 can be larger than the grain size of the second tungsten pattern 51 grown from the second surface of the first tungsten pattern 41. In other words, as... Figure 8A and 8B As shown, the grain size of the second tungsten pattern 51 can be larger in the upper part of the connecting structure 70 than in the lower part of the connecting structure 70. Figure 8A As shown, in the upper part of the connecting structure 70, the size of the grains of the second tungsten pattern 51 can be larger than the size of the grains of the first tungsten pattern 41. For example... Figure 8BAs shown, in the lower part of the connecting structure 70, the size of the grains of the second tungsten pattern 51 can be similar to the size of the grains of the first tungsten pattern 41.

[0070] Alternatively, in reference Figure 4 When the entire sidewall of the recessed area 45 is treated by a surface treatment process, the grain size of the second tungsten pattern 51 in the lower and upper parts of the connecting structure 70 can be larger than the grain size of the first tungsten pattern 41, such as... Figure 8C As shown.

[0071] Figure 10 and 11 This is a cross-sectional view illustrating methods for manufacturing semiconductor devices according to some exemplary embodiments of the disclosed subject matter. In this exemplary embodiment, for ease of explanation, references to the references will be omitted or briefly mentioned. Figure 1 and 2 The description of the same technical features in the described process.

[0072] like Figure 10 As shown, the barrier metal layer 30 and the first tungsten layer 40 can be sequentially deposited on the inner surface of the opening 25 that exposes the lower conductor 15.

[0073] A first tungsten layer 40 may define a recessed region 45 in the opening 25 and may be deposited on the surface of the barrier metal layer 30. The recessed region 45 may have sidewalls facing each other and a bottom surface connecting the lower ends of the sidewalls. In some exemplary embodiments, the depth of the recessed region 45 may be greater than half the depth of the opening 25 (i.e., half the thickness of the superstructure 20).

[0074] In some exemplary embodiments, after the deposition of the first tungsten layer 40, a metal nitride layer 42 can be formed on a portion of the surface of the first tungsten layer 40 using a deposition method with poor step coverage characteristics. For example, the metal nitride layer 42 may include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, or TaAlN.

[0075] For example, deposition methods with poor step coverage characteristics may include PVD methods, metal-organic CVD (MOCVD) methods, collimated sputtering methods, ionized metal PVD (IMP) methods, or any combination thereof.

[0076] The metal nitride layer 42 can be thinner than the first tungsten layer 40. Additionally, the metal nitride layer 42 can be thinner than the barrier metal layer 30. When a deposition method with poor step coverage characteristics is performed to deposit the metal nitride layer 42, the characteristics of the deposition method result in the metal nitride layer 42 deposited on the sidewall of the opening 25 being thinner than the metal nitride layer 42 deposited on the top surface of the upper structure 20. In other words, an overhang of the metal nitride layer 42 can be formed at the upper end of the opening 25, thus the metal nitride layer 42 can gradually thin from the upper region 25U of the opening 25 towards the lower region 25L. The metal nitride layer 42 can be formed in the upper region 25U and the curved region 25B of the opening 25, and a portion of the first tungsten layer 40 formed in the lower region 25L of the opening 25 can be exposed.

[0077] The metal nitride layer 42 formed in the upper region 25U and the curved region 25B of the opening 25 can inhibit tungsten deposition during subsequent processes that form the second tungsten layer 50.

[0078] like Figure 11 As shown, a second tungsten layer 50 can be deposited to fill the recessed region 45 of the first tungsten layer 40 in which a metal nitride layer 42 is formed.

[0079] During the deposition of the second tungsten layer 50, the deposition rate of tungsten in the upper region 25U and the curved region 25B of the opening 25 in which the metal nitride layer 42 is formed can be lower than the deposition rate of tungsten in the lower region 25L of the opening 25. In other words, during the deposition of the second tungsten layer 50, the deposition rate of tungsten on the surface of the metal nitride layer 42 can be lower than the deposition rate of tungsten on the surface of the first tungsten layer 40. Therefore, the second tungsten layer 50 can fill the opening 25 from the lower region 25L. As a result, the second tungsten layer 50 can completely fill the recessed region 45 with a large aspect ratio.

[0080] In some exemplary embodiments, the metal nitride layer 42 may be disposed between the grains of the first tungsten layer 40 and the grains of the second tungsten layer 50 in the upper region 25U of the opening 25. In the lower region 25L of the opening 25, the grains of the first tungsten layer 40 may be in direct contact with the grains of the second tungsten layer 50.

[0081] The grains of the second tungsten layer 50, grown from the surfaces of the metal nitride layer 42 and the first tungsten layer 40, can grow laterally until they contact each other. In other words, the grains of the second tungsten layer 50, grown from the opposite sidewalls of the recessed region 45, can meet each other in the central region of the recessed region 45, so that the second interface IF2 formed by the grains of the second tungsten layer 50 can be formed in the central region of the recessed region 45.

[0082] Subsequently, a planarization process can be performed on the second tungsten layer 50, the first tungsten layer 40, and the barrier metal layer 30 to form a connection structure in the opening 25.

[0083] Figure 12 This is a schematic block diagram illustrating some exemplary implementations of three-dimensional (3D) semiconductor memory devices based on the disclosed subject matter. Figure 13 This is a schematic circuit diagram showing a cell array of 3D semiconductor memory devices according to some exemplary implementations of the disclosed subject matter.

[0084] like Figure 12 As shown, a 3D semiconductor memory device may include a memory cell array 1, a row decoder 2, a page buffer 3, a column decoder 4, and a control circuit 5.

[0085] The memory cell array 1 may include multiple memory blocks BLK0 to BLKn. Each memory block BLK0 to BLKn may include multiple memory cells, multiple word lines, and multiple bit lines. The word lines and bit lines may be electrically connected to the memory cells.

[0086] Row decoder 2 can decode address signals input from an external system to select one of the word lines. The address signals decoded in row decoder 2 can be provided to the row driver (not shown). The row driver can provide word line voltages generated from voltage generation circuit (not shown) to the selected and unselected word lines in response to control signals from control circuit 5. Row decoder 2 can be connected to multiple memory blocks BLK0 to BLKn and can provide drive signals to the word lines of the memory blocks selected by the block selection signals.

[0087] Page buffer 3 can be connected to memory cell array 1 via bit lines to sense data stored in the memory cells. Page buffer 3 can be connected to bit lines selected by address signals decoded in column decoder 4. Depending on the operating mode, page buffer 3 can temporarily store data to be stored in the memory cells or sense data stored in the memory cells. For example, page buffer 3 can operate as a write driver during programming operation mode and as a sense amplifier during sensing operation mode. Page buffer 3 can receive power (e.g., voltage or current) from control circuitry 5 and can provide the received power to the selected bit lines.

[0088] Column decoder 4 provides a data transfer path between page buffer 3 and external devices (e.g., memory controllers). Column decoder 4 can decode address signals input from external devices to select one of the bit lines. Column decoder 4 can be connected to multiple memory blocks BLK0 to BLKn and can provide data to the bit lines of the memory block selected by the block select signal.

[0089] Control circuit 5 can control the entire operation of the 3D semiconductor memory device. Control circuit 5 can receive control signals and external voltages and can be operated in response to the received control signals. Control circuit 5 may include a voltage generator that generates voltages necessary for internal operation (e.g., programming voltage, read voltage, and erase voltage) based on an external voltage. Control circuit 5 can control read operations, write operations, and / or erase operations in response to control signals.

[0090] like Figure 13 As shown, a cell array of a 3D semiconductor memory device according to some exemplary embodiments may include a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR connected between the common source line CSL and the bit lines BL.

[0091] Bit lines BL can be arranged in a two-dimensional configuration. Multiple unit strings CSTR can be connected in parallel to each bit line BL. The unit strings CSTR can be connected together to a common source line CSL. In other words, multiple unit strings CSTR can be positioned between a common source line CSL and multiple bit lines BL. In some exemplary embodiments, the common source line CSL may include multiple common source lines CSL arranged in a two-dimensional configuration. In exemplary embodiments, the same voltage can be applied to multiple common source lines CSL. In exemplary embodiments, the common source lines CSL can be electrically controlled independently of each other.

[0092] Each cell string (CSTR) may include a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), and multiple memory cell transistors (MCTs) interposed between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors (SSTs) may be connected in series with each other in a specified order.

[0093] The common source line CSL can be connected to the source of the ground select transistor GST. The ground select line GSL, multiple word lines WL0 to WL3, and the string select line SSL, located between the common source line CSL and the bit line BL, can be used as the gate electrodes of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. Each memory cell transistor MCT may include data storage elements.

[0094] Figure 14 This is a plan view showing a 3D semiconductor memory device according to some exemplary implementations. Figures 15 to 24 It is along Figure 14 The cross-sectional view obtained by line I-I' is shown to illustrate a method for manufacturing 3D semiconductor memory devices according to some exemplary implementations of the inventive concept. Figure 25A and 25Byes Figure 22 A magnified view of part 'A'. Figure 26A , 26B 26C and 26D are Figure 22 A magnified view of part 'B'.

[0095] like Figure 14 and 15 As shown, the sacrificial layer SL and the insulating layer ILD can be alternately and repeatedly stacked on the substrate 10 to form a thin layer structure 110.

[0096] The substrate 10 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer obtained by performing a selective epitaxial growth (SEG) process.

[0097] In the thin-layer structure 110, the sacrificial layer SL can be formed of a material that has etch selectivity relative to the insulating layer ILD. For example, the difference between the etch rate of the sacrificial layer SL and the etch rate of the insulating layer ILD can be relatively large in a wet etching process using a chemical solution, while the difference between the etch rate of the sacrificial layer SL and the etch rate of the insulating layer ILD can be relatively small in a dry etching process using an etching gas.

[0098] In some exemplary embodiments, the sacrificial layer SL and the insulating layer ILD can be formed of insulating materials that are etch-selective relative to each other. For example, each sacrificial layer SL may include at least one of an undoped silicon layer, a silicon oxide layer, an undoped silicon carbide layer, an undoped silicon germanium layer, a silicon oxide nitride layer, or a silicon nitride layer. Each insulating layer ILD may include at least one of an undoped silicon layer, a silicon oxide layer, an undoped silicon carbide layer, a silicon oxide nitride layer, or a silicon nitride layer. In this case, the insulating layer ILD may be formed of a different material than the sacrificial layer SL. In some exemplary embodiments, the sacrificial layer SL may be formed of a silicon nitride layer, and the insulating layer ILD may be formed of a silicon oxide layer. In some exemplary embodiments, the sacrificial layer SL may be formed of a conductive material, and the insulating layer ILD may be formed of an insulating material.

[0099] The sacrificial layer SL and the insulating layer ILD can be deposited using thermal CVD, plasma-enhanced CVD, physical CVD, or ALD techniques.

[0100] In some exemplary embodiments, the thicknesses of the sacrificial layers SL can be substantially equal to each other. In some exemplary embodiments, the lowermost and uppermost sacrificial layers in the sacrificial layers SL can be thicker than the other sacrificial layers disposed between the lowermost and uppermost sacrificial layers. In some exemplary embodiments, the thicknesses of the insulating layers ILD can be equal to each other. In some exemplary embodiments, the thickness of one or more insulating layers ILD can differ from the thickness of the other insulating layers ILD. In some exemplary embodiments, the lowermost insulating layer ILD of the thin-layer structure 110 can be thinner than the sacrificial layers SL and insulating layers ILD disposed thereon. The lowermost insulating layer ILD may comprise a silicon oxide layer formed by a thermal oxidation process.

[0101] like Figure 14 and 16 As shown, the vertical structure VS can be formed as a penetrating thin-layer structure 110. The vertical structure VS can be connected to the substrate 10 (e.g., a semiconductor substrate) and may include semiconductor material or conductive material.

[0102] In some exemplary implementations, forming the vertical structure VS may include forming an opening through the thin-film structure 110 and forming semiconductor patterns in the opening.

[0103] A mask pattern (not shown) can be formed on the thin layer structure 110, which can be anisotropically etched using the mask pattern (not shown) as an etching mask to form openings. The top surface of the substrate 10 below the opening can be over-etched in an anisotropic etching process, so that the top surface of the substrate 10 exposed by the opening can be recessed to a predetermined depth. The width of the lower region of the opening can be smaller than the width of the upper region of the opening. When viewed in plan view, the openings can be arranged in a row or in a zigzag pattern along one direction.

[0104] Forming a semiconductor pattern in the opening may include forming semiconductor spacers that expose the substrate 10 and cover the sidewalls of the opening, and forming a semiconductor body portion connected to the substrate 10 in the opening. The semiconductor pattern may have a hollow tube shape or a hollow macaron shape. In this case, the semiconductor pattern may have a closed bottom end. The semiconductor pattern may include silicon (Si), germanium (Ge), or a combination thereof. The semiconductor pattern may include a doped semiconductor or an intrinsic semiconductor without dopant. The semiconductor pattern may have a crystal structure including at least one of a single-crystal structure, an amorphous structure, or a polycrystalline structure. The vertical structure VS may include a conductive pad formed in the top portion of the vertical structure VS. The conductive pad may be a doped region or may be formed of a conductive material.

[0105] In some exemplary implementations, such as Figure 24As shown, forming the vertical structure VS may include forming openings penetrating the thin-film structure 110, forming a lower semiconductor pattern LSP filling a lower region of each opening, forming a vertical insulating pattern VP in each opening having the lower semiconductor pattern LSP, and forming an upper semiconductor pattern USP in each opening having the vertical insulating pattern VP, the upper semiconductor pattern USP being connected to the lower semiconductor pattern LSP. Here, the lower semiconductor pattern LSP can be used as a reference. Figure 13 The described ground selection transistor GST has a channel region. The lower semiconductor pattern LSP can be formed from a semiconductor material doped with a dopant of the same conductivity type as the substrate 10. In some exemplary embodiments, the lower semiconductor pattern LSP can be an epitaxial pattern formed using epitaxial technology or laser crystallization technology and utilizing the substrate 10 as a seed. In this case, the lower semiconductor pattern LSP can have a single-crystal structure or a polycrystalline structure, the polycrystalline structure having a larger grain size than the semiconductor material formed by CVD technology. In some exemplary embodiments, the lower semiconductor pattern LSP can be formed from a polycrystalline semiconductor material (e.g., polycrystalline silicon). In some exemplary embodiments, an insulating pattern adjacent to the lower semiconductor pattern LSP can be in direct contact with the sidewalls of the lower semiconductor pattern LSP. In some exemplary embodiments, the lower semiconductor pattern LSP can have a pillar shape penetrating the lowermost sacrificial layer SL. The bottom surface of the lower semiconductor pattern LSP can be disposed at a level lower than the top surface of the substrate 10, and the top surface of the lower semiconductor pattern LSP can be disposed at a level higher than the top surface of the lowermost sacrificial layer SL.

[0106] In some exemplary embodiments, the vertical insulation pattern VP may be formed in the opening before the vertical structure VS is formed. The vertical insulation pattern VP may comprise one or more thin layers. According to exemplary embodiments, the vertical insulation pattern VP may correspond to a portion of the data storage layer. The data storage layer will be referred to later. Figures 26A to 26D To describe in more detail.

[0107] like Figure 16 As shown, after the vertical structure VS is formed, the cap dielectric layer 120 can be formed on the top surface of the thin layer structure 110.

[0108] like Figure 16 and 17 As shown, the cap dielectric layer 120 and the thin layer structure 110 can be patterned to form trenches T between the vertical structures VS that expose the substrate 10.

[0109] Forming the trench T may include forming a mask pattern (not shown) on the thin layer structure 110 that defines the planar location of the trench T, and anisotropically etching the thin layer structure 110 using the mask pattern (not shown) as an etching mask.

[0110] The trench T can be spaced apart from the vertical structure VS and can expose the sidewalls of the sacrificial layer SL and the insulating layer ILD. When viewed in plan view, the trench T can have a linear or rectangular shape extending in the first direction D1. As described above, when viewed in cross-sectional view, the trench T can expose the substrate 10. The top surface of the substrate 10 exposed by the trench T can be recessed to a predetermined depth by an over-etching process that forms the trench T. In some exemplary embodiments, the trench T can have sloping sidewalls.

[0111] Because of the formation of the groove T, the thin-layer structure 110 can be divided into linear structures extending in the first direction D1. Figure 14 Additionally, the dielectric pattern 125 can be formed on each linear structure of the thin-layer structure 110, such as... Figure 17 As shown. Multiple vertical structures VS can penetrate each linear structure of the thin-layer structure 110.

[0112] In some exemplary implementations, each trench T may include an upper region (see...). Figure 1 25U), lower region (see Figure 1 25L), and the curved area between the upper and lower regions (see Figure 1 25B), similar to reference Figure 1 The described opening 25. Each groove T may have the maximum width in the curved region (see...). Figure 1 (W3). In some exemplary implementations, the curved region of the trench T may be set at a level higher than the bottom surface of the uppermost sacrificial layer SL. Alternatively, the curved region of the trench T may be set at a level higher than the top surface of the uppermost sacrificial layer SL.

[0113] refer to Figure 14 and 18 The sacrificial layer SL exposed by the trench T can be removed to form the gate region GR between the insulating layers ILD.

[0114] The sacrificial layer SL can be isotropically etched using an etch formulation that is etch-selective relative to the insulating layer ILD, the vertical structure VS, and the substrate 10 to form the gate region GR. In this case, the sacrificial layer SL can be completely removed by an isotropic etching process. For example, if the sacrificial layer SL is a silicon nitride layer and the insulating layer ILD is a silicon oxide layer, the sacrificial layer SL can be isotropically etched using an etch solution including phosphoric acid. Additionally, during the isotropic etching process used to form the gate region GR, the vertical insulating pattern VP can be used as an etch stop layer.

[0115] The gate region GR can extend laterally from the trench T between the insulating layers ILD and can expose a portion of the sidewalls of the vertical insulating pattern VP or the vertical structure VS. In other words, each gate region GR can be defined by the sidewalls of the vertical insulating pattern VP and the vertically adjacent insulating layers ILD.

[0116] like Figure 14 and 19 As shown, the horizontal insulating layer can be formed to conformally cover the inner surface of the gate region GR.

[0117] The horizontal insulating layer may have a substantially uniform thickness on the inner surface of the gate region GR. The horizontal insulating layer may be formed from one or more thin layers. In some exemplary embodiments, the horizontal insulating layer may be part of the data storage layer of a charge-trapping flash memory transistor. Subsequently, a gate conductive layer may be formed to fill the gate region GR having the horizontal insulating layer. The gate conductive layer may partially or completely fill the trench T. In some exemplary embodiments, the gate conductive layer may include a barrier metal layer and a metal layer deposited sequentially. For example, the barrier metal layer may include a metal nitride layer, such as TiN, TaN, or WN. For example, the metal layer may include a metallic material, such as W, Al, Ti, Ta, Co, or Cu. The gate conductive layer and the horizontal insulating layer disposed outside the gate region GR may then be removed to form the electrode EL and the horizontal insulating pattern HP, respectively, in a confined manner within the gate region GR.

[0118] Since the electrode EL is formed in the gate region GR, the stacked structure ST can be formed on the substrate 10. Each stacked structure ST may include an insulating layer ILD and an electrode EL alternately and repeatedly stacked on the substrate 10. The stacked structure ST may extend in a first direction D1, and the sidewalls of the stacked structure ST may be exposed through trenches T. In addition, the substrate 10 may be exposed between adjacent stacked structures ST.

[0119] like Figure 14 and 20 As shown, a common source region (CSR) can be formed in a substrate 10 beneath a trench T between the stacked structures ST. The common source region CSR can extend parallel to a first direction D1 and can be spaced apart from each other in a second direction D2 intersecting the first direction D1. Dopant can be implanted into the substrate 10 to form the common source region CSR. The conductivity type of the common source region CSR can be different from the conductivity type of the substrate 10.

[0120] Insulating spacers SP can be formed to cover the sidewalls of the trench T. Forming insulating spacers SP can include conformally depositing a spacer layer on a substrate 10 having a stacked structure ST, and performing an etch-back process on the spacer layer to expose the common source region CSR. The spacer layer can be formed of an insulating material, and the thickness of the deposited spacer layer can be less than approximately half the minimum width of the trench T. For example, the spacer layer can be formed of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, or a low-k dielectric layer having a low dielectric constant.

[0121] In some exemplary implementations, the thickness of the insulating spacer SP formed on the upper sidewall of the laminated structure ST can be reduced by an etch-back process performed on the spacer layer. In other words, the thickness of the insulating spacer SP can gradually decrease towards the top surface of the uppermost insulating layer ILD.

[0122] like Figure 14 and 21 As shown, the common source line structure CSP can be formed in each trench T having insulating spacers SP.

[0123] According to some exemplary embodiments, in 3D semiconductor memory devices, a common source line structure (CSP) can be disposed between laterally adjacent electrodes (EL), and insulating spacers (SP) can be disposed between the common source line structure (CSP) and the electrodes (EL). In other words, the insulating spacers (SP) can cover the sidewalls of the common source line structure (CSP).

[0124] In some exemplary implementations, the Common Source Line Structure (CSP) can use reference [reference]. Figures 1 to 11 At least one of the methods for manufacturing the described semiconductor device is formed. In other words, forming a common source line structure CSP may include depositing a first tungsten layer 141 covering the inner surface of a trench T, processing a portion of the surface of the first tungsten layer 141, and depositing a second tungsten layer 151 on the first tungsten layer 141 to completely fill the trench T.

[0125] For more details, see references Figure 2 As described, the barrier metal layer 131 and the first tungsten layer 141 can be sequentially deposited on the inner surface of a trench having insulating spacers SP. The first tungsten layer 141 may have a thickness less than approximately half the minimum width of the trench, thus defining a recessed region in each trench. The depth of the recessed region may be greater than approximately half the depth of the trench. In other words, the depth of the recessed region may be greater than approximately half the thickness (or height) of the laminated structure ST.

[0126] Then, as referenced Figure 3 and 4As described, the surface treatment process can be performed on a portion of the surface of the first tungsten layer 141. For example, a plasma treatment process can be performed as a surface treatment process. After the plasma treatment process, the first tungsten layer 141 may have a first surface treated by the plasma treatment process and a second surface not treated by the plasma treatment process. Here, the area of ​​the first surface of the first tungsten layer 141 can be varied depending on the intensity of the plasma and / or the aspect ratio of the trenches. Meanwhile, instead of a surface treatment process, a metal nitride layer can be deposited on a portion of the first tungsten layer 141, as described in the reference... Figure 10 As described.

[0127] Subsequently, as referenced Figure 5 As described, the second tungsten layer 151 can be deposited to completely fill the recessed area of ​​the first tungsten layer 141. When the second tungsten layer 151 is deposited, the growth rate (i.e., deposition rate) and size of the tungsten grains can be varied according to the surface condition of the first tungsten layer 141. In other words, as... Figure 25A and 25B As shown, in the upper region of the trench, the grain size of the second tungsten layer 151 can be larger than the grain size of the first tungsten layer 141. Additionally, as shown in the reference... Figure 8A and 8B As described, the grain size of the second tungsten layer 151 in the upper region of the trench can be larger than the grain size of the second tungsten layer 151 in the lower region of the trench. In some exemplary embodiments, the thickness t2 of the second tungsten layer 151 can be greater than the thickness t1 of the first tungsten layer 141, such as... Figure 25A As shown. Alternatively, the thickness t2 of the second tungsten layer 151 can be substantially equal to the thickness t1 of the first tungsten layer 141, as... Figure 25B As shown.

[0128] like Figure 25A and 25B As shown, the grains of the second tungsten layer 151 can grow laterally from the sidewalls of the recessed region of the first tungsten layer 141. Therefore, the common source line structure CSP can have a second interface IF2 formed by the grains of the second tungsten layer 151 in the central region of the common source line structure CSP. Alternatively, the common source line structure CSP can also have a first interface IF1 formed by the dimensional difference between the grains of the first tungsten layer 141 and the grains of the second tungsten layer 151.

[0129] At the same time, such as Figure 23As shown, because the thickness of the insulating spacer SP adjacent to the upper part of the stacked structure ST gradually decreases towards the top of the stacked structure ST, the common source line structure CSP can have a maximum width W4 at its top surface. In other words, the common source line structure CSP can include the upper part adjacent to the uppermost insulating layer ILD, and the width of the upper part of the common source line structure CSP can gradually increase towards the top surface of the cover dielectric pattern 125. The common source line structure CSP can have a minimum width W2 at its bottom surface. The bottom surface of the common source line structure CSP can contact the common source electrode region CSR. Figure 14 and 22 As shown, the upper filling insulation layer 200 covering the top surface of the common source line structure CSP can be formed on the laminated structure ST.

[0130] Bit line contact plugs (BPLG) can be formed to penetrate the upper filler insulating layer 200 and can be connected to the vertical structure VS. Bit lines (BL) extending in the second direction D2 can then be formed on the upper filler insulating layer 200. Bit lines (BL) can be connected to the bit line contact plugs (BPLG). Additionally, common source lines (CSL) can also be formed on the upper filler insulating layer 200. Common source lines (CSL) can extend parallel to the bit lines (BL) along the second direction D2 and can be positioned between adjacent bit lines (BL). Common source lines (CSL) can be electrically connected to the common source line structure (CSP) via common source plugs (CSPLG).

[0131] Reference Figures 26A to 26D A detailed description of a data storage layer based on an exemplary implementation of the inventive concept.

[0132] According to an exemplary embodiment of the inventive concept, the 3D semiconductor memory device can be a NAND flash memory device. For example, the data storage layer DS between the vertical structure VS and the stacked structure ST may include a tunnel insulating layer TIL, a charge storage layer CIL, and a barrier insulating layer BK. The data stored in the data storage layer DS can be altered using the Flower-Nordheim tunneling phenomenon, which is caused by the voltage difference between the vertical structure VS, which comprises semiconductor material, and the electrode EL.

[0133] according to Figure 26A The exemplary implementation shown in the figure extends from between the electrode EL and the vertical structure VS to between the insulating layer ILD and the vertical structure VS.

[0134] according to Figure 26BIn the exemplary implementation shown, the tunnel insulation layer (TIL) and the charge storage layer (CIL) can extend from between the electrode EL and the vertical structure VS to between the insulation layer ILD and the vertical structure VS. The barrier insulation layer (BK) can extend from between the electrode EL and the vertical structure VS to the top and bottom surfaces of the electrode EL.

[0135] according to Figure 26C The exemplary implementation shown herein allows the tunnel insulation layer (TIL) to extend from between the electrode EL and the vertical structure VS to between the insulation layer ILD and the vertical structure VS. The charge storage layer (CIL) and the barrier insulation layer (BK) can extend from between the electrode EL and the vertical structure VS to the top and bottom surfaces of the electrode EL.

[0136] according to Figure 26D The exemplary implementation shown in the figure shows that the tunnel insulation layer TIL, the charge storage layer CIL, and the barrier insulation layer BK can extend from between the electrode EL and the vertical structure VS to the top and bottom surfaces of the electrode EL.

[0137] In the data storage layer (DS), the charge storage layer (CIL) may include at least one selected from the group consisting of trap site-rich insulating layers and insulating layers comprising nanoparticles, and may be formed using CVD or ALD techniques. For example, the charge storage layer (CIL) may include at least one of a trap insulating layer, a floating gate electrode, or an insulating layer comprising conductive nanodots. More specifically, the charge storage layer (CIL) may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxide nitride layer, a silicon nitride-rich layer, a nanocrystalline silicon layer, or a stacked trap layer.

[0138] The tunnel insulating layer (TIL) may include at least one of materials having a band gap larger than that of the charge storage layer (CIL) and may be formed by CVD or ALD techniques. For example, the TIL may include a silicon oxide layer formed using CVD or ALD techniques. Alternatively, the TIL may include at least one of high-k dielectric layers, such as an aluminum oxide layer and a hafnium oxide layer.

[0139] The barrier insulating layer BK may include first and second barrier insulating layers formed of different materials. One of the first and second barrier insulating layers may include a material whose band gap is smaller than that of the tunnel insulating layer TIL and larger than that of the charge storage layer CIL. The first and second barrier insulating layers may be formed using CVD or ALD techniques. In some exemplary embodiments, at least one of the first and second barrier insulating layers may be formed using a wet oxidation process. In some exemplary embodiments, the first barrier insulating layer may include at least one high-k dielectric layer, such as an aluminum oxide layer and a hafnium oxide layer, and the second barrier insulating layer may include a material whose dielectric constant is lower than that of the first barrier insulating layer. In some exemplary embodiments, the second barrier insulating layer may include at least one high-k dielectric layer, and the first barrier insulating layer may include a material whose dielectric constant is lower than that of the second barrier insulating layer.

[0140] Figure 27 This is a plan view showing some exemplary embodiments of 3D semiconductor memory devices based on the inventive concept. Figure 28 and 29 It is along Figure 27 The cross-sectional views obtained along lines I-I' and II-II' illustrate a method for manufacturing 3D semiconductor memory devices according to some exemplary implementations of the inventive concept. Figure 30 and 31 This is an enlarged cross-sectional view of a portion of a 3D semiconductor memory device, illustrating a method for manufacturing the 3D semiconductor memory device. In this exemplary embodiment, for ease of explanation, references to [specific components / methods] will be omitted or briefly mentioned. Figures 14 to 24 The same technical features are described in the exemplary implementation.

[0141] refer to Figure 27 and 28 The substrate 10 may include a cell array region (CAR), a peripheral circuit region (PERI), and a contact region (CTR) between the cell array region (CAR) and the peripheral circuit region (PERI). In some exemplary embodiments, the contact region (CTR) may include a first contact region (CTR1) adjacent to the peripheral circuit region (PERI) and a second contact region (CTR2) adjacent to the cell array region (CAR). The substrate 10 of the peripheral circuit region (PERI) may include an active region (ACT) defined by a device isolation layer 11.

[0142] The substrate 10 may include a material having semiconductor properties (e.g., a silicon wafer), an insulating material (e.g., glass), or a semiconductor or conductor covered with an insulating material. In some exemplary embodiments, the substrate 10 may be a silicon wafer having a first conductivity type.

[0143] In some exemplary embodiments, the cell array structure can be disposed on the substrate of the cell array region CAR, and the peripheral logic structure can be disposed on the substrate 10 of the peripheral circuit region PERI. The cell array structure may have a first height from the top surface of the substrate 10, and the peripheral logic structure may have a second height from the top surface of the substrate 10. The second height may be less than the first height.

[0144] Pickup regions 10P can be disposed in the substrate 10 and can be adjacent to the cell array structure. When viewed in plan view, pickup regions 10P can be positioned adjacent to both ends of each stacked structure ST included in the cell array structure. In other words, when viewed in plan view, pickup regions 10P can be spaced apart from each other in the first direction D1. Pickup regions 10P can be doped with dopants having the same conductivity type as the substrate 10.

[0145] In some exemplary implementations, the peripheral logic structure of the Peripheral Circuits Area (PERI) may include... Figure 12 Row decoder 2 and column decoder 4 Figure 12 Page buffer 3, and Figure 12 The control circuit 5. In other words, the peripheral logic structure may include NMOS and PMOS transistors, resistors, and capacitors, which are electrically connected to the cell array structure.

[0146] More specifically, the active region ACT can be defined by a device isolation layer 11 formed in the substrate 10 of the peripheral circuit region PERI. A peripheral gate electrode PG can be disposed on the active region ACT in the peripheral circuit region PERI, and source / drain doped regions can be formed in the active region ACT on both sides of the peripheral gate electrode PG. A gate insulating layer can be disposed between the peripheral gate electrode PG and the active region ACT. Additionally, a resistor pattern PR can be disposed on the substrate of the peripheral circuit region PERI.

[0147] The peripheral gate electrode PG can be formed of doped polysilicon or of a conductive material having a work function higher than that of doped polysilicon. For example, a conductive material with a high work function can include at least one of a metal (e.g., molybdenum) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or titanium aluminum nitride). The gate insulating layer can include at least one of an oxide, nitride, oxynitride, or a high-k dielectric material (e.g., an insulating metal oxide, such as hafnium oxide or aluminum oxide). The conductivity type of the source / drain doped regions can differ from that of the active region ACT.

[0148] In some exemplary implementations, the cell array structure may include a reference Figures 15 to 26 describes the stacked structure ST and the vertical structure VS. The vertical structure VS is permeable to the stacked structure ST. In some exemplary embodiments, the stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2, the first stacked structure ST1 including a plurality of first electrodes EL1 vertically stacked on the substrate 10, and the second stacked structure ST2 including a plurality of second electrodes EL2 vertically stacked on the first stacked structure ST1. An insulating layer ILD may be disposed between the first electrodes EL1 and between the second electrodes EL2.

[0149] The stacked structure ST can extend from the cell array region CAR into the contact region CTR. The stacked structure ST can have a stepped structure within the contact region CTR to electrically connect electrodes EL1 and EL2 to the peripheral logic structure. In other words, the vertical height of the stacked structure ST within the contact region CTR can increase as the distance from the cell array region CAR decreases. That is, the stacked structure ST can have a sloping outline within the contact region CTR.

[0150] More specifically, the end portion of the first electrode EL1 can be disposed on the substrate 10 of the first contact area CTR1, and the first stacked structure ST1 can have a stepped structure in the first contact area CTR1. The area of ​​the first electrode EL1 can decrease as the vertical distance from the top surface of the substrate 10 increases. The end portion of the second electrode EL2 can be disposed on the substrate 10 of the second contact area CTR2, and the second stacked structure ST2 can have a stepped structure in the second contact area CTR2. Here, the maximum length of the second electrode EL2 can be less than the minimum length of the first electrode EL1. The area of ​​the second electrode EL2 can decrease as the vertical distance from the top surface of the substrate 10 increases.

[0151] In some exemplary embodiments, the vertical structure VS can penetrate the stacked structure ST to connect to the substrate 10. The vertical structure VS may include semiconductor material and conductive material. In exemplary embodiments, when viewed in plan view, the vertical structures VS penetrating a stacked structure ST can be arranged in a row. In exemplary embodiments, when viewed in plan view, the vertical structures VS penetrating a stacked structure ST can be arranged in a zigzag pattern.

[0152] For reference Figures 19 to 22 As described, the insulating spacer SP and the common source line structure CSP can be disposed between the laminated structures ST extending along the first direction D1. In other words, the insulating spacer SP and the common source line structure CSP can extend in the first direction D1.

[0153] In some exemplary embodiments, the top fill insulating layer 200 can be formed on the entire top surface of the substrate 10 by covering the stacked structure ST and the peripheral logic structure. The top fill insulating layer 200 may have a planarized top surface and may cover the end portions of the stacked structure ST. The top fill insulating layer 200 may include one insulating layer or multiple stacked insulating layers.

[0154] At least one patterning process can be performed on the upper filling insulating layer 200 to form a lower contact hole LH for the first contact area CTR1, an upper contact hole UH for the second contact area CTR2, and a peripheral contact hole PH for the peripheral circuit area PERI. The lower contact hole LH can expose portions of the first electrode EL1, and the upper contact hole UH can expose portions of the second electrode EL2. In some exemplary embodiments, the upper contact hole UH can be formed prior to the formation of the lower contact hole LH and the peripheral contact hole PH. Due to the stepped structure ST of the stacked structure, the upper contact hole UH and the lower contact hole LH can locally expose electrodes EL1 and EL2 located at different heights from each other. In other words, the depths of the upper contact hole UH and the lower contact hole LH can be different from each other.

[0155] The peripheral contact hole PH can penetrate the upper filling insulating layer 200 to expose a portion of the peripheral logic structure. The peripheral contact hole PH can locally expose the source / drain doped regions, the peripheral gate electrode PG, and / or the resistor pattern PR.

[0156] Additionally, each of the lower contact hole LH, upper contact hole UH, and peripheral contact hole PH may include an upper region, a lower region, and a curved region between the upper and lower regions, similar to the reference. Figure 1 The described opening is 25. The lower contact hole LH, the upper contact hole UH, and the peripheral contact hole PH can each have a maximum width in their curved areas.

[0157] like Figure 29 As shown, the first contact plug PLG1 can be formed in the lower contact hole LH, and the second contact plug PLG2 can be formed in the upper contact hole UH. Simultaneously, the peripheral contact plug CP can be formed in the peripheral contact hole PH of the peripheral circuit area PERI.

[0158] Forming the first and second contact plugs PLG1 and PLG2, as well as the peripheral contact plug CP, may include forming a conductive layer that fills the upper contact hole, the lower contact hole, and the peripheral contact hole, and performing a planarization process on the conductive layer until the top surface of the upper filling insulating layer 200 is exposed. Therefore, the top surfaces of the first contact plug PLG1 and the second contact plug PLG2 may be substantially coplanar with the top surface of the peripheral contact plug CP.

[0159] In some exemplary embodiments, forming a conductive layer that fills the upper contact hole UH, the lower contact hole LH, and the peripheral contact hole PH may include depositing a first tungsten layer 41 covering the inner surfaces of the contact holes UH, LH, and PH; performing a surface treatment process on a portion of the surface of the first tungsten layer 41; and depositing a second tungsten layer 51 on the first tungsten layer 41 that completely fills the contact holes UH, LH, and PH, as shown in the reference. Figures 1 to 11 As described.

[0160] More in detail, such as Figure 30 As shown, the barrier metal layer 31 and the first tungsten layer 41 can be sequentially deposited in the upper contact hole UH, the lower contact hole LH, and the peripheral contact hole PH. In this case, the first tungsten layer 41 can define a recessed area in each contact hole UH, LH, and PH.

[0161] Then, as referenced Figure 3 and 4 As described, the surface treatment process can be performed on a portion of the first tungsten layer 41. In some exemplary embodiments, a plasma treatment process, as a surface treatment process, can be performed on a portion of the first tungsten layer 41. In some exemplary embodiments, instead of a surface treatment process, a metal nitride layer can be deposited on a portion of the first tungsten layer 41 formed in the upper regions of contact holes UH, LH, and PH, as referenced. Figure 10 As described.

[0162] In some exemplary implementations, the surface treatment process can be performed simultaneously on the first tungsten layer 41 formed in contact holes UH, LH, and PH with different vertical depths. Therefore, as... Figure 30 As shown, the areas of the second surfaces S2, respectively provided in the upper contact hole UH, lower contact hole LH, and peripheral contact hole PH, can be different from each other. The second surface S2 corresponds to the surface of the first tungsten layer 41 that has not been treated by the surface treatment process, as described above. For example, since plasma is supplied downwards to the upper regions of contact holes UH, LH, and PH during the plasma treatment process, the plasma reaching depths of contact holes UH, LH, and PH can be substantially equal, even if the depths of contact holes UH, LH, and PH are different. Therefore, the areas of the first surfaces S1, respectively provided in the upper contact hole UH, lower contact hole LH, and peripheral contact hole PH, can be substantially similar to each other. The first surface S1 corresponds to the surface of the first tungsten layer 41 that has been treated by the surface treatment process.

[0163] Subsequently, as Figure 31As shown, a second tungsten layer 51 can be deposited to fill the recessed area of ​​the first tungsten layer 41. When the second tungsten layer 51 is deposited, the growth rate (i.e., deposition rate) and size of the tungsten grains can be varied depending on the surface condition of the first tungsten layer 41. In other words, the grains of the second tungsten layer 51 deposited on the plasma-treated first surface S1 of the first tungsten layer 41 can be larger than the grains of the first tungsten layer 41. The grains of the second tungsten layer 51 can grow laterally from the sidewalls of the recessed area of ​​the first tungsten layer 41. The laterally grown grains of the second tungsten layer 51 can contact each other to form a second interface IF2 in the central region of the first and second contact plugs PLG1 and PLG2 and the peripheral contact plug CP.

[0164] In some exemplary embodiments, the grain size of the upper portion of the second tungsten layer 51 of the second contact plug PLG2 filling one of the upper contact holes UH can be substantially equal to the grain size of the lower portion of the second tungsten layer 51 of the second contact plug PLG2 filling the one upper contact hole UH, as shown in the reference. Figure 8A and 8C As described. The grain size of the second tungsten layer 51 on the upper part of the first contact plug PLG1 filling one of the lower contact holes LH can be larger than the grain size of the second tungsten layer 51 on the lower part of the first contact plug PLG1 filling the lower contact hole LH, as described in reference. Figure 8A and 8B As described. The grain size of the second tungsten layer 51 on the upper part of the peripheral contact plug CP filling one of the peripheral contact holes PH can be larger than the grain size of the second tungsten layer 51 on the lower part of the peripheral contact plug CP filling the one peripheral contact hole PH, as described in the reference. Figure 8A and 8C As described.

[0165] like Figure 27 and 29As shown, bit lines BL can then be formed as a cross-layered structure ST in the cell array region CAR. Bit lines BL can extend in the second direction D2. Bit lines BL can be electrically connected to the vertical structure VS via bit line contact plugs BPLG. A first connection line CL1 can be formed in a first contact area CTR1, and a second connection line CL2 can be formed in a second contact area CTR2. Multiple peripheral circuit interconnects ICL can be formed on the upper fill insulating layer 200 of the peripheral circuit region PERI. Peripheral circuit interconnects ICL can extend from the peripheral circuit region PERI into the cell array region CAR. In some exemplary embodiments, peripheral circuit interconnects ICL can electrically connect the peripheral logic circuits of the peripheral circuit region PERI to the memory cells of the cell array region CAR. Each peripheral circuit interconnect ICL can be electrically connected to one of the peripheral contact plugs CP. In some exemplary embodiments, a conductive layer can be deposited on the upper fill insulating layer 200, and the deposited conductive layer can be patterned to form bit lines BL, first and second connection lines CL1 and CL2, and peripheral circuit interconnects ICL.

[0166] Figure 32 This is a schematic block diagram illustrating some exemplary embodiments of 3D semiconductor memory devices based on the inventive concept.

[0167] like Figure 32 As shown, the 3D semiconductor memory device according to the exemplary embodiment may include a peripheral logic structure PS and a cell array structure CS. The cell array structure CS may be stacked on the peripheral logic structure PS. In other words, when viewed from a planar perspective, the cell array structure CS may overlap with the peripheral logic structure PS.

[0168] In some exemplary implementations, the peripheral logic structure PS may include a reference. Figure 12 The described row and column decoders 2 and 4, page buffer 3, and control circuitry 5 are also described. The cell array structure CS may include memory blocks BLK1 to BLKn, each corresponding to a data erasure cell. Each of the memory blocks BLK1 to BLKn may include a structure stacked on a plane defined by a first direction D1 and a second direction D2, extending along a third direction D3. Each of the memory blocks BLK1 to BLKn may include a memory cell array with a 3D structure (or a vertical structure). The memory cell array may include a plurality of three-dimensionally arranged memory cells and word lines and bit lines electrically connected to the memory cells, referenced to... Figure 13 Described.

[0169] Figure 33 This is a plan view showing some exemplary embodiments of 3D semiconductor memory devices based on the inventive concept. Figure 34 For along Figure 33 The cross-sectional view obtained by line I-I'. Figure 35 It is shown Figure 34An enlarged cross-sectional view of the connecting plug. In this exemplary embodiment, for ease of explanation, references to the connecting plug will be omitted or briefly mentioned. Figures 15 to 27 The same technical features are described in the exemplary implementation.

[0170] like Figure 33 and 34 As shown, the peripheral logic structure PS and the cell array structure CS can be sequentially stacked on the substrate 10. In other words, the peripheral logic structure PS can be disposed between the substrate 10 and the cell array structure CS. When viewed from a plan view, the peripheral logic structure PS can overlap with the cell array structure CS.

[0171] The peripheral logic structure PS may include Figure 12 The row and column decoders 2 and 4, page buffer 3, and control circuitry 5 are included. In other words, the peripheral logic structure PS may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the cell array structure CS. The peripheral circuitry of the peripheral logic structure PS can be formed on the entire top surface of the substrate 10. Additionally, the substrate 10 may include an N-well region NW doped with N-type dopant and a P-well region PW doped with P-type dopant. Active regions can be defined in the N-well region NW and the P-well region PW by a device isolation layer 11.

[0172] The peripheral logic structure PS may include a peripheral gate electrode PG, source / drain regions on both sides of each peripheral gate electrode PG, a peripheral contact plug CP, a peripheral circuit interconnect ICL, and a lower fill insulating layer 90 covering the peripheral circuit. Specifically, a PMOS transistor may be formed on an N-well region NW, and an NMOS transistor may be formed on a P-well region PW. The peripheral circuit interconnect ICL can be electrically connected to the peripheral circuit via the peripheral contact plug CP. For example, the peripheral contact plug CP and the peripheral circuit interconnect ICL can be electrically connected to NMOS and PMOS transistors.

[0173] The lower fill insulating layer 90 may cover the peripheral circuit, the peripheral contact plug CP, and the peripheral circuit interconnect ICL. The lower fill insulating layer 90 may include multiple stacked insulating layers.

[0174] The cell array structure CS can be disposed on the lower filling insulating layer 90 and may include a horizontal semiconductor layer 100, a stacked structure ST and a vertical structure VS.

[0175] A horizontal semiconductor layer 100 may be formed on a lower fill insulating layer 90 covering the peripheral circuitry. In other words, the bottom surface of the horizontal semiconductor layer 100 may be in contact with the lower fill insulating layer 90. The horizontal semiconductor layer 100 may include a cell array region CAR and a contact region CTR adjacent to the cell array region CAR.

[0176] The horizontal semiconductor layer 100 may be formed of a semiconductor material. For example, the horizontal semiconductor layer 100 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any combination thereof. Additionally, the horizontal semiconductor layer 100 may include a semiconductor doped with a dopant of a first conductivity type and / or an intrinsic semiconductor without dopant. The horizontal semiconductor layer 100 may have a crystal structure including at least one of a single-crystal structure, an amorphous structure, or a polycrystalline structure.

[0177] The stacked structures ST can extend parallel to each other along a first direction D1 on the horizontal semiconductor layer 100 and can be spaced apart from each other in a second direction D2. Each stacked structure ST may include electrodes EL vertically stacked on the horizontal semiconductor layer 100 and insulating layers ILD disposed between the electrodes EL. The thickness of the insulating layers ILD can be varied depending on the characteristics of the semiconductor memory device. In some exemplary embodiments, the bottommost insulating layer ILD may be thinner than the other insulating layers ILD. In some exemplary embodiments, one or more insulating layers ILD may be thicker than the other insulating layers ILD.

[0178] The stacked structure ST may have a stepped structure for electrically connecting the electrode EL to the peripheral logic structure PS, and the stepped structure may be disposed in the contact area CTR. An upper fill insulating layer 200 may be disposed on the horizontal semiconductor layer 100 to cover the end portion of the electrode EL with the stepped structure. A cover insulating layer 205 may cover the stacked structure ST and the upper fill insulating layer 200. A bit line BL may be disposed on the cover insulating layer 205 and may extend in the second direction D2 to intersect the stacked structure ST. The bit line BL may be electrically connected to the vertical structure VS via a bit line contact plug BPLG.

[0179] The vertical structure VS can penetrate each stacked structure ST to connect to the horizontal semiconductor layer 100. In some exemplary embodiments, the vertical structure VS may include semiconductor material. The bottom surface of the vertical structure VS may be disposed horizontally between the top and bottom surfaces of the horizontal semiconductor layer 100. Contact pads may be disposed in the top portion of the vertical structure VS and may connect to the bit line contact plug BPLG.

[0180] The data storage layer DS can be disposed between the vertical structure VS and the stacked structure ST. The data storage layer DS may include a vertical insulating pattern VP penetrating the stacked structure ST and horizontal patterns HP extending from between the electrode EL and the vertical insulating pattern VP to the top and bottom surfaces of the electrode EL, as shown in the reference. Figure 19 As described.

[0181] A common source region (CSR) can be disposed in the horizontal semiconductor layer 100. Each common source region (CSR) can be disposed in the horizontal semiconductor layer 100 between adjacent stacked structures. The common source region (CSR) can extend in a first direction D1 parallel to the stacked structure ST. The common source region (CSR) can be formed by doping the horizontal semiconductor layer 100 with a dopant of a second conductivity type. For example, the common source region (CSR) can be doped with an N-type dopant (e.g., arsenic (As) or phosphorus (P)).

[0182] A common source structure CSP can be connected to each common source region CSR, and a sidewall insulating spacer SP can be disposed between the common source structure CSP and the stacked structure ST. In some exemplary embodiments, the common source structure CSP can extend in a first direction D1, and the sidewall insulating spacer SP can also extend in the first direction D1 between the common source structure CSP and the stacked structure ST. In some exemplary embodiments, the sidewall insulating spacer SP can fill the space between adjacent stacked structures ST, and the common source structure CSP can penetrate the sidewall insulating spacer SP to locally connect to the common source region CSR. In some exemplary embodiments, forming the common source structure CSP may include depositing a first tungsten layer covering the inner surface of the trench, performing a surface treatment process on a portion of the first tungsten layer, and depositing a second tungsten layer on the first tungsten layer to completely fill the trench, as shown in the reference. Figures 19 to 22 As described.

[0183] Pickup regions 10P can be disposed in the horizontal semiconductor layer 100 within the contact region CTR. Pickup regions 10P can be adjacent to both ends of each stacked structure ST. In other words, pickup regions 10P can be spaced apart from each other in the first direction D1. Pickup regions 10P can be formed by doping portions of the horizontal semiconductor layer 100 with a dopant of a first conductivity type. In other words, pickup regions 10P can have the same conductivity type as the horizontal semiconductor layer 100, and the dopant concentration of pickup regions 10P can be higher than the dopant concentration of the horizontal semiconductor layer 100.

[0184] Interconnection structures for electrically connecting the cell array structure CS to the peripheral logic structure PS can be disposed on the end portions of the stacked structure ST constituting a stepped structure. The interconnection structures may include contact plugs PLG and connecting lines CL. The contact plugs PLG can penetrate the upper filler insulating layer 200 covering the end portions of the stacked structure ST and can be connected to the end portions of the electrodes EL. Connecting lines CL can be disposed on the upper filler insulating layer 200 to connect to the contact plugs PLG. The vertical length of the contact plugs PLG can decrease in a stepped manner as the distance from the cell array region decreases.

[0185] The pickup contact plug PPLG can penetrate the upper filler insulation layer 200 to connect to the pickup area 10P respectively. The top surface of the pickup contact plug PPLG can be substantially coplanar with the top surface of the contact plug PLG. The pickup contact plug PPLG can be electrically connected to the peripheral logic structure PS through the well conductor PCL and the connection plug CPLG.

[0186] The connection plug CPLG electrically connects the cell array structure CS to the peripheral logic structure PS. The connection plug CPLG can penetrate the upper filler insulating layer 200 and the horizontal semiconductor layer 100 to connect to the peripheral circuit interconnect ICL of the peripheral logic structure PS. The insulating spacer SSP surrounds the connection plug CPLG to electrically insulate it from the horizontal semiconductor layer 100.

[0187] like Figure 35 As shown, the conductive layer can be formed to fill vias that penetrate the upper insulating layer 200 and the horizontal semiconductor layer 100 to expose the peripheral circuit interconnect ICL. Then, a planarization process can be performed on the conductive layer to form the connection plug CPLG. Here, the conductive layer forming the via may include sequentially depositing a barrier metal layer 31 and a first tungsten layer 41 covering the inner surface of the via, performing a surface treatment process on a portion of the first tungsten layer 41, and depositing a second tungsten layer on the first tungsten layer 41 to completely fill the trench, as shown in the reference. Figures 2 to 4 As described. Additionally, before forming the conductive layer, insulating spacers (SSPs) can be formed in vias to expose the peripheral circuit interconnects (ICLs).

[0188] Before depositing the second tungsten layer 51, the first tungsten layer 41 may have a first surface S1 treated by a surface treatment process and a second surface S2 not treated by a surface treatment process. The grains of the second tungsten layer 51 deposited on the first surface S1 may be larger than the grains of the first tungsten layer 41. The grains of the second tungsten layer 51 may grow laterally from the sidewalls of the recessed area defined by the first tungsten layer 41, so that the second interface IF2 may be formed in the central region of the connecting plug CPLG by the grains of the second tungsten layer 51 that are in contact with each other. The grains of the second tungsten layer 51 in the upper part of the connecting plug CPLG may be larger than the grains of the second tungsten layer 51 in the lower part of the connecting plug CPLG, as shown in the reference. Figure 8A and 8B As described.

[0189] Figure 36 This is a cross-sectional view showing some exemplary implementations of semiconductor memory devices based on the disclosed subject matter.

[0190] like Figure 36As shown, the substrate 10 may include a cell array region (CAR) and a peripheral circuit region (PERI). Memory cells may be formed in the cell array region (CAR), and the peripheral circuitry controlling the memory cells may be formed in the peripheral circuit region (PERI).

[0191] Each memory cell on the substrate 10 of the cell array region CAR may include a selection element and a data storage element. In some exemplary embodiments, the selection element may be a MOS transistor or a diode. In some exemplary embodiments, the data storage element may be a capacitor or a variable resistor. Peripheral circuitry (NMOS and / or PMOS transistors, diodes and / or resistors) may be formed on the substrate 10 of the peripheral circuitry region PERI.

[0192] In some exemplary embodiments, word lines (not shown) and bit lines BL crossing word lines can be formed on the substrate 10 of the cell array region CAR, and data storage elements can be formed at the intersections of the word lines and bit lines BL, respectively. In some exemplary embodiments, the data storage element may include a capacitor CAP, which includes a bottom electrode BE, a top electrode TE, and a dielectric layer DI between the bottom electrode BE and the top electrode TE.

[0193] Bit lines BL can be disposed on the substrate 10 of the cell array region CAR to intersect word lines (not shown). Bit lines BL can be electrically connected to some source / drain regions. A lower filler insulating layer 150 can cover the bit lines BL, and contact plugs BC can be formed in the lower filler insulating layer 150. Contact plugs BC can electrically connect data storage elements to other source / drain regions. Contact pads PAD can be formed on the contact plugs BC respectively. Contact pads PAD can increase the contact area between the contact plugs BC and the bottom electrode BE formed on the contact pads PAD.

[0194] Peripheral circuitry, such as transistors TR, can be formed on the substrate 10 of the peripheral circuitry region PERI. Specifically, a device isolation layer 11 can be formed in the substrate 10 from the peripheral circuitry region PERI to the peripheral active region, a peripheral gate electrode PG can be formed across the peripheral active region, and source / drain doped regions can be formed in the peripheral active regions on both sides of each peripheral gate electrode PG. Additionally, contact plugs can be formed to connect to the source / drain regions and the peripheral gate electrode PG.

[0195] The lower filling insulating layer 150 can cover the word lines (not shown) and bit lines BL of the cell array region CAR and the transistors TR of the peripheral circuit region PERI.

[0196] In the cell array region CAR, the bottom electrode BE of the capacitor CAP can be formed on the contact pad PAD. After forming the bottom electrode BE, the dielectric layer DI can be formed to conformally cover the surface of the bottom electrode BE. The top electrode TE can be formed on the dielectric layer DI. The bottom electrode BE can have a cylindrical or columnar shape. The top electrode TE can be formed on the dielectric layer DI to cover multiple bottom electrodes TE. In addition, the top electrode TE can fill the internal space of the cylindrical bottom electrode BE in which the dielectric layer DI is formed.

[0197] In some exemplary implementations, the capacitance of capacitor CAP can be proportional to the surface area of ​​the bottom electrode BE, thus allowing the height of the bottom electrode BE to be increased to maximize its surface area within a limited region. In other words, the aspect ratio (i.e., the height-to-width ratio) of the bottom electrode BE can increase as the capacitance of capacitor CAP increases. Due to the increased height of the bottom electrode BE, the upper insulating layer 200 of the peripheral circuit region PERI can have a thickness equal to or greater than the height of capacitor CAP. Consequently, the peripheral contact plug CP of transistor TR, electrically connected to the peripheral circuit region PERI, can have a large aspect ratio.

[0198] In some exemplary embodiments, forming the peripheral contact plug CP may include: forming a contact hole penetrating the upper filling insulating layer 200 to expose a portion of the contact pad PAD of the peripheral circuit area PERI; sequentially depositing a barrier metal layer 31 and a first tungsten layer 41 covering the inner surface of the contact hole; performing a surface treatment process on a portion of the first tungsten layer 41; and depositing a second tungsten layer 51 that completely fills the contact hole on the first tungsten layer 41, as referenced. Figures 1 to 11 As described. Here, the height of the contact hole can be greater than the height of the capacitor. For example, the contact hole can have a large aspect ratio of approximately 5:1 to approximately 20:1. In some exemplary embodiments, the contact hole can be substantially circular when viewed in plan view. Additionally, the contact hole may include a curved region in which the width increases, as shown in the reference. Figure 1 As described.

[0199] Before depositing the second tungsten layer 51, the first tungsten layer 41 may have a first surface S1 treated by a surface treatment process and a second surface S2 not treated by a surface treatment process. The grains of the second tungsten layer 51 deposited on the first surface S1 may be larger than the grains of the first tungsten layer 41. The grains of the second tungsten layer 51 may grow laterally from the sidewalls of the recessed area defined by the first tungsten layer 41, so that the second interface IF2 may be formed in the central region of the peripheral contact plug CP by the grains of the second tungsten layer 51 that are in contact with each other. The grains of the second tungsten layer 51 in the upper part of the peripheral contact plug CP may be larger than the grains of the second tungsten layer 51 in the lower part of the peripheral contact plug CP, as shown in the reference. Figure 8A and 8B As described.

[0200] According to an exemplary embodiment of the disclosed subject matter, the interconnect structure can be formed by depositing a conductive material on the inner wall of an opening with a large aspect ratio. Here, a first tungsten layer can be deposited, and then a surface treatment process can be performed on a portion of the first tungsten layer deposited in the upper part of the opening. Subsequently, a second tungsten layer can be deposited on the first tungsten layer to fill the opening. When the second tungsten layer is deposited, the growth rate of tungsten grains in the upper region of the opening can be lower than the growth rate of tungsten grains in the lower region of the opening. Therefore, the opening with a large aspect ratio can be completely filled with tungsten layers without seams or voids. As a result, the resistance of the interconnect structure with a large aspect ratio can be reduced to improve the electrical reliability of the semiconductor device.

[0201] While exemplary embodiments of the disclosed subject matter have been described above with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the exemplary embodiments. Therefore, it should be understood that the above exemplary embodiments are not limiting but illustrative. Consequently, the scope of the exemplary embodiments is determined by the widest permissible interpretation of the claims and their equivalents, and should not be limited or constrained by the foregoing description.

[0202] This application claims priority to Korean Patent Application No. 10-2015-0121910, filed with the Korean Patent Office on August 28, 2015, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A superstructure is formed with an opening that exposes the lower conductor; A first tungsten layer is deposited to cover the inner surface of the opening, the first tungsten layer defining a recessed area in the opening; A surface treatment process is performed on a portion of the first tungsten layer, such that the first tungsten layer has a first surface in the upper region of the opening that is treated by the surface treatment process and a second surface in the lower region of the opening that is not treated by the surface treatment process. as well as A second tungsten layer is simultaneously deposited on both the first and second surfaces of the first tungsten layer, such that the second tungsten layer fills the entire recessed area. When the second tungsten layer is deposited simultaneously on the first surface and the second surface, the growth rate of tungsten grains grown from the first surface is lower than the growth rate of tungsten grains grown from the second surface.

2. The method of claim 1, wherein the size of the tungsten grains grown from the first surface of the second tungsten layer is larger than the size of the tungsten grains grown from the second surface of the second tungsten layer.

3. The method according to claim 1, wherein the number of dangling keys on the first surface is less than the number of dangling keys on the second surface.

4. The method according to claim 1, wherein the second tungsten layer is formed of a single layer.

5. The method of claim 1, wherein the tungsten grains of the second tungsten layer grow laterally from the sidewall of the recessed region to form an interface in the central region of the opening.

6. The method of claim 1, wherein the depth of the recessed area is greater than half the depth of the opening.

7. The method of claim 1, wherein performing the surface treatment process comprises: Perform plasma processing.

8. The method of claim 1, wherein performing the surface treatment process comprises: A metal nitride layer is formed on a portion of the surface of the first tungsten layer.

9. The method of claim 1, wherein the opening has a linear shape extending in a first direction, and The opening extends parallel to the upper structure.

10. The method of claim 1, wherein the thickness of the first tungsten layer on the bottom surface of the opening is greater than the thickness of the first tungsten layer on the sidewall of the opening.

11. The method of claim 1, wherein the opening includes a curved region between the top and bottom surfaces of the superstructure, and The opening therein has its maximum width in the curved region.

12. A method for manufacturing a semiconductor device, the method comprising: A stacked structure extending in one direction is formed on a substrate, the stacked structures being spaced apart from each other, and each of the stacked structures including vertically stacked electrodes; Forming a vertical structure that penetrates the stacked structure; A common source line structure is formed between the stacked structures that are adjacent to each other and spaced apart from the vertical structure, the common source line structure extending parallel to the electrode; as well as An insulating spacer is formed between the common source line structure and the laminated structure. The common source line structure includes: A trench is formed between adjacent layers in the stacked structure, the trench exposing a portion of the substrate; A first tungsten layer is deposited on the inner wall of the trench, the first tungsten layer covering the insulating spacer and defining a recessed area, the recessed area including a lower portion adjacent to the lowermost electrode of the electrodes and an upper portion adjacent to the uppermost electrode of the electrodes; A surface treatment process is performed on a portion of the recessed area of ​​the first tungsten layer, such that the first tungsten layer has a first surface treated by the surface treatment process in the upper region of the trench and a second surface not treated by the surface treatment process in the lower region of the trench; and A second tungsten layer is simultaneously deposited on both the first and second surfaces of the first tungsten layer to fill the entire recessed area. When the second tungsten layer is deposited simultaneously on the first surface and the second surface, the growth rate of the tungsten grains is lower at the upper part of the recessed region than at the lower part of the recessed region.

13. The method of claim 12, wherein the number of dangling keys on the first surface is less than the number of dangling keys on the second surface.

14. The method of claim 12, wherein forming the common source line structure further comprises forming a barrier metal layer between the inner wall of the trench and the first tungsten layer, and The first tungsten layer is deposited on the surface of the barrier metal layer.

15. The method of claim 12, wherein the second tungsten layer is formed of a single layer.

16. The method of claim 12, wherein the second tungsten layer comprises an upper portion adjacent to the uppermost electrode of the electrodes and a lower portion adjacent to the lowermost electrode of the electrodes, and The average grain size of the upper part of the second tungsten layer is greater than the average grain size of the lower part of the second tungsten layer.

17. The method of claim 12, wherein the common source line structure comprises: A first interface is formed by the grains of the first tungsten layer and the grains of the second tungsten layer that are in contact with the grains of the first tungsten layer; And a second interface formed by the grains of the second tungsten layer in the central region of the common source line structure.

18. The method of claim 17, wherein the first interface and the second interface of the common source line structure extend parallel to the stacked structure along the one direction.

19. The method of claim 12, wherein the vertical length of the second tungsten layer is greater than half the vertical length of each stacked structure.

20. The method of claim 12, wherein the common source line structure has its maximum width in a curved region disposed between the top and bottom surfaces of the common source line structure, and The curved region is positioned at a level higher than the bottom surface of the uppermost electrode in the electrode configuration.

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