Chip linearity test method and system, and linearity signal providing device

Abstract

The present invention discloses a method and system for testing the linearity of a chip and a linearity signal providing device. The method for testing the linearity of a chip includes: providing a reference clock signal and a receiver input signal to a chip under test, wherein there is a time phase difference between the reference clock signal and the receiver input signal; and determining the linearity of an interpolation circuit in the chip under test according to a plurality of phase signals corresponding to the reference clock signal and the receiver input signal in the chip under test.

Description

Technical Field

[0001] The present invention relates to a method and system for testing the linearity of a chip and a linearity signal providing device, and particularly to a low-cost method and system for testing the linearity of a chip and a linearity signal providing device. Background Art

[0002] In the past, if a phase interpolation circuit wanted to verify its linearity, it had to pull out the pin of the circuit phase signal from inside the chip and then input it to an oscilloscope for measurement, which required a large amount of test costs.

[0003] Therefore, how to provide a low-cost chip linearity test system, a linearity signal providing device, and a chip linearity test method has become one of the important issues to be solved in this field. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for testing the linearity of a chip in view of the deficiencies of the prior art, including: providing a reference clock signal and a receiver input signal to the chip under test, where there is a time phase difference between the reference clock signal and the receiver input signal; and judging the linearity of the interpolation circuit in the chip under test according to a plurality of phase signals corresponding to the reference clock signal and the receiver input signal in the chip under test.

[0005] To solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a chip linearity test system, including: a linearity signal providing device that provides a reference clock signal and a receiver input signal, where there is a time phase difference between the reference clock signal and the receiver input signal; and a chip under test that receives the reference clock signal and the receiver input signal and performs a linearity test.

[0006] To solve the above technical problems, another technical solution adopted by the present invention is to provide a linearity signal providing device, comprising: a controller; a first signal generating circuit electrically connected to the controller to generate a reference clock signal; a second signal generating circuit electrically connected to the controller to generate an initial receiver input signal; a data delay circuit electrically connected to the second signal generating circuit, after the initial receiver input signal passes through the data delay circuit, a receiver input signal is generated, and there is a time phase difference between the receiver input signal and the reference clock signal; a first output circuit electrically connected to the first signal generating circuit; a second output circuit electrically connected to the data delay circuit to output the receiver input signal; wherein, when the linearity signal providing device is connected to a chip under test for linearity testing, the controller of the linearity signal providing device sends a first control signal to the first signal generating circuit to output the reference clock signal to the chip under test by using the first output circuit, and moreover, the controller of the linearity signal providing device simultaneously sends a second control signal to the second signal generating circuit to output the receiver input signal to the chip under test by using the second output circuit.

[0007] One beneficial effect of the present invention is that the chip linearity testing system, the linearity signal providing device and the chip linearity testing method provided by the present invention only need to provide two signals with a time phase difference to the chip under test, and then linearity analysis can be performed by using jitter tolerance testing, which can greatly reduce the testing cost and time.

[0008] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration, and are not used to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of the chip linearity testing system according to the first embodiment of the present invention.

[0010] Figure 2 is another schematic diagram of the chip linearity testing system according to the first embodiment of the present invention.

[0011] Figure 3 is a schematic diagram of the chip linearity testing system performing jitter tolerance testing according to the present invention.

[0012] Figure 4 is a schematic diagram of the linearity signal providing device according to the second embodiment of the present invention.

[0013] Figure 5 is a flowchart of the chip linearity testing method according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following is an implementation manner of the "chip linearity test system, linearity signal providing device, and chip linearity test method" disclosed in the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only for simple schematic illustration and are not drawn according to actual dimensions, as stated in advance. The following implementation manners will further detail the related technical content of the present invention, but the disclosed content is not used to limit the protection scope of the present invention. In addition, the term "or" used herein should, depending on the actual situation, may include any one or a combination of more of the associated listed items.

[0015] [First Embodiment]

[0016] The present invention proposes to use a linearity signal providing device to simultaneously generate a reference clock signal and a receiver input signal, and the linearity signal providing device generates a time phase difference between these two signals to be input into the chip simultaneously. Then, a jitter tolerance test mechanism is used to test the available interpolation phase. If the interpolation phase linearity is good, the available interpolation phases of the two signals with a time phase difference should be the same. If the linearity of the interpolation phase is poor, the available interpolation phases will be different.

[0017] Please refer to Figure 1 、 Figure 2 and Figure 3 , Figure 1 which is a schematic diagram of the chip linearity test system according to the first embodiment of the present invention. Figure 2 which is another schematic diagram of the chip linearity test system according to the first embodiment of the present invention. Figure 3 which is a schematic diagram of the chip linearity test system of the present invention performing a jitter tolerance test.

[0018] The chip linearity test system SYS1 includes a linearity signal providing device 1 and a chip under test 2.

[0019] The linearity signal providing device 1 provides a reference clock signal CLS and a receiver input signal RXIS. There is a time phase difference between the reference clock signal CLS and the receiver input signal RXIS.

[0020] The chip under test 2 receives the reference clock signal CLS and the receiver input signal RXIS to perform a linearity test.

[0021] Please refer to Figure 2, the chip under test 2 at least includes a digital clock recovery circuit 21 and a phase-locked loop (PLL) circuit 22. The digital clock recovery circuit 21 is electrically connected to the phase-locked loop circuit 22. The phase-locked loop circuit 22 receives a reference clock signal CLS. The digital clock recovery circuit 21 receives a receiver input signal RXIS.

[0022] The digital clock recovery circuit (Clock Data Recovery) 21 includes a sampler circuit 211, a phase detector circuit 212, a digital low-pass filter circuit 213, and a phase interpolator circuit 214. The sampler circuit 211 is electrically connected to the phase detector circuit 212. The phase detector circuit 212 is electrically connected to the digital low-pass filter circuit 213. The phase interpolator circuit 214 is electrically connected to the digital low-pass filter circuit 213 and the sampler circuit 211.

[0023] In addition, the sampler circuit 211 is used to output a recovered clock signal clock and data.

[0024] Furthermore, the linearity signal providing device 1 can simultaneously provide a reference clock signal CLS and a receiver input signal RXIS.

[0025] In addition, as Figure 3 shown, more available phases indicate that the internal interpolation phases are denser, and fewer available phases indicate that the internal interpolation phases are sparser. That is, when the time phase difference is in the case of more available phases, the jitter tolerance test will be better, and vice versa, the jitter tolerance test will be worse. Among them, curve L1 is the jitter test result under different phase differences between the reference clock signal CLS and the receiver input signal RXIS. Curve L2 is the curve of the number of available phases under different phase differences between the reference clock signal CLS and the receiver input signal RXIS. In addition, the horizontal axis is the phase difference, and the unit of the phase difference is 125 / 64 picoseconds.

[0026] When the time phase difference between the reference clock signal CLS and the receiver input signal RXIS is 19.5 picoseconds ((10 / 64)*1UI(125ps)) to 29.3 picoseconds ((15 / 64)*1UI(125ps)), the available phase can reach more than 45. However, when the time phase difference is 80 picoseconds ((41 / 64)*1UI(125ps)) to 93.8 picoseconds ((48 / 64)*1UI(125ps)), the available phase is only less than 30. It can also be found from the jitter tolerance test that when the available phase is more than 45, the digital clock recovery circuit can handle jitter below 0.5UI. However, when the available phase is less than 30, the jitter that the digital clock recovery circuit can handle is reduced to below 0.35UI.

[0027] In addition, in this embodiment, the linearity can be compared based on the number of available phases. For example, when the number of available phases is greater than or equal to the predetermined number of phases, it is determined that the linearity of the chip under test 2 is excellent. When the number of available phases is less than the predetermined number of phases, it is determined that the linearity of the chip under test 2 is poor.

[0028] [Second Embodiment]

[0029] Please refer to Figure 4 , Figure 4 which is a schematic diagram of the linearity signal providing device according to the second embodiment of the present invention.

[0030] The linearity signal providing device 1 includes a controller 11, a first signal generation circuit 12, a second signal generation circuit 13, a data delay circuit (Data delay Module) 14, a first output circuit 15, and a second output circuit 16.

[0031] The controller 11 is electrically connected to the first signal generation circuit 12 and the second signal generation circuit 13. The first signal generation circuit 12 is electrically connected to the first output circuit 15. The second signal generation circuit 13 is electrically connected to the data delay circuit 14. The data delay circuit 14 is electrically connected to the second output circuit 16.

[0032] The first signal generation circuit 12 is used to generate a reference clock signal CLS. The second signal generation circuit 13 is used to generate a receiver input signal RXIS. There is a time phase difference between the receiver input signal RXIS and the reference clock signal CLS. That is, when the first signal generation circuit 12 and the second signal generation circuit 13 generate signals, the phases of the two signals are the same. The initial receiver input signal PRXIS generated by the second signal generation circuit 13 needs to be delayed by the data delay circuit 14 before it becomes the receiver input signal RXS and has a time phase difference from the reference clock signal CLS generated by the first signal generation circuit 12.

[0033] When the linearity signal providing device 1 is connected to the chip under test 2 for linearity testing, the controller 11 of the linearity signal providing device 1 sends a first control signal to the first signal generation circuit to output a reference clock signal CLS to the chip under test 2 by using the first output circuit 15. The controller 11 of the linearity signal providing device 1 will simultaneously send a second control signal to the second signal generation circuit 13 to output a receiver input signal RXIS to the chip under test 2 by using the second output circuit 16.

[0034] [Third Embodiment]

[0035] Please refer to Figure 5 、 Figure 5 is a flowchart of the chip linearity testing method according to the third embodiment of the present invention.

[0036] The chip linearity testing method in this embodiment is applicable to the chip linearity testing system SYS1 and the linearity testing device 1 in the first embodiment and the second embodiment. However, it is not limited to the systems and devices in the foregoing embodiments, and their functions and structures will not be elaborated herein.

[0037] The chip linearity testing method includes the following steps:

[0038] Providing a reference clock signal and a receiver input signal to the chip under test, wherein there is a time phase difference between the reference clock signal and the receiver input signal (step S110); and

[0039] Judging the linearity of the interpolation circuit in the chip under test according to a plurality of phase signals corresponding to the reference clock signal and the receiver input signal transmitted in the chip under test (step S120).

[0040] In step S110, the chip linearity testing system SYS1 includes a linearity signal providing device 1 and a chip under test 2.

[0041] The linearity signal providing device 11 provides a reference clock signal CLS and a receiver input signal RXIS. There is a time phase difference between the reference clock signal CLS and the receiver input signal RXIS.

[0042] The chip under test 2 receives the reference clock signal CLS and the receiver input signal RXIS for linearity testing.

[0043] The chip under test 2 includes at least a digital clock recovery circuit 21 and a phase-locked loop circuit (PLL) 22. The digital clock recovery circuit 21 is electrically connected to the phase-locked loop circuit 22. The phase-locked loop circuit 22 receives the reference clock signal CLS. The digital clock recovery circuit 21 receives the receiver input signal RXIS.

[0044] As described above, in some embodiments, the digital clock recovery circuit 21 includes a sampling and locking circuit 211, a phase detection circuit 212, a digital low-pass filter circuit 213, and a phase interpolation circuit 214. For the connection relationship, please refer to Figure 2 .

[0045] The sampling and locking circuit 211 can output the recovered clock signal clock and data.

[0046] The linearity signal providing device 1 can provide the reference clock signal CLS and the receiver input signal RXIS simultaneously.

[0047] In step S120, the linearity is judged by the amount of available phase in the jitter tolerance test. Near more available phase indicates that the internal interpolation phases are denser, and near less available phase indicates that the internal interpolation phases are sparser. That is, when the time phase difference is in the case of more available phase, the jitter tolerance test will be better, and vice versa, the jitter tolerance test will be worse.

[0048] [Advantageous Effects of the Embodiment]

[0049] One of the advantageous effects of the present invention is that for the chip linearity test system, the linearity signal providing device, and the chip linearity test method provided by the present invention, only two signals with a time phase difference need to be provided to the chip under test, and the linearity analysis can be carried out by using the jitter tolerance test, which can greatly reduce the test cost and time.

[0050] The content disclosed above is only the preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

[0051] Explanation of Reference Numerals:

[0052] SYS1: Chip linearity test system

[0053] 1: Linearity signal providing device

[0054] 2: Chip under test

[0055] CLS: Reference clock signal

[0056] RXIS: Receiver input signal

[0057] 11: Controller

[0058] 12: First signal generation circuit

[0059] 13: Second signal generation circuit

[0060] 14: Data delay circuit

[0061] 15: First output circuit

[0062] 16: Second output circuit

[0063] PRXIS: Initial receiver input signal

[0064] S110 - S120: Steps

[0065] 21: Digital clock recovery circuit

[0066] 22: Phase - locked loop circuit

[0067] 211: Sampling lock circuit

[0068] 212: Phase detection circuit

[0069] 213: Digital low - pass filter circuit

[0070] 214: Phase interpolation circuit

[0071] clock: Clock signal

[0072] L1, L2: Curves

Claims

1. A method for testing the linearity of a chip, comprising: Providing a reference clock signal and a receiver input signal to the chip under test, wherein there is a time phase difference between the reference clock signal and the receiver input signal; And Based on a plurality of phase signals corresponding to the reference clock signal and the receiver input signal in the chip under test, determining the linearity of the chip under test by using the amount of available phase in jitter tolerance testing.

2. The chip linearity test method according to claim 1, wherein, The chip under test at least includes a digital clock recovery circuit and a phase-locked loop circuit. The digital clock recovery circuit is electrically connected to the phase-locked loop circuit. The phase-locked loop circuit receives the reference clock signal, and the digital clock recovery circuit receives the receiver input signal.

3. The chip linearity test method according to claim 2, wherein, The digital clock recovery circuit includes a sampling and locking circuit, a phase detection circuit, a digital low-pass filter circuit, and a phase interpolation circuit. The sampling and locking circuit is electrically connected to the phase detection circuit. The phase detection circuit is electrically connected to the digital low-pass filter circuit. The phase interpolation circuit is electrically connected to the digital low-pass filter circuit and the sampling and locking circuit.

4. The chip linearity test method according to claim 3, wherein, The linearity signal providing device simultaneously provides the reference clock signal and the receiver input signal.

5. A chip linearity test system, comprising: A linearity signal providing device, providing a reference clock signal and a receiver input signal, wherein there is a time phase difference between the reference clock signal and the receiver input signal; And A chip under test, receiving the reference clock signal and the receiver input signal, and performing a linearity test by using the amount of available phase in jitter tolerance testing.

6. The chip linearity test system according to claim 5, wherein, The chip under test at least includes a digital clock recovery circuit and a phase-locked loop circuit. The digital clock recovery circuit is electrically connected to the phase-locked loop circuit. The phase-locked loop circuit receives the reference clock signal, and the digital clock recovery circuit receives the receiver input signal.

7. The chip linearity test system according to claim 6, wherein, The digital clock recovery circuit includes a sampling and locking circuit, a phase detection circuit, a digital low-pass filter circuit, and a phase interpolation circuit. The sampling and locking circuit is electrically connected to the phase detection circuit. The phase detection circuit is electrically connected to the digital low-pass filter circuit. The phase interpolation circuit is electrically connected to the digital low-pass filter circuit and the sampling and locking circuit. The linearity signal providing device simultaneously provides the reference clock signal and the receiver input signal.

8. The chip linearity test system according to claim 5, wherein, The linearity signal providing device includes: A controller; A first signal generation circuit, electrically connected to the controller, for generating a reference clock signal; A second signal generation circuit, electrically connected to the controller, for generating an initial receiver input signal; A data delay circuit, electrically connected to the second signal generation circuit. After the initial receiver input signal passes through the data delay circuit, a receiver input signal is generated, and there is a time phase difference between the receiver input signal and the reference clock signal; A first output circuit, electrically connected to the first signal generation circuit; and A second output circuit, electrically connected to the data delay circuit, for outputting the receiver input signal.

9. The chip linearity test system according to claim 8, wherein, When the linearity signal providing device is connected to the chip under test for linearity testing, the controller of the linearity signal providing device sends a first control signal to the first signal generation circuit to output the reference clock signal to the chip under test by using the first output circuit. Moreover, the controller of the linearity signal providing device simultaneously sends a second control signal to the second signal generation circuit to output the receiver input signal to the chip under test by using the second output circuit.

10. A linearity signal providing device, comprising: A controller; A first signal generation circuit, electrically connected to the controller, for generating a reference clock signal; A second signal generation circuit, electrically connected to the controller, for generating an initial receiver input signal; A data delay circuit, electrically connected to the second signal generation circuit, after the initial receiver input signal passes through the data delay circuit, a receiver input signal is generated, and there is a time phase difference between the receiver input signal and the reference clock signal; A first output circuit, electrically connected to the first signal generation circuit; And A second output circuit, electrically connected to the data delay circuit for outputting the receiver input signal; Wherein, when the linearity signal providing device is connected to the chip under test for linearity testing by using the amount of available phase in the jitter tolerance test, the controller of the linearity signal providing device sends a first control signal to the first signal generation circuit to output the reference clock signal to the chip under test by using the first output circuit. Moreover, the controller of the linearity signal providing device simultaneously sends a second control signal to the second signal generation circuit to output the receiver input signal to the chip under test by using the second output circuit.

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