Pixel Refreshing Method and Device, Storage Medium, and Display

Abstract

A pixel refreshing method, device, storage medium, and display. The pixel refreshing method includes: in the pixel refreshing stage, scanning the pixel array row by row in response to a gate scanning signal; when scanning each row of pixels, driving the voltages of the sub-pixel data of each column to a preset data level in response to a source scanning signal; when scanning each row of pixels, if the voltages of the sub-pixel data of each column of the current row of pixels reach the preset data level, immediately start scanning the next row of pixels; after the scanning of the current frame of pixel array is completed, the display enters a pixel holding stage for maintaining the display screen; wherein, in the pixel refreshing stage, the display is in a pixel driving mode, and in the pixel holding stage, the display is in a pixel holding mode, and the power consumption of the display in the pixel holding stage is lower than the power consumption of the display in the pixel refreshing stage. The technical solution of the present invention can reduce the power consumption of the display without reducing the refresh frame rate and display quality.

Description

Technical Field

[0001] The present invention relates to the technical field of data display, and in particular, to a pixel refreshing method and device, a storage medium, and a display. Background Art

[0002] With the rapid development of the times, portable consumer electronic products such as mobile phones, smart watches, and laptops are becoming more and more lightweight and miniaturized, and at the same time, require longer battery life. As the carrier for displaying information of the above electronic systems and an essential component for human-computer interaction, the display not only has very high quality requirements for the display quality of the display, but also has increasingly stringent requirements for its power consumption during operation, so that the battery life of the electronic system can be maximized with the same battery capacity.

[0003] The frame rate is the frequency at which the display refreshes the screen. For example, a 60Hz refresh rate means that the display screen is refreshed 60 times per second. The larger the frame rate, the greater the power consumption required to refresh the display screen. For example, the power consumption of refreshing the panel at a 60Hz refresh rate is approximately twice that of refreshing the panel at a 30Hz refresh rate.

[0004] However, reducing the refresh rate can reduce the power consumption of the display, but at the cost of reducing the display quality of the display; for example, reducing the refresh rate will cause display anomalies such as screen flickering and uneven image quality. Summary of the Invention

[0005] The technical problem solved by the present invention is how to reduce the power consumption of the display without reducing the refresh frame rate and display quality.

[0006] To solve the above technical problem, an embodiment of the present invention provides a pixel refreshing method for a display. During a single-frame display time, it includes a pixel refreshing stage for scanning the pixel array row by row and a pixel maintaining stage after the pixel array scanning is completed; the pixel refreshing method includes: during the pixel refreshing stage, scanning the pixel array row by row in response to a gate scanning signal; when scanning each row of pixels, driving the voltage of each column of sub-pixel data to a preset data level in response to a source scanning signal; when scanning each row of pixels, if the voltage of each column of sub-pixel data of the current row of pixels reaches the preset data level, immediately start scanning the next row of pixels; after the current frame of pixel array scanning is completed, the display enters the pixel maintaining stage for maintaining the display screen; wherein, during the pixel refreshing stage, the display is in a pixel driving mode, and during the pixel maintaining stage, the display is in a pixel maintaining mode, and the power consumption of the display during the pixel maintaining stage is lower than the power consumption of the display during the pixel refreshing stage.

[0007] Optionally, during the pixel holding stage, one or more circuit modules in the display are in an off state or a low-power state, only meeting the display requirements of the display panel to reduce the power consumption of the display during the pixel holding stage.

[0008] Optionally, the starting to scan the next row of pixels if the voltages of the column sub-pixel data of the current row of pixels reach the preset data level includes: starting to scan the next row of pixels if the voltages of the column sub-pixel data of the current row of pixels reach the preset data level and the preset data level is correctly locked in the corresponding sub-pixel.

[0009] Optionally, the display includes a gate driver circuit for generating the gate scan signal; after all pixel arrays of the current frame are scanned, the display enters the pixel holding stage, and the gate driver circuit only outputs the gate scan signal that meets the display requirements until the beginning of the next frame scan.

[0010] Optionally, the display further includes a first boost circuit for providing the power supply for the gate driver circuit; after all pixel arrays of the current frame are scanned, the display enters the pixel holding stage, and the first boost circuit enters the low-power state so that the gate driver circuit outputs only the gate scan signal that meets the display requirements until the beginning of the next frame scan.

[0011] Optionally, the display includes a source driver circuit for generating the source scan signal; after all pixel arrays of the current frame are scanned, the display enters the pixel holding stage, and the source driver circuit is in a fully off state or enters the low-power state, and in this low-power state, the source driver circuit only outputs the source scan signal that meets the display requirements until the beginning of the next frame scan.

[0012] Optionally, the display further includes a second boost circuit for providing the power supply for the source driver circuit; after all pixel arrays of the current frame are scanned, the display enters the pixel holding stage, and the second boost circuit is in a fully off state or the second boost circuit is in the low-power state so that the source driver circuit outputs only the source scan signal that meets the display requirements until the beginning of the next frame scan.

[0013] Optionally, the display further includes a timing controller. After all pixel arrays of the current frame are scanned, the display enters the pixel holding stage, and the timing controller controls the gate driver circuit, the first boost circuit, the source driver circuit, and the second boost circuit to enter the low-power state until the beginning of the next frame scan.

[0014] Optionally, the display further includes a timing controller. After all pixel arrays of the current frame are scanned, the display enters a pixel holding stage, and a control signal provided by the display controls the timing controller to enter the low power state until the beginning of the next frame scan.

[0015] Optionally, the display time of the current frame is determined according to the refresh frequency of the display.

[0016] To solve the above technical problems, an embodiment of the present invention also discloses a pixel refreshing device, which includes: a gate driving circuit for generating a gate scan signal; a first boosting circuit for providing a working power supply for the gate driving circuit; a source driving circuit for generating a source scan signal; a second boosting circuit for providing a working power supply for the source driving circuit; a timing controller for generating a timing control signal to control the execution of the steps of the pixel refreshing method.

[0017] An embodiment of the present invention also discloses a storage medium, on which a computer program is stored, and when the computer program is run by a processor, it executes the steps of the pixel refreshing method.

[0018] An embodiment of the present invention also discloses a display, including: a display panel; the pixel refreshing device.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] In the technical solution of the present invention, the single-frame display time includes a pixel refreshing stage for scanning each row of the pixel array line by line and a pixel holding stage after the pixel array scanning is completed; in the pixel refreshing stage, when scanning each row of pixels, if the voltages of the sub-pixels in each column of the current row of pixels reach the preset data level, the scanning of the next row of pixels is immediately started; after the current frame pixel array scanning is completed, the display enters the pixel holding stage for maintaining the display screen. In the pixel refreshing stage, the display is in the pixel driving mode, and in the pixel holding stage, the display is in the pixel holding mode; the power consumption of the display in the pixel holding stage is lower than the power consumption of the display in the pixel refreshing stage. The technical solution of the present invention enters the pixel holding stage after the pixel array scanning is completed, thereby realizing the reduction of the display power consumption without reducing the frame rate and without reducing the display quality of the display.

[0021] Further, in the pixel holding stage, one or more circuit modules in the display are in the off state or the low-power state, only meeting the display requirements of the display panel, so as to reduce the power consumption of the display in the pixel holding stage. In the technical solution of the present invention, since there is no need to scan the pixel array in the pixel holding stage, one or more circuit modules in the display can be put into the off state or the low-power state to reduce the power consumption of the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of a display in the prior art;

[0023] Figure 2 is a flowchart of a pixel refreshing method according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a pixel array refreshing method in the prior art;

[0025] Figure 4 is a schematic diagram of a specific application scenario according to an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of another specific application scenario according to an embodiment of the present invention;

[0027] Figure 6 is a schematic structural diagram of a pixel refreshing device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] As described in the background art, reducing the refresh rate can reduce the power consumption of the display, but at the cost of reducing the display quality of the display; in addition, reducing the refresh rate will cause display anomalies such as screen flickering and uneven image quality.

[0029] Please refer to Figure 1 , Figure 1 which shows a display structure.

[0030] The display 10 includes a display panel 100, a gate driving circuit 200, a first boosting circuit 300, a timing controller 400, a source driving circuit 500, and a second boosting circuit 600.

[0031] In a specific implementation, the display panel 100 can be any known carrier for supporting screen display, such as a well-known liquid crystal display (LCD), an active-matrix organic light-emitting diode (AMOLED) panel, etc. The display panel 100 includes m horizontal scan lines G1, G2, G3, ……, Gm, n vertical scan lines S1, S2, S3, ……, Sn, and a pixel array 101. Without loss of generality, the pixel array 101 includes a plurality of pixel units 102, and each pixel unit 102 includes three sub-pixels. Each horizontal scan line is simultaneously connected to the n-column sub-pixels corresponding to its current row, each vertical scan line is connected to the m-row sub-pixels corresponding to its current position, and each sub-pixel is connected to a horizontal scan line and a vertical scan line, thus forming a pixel array 101 composed of m·n sub-pixels in total. The gate driving circuit 200 is connected to all m horizontal scan lines of the display panel 100 and is adapted to generate m gate scan signals G1, G2, G3, ……, Gm to turn on the corresponding horizontal scan lines; the source driving circuit 500 is connected to all vertical scan lines of the display panel 100 and is adapted to generate n source scan signals S1, S2, S3, ……, Sn to provide data voltages to the pixel units connected to the corresponding horizontal scan lines through the n vertical scan lines based on the turning-on rules of the m gate scan signals; the first boosting circuit 300 generates the power supply for the gate driving circuit and drives the m horizontal scan lines to a certain required level; the second boosting circuit 600 generates the power supply for the source driving circuit and drives the n vertical scan lines to the pixel data level; the timing controller 400 is respectively connected to the gate driving circuit 200, the source driving circuit 500, the first boosting circuit 300, and the second boosting circuit 600, and is adapted to control the first boosting circuit 300 and the second boosting circuit 600 to generate two pairs of power signals VGD and VSD required by the gate driving circuit 200 and the source driving circuit 500. At the same time, the timing controller 400 also controls the gate driving circuit 200 and the source driving circuit 500 to generate m gate scan signals and n source scan signals respectively.

[0032] The display screen of the display refreshes all pixel arrays of the display in units of frames.

[0033] It should be noted that the pixel refreshing method of the embodiments of the present invention can also be used in the above display structure.

[0034] The technical solution of the present invention enters the pixel holding stage after the pixel array scanning is completed. The power consumption of the display in the pixel holding stage is lower than that in the pixel refreshing stage, thereby realizing the reduction of the display power consumption without reducing the frame rate and without reducing the display quality of the display.

[0035] Furthermore, in the technical solution of the present invention, since it is not necessary to scan the pixel array during the pixel maintenance stage, one or more circuit modules in the display can be turned off or into a low-power state to reduce the power consumption of the display.

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0037] Figure 2 It is a flowchart of a pixel refreshing method according to an embodiment of the present invention.

[0038] In the embodiment of the present invention, the pixel refreshing method provided in the following steps S101 to S104 can be executed by a terminal device. Specifically, the following steps S101 to S104 can be executed by a display in the terminal device, or by a chip in the terminal device, or by a chip module in the terminal device.

[0039] Specifically, the pixel refreshing method may include the following steps:

[0040] Step S101: In the pixel refreshing stage, scan the pixel array row by row in response to a gate scan signal;

[0041] Step S102: When scanning each row of pixels, drive the voltage of each column of sub-pixel data to a preset data level in response to a source scan signal;

[0042] Step S103: When scanning each row of pixels, if the voltage of each column of sub-pixel data of the current row of pixels reaches the preset data level, immediately start scanning the next row of pixels;

[0043] Step S104: After the current frame of pixel array is scanned, the display enters the pixel maintenance stage to maintain the display screen.

[0044] It should be noted that the serial numbers of the steps in this embodiment do not represent the limitation of the execution order of each step.

[0045] When the refresh rate of the display is known, the display time of each frame of data is fixed. For example, if the frame rate is 60 frames per second, the display time of each frame is 1 / 60 second. In this embodiment, the single-frame display time is divided into a pixel refreshing stage and a pixel maintenance stage. During the pixel refreshing stage, the pixel array is scanned, and during the pixel maintenance stage, the display of the pixels is maintained.

[0046] In the specific implementation of steps S101 and S102, when refreshing the pixel array in the pixel refreshing stage, the voltage of each column of sub-pixel data is driven to a preset data level.

[0047] In the specific implementation of step S103, if the voltages of the sub-pixel data of each column of the current row of pixels reach the preset data level, the scanning of the next row of pixels is immediately started.

[0048] Furthermore, if the voltages of the sub-pixel data of each column of the current row of pixels reach the preset data level and the preset data level is correctly locked in the corresponding sub-pixel, the scanning of the next row of pixels is started.

[0049] Specifically, after driving the sub-pixel data to the expected level Vdata (i.e., the preset data level), a certain time is maintained to correctly lock the data into the corresponding sub-pixel, and the required time is t E , and this time is called the effective driving time.

[0050] Please refer to Figure 3 , in the prior art, when the horizontal scan line G1 is turned on, all n columns of sub-pixels connected to this horizontal scan line in the display panel of the display are turned on; at the same time, n source scan signals S1, S2, S3,..., Sn drive the data corresponding to all n columns of sub-pixels through n vertical scan lines, and during the period when G1 is on, the sub-pixel data is driven to the data level Vdata1 ( Figure 3 Taking S1 and S2 as examples in , the driving waveforms of other S3, S4,..., Sn are similar to those of S1 and S2). The data level Vdata1 varies according to the picture content of these n columns of sub-pixels. After driving the sub-pixel data to the expected data level Vdata1, a certain time is maintained to correctly lock the data into the corresponding sub-pixel, and the required time is t E , and this time is called the effective driving time. During the scanning time t H of each row of pixels, in addition to the effective driving time t E , it also includes an invalid driving time t INE , that is, t H = t E + t INE . Among them, the scanning time t H of each row of pixels = 1 / m, where m is the number of rows of the pixel array. During the period of the invalid driving time t INE , the working modes of each module of the display are the same as those during the effective driving time t E . Therefore, within one frame of refreshing the pixel array of the display, when m horizontal scan lines are sequentially turned on, there will be T INE = m·t INE of invalid driving time, increasing the additional power consumption of the display.

[0051] In the embodiments of the present invention, by immediately starting to scan the next row of pixels when the voltages of the sub-pixel data in each column of the current row of pixels reach the preset data level, and entering the pixel holding stage after the scanning of the pixel array is completed, the display is prevented from performing the same operations during the invalid driving time as during the effective driving time; in other words, the difference from the traditional display driving method is that the embodiments of the present invention eliminate a large amount of invalid driving time T of the traditional display driving. INE , thereby reducing the power consumption of the display.

[0052] Please refer to Figure 1 and Figure 4 , Figure 4 which shows a schematic diagram of the display time of each frame in the embodiments of the present invention.

[0053] As Figure 4 shown, VSYNC is a frame indication signal, and the jump period of the VSYNC signal jump pulse is the time Tf for refreshing one frame of the display screen. When the refresh frequency is 60 Hz, Tf = 1 / 60 ≈ 16.67 ms.

[0054] The time Tf for refreshing one frame of the display = Vbp + Vfp + Tr + Thd. Among them, Tr is the driving time for refreshing all pixel arrays of the display, that is, the duration of the pixel refresh stage; Thd is the time for the current frame of the display to maintain its display screen, that is, the duration of the pixel holding stage, Vbp is the preset waiting time before refreshing, and Vfp is the preset waiting time after refreshing.

[0055] In specific implementation, at the beginning of refreshing one frame of the display, after a short waiting time Vbp, it enters the pixel refresh stage Tr. The timing controller 400 controls the gate driving circuit 200 and the first boosting circuit 300 to generate m gate scanning signals for scanning the pixel array 101 of the display, and successively turn on the horizontal scanning lines in a certain specified timing. For example, the m horizontal scanning lines are successively turned on in the order of G1, G2, G3,..., Gm until the last horizontal scanning line is scanned, and then it enters the pixel holding stage Thd. During the pixel holding stage Thd, the display 10 is in the pixel holding mode.

[0056] During the pixel refresh stage Tr, the timing controller 400 controls the source driving circuit 500 and the boosting circuit 600 to generate n source scanning signals for scanning the pixel array 101 of the display, and according to the opening order of the m gate scanning signals, successively write the data voltages of the corresponding sub-pixels into the sub-pixels through the n vertical scanning lines (that is, provide an m×1 data voltage matrix) until all the sub-pixels corresponding to the last horizontal scanning line complete data writing, and then it enters the pixel holding stage Thd.

[0057] During the pixel refresh stage Tr, the timing controller 400 controls the first boost circuit 300 to operate in the pixel driving mode to generate a power supply pair VGD. This power supply pair VGD is used to satisfy the requirements of the gate driving circuit 200 for generating m gate scanning signals with functions and timing satisfied.

[0058] During the pixel refresh stage Tr, the timing controller 400 controls the second boost circuit 600 to operate in the pixel driving mode to generate a power supply pair VSD. This power supply pair VSD is used to satisfy the requirements of the source driving circuit 500 for generating n source scanning signals with functions and timing satisfied.

[0059] During the pixel refresh stage Tr, the timing controller 400 itself also operates in the pixel driving mode to meet the functional requirements of the gate driving circuit 200, the first boost circuit 300, the source driving circuit 500, and the second boost circuit 600.

[0060] Refer to Figure 5 At the same time, during the pixel refresh stage Tr, when m horizontal scanning lines are sequentially turned on in a certain order, the corresponding n source scanning signals write the corresponding data voltages into the sub-pixels. Taking the first 4 gate scanning signals (a total of m) and the first 2 source scanning signals (a total of n) at the beginning of each frame of the display as an example for illustration.

[0061] At the beginning of refreshing one frame of the pixel array of the display, after a short waiting time Vbp, the horizontal scanning line G1 is turned on, that is, all n columns of sub-pixels connected to this horizontal scanning line in the display panel 100 of the display are turned on; at the same time, n source scanning signals S1, S2, S3,..., Sn scan and read the data corresponding to the n columns of sub-pixels connected to the horizontal sketch line G1 through n vertical scanning lines, that is, during the period when G1 is on, the sub-pixel data is driven to the data level Vdata1 (taking S1 and S2 as examples in the figure, and the driving waveforms of other S3, S4,..., Sn are similar to that of S1 and S2). Among them, the data level Vdata1 depends on whether the picture contents of these n columns of sub-pixels are the same or different. Correspondingly, during the period when G2 is on, the sub-pixel data is driven to the data level Vdata2; during the period when G3 is on, the sub-pixel data is driven to the data level Vdata3; during the period when G4 is on, the sub-pixel data is driven to the data level Vdata4.

[0062] Specifically, it takes time t to drive the sub-pixel data to the expected level Vdata and maintain it for a certain time to correctly lock the data into the corresponding sub-pixels. E This time is called the effective driving time, and this effective driving time can be adjusted according to the actual working state of the display, and the embodiments of the present invention do not limit this.

[0063] During the period of the effective driving time t E the gate driving circuit 200, the first boosting circuit 300, the source driving circuit 500, and the second boosting circuit 600 of the display all operate in the pixel driving mode.

[0064] After the pixel refreshing stage Tr ends, the display enters the pixel holding stage Thd. During the pixel holding stage Thd, the display does not need to perform a refreshing operation on the pixel data, and the gate scanning signal remains at a fixed level, so as to ensure that the data written into the pixel array during the display refreshing stage remains unchanged, without requiring all modules of the display to remain in the state of the pixel refreshing stage Tr.

[0065] In a non-limiting embodiment of the present invention, during the pixel holding stage, one or more circuit modules in the display are in a closed state or a low-power state, only meeting the display requirements of the display panel, so as to reduce the power consumption of the display during the pixel holding stage. In the present invention, the low-power state includes that the circuit module is in a low-level state or a fixed-level state, or the operating frequency of the circuit module is in a reduced state. Of course, it may also include other low-power states, which are not listed one by one here.

[0066] One or more circuit modules referred to in the embodiments of the present invention may be the gate driving circuit 200, the first boosting circuit 300, the source driving circuit 500, the second boosting circuit 600, and / or the timing controller 400.

[0067] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, the gate driving circuit 200 only outputs a gate scanning signal that meets the display requirements until the beginning of the next frame of scanning.

[0068] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, the first boosting circuit 300 enters a low-power state, so that the gate driving circuit 200 outputs a gate scanning signal that only meets the display requirements until the beginning of the next frame of scanning.

[0069] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, the source driving circuit 500 is in a completely closed state or enters a low-power state. In this low-power state, the source driving circuit 500 only outputs a source scanning signal that meets the display requirements until the beginning of the next frame of scanning.

[0070] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, the second boosting circuit 600 is in a completely closed state, or the second boosting circuit 600 is in a low-power state, so that the source driving circuit 500 outputs a source scanning signal that only meets the display requirements until the beginning of the next frame of scanning.

[0071] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, the timing controller controls the gate driving circuit 200, the first boosting circuit 300, the source driving circuit 500, and the second boosting circuit 600 to enter the low power consumption state until the beginning of the next frame scan.

[0072] In a non-limiting embodiment of the present invention, after the display enters the pixel holding stage, a control signal provided by the display controls the timing controller 400 to enter the low power consumption state until the beginning of the next frame scan.

[0073] In a specific embodiment of the present invention, the timing controller 400 controls the gate driving circuit 200 to generate gate scan signals G1, G2, G3, ……, Gm for maintaining the stability of the display screen of the display; the scan signals are used to turn off the refresh paths of all sub-pixels in the pixel array of the display to prevent the sub-pixel data from changing. In a specific implementation, the gate scan signals G1, G2, G3, ……, Gm are defined according to the display panel, and the gate driving circuit 200 enters the low power consumption state.

[0074] The timing controller 400 controls the first boosting circuit 300 to generate a power supply pair VGD'. This power supply pair is suitable for maintaining the gate scan signals G1, G2, G3, ……, Gm whose output functions and performances of the gate driving circuit 200 meet the panel requirements. In a specific implementation, the level and driving ability of this power supply pair VGD' are different from those of VGD when the display is in the pixel refresh stage. Generally speaking, the absolute value of the level and the driving ability of this power supply pair VGD' are significantly lower than those of VGD when the display is in the pixel refresh stage. Thus, the timing controller 400 adjusts the working state of the first boosting circuit 300 to make the first boosting circuit 300 enter the low power consumption state.

[0075] The timing controller 400 controls the source driving circuit 500 to generate source scan signals S1, S2, S3, ……, Sn for maintaining the stability of the display screen of the display. In a specific implementation, the source scan signals S1, S2, S3, ……, Sn are defined according to the display panel. Generally speaking, since the display needs to turn off all the sub-pixel refresh data paths in its pixel array to maintain the stability of its screen, the timing controller 400 controls the source driving circuit 500 to be in a completely off state or output a fixed level. Thus, the source driving circuit enters the low power consumption state.

[0076] The timing controller 400 controls the second boost circuit 600 to generate a power supply pair VSD'. This power supply pair is suitable for maintaining the gate scan signals S1, S2, S3, ……, Sn output by the source driver circuit 500 so that its output function and performance meet the panel requirements; in a specific implementation, the level and driving ability of this power supply pair VSD' are different from those of VSD when the display is in the pixel refresh stage. Generally speaking, the absolute value of the level and the driving ability of this power supply pair VSD' are significantly lower than those of VSD when the display is in the pixel refresh stage. Thus, the timing controller 400 adjusts the working state of the second boost circuit 600 to a low-power state or completely shuts down this boost circuit, so that the second boost circuit 600 enters the low-power state.

[0077] The display panel 100 does not need to update any sub-pixel data in the display array and keeps the data unchanged after pixel refresh. Therefore, through m gate scan signals and n source scan signals, the current display picture of the display is maintained unchanged. Furthermore, the unchanged pixel data ensures the stability of the display picture quality of the display, so that the display panel 100 also enters the low-power state.

[0078] Since the gate driver circuit 200, the first boost circuit 300, the source driver circuit 500, the second boost circuit 600, and the display panel 100 have all entered the low-power state, the timing controller 400 does not need to remain in the normal pixel refresh state either. The requirements of the former multiple module circuits for the timing controller 400 are reduced to the lowest level, and some functions do not need to be provided. Therefore, the timing controller 400 also enters the low-power state.

[0079] Thus, the entire display is in the low-power pixel holding mode.

[0080] That is to say, in the pixel holding stage, the display only needs to maintain each circuit module in the off state or the low-power state. The holding time can be controlled by the timing controller 400. In one frame display time, by reducing the time Tr of the pixel refresh stage and increasing the time Thd of the pixel holding stage, the purpose of reducing the power consumption of the display in the present invention is achieved.

[0081] Continue to refer to Figure 4 , in the Vfp stage, the timing controller 400 controls its own circuit and the gate driver circuit 200, the first boost circuit 300, the source driver circuit 500, and the second boost circuit 600 to turn on some functions or circuit modules to adjust the state of the display and enter the pixel refresh preparation stage.

[0082] The operations performed by the timing controller 400 in the Vfp stage are the reverse processes of the operations performed by the timing controller 400 in the pixel holding stage.

[0083] Furthermore, the time Thd of the pixel holding stage is the ineffective driving time saved in the pixel refreshing stage, that is: Thd = m × t INE .

[0084] Compared with the traditional driving method, the power consumption ΔW saved by the pixel refreshing method provided by the embodiment of the present invention is: ΔW = VDD × m × (t IN × I IN - t INE × I INE ); where, VDD represents the power supply of the display; m represents the number of gate scanning signals of the display; t IN represents the effective driving time of the display corresponding to each gate scanning signal of the display; I IN represents the average current consumption of the display during the effective driving time stage of each gate scanning signal; t INE represents the ineffective driving time of the display corresponding to each gate scanning signal; I INE represents the average current consumption of the display during the ineffective driving time stage of each gate scanning signal.

[0085] In the embodiment of the present invention, for one frame, the display time Tf does not change, so the frame rate of the display is ensured to be unchanged. Thus, on the premise of ensuring the unchanged display quality of the display, the power consumption of the display is greatly reduced, and the battery life of the electronic product is improved on the premise that the capacity of the power supply battery is limited.

[0086] Please refer to Figure 6 , the embodiment of the present invention also discloses a pixel refreshing device. The pixel refreshing device 50 may include some circuit modules in the display.

[0087] Specifically, the pixel refreshing device 50 may include:[[]]

[0088] A gate driving circuit 200 for generating gate scanning signals;

[0089] A first boosting circuit 300 for providing the working power supply of the gate driving circuit 200;

[0090] A source driving circuit 500 for generating source scanning signals;

[0091] A second boosting circuit 600 for providing the working power supply of the source driving circuit 500;

[0092] A timing controller 400 for generating timing control signals to control the above circuit modules to execute the steps of the pixel refreshing method.

[0093] For more content about the working principle and working mode of the pixel refreshing device 50, reference can be made to Figures 1 to 4The relevant descriptions in [reference] are not elaborated here.

[0094] An embodiment of the present invention also discloses a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program runs, it can execute Figure 1 the steps of the method shown in [reference]. The storage medium may include ROM, RAM, a magnetic disk, an optical disc, etc. The storage medium may also include a non-volatile memory or a non-transitory memory, etc.

[0095] It should be understood that the term "and / or" in this article is only a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0096] In the embodiments of this application, "a plurality of" means two or more.

[0097] In the embodiments of this application, the descriptions such as first and second are only for schematic and distinguishing description objects, without an order, and do not represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation to the embodiments of this application.

[0098] In the embodiments of this application, "connection" refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and this application does not make any limitation on this.

[0099] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU for short), and this processor may also be other general-purpose processors, digital signal processors (DSP for short), application specific integrated circuits (ASIC for short), field programmable gate arrays (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0100] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0101] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more collections of available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0102] It should be understood that in various embodiments of the present application, the sequence numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0103] In several embodiments provided in the present application, it should be understood that the disclosed methods, devices, and systems can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only a logical function division, and there can be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0105] In addition, in each embodiment of the present invention, each functional unit can be integrated into one processing unit, can be physically included separately for each unit, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware, or in the form of a hardware plus software functional unit.

[0106] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit stored in a storage medium includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute some steps of the methods described in each embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM for short), random access memories (RAM for short), magnetic disks, or optical discs that can store program codes.

[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A pixel refreshing method for a display, characterized in that, Divide the single-frame display time into a pixel refresh stage for scanning the pixel array row by row and a pixel holding stage after the pixel array scanning is completed. When the refresh frame rate of the display is known, the display time of the single-frame data is fixed; In the pixel refresh stage, scan the pixel array row by row in response to the gate scan signal; When scanning each row of pixels, drive the voltage of each column of sub-pixel data to a preset data level in response to the source scan signal; When scanning each row of pixels, if the voltage of each column of sub-pixel data of the current row of pixels reaches the preset data level, immediately start scanning the next row of pixels; After the scanning of the current frame pixel array is completed, the display enters the pixel holding stage for maintaining the display screen; Wherein, in the pixel refresh stage, the display is in the pixel driving mode, and in the pixel holding stage, the display is in the pixel holding mode. The power consumption of the display in the pixel holding stage is lower than the power consumption of the display in the pixel refresh stage.

2. The pixel refreshing method according to claim 1, wherein In the pixel holding stage, one or more circuit modules in the display are in the off state or the low-power state, only meeting the display requirements of the display panel to reduce the power consumption of the display in the pixel holding stage.

3. The pixel refreshing method according to claim 1, wherein The "if the voltage of each column of sub-pixel data of the current row of pixels reaches the preset data level, then start scanning the next row of pixels" includes: If the voltage of each column of sub-pixel data of the current row of pixels reaches the preset data level, and the preset data level is correctly locked in the corresponding sub-pixel, then start scanning the next row of pixels.

4. The pixel refreshing method according to claim 2, wherein The display includes a gate driving circuit for generating the gate scan signal; after the scanning of all pixel arrays in the current frame is completed, the display enters the pixel holding stage, and the gate driving circuit only outputs the gate scan signal that meets the display requirements until the beginning of the next frame scan.

5. The pixel refreshing method according to claim 4, wherein The display further includes a first boost circuit for providing the power supply for the gate driving circuit; after the scanning of all pixel arrays in the current frame is completed, the display enters the pixel holding stage, and the first boost circuit enters the low-power state so that the gate driving circuit outputs only the gate scan signal that meets the display requirements until the beginning of the next frame scan.

6. The pixel refreshing method according to claim 2, characterized in that The display includes a source driving circuit for generating the source scan signal; after the scanning of all pixel arrays in the current frame is completed, the display enters the pixel holding stage, and the source driving circuit is in the fully off state or enters the low-power state. In this low-power state, the source driving circuit only outputs the source scan signal that meets the display requirements until the beginning of the next frame scan.

7. The pixel refreshing method according to claim 6, wherein The display further includes a second boost circuit for providing the power supply for the source driving circuit; after the scanning of all pixel arrays in the current frame is completed, the display enters the pixel holding stage, and the second boost circuit is in the fully off state, or the second boost circuit is in the low-power state so that the source driving circuit outputs only the source scan signal that meets the display requirements until the beginning of the next frame scan.

8. The pixel refresh method according to claim 4, wherein The display further includes a timing controller. After all pixel arrays of the current frame are scanned, the display enters a pixel holding stage, and the timing controller controls the gate driving circuit, the first boosting circuit, the source driving circuit, and the second boosting circuit to enter a low power consumption state until the beginning of the next frame scan.

9. The pixel refreshing method according to claim 2, wherein The display further includes a timing controller. After all pixel arrays of the current frame are scanned, the display enters a pixel holding stage, and a control signal provided by the display controls the timing controller to enter the low power consumption state until the beginning of the next frame scan.

10. A pixel refreshing device, characterized in that, Comprising: A gate driving circuit for generating a gate scan signal; A first boosting circuit for providing a working power supply for the gate driving circuit; A source driving circuit for generating a source scan signal; A second boosting circuit for providing a working power supply for the source driving circuit; A timing controller for generating timing control signals to control the steps of performing the pixel refreshing method according to any one of claims 1 to 9.

11. A storage medium, on which a computer program is stored, characterized in that, When the computer program is run by a processor, it executes the steps of the pixel refreshing method according to any one of claims 1 to 9.

12. A display, characterized in that, Comprising: A display panel; The pixel refreshing device according to claim 10.

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