On-chip low leakage interconnect signal line system and addressable test array circuit
By introducing an on-chip low-leakage interconnect signal line system and an addressable test array circuit into the semiconductor test structure, and utilizing the signal protection path formed by the shielding layer and shielding wall, combined with the MOSFET ring gate and high-impedance voltage measurement, the problem of interconnect signal line leakage is solved, and the test efficiency and accuracy are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU PFTN SEMICON CO LTD
- Filing Date
- 2022-08-11
- Publication Date
- 2026-06-05
AI Technical Summary
In existing semiconductor testing structures, interconnect signal lines are prone to leakage, resulting in low testing efficiency, low area utilization, and long probe travel time.
An on-chip low-leakage interconnect signal line system is adopted, with the interconnect signal lines surrounded by first and second shielding layers and shielding walls, configured with the same voltage to suppress leakage current; in the addressable test array circuit, a signal protection path is used in conjunction with the test signal line, and the ring gate structure of the MOSFET and the high-impedance voltage measurement circuit are used to reduce leakage current.
It effectively suppressed leakage current in interconnect signal lines, improved the area utilization and time efficiency of the test structure, and ensured test accuracy.
Smart Images
Figure CN115188740B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor testing technology, specifically relating to an on-chip low-leakage interconnect signal line system and an addressable test array circuit using the same. Background Technology
[0002] In semiconductor development, it is typically necessary to use semiconductor test structures to test process maturity and semiconductor device performance. Figure 1 In existing test structures, each port of the device under test is directly connected to the chip pad via on-chip metal wires, and the instrument performs measurements by contacting the pad with probes.
[0003] Typically, the size of a test pad is around 60μm × 60μm. Testing one device under test (DUT) requires 2 to 4 pads, while the size of a DUT is usually within 3μm². Therefore, pads occupy a large portion of the test structure's area, resulting in low area utilization. Furthermore, when testing different DUTs, probes need to be moved to the pads of other test structures for measurement; generally, the probe movement time is much longer than the measurement time, further reducing the time efficiency of the testing process.
[0004] To address the aforementioned issues, a method has been proposed that allows multiple devices under test to share a pad by selectively connecting to specific devices under test (DUTs), thereby improving the utilization of the test structure's area and the test process time. However, such a structure may present the challenge of leakage current in the interconnect signal lines. Summary of the Invention
[0005] The purpose of this invention is to provide an on-chip low-leakage interconnect signal line system, which solves the problem of leakage in interconnect signal lines.
[0006] To achieve the above objectives, the present invention provides an on-chip low-leakage interconnect signal line system, applied on a chip, including interconnect signal lines configurable to have equal voltages and a signal protection path, wherein the signal protection path includes:
[0007] A first shielding layer and a second shielding layer, wherein the first shielding layer and the second shielding layer cover the interconnect signal line in the vertical projection direction of the chip, and the interconnect signal line is located between the first shielding layer and the second shielding layer;
[0008] A first shielding wall and a second shielding wall are respectively connected to the first shielding layer and the second shielding layer, and the interconnecting signal line is located between the first shielding wall and the second shielding wall.
[0009] In one embodiment, the first shielding layer includes a metal layer in the on-chip interconnect layer.
[0010] In one embodiment, the second shielding layer includes a substrate isolation trap of the chip or a gate layer of the chip; or,
[0011] The second shielding layer includes a metal layer in the interconnect layer on the chip.
[0012] In one embodiment, the first shielding wall and the second shielding wall respectively comprise via-filled dielectric in the inner dielectric layer of the chip; or,
[0013] The first and second shielding walls respectively include via-filled dielectric in the inner dielectric layer of the chip, and via-filled dielectric and metal layer in the interconnect layer; or,
[0014] The first shielding wall and the second shielding wall respectively include the via filling medium and the metal layer in the two interconnect layers on the chip.
[0015] This application also provides an addressable test array circuit for testing multiple devices under test, including:
[0016] Test signal line;
[0017] A signal protection path, which can be configured to be equal to the voltage on the test signal line;
[0018] Multiple addressable switches are connected to test signal lines and corresponding devices under test (DUTs).
[0019] The signal protection path includes:
[0020] A first shielding layer and a second shielding layer, wherein the first shielding layer and the second shielding layer cover the interconnect signal line in the vertical projection direction of the test array circuit, and the interconnect signal line is located between the first shielding layer and the second shielding layer.
[0021] A first shielding wall and a second shielding wall are respectively connected to the first shielding layer and the second shielding layer, and the interconnecting signal line is located between the first shielding wall and the second shielding wall.
[0022] In one embodiment, the first shielding layer includes a metal layer in the interconnect layer of the test array circuit.
[0023] In one embodiment, the second shielding layer includes a substrate isolation trap or a gate layer of the test array circuit; or,
[0024] The second shielding layer includes a metal layer in the interconnect layer of the test array circuit.
[0025] In one embodiment, the first shielding wall and the second shielding wall respectively comprise via-filled dielectric in the inner dielectric layer of the test array circuit; or,
[0026] The first and second shielding walls respectively include via-filled dielectric in the inner dielectric layer of the test array circuit, and via-filled dielectric and metal layer in the interconnect layer; or,
[0027] The first and second shielding walls respectively include via-filled dielectric and metal layers in the two interconnect layers of the test array circuit.
[0028] In one embodiment, the switch includes a MOS transistor, the gate of which has a ring-shaped vertical projection on its active region.
[0029] In one embodiment, the MOSFETs include at least two MOSFETs, and the at least two MOSFETs are configured to share a common gate; and / or,
[0030] The test signal line is connected to the low-leakage active region of the MOS transistor, wherein the low-leakage active region is a portion of the active region within the vertical projection of the gate of the MOS transistor onto its active region.
[0031] In one embodiment, the test signal line includes a drain voltage signal line for measuring the current of the device under test, and / or,
[0032] The test signal lines include drain induction signal lines used to measure the voltage of the device under test.
[0033] Compared with the prior art, in the on-chip low leakage interconnect signal line system of this application, the signal protection path and the interconnect signal line can be configured to the same voltage. In terms of process structure, the signal protection path can be arranged "around" the interconnect signal line through the cooperation of the first shielding layer, the second shielding layer, the first shielding wall and the second shielding wall, so that there is almost no voltage difference between the interconnect signal line and the signal protection path in its extension direction, thereby suppressing the leakage that may be generated by the interconnect signal line.
[0034] In another aspect, in the on-chip low-leakage interconnect signal line system of this application, the signal protection path can be constructed using existing semiconductor structures in the application scenario, resulting in lower implementation costs. Attached Figure Description
[0035] Figure 1 This is a schematic diagram of a semiconductor testing structure in the prior art;
[0036] Figure 2 This is a schematic diagram illustrating the application scenario of the on-chip low-leakage interconnect signal line system of this application;
[0037] Figure 3It is a schematic structural diagram of a on-chip low-leakage interconnect signal line system according to an embodiment of the present application;
[0038] Figure 4 It is a schematic structural diagram of a on-chip low-leakage interconnect signal line system according to another embodiment of the present application;
[0039] Figures 5 to 9 It is a schematic diagram of an application scenario of the on-chip low-leakage interconnect signal line system in various embodiments of the present application;
[0040] Figure 10 It is a schematic structural diagram of an addressable test array according to an embodiment of the present application;
[0041] Figure 11 It is a schematic structural diagram of the cooperation between a signal protection path and a test signal line in an addressable test array circuit according to an embodiment of the present application;
[0042] Figure 12 It is a schematic diagram of a surrounding gate structure of a MOS transistor in an addressable test array circuit according to an embodiment of the present application. Detailed implementation manners
[0043] The following will describe in detail the specific implementation manners of the present invention in conjunction with the accompanying drawings. However, it should be understood that the protection scope of the present invention is not limited by the specific embodiments.
[0044] Unless otherwise clearly stated, in the entire specification and claims, the term "comprising" or its variations such as "including" or "having" etc. will be understood to include the stated elements or components, and does not exclude other elements or other components.
[0045] Refer Figure 3 , and introduce a specific embodiment of the on-chip low-leakage interconnect signal line system 100 of the present application. In this embodiment, the low-leakage interconnect signal line system 100 includes an interconnect signal line 11 and a signal protection path 12.
[0046] The low-leakage interconnect signal line system 100 provided by the present application can be applied to various chips, especially chip types sensitive to leakage. The signal protection path 12 and the interconnect signal line 11 can be configured to have equal voltages. And, in the process structure, the signal protection path 12 is arranged "around" the interconnect signal line 11, so that there is almost no voltage difference between the interconnect signal line 11 and the signal protection path 12 in its extending direction, thereby suppressing the leakage that may occur in the interconnect signal line 11.
[0047] In one embodiment, the signal protection path 12 can copy the voltage on the interconnect signal line 11 through a voltage follower buffer, or the interconnect signal line 11 and the signal protection path 12 can be respectively connected to pads with equal voltages.
[0048] The signal protection path 12 includes a first shielding layer 121, a second shielding layer 122, a first shielding wall 123, and a second shielding wall 124. The first shielding layer 121 and the second shielding layer 122 shield the interconnect signal line 11 in the vertical projection direction of the chip, and the interconnect signal line 11 is located between the first shielding layer 121 and the second shielding layer 122; at the same time, the first shielding wall 123 and the second shielding wall 124 are respectively connected to the first shielding layer 121 and the second shielding layer 122, and the interconnect signal line 11 is located between the first shielding wall 123 and the second shielding wall 124.
[0049] In the above-described process structure, the first shielding layer 121, the second shielding layer 122, the first shielding wall 123, and the second shielding wall 124 form a shielding structure around the interconnecting signal line 11 on its periphery. It should be noted that the first shielding layer 121, the second shielding layer 122, the first shielding wall 123, and the second shielding wall 124 are not structurally required to be completely continuous. In some embodiments, it may be sufficient that the signal protection path 12 formed by the first shielding layer 121, the second shielding layer 122, the first shielding wall 123, and the second shielding wall 124 can provide leakage current suppression for the interconnecting signal line 11 to a certain extent or partially. This will be specifically explained in the following embodiments.
[0050] Coordination Figure 2 In a typical chip used in the on-chip low-leakage interconnect signal line system 100 of this application, multiple semiconductor devices may be included, such as field-effect transistors (FETs). Structurally, the parts related to the signal protection path 12 in the various embodiments of this application may mainly include the chip's substrate isolation well, gate layer, inner dielectric layer (ILD), interconnect layer, via filling medium, etc.
[0051] It can be understood that the substrate isolation well and the gate layer here can correspond to the isolation wells and gate layers of multiple semiconductor devices in the chip. The chip interconnect layer refers to a functional layer formed on the semiconductor device region in the back-end process (Back End of Line, BEOL) of chip fabrication for connecting semiconductor devices to external circuits. Generally, multiple interconnect layers can be fabricated on the chip, and each interconnect layer also includes a dielectric layer and a metal layer. The metal layer is used to connect the gates, source electrodes, or drain electrodes of different devices, and the dielectric layer is used to isolate the metal layers between different interconnect layers. The interconnect layer includes vias that penetrate the dielectric layer, and the vias are filled with conductive via filling media to electrically connect the metal layers in different interconnect layers. The inner dielectric layer refers to the dielectric layer between the first interconnect layer closest to the substrate and the substrate. Similarly, the inner dielectric layer also includes vias that penetrate it and is also filled with via filling media to electrically connect the semiconductor devices on the chip and the metal layers in the interconnect layer.
[0052] Exemplarily, the material of the above substrate can be single-crystalline silicon (Si), single-crystalline germanium (Ge), germanium-silicon (GeSi), or silicon carbide (SiC), or can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or can also be other materials, such as III-V group compounds like gallium arsenide. The gate layer can be doped polysilicon or high-k metal. The dielectric layer in the interconnect layer can be dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc., and Low-K materials such as Black Diamond, carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.; the metal layer material in the interconnect layer can be copper (Cu). The via filling media can be tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), their alloys, and / or their multilayers. The inner dielectric layer can be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), etc.
[0053] The following specifically introduces the specific process structures of the low-leakage interconnect signal line system in each embodiment of the present application.
[0054] Embodiment 1
[0055] Refer Figure 5 , the first shielding layer 121A is the metal layer in the interconnect layer 30A on the chip, the second shielding layer 122A is the substrate isolation well of the chip, and the first shielding wall 123A and the second shielding wall 124A are the via filling media in the inner dielectric layer 20A on the chip.
[0056] The 20A in the inner dielectric layer may include a plurality of continuously arranged through holes. That is, there may be a certain spacing between the adjacent through hole filling media. Moreover, the first shielding layer 121A and the second shielding layer 122A may also be provided with corresponding interconnection structures according to the requirements of chip design. In this way, a signal protection path is constructed using the existing semiconductor structures in the chip manufacturing process, and the implementation cost is relatively low.
[0057] It can be seen that at this time, the signal protection path can be used to prevent the leakage of the interconnection signal line 11A disposed in the inner dielectric layer 20A on the chip, and the interconnection signal line 11A can be disposed using the gate layer material.
[0058] Embodiment 2
[0059] Refer to Figure 6 , the first shielding layer 121B is a metal layer in the interconnection layer 32B on the chip, the second shielding layer 122B is the gate layer of the chip, and the first shielding wall 123B and the second shielding wall 124B include the through hole filling medium 21B in the inner dielectric layer 20B on the chip, and the through hole filling medium 311B and the metal layer 312B in the interconnection layer 31B.
[0060] It can be seen that at this time, the signal protection path substantially includes the semiconductor structures in the inner dielectric layer 20B and at least two interconnection layers 31B and 32B. The difference from Embodiment 1 is that in Embodiment 2, the gate layer of the chip is used as the second shielding layer 122B. At this time, the signal protection path can be used to prevent the leakage of the interconnection signal line 11B disposed in the interconnection layer 31B on the chip, and the interconnection signal line 11B can be disposed using the metal layer 312B material in the interconnection layer 31B.
[0061] Embodiment 3
[0062] Refer to Figure 7 , the first shielding layer 121C is a metal layer in the interconnection layer 32C on the chip, the second shielding layer 122C is the substrate isolation well of the chip, and the first shielding wall 123C and the second shielding wall 124C include the through hole filling medium 21C in the inner dielectric layer 20C on the chip, and the through hole filling medium 311C and the metal layer 312C in the interconnection layer 31C.
[0063] It can be seen that at this time, the signal protection path also includes the semiconductor structures in the inner dielectric layer 20C and at least two interconnection layers 31C and 32C. The difference from Embodiment 2 is that in Embodiment 3, the substrate isolation well of the chip is used as the second shielding layer 122C, and moreover, the interconnection signal line 11C can be disposed using the metal layer 312C material or the gate layer material in the interconnection layer 31C.
[0064] Embodiment 4
[0065] Refer to Figure 8 The first shielding layer 121D and the second shielding layer 122D are metal layers in two non - adjacent interconnect layers 33D and 31D on the chip. The first shielding wall 123D and the second shielding wall 124D include via fill media and metal layers in two interconnect layers 31D and 32D. Specifically, it can be considered that the first shielding wall 123D and the second shielding wall 124D include the via fill media 311D in the interconnect layer 31D, as well as the via fill media 321D and the metal layer 322D in the interconnect layer 32D.
[0066] It can be seen that at this time, the signal protection path substantially includes semiconductor structures in three consecutive interconnect layers 31D, 32D, and 33D. In such an embodiment, the interconnect signal line 11D can be arranged using the material of the metal layer 322D in the interconnect layer 32D.
[0067] It can be understood that in a substitution method similar to this embodiment, the signal protection path can also be constructed by semiconductor structures in four or more consecutive interconnect layers. In this way, the interconnect signal line can be arranged using the material of the metal layer in the non - top - layer / non - bottom - layer interconnect layer.
[0068] Embodiment 5
[0069] Refer Figure 9 The first shielding layer 121E is a metal layer in the interconnect layer 33E on the chip. The second shielding layer 122E is the substrate isolation well of the chip. The first shielding wall 123E and the second shielding wall 124E are the via fill media 21E in the inner dielectric layer 20E on the chip, as well as the via fill media 311E, 321E and the metal layers 312E, 322E in two interconnect layers 31E and 32E.
[0070] It can be seen that at this time, the signal protection path substantially includes semiconductor structures in the inner dielectric layer 20E and three interconnect layers 31E, 32E, and 33E. In such an embodiment, the interconnect signal line 11E can be arranged using the material of the metal layer 312E in the interconnect layer 31E, the material of the metal layer 322E in the interconnect layer 32E, or the gate layer material.
[0071] In the above Embodiments 1 to 5, except that the second shielding layer in Embodiment 4 is a metal layer, the second shielding layers in other illustrated embodiments are all substrate isolation wells or gate layers. That is, the signal protection path can be constructed with only the metal layer in one interconnect layer. In this way, in some application scenarios with fewer interconnect layers, there is no need to additionally set more metal layers for constructing the signal protection path, and the process cost is relatively low.
[0072] Refer again to Figure 3 and Figure 4, in an embodiment where the substrate isolation well serves as the second shielding layer 122, the vertical projection of the interconnect signal line 11 on the chip substrate may be located within or not within the shallow trench isolation (STI) that is on the isolation well. Among them, when the vertical projection of the interconnect signal line 11 on the chip substrate is located within the shallow trench isolation on the isolation well (as Figure 3 shown), it may have less leakage and is easy to draw the process layout. It can be understood that in the process structures shown in the above Embodiment 1 to Embodiment 5, the positional relationship between the shallow trench isolation in the isolation well and the interconnect signal line can be optionally referred to Figure 3 or Figure 4 shown according to the needs of different layout designs, and will not be elaborated here.
[0073] Refer Figure 10 , and an embodiment of the addressable test array circuit 200 of the present application will be introduced. In this embodiment, the addressable test array circuit 200 includes test signal lines 21, signal protection paths 22, and switches 23.
[0074] The addressable test array circuit 200 can be used for testing multiple devices under test. Generally, each switch 23 corresponds to one device under test. It should be noted that according to the differences of the devices under test, the number of test ports corresponding to each device under test may also be different. The so-called "each switch 23 corresponds to one device under test" means that this switch 23 only corresponds to controlling the connection to this device under test or a certain port of this device under test.
[0075] Taking the device under test having a gate (G), a source (S), a drain (D), and a well (B) as an example, the gates, sources, and wells of multiple devices under test can be connected to a common pad, and the non-reusable drains are connected to another pad through multiple switches 23. The test array can control whether the switch 23 is connected to the drain of the device under test through a shift register, and at the same time, the test array will only select one device under test for testing.
[0076] In a specific circuit, the output end of the row-column switch circuit is connected to the input end of the device under test. The output signals of the row address decoder and the column address decoder in the addressing circuit are determined. The row address decoder and the column address decoder share the clock signal CK, and the combined signal is transmitted to the switch circuit, thereby determining the on-off of the switch 23 of the device under test at the corresponding position.
[0077] For the circuit for determining the specific row-column switch, a multi-stage transmission gate can be adopted. That is: the output end of the higher-level transmission gate is connected to the input end of the lower-level transmission gate connected thereto, and the output end of the lowest-level transmission gate is connected to the input end of the last device under test, thereby determining the on-off of the switch 23 of the device under test at a specific position.
[0078] The test signal line 21 can be used to measure the current and / or voltage at each port of the device under test (DUT). The multiple switches 23 are respectively connected to the test signal line 21 and the corresponding DUT to control the connection and disconnection between the test signal line 21 and the DUT. For example, to measure the drain current and voltage of the DUT, a corresponding voltage can be applied to the drain of the DUT and the switch 23 connected to its drain can be closed. At this time, the corresponding current and voltage can be measured at a suitable location on the test signal line 21.
[0079] In the embodiments of the addressable test array circuit 200 of this application, the test signal line 21 can be considered as a type of interconnect signal line. That is, in this embodiment, the on-chip low-leakage interconnect signal line system scheme of the above embodiments is essentially applied. The signal protection path 22 prevents leakage current that may be generated by the test signal line 21, thereby ensuring the accuracy of the addressable test array circuit 200 in testing the device under test. In particular, the improvement in test accuracy will be more obvious when the device under test is turned off.
[0080] Coordination Figure 11 The signal protection path 22 includes a first shielding layer 221, a second shielding layer 222, a first shielding wall 223, and a second shielding wall 224. The first shielding layer 221 and the second shielding layer 222 shield the test signal line 21 in the vertical projection direction of the test array circuit 200, and the interconnecting signal line is located between the first shielding layer 221 and the second shielding layer 222; at the same time, the first shielding wall 223 and the second shielding wall 224 are respectively connected to the first shielding layer 221 and the second shielding layer 222, and the test signal line 21 is located between the first shielding wall 223 and the second shielding wall 224.
[0081] Similarly, the components of the signal protection path 22 here are not necessarily required to be completely continuous. For example... Figure 11 In this configuration, the test signal line 21 can be connected to a designated area on the substrate isolation trap via a conductive medium, which may result in a "gap" in the second shielding layer 222; alternatively, the first shielding wall 223 and the second shielding 224 may include via-filled media, and the via-filled media located in the multiple vias may also have corresponding "gaps" in their structure. However, these illustrated "gap" and "gaps" will not cause the signal protection path 22 to fail in its function of preventing leakage current from the test signal line 21.
[0082] In the addressable test array circuit 200 of this application, multiple semiconductor devices, such as field-effect transistors, fabricated on the substrate can also be included. Thus, structurally, the signal protection path 22 here can also be constructed using substrate isolation traps, gate layers, inner dielectric layers on the chip, interconnect layers, via filling dielectrics, etc.
[0083] Overall, the first shielding layer 221 may include a metal layer in the interconnect layer of the test array circuit. The second shielding layer 222 may include a substrate isolation well, a gate layer, or a metal layer in the interconnect layer of the test array circuit. The first shielding wall 223 and the second shielding wall 224 may respectively include via-filled dielectric in the inner dielectric layer of the test array circuit, or include via-filled dielectric in the inner dielectric layer of the test array circuit, and via-filled dielectric and metal layer in the interconnect layer, or include via-filled dielectric and metal layer in two interconnect layers of the test array circuit.
[0084] In specific embodiments, the process structure of the signal protection path 22 can refer to Embodiments 1 to 5 of the low leakage interconnect signal line system described above, and will not be repeated here.
[0085] In this embodiment, the signal protection path 22 can also replicate the voltage on the test signal line 21 through a voltage follower buffer, or the test signal line 21 and the signal protection path 22 can be connected to pads of equal voltage respectively.
[0086] In this embodiment, a MOSFET can be used to construct switch 23. In a conventional MOSFET, ideally, when the gate is not energized, the source signal has difficulty passing through the non-conductive inversion layer to reach the drain region, and there is no conduction between the drain (D) and the source (S). However, if a voltage is applied between the gate and the substrate, the charge in the inversion layer will accumulate in large quantities under the insulating oxide layer below the gate, forming a channel that makes the source and drain conduct, allowing current to be smoothly transferred from the source to the drain. However, due to the commonly used single-gate or double-gate structure, even when no turn-on voltage is applied to the gate, leakage current will accumulate at the edge of the gate, ultimately affecting the measurement results of the device under test.
[0087] Coordination Figure 12 In this embodiment, the gate of the MOS transistor in switch 23 is projected vertically onto its active region in a ring shape (ring gate). That is, the gate edge of the MOS transistor is "eliminated", thereby avoiding the possibility of leakage current accumulation.
[0088] In this embodiment, each switch 23 includes at least two MOSFETs, and these two MOSFETs are configured with a common gate. (See reference...) Figure 10 Taking switch 23 as an example, which includes a first MOSFET 231 and a second MOSFET 232, the second MOSFET 232 is connected to the high-resistance voltage measurement circuit.
[0089] The first MOSFET 231 and the second MOSFET 232 are configured to control the switching of the measurement circuits for the current and voltage of the device under test (DUT), respectively. Correspondingly, the test signal line 21 may include two lines: a drain voltage signal line 211 and a drain sensing signal line 212. The drain of the first MOSFET 231 is connected to the drain voltage signal line 211, and the drain of the second MOSFET 232 is connected to the drain sensing signal line 212. The sources of the first MOSFET 231 and the second MOSFET 232 are connected to the DUT, and the first MOSFET 231 and the second MOSFET 232 are configured with a common gate. Thus, the first MOSFET 231 and the second MOSFET 232 can be simultaneously turned on or off using the same gate voltage-controlled signal, thereby allowing for the measurement of the corresponding port current and voltage of the DUT on the drain voltage signal line 211 and the drain sensing signal line 212, respectively.
[0090] The "high-impedance voltage measurement circuit" mentioned here refers to a measurement circuit whose resistance can be set to extremely high so that the current flowing through it during measurement can approach zero. Since milliampere-level current may flow through switch 23 when it is on, and due to the inherent on-resistance of switch 23, this milliampere-level current will cause significant voltage transfer loss, ultimately leading to errors in the leakage current measurement results. However, by configuring the voltage measurement of the drain induction signal line 212 to be performed in the high-voltage resistance measurement circuit, interference from the resistance of the addressable test array circuit 200 itself can be eliminated. Furthermore, the voltage on the drain voltage signal line 211 does not affect the voltage in the high-impedance voltage measurement circuit. Therefore, the voltage of the device under test can be accurately measured at the voltage measurement terminal of the drain induction signal line 212.
[0091] The high-resistance voltage measurement circuit can be implemented in various ways. For example, a resistor with an extremely high resistance can be connected in series in the circuit, or a high-resistance voltmeter can be directly configured at the voltage measurement terminal of the drain induction signal line 212 for voltage measurement. It can be seen that the "high-resistance voltage measurement circuit" can either have high-resistance characteristics itself, or it can be used in conjunction with an external high-resistance measuring instrument to achieve high-resistance measurement.
[0092] Continue to participate Figure 10 The switch 23 may also include a third MOSFET 233, the drain of which is connected to the signal protection path 22. The sink voltages of the first MOSFET 231, the second MOSFET 232, and the third MOSFET 233 are configured to be equal to the voltage on the signal protection path 22, and the source of the third MOSFET 233 is also connected to the device under test. By applying a voltage-controlled signal to the gate of the third MOSFET 233 to control its turn-on and turn-off, the switch 23 can have a "low leakage current" characteristic.
[0093] Specifically, for switch 23, when a first voltage-controlled signal is applied to the gate of the first MOSFET 231 to turn on the first MOSFET 231 and a third voltage-controlled signal is applied to the gate of the third MOSFET 233 to turn off the third MOSFET 233, the switch 23 is closed; correspondingly, when a first voltage-controlled signal is applied to the gate of the first MOSFET 231 to turn off the first MOSFET 231 and a third voltage-controlled signal is applied to the gate of the third MOSFET 233 to turn off the third MOSFET 233, the switch 23 is open.
[0094] In such a switch 23, possible leakage currents include: ① inherent drain leakage current of the first MOSFET 231 when the switch 23 is open; ② leakage current from the drain to the well of the first MOSFET 231 when the switch 23 is closed.
[0095] Specifically, when switch 23 is open, the inherent drain leakage of the first MOSFET 231 includes: drain-to-well leakage, drain-to-source leakage, and well-to-source leakage. At this time, since the third MOSFET 233 is in the ON state, and the well voltage of the first MOSFET 231 is equal to the voltage on the drain voltage signal line 211, the drain voltage, well voltage, and source voltage of the first MOSFET 231 are pulled to equality, thereby effectively eliminating the inherent source leakage of the first MOSFET 231. Similarly, when switch 23 is closed, the drain-to-well leakage of the first MOSFET 231 is also effectively eliminated because the well voltage of the first MOSFET 231 is pulled to equality with the drain voltage.
[0096] Similarly, the third MOSFET 233 can also have a ring gate configuration, which will not be elaborated here.
[0097] In this embodiment, the test signal line 21 can be connected to the low-leakage active region of the MOSFET in the switch 23, wherein the low-leakage active region is a portion of the active region within the vertical projection of the MOSFET gate onto its active region. When the test signal line 21 is connected to the switch 23, by being aligned with the low-leakage active region of the MOSFET in the switch 23, any possible leakage current at the switch 23 can be further eliminated.
[0098] Specifically, since the first MOSFET 231 and the second MOSFET 232 are used for switching control of the measurement circuits of the current and voltage of the device under test, the drain voltage signal line 211 can be connected to the low-leakage active region of the first MOSFET 231, and the drain sensing signal line 212 can be connected to the low-leakage active region of the second MOSFET.
[0099] It should be noted that, since this involves the field of precision measurement, the "equal" defined in the functional definition of the various embodiments / examples of this application does not take into account the influence of unavoidable factors such as the characteristics of each device in the circuit and circuit transmission losses. Taking "the signal protection path is configured to be equal to the voltage on the test signal line" as an example, the voltage transmission loss on the test signal line is not considered. The actual purpose of this setting is to make the voltage on the signal protection path infinitely close to the actual voltage at the measurement terminal of the device under test. Therefore, in the embodiment of setting a high-impedance voltage measurement circuit, the signal protection path can be more preferably set to replicate the voltage on the voltage sensing signal line with almost no voltage transmission loss.
[0100] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.
Claims
1. An on-chip low-leakage interconnect signal line system, applied on a chip, characterized in that, Includes interconnecting signal lines that can be configured to have equal voltages and signal protection paths, wherein the signal protection paths include: A first shielding layer and a second shielding layer, wherein the first shielding layer and the second shielding layer cover the interconnect signal line in the vertical projection direction of the chip, and the interconnect signal line is located between the first shielding layer and the second shielding layer; A first shielding wall and a second shielding wall are respectively connected to the first shielding layer and the second shielding layer, and the interconnecting signal line is located between the first shielding wall and the second shielding wall. The first shielding layer, the second shielding layer, the first shielding wall, and the second shielding wall are all made of conductive materials and have the same voltage as the interconnecting signal lines.
2. The on-chip low-leakage interconnect signal line system according to claim 1, characterized in that, The first shielding layer includes a metal layer in the interconnect layer on the chip.
3. The on-chip low-leakage interconnect signal line system according to claim 1, characterized in that, The second shielding layer includes the substrate isolation well of the chip or the gate layer of the chip; or, The second shielding layer includes a metal layer in the interconnect layer on the chip.
4. The on-chip low-leakage interconnect signal line system according to claim 1, characterized in that, The first and second shielding walls respectively comprise via-filled dielectrics in the inner dielectric layer of the chip; or, The first and second shielding walls respectively include via-filled dielectric in the inner dielectric layer of the chip, and via-filled dielectric and metal layer in the interconnect layer; or, The first shielding wall and the second shielding wall respectively include the via filling medium and the metal layer in the two interconnect layers on the chip.
5. An addressable test array circuit for testing multiple devices under test, characterized in that, include: Test signal line; A signal protection path, which can be configured to be equal to the voltage on the test signal line; Multiple addressable switches are connected to test signal lines and corresponding devices under test (DUTs). The signal protection path includes: A first shielding layer and a second shielding layer, wherein the first shielding layer and the second shielding layer cover the interconnect signal lines in the vertical projection direction of the addressable test array circuit, and the interconnect signal lines are located between the first shielding layer and the second shielding layer. A first shielding wall and a second shielding wall are respectively connected to the first shielding layer and the second shielding layer, and the interconnecting signal line is located between the first shielding wall and the second shielding wall. The first shielding layer, the second shielding layer, the first shielding wall, and the second shielding wall are all made of conductive materials and have the same voltage as the interconnecting signal lines.
6. The addressable test array circuit according to claim 5, characterized in that, The first shielding layer includes a metal layer in the interconnect layer of the test array circuit.
7. The addressable test array circuit according to claim 5, characterized in that, The second shielding layer includes the substrate isolation well or gate layer of the test array circuit; or, The second shielding layer includes a metal layer in the interconnect layer of the test array circuit.
8. The addressable test array circuit according to claim 5, characterized in that, The first and second shielding walls respectively comprise via-filled dielectric in the inner dielectric layer of the test array circuit; or, The first and second shielding walls respectively include via-filled dielectric in the inner dielectric layer of the test array circuit, and via-filled dielectric and metal layer in the interconnect layer; or, The first and second shielding walls respectively include via-filled dielectric and metal layers in the two interconnect layers of the test array circuit.
9. The addressable test array circuit according to any one of claims 5 to 8, characterized in that, The switch includes a MOS transistor, the gate of which has a ring-shaped vertical projection on its active region.
10. The addressable test array circuit according to claim 9, characterized in that, The MOSFETs include at least two, and the at least two MOSFETs are configured to share a common gate; and / or, The test signal line is connected to the low-leakage active region of the MOS transistor, wherein the low-leakage active region is a portion of the active region within the vertical projection of the gate of the MOS transistor onto its active region.
11. The addressable test array circuit according to any one of claims 5 to 8, characterized in that, The test signal lines include a drain voltage signal line for measuring the current of the device under test, and / or, The test signal lines include drain induction signal lines used to measure the voltage of the device under test.