Voltage reference circuit

Abstract

This application relates to the field of analog integrated circuit technology and discloses a voltage reference circuit suitable for high power supply voltages. The circuit replaces the Zener diode pre-regulation architecture with a voltage-limiting loop biased by a positive temperature coefficient current source. A stable low power supply voltage is generated by forming a negative feedback loop through a high-voltage regulating transistor and a feedback sampling transistor. A reference voltage is generated by subtracting the gate-source voltages of two sets of transistors with different threshold voltages. Furthermore, it incorporates a frequency-band coordinated power supply rejection ratio enhancement module, a pre-charging and automatic loop exit startup acceleration module, and a dual-branch complementary control trimming module. This circuit achieves a comprehensive performance of small area, low power consumption, high power supply rejection ratio, and fast startup.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and in particular to a voltage reference circuit technology suitable for high power supply voltages. Background Technology

[0002] Voltage reference circuits are fundamental modules in analog and mixed-signal integrated circuits. Their output reference voltage directly affects the accuracy and reliability of subsequent circuits such as data converters, power management chips, sensor interfaces, and clock oscillators. In applications such as industrial control, automotive electronics, and power electronics, the system front-end often needs to connect to a power supply bus of tens or even hundreds of volts. For example, in automotive electronic systems, the nominal battery voltage is 12V or 24V, but under conditions such as cold starts or load dumping, the power supply voltage may spike to a level far exceeding the nominal value. In industrial sensor or motor drive interface circuits, the fieldbus voltage typically varies between 24V and 48V. In LED lighting drivers or DC-DC converter control chips, the input power supply voltage may also reach high levels. All of these scenarios require on-chip voltage reference circuits to operate reliably under a wide range of high power supply voltages and to have sufficient suppression capability against power supply voltage fluctuations.

[0003] In traditional reference voltage generation architectures suitable for high supply voltages, the high supply voltage typically needs to be stepped down to a low supply voltage first through a low-precision pre-regulator containing a Zener diode, resistors, and an LDMOS transistor, before the required reference voltage is generated by the subsequent voltage reference circuit. This architecture faces several technical challenges in practical applications. First, the fabrication of the Zener diode requires an additional mask layer, increasing process complexity and manufacturing costs, which is particularly disadvantageous in applications seeking low-cost integration. Second, to maintain low quiescent power consumption under high supply voltage conditions, the pre-regulator must use resistors with extremely high resistance values. Large resistors significantly increase chip area, and the higher the supply voltage, the larger the required resistor becomes, making the trade-off between area and power consumption increasingly difficult to reconcile. Third, the power supply rejection ratio (PSRR) of the reference voltage in traditional architectures is often insufficient in the mid-to-high frequency range, making it difficult to meet the requirements of high-performance analog systems. Fourth, introducing filtering devices to improve the PSRR can easily lead to a decrease in circuit startup speed, creating a constraint in applications with strict power-up time requirements. Fifth, the impact of process deviations on the accuracy of the reference voltage is difficult to eliminate effectively, which places higher demands on the adjustment accuracy and adjustment range. Therefore, there is an urgent need for a new voltage reference circuit technology that can simultaneously meet the performance requirements of small area, low cost, low power consumption, high power supply rejection ratio, fast start-up, and high-precision adjustment under high power supply voltage conditions. Summary of the Invention

[0004] The purpose of this application is to provide a voltage reference circuit to solve the problems mentioned in the background art.

[0005] The voltage reference circuit of this application achieves corresponding technical effects in multiple dimensions, such as high power supply voltage applicability, chip area, manufacturing cost, static power consumption, power supply rejection ratio, startup speed and reference voltage accuracy, through the tight structural coupling and causal relationship between the modules. The following describes the specific technical means of each module and their cooperative cooperation.

[0006] At the overall architecture level, this application employs a voltage-limiting loop based on a positive temperature coefficient current source module (100) bias to replace the traditional pre-regulator architecture that relies on Zener diodes and high-voltage, large resistors. In this voltage-limiting loop, the source of the high-voltage regulating transistor MP5 is connected to the high power supply voltage input terminal VIN, its gate is controlled by the control node D, and its drain outputs a low power supply voltage node VL. The gate of the feedback sampling transistor MN0 is connected to this low power supply voltage node VL. The resulting negative feedback loop can maintain VL at a stable low voltage level even under fluctuations in the high power supply voltage VIN. Since this architecture fundamentally eliminates the additional mask layer required by the Zener diode and avoids the significant occupation of chip area by high-voltage, large resistors, it helps to reduce process complexity and manufacturing costs, and also helps to reduce chip area. Furthermore, since most of the voltage difference between the high supply voltage VIN and the low supply voltage VL is borne only by the high-voltage regulating transistor MP5, the feedback sampling transistor MN0, and the high-voltage isolation transistor MN7, all the low-voltage devices in the subsequent stage operate within the VL power supply domain and do not directly bear the high supply voltage. This allows the withstand voltage capability to be improved simply by changing the withstand voltage rating of the aforementioned high-voltage devices or stacking multiple high-voltage devices when changing the applicable high supply voltage range, without having to modify any circuit topology in the low-voltage domain. This provides better flexibility and portability for circuit design.

[0007] Regarding the internal structure of the positive temperature coefficient current source module (100), the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected together. The source of MP1 is connected to the high power supply voltage input terminal VIN through the first resistor R1, and the source of MP2 is directly connected to VIN. The voltage difference between their sources is the voltage drop across R1, thereby determining the first current IPTAT with positive temperature coefficient characteristics. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 form a common source and common gate structure with MP1 and MP2, which is beneficial to improving the output impedance and mirror accuracy of the current mirror and suppressing the influence of channel length modulation effect on the matching accuracy of the current branch. The connection method in which the gate of the third PMOS transistor MP3 is connected to the node where the drain of the feedback sampling transistor MN0 is located, the drain of the feedback sampling transistor MN0 is connected to the drain of MP3 through the second resistor R2, and the source of MN0 is connected to the first node B through the third resistor R3, enables the feedback signal of the voltage limiting loop to be transmitted to the control node D with high accuracy, which is beneficial to improving the adjustment accuracy of the voltage limiting loop. The compensation capacitor Cc is connected at one end to the drain of the second PMOS transistor MP2 and at the other end to the low power supply voltage node VL, forming an Ahuja compensation structure. This structure helps to achieve frequency separation between the main pole and the secondary pole of the voltage limiting loop, thereby obtaining sufficient phase margin at the open-loop gain crossing point to ensure loop stability.

[0008] In the core voltage reference module, the first group of transistors MN1, MN2, and MN3 are type 1 NMOS transistors connected in series as diodes and operate in the saturation region. The second group of transistors MN4, MN5, and MN6 are type 2 NMOS transistors with threshold voltages significantly lower than those of the type 1 transistors and operate in the subthreshold region. The reference voltage VREF is obtained by subtracting the sum of the gate-source voltages of the second group of transistors from the sum of the gate-source voltages of the first group of transistors. This gate-source voltage subtraction method, compared to directly superimposing the gate-source voltages, utilizes the correlation of threshold voltage deviations of transistors of the same type on the same chip, allowing the threshold voltage fluctuations of the two groups of transistors to cancel each other out during the subtraction operation. This helps reduce the impact of process corner variations on the accuracy of the reference voltage and improves the process robustness of the circuit. Furthermore, the channel length of the type 1 NMOS transistors is greater than that of the type 2 NMOS transistors, which helps reduce the influence of channel length modulation effects and thus improves the power supply rejection ratio of the output voltage. The gates of the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12 in the current bias module (110) are all connected to the mirror bias node C, forming a current mirror structure with the third NMOS transistor MN3 to provide bias current to MN4, MN5, and MN6 respectively. Since the bias current and the first current IPTAT maintain a mirror ratio relationship, the positive temperature coefficient current source module (100) and the voltage reference core module form a main chain of "same source bias - low voltage domain power supply - core output", which allows the temperature coefficient of the reference voltage to be optimized by adjusting the relevant device parameters.

[0009] Regarding the power supply rejection ratio enhancement module (130), the stacked transistor MN13 is connected between the low power supply voltage node VL and the drain power supply path of the sixth NMOS transistor MN6. Its gate is connected to the first node B through the first filter resistor Rp1 and operates in the saturation region. In a common-gate isolation manner, a high-impedance isolation stage is added to the signal transmission path between the VL node and the reference core circuit, which is beneficial to enhance the power supply rejection ratio in the low-frequency band and reduce linear sensitivity. The first-stage low-pass filter composed of the first filter resistor Rp1 and the first filter capacitor Cp1 is inserted into the gate bias line of the second group of transistors MN4 to MN6. The second-stage low-pass filter composed of the second filter resistor Rp2 and the second filter capacitor Cp2 is inserted into the gate bias line of the bias transistors MN10 to MN12 in the current bias module (110). The two together filter out noise and voltage fluctuations in the intermediate frequency and high frequency bands, which is beneficial to improve the power supply rejection ratio in the intermediate and high frequency bands. An isolation transistor M0, connected in series with a diode between the startup capacitor Cs1 and ground, is in a conducting state during startup due to current flow, ensuring that the startup capacitor Cs1 performs its coupling startup function normally. During steady-state startup, it automatically switches to a turning-off state because the current is essentially zero, effectively isolating the path between the startup capacitor Cs1 and ground. This eliminates the adverse effects of the startup capacitor on the voltage limiting loop bandwidth and the mid-frequency power rejection ratio. These three sub-modules are responsible for eliminating the side effects of the low-frequency, mid-to-high-frequency, and startup capacitor bands, respectively, in the frequency domain. Their coordinated operation across frequency bands contributes to improving the power rejection ratio across the entire frequency band.

[0010] However, the introduction of the aforementioned low-pass filter submodule objectively leads to a decrease in startup speed. The filter capacitors Cp1 and Cp2 need to undergo a charging process from zero voltage to near steady-state voltage during startup, while the series-connected filter resistors Rp1 and Rp2 limit the charging current, thus extending the charging time. To address this technical contradiction introduced by the power supply rejection ratio enhancement module's own structure, the startup acceleration module (140) uses a voltage coupling submodule where one end of the coupling capacitor Cs2 is connected to the low power supply voltage node VL and the other end to the internal node E. During startup, the rising change in VL is coupled to the internal node E to activate transistors M2 and M3 to M5 in the pre-charging submodule. This establishes a fast charging path between the low power supply voltage node VL and the filter capacitors Cp1 and Cp2, bypassing the current-limiting effect of the filter resistors Rp1 and Rp2, allowing the filter capacitors to quickly charge to near steady-state voltage levels, thereby accelerating the establishment of the reference voltage. In this circuit, the gates of the second transistor M2 and the third transistor M3 are both connected to the internal node E, and their drains are both connected to the low power supply voltage node VL. The source of M2 is connected to the non-grounded terminal of the first filter capacitor Cp1, and the source of M3 is connected to the non-grounded terminal of the second filter capacitor Cp2 via the fourth transistor M4 and the fifth transistor M5, which are connected in a diode configuration. This connection method allows the pre-charge current to quickly charge the two filter capacitors respectively. It is worth noting that the pre-charge current generated by the pre-charge sub-module that is turned on during the startup phase also acts as an additional load for the low power supply voltage node VL, which helps to accelerate the voltage stabilization process of the VL node in the voltage limiting loop. This reflects the bidirectional coupling relationship between the startup acceleration module (140) and the voltage limiting loop. The gate of the discharge transistor M1 is connected to the mirror bias node C. After the working state of the voltage reference core module is basically established, the voltage of the mirror bias node C reaches a level sufficient to turn on M1. After M1 is turned on, the voltage of the internal node E is pulled down through the discharge resistor Rs, causing the pre-charge transistors M2 to M5 to turn off, and the startup acceleration module automatically exits operation. The bleeder resistor Rs provides a continuous bleeder path for the internal node E during startup and transition, which helps prevent the internal node E from being in an uncertain voltage state due to floating. After the startup acceleration module exits operation, the transistors in the precharge submodule are in a completely off state, without introducing additional quiescent current or parasitic disturbances. This "precharge-automatic exit" closed-loop design helps to balance the requirements of fast startup and low power consumption without sacrificing power supply rejection ratio performance.

[0011] In terms of overvoltage protection, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are both connected in series with diodes to form a series clamping branch between the high power supply voltage input terminal VIN and the control node D. When the drain-source voltage difference exceeds the threshold voltage under abnormal conditions, it will automatically turn on to provide clamping protection, which helps to prevent the internal low-voltage devices from being damaged by overvoltage. As a protection measure in addition to the voltage limiting loop, it further enhances the reliability of the circuit in the high power supply voltage environment.

[0012] In the tuning module (210), the first part of the resistor array (211) is connected in series between the source of the third NMOS transistor MN3 and ground, and the second part of the resistor is connected in series between the source of the ninth NMOS transistor MN9 and ground. The logic circuit (212) receives the tuning control signal and generates a selection signal and its inverted selection signal to control the switching transistor connected across the first part of the resistor and the second part of the resistor in a complementary manner, thereby adjusting the source voltage difference of MN3 and MN9 to finely adjust the magnitude of the first current IPTAT, and finally indirectly achieve fine tuning of the reference voltage VREF. The first part of the resistor includes a normally connected unit resistor that is not controlled by the switching transistor and a first controlled resistor group divided into n groups according to binary weight. The second part of the resistor includes a second controlled resistor group that is also divided into n groups according to binary weight. For the first controlled resistor group and the second controlled resistor group with the same weight, their corresponding switching transistors are driven by complementary control signals, so that when a controlled resistor group on one side is short-circuited by a switching transistor that is turned on, the controlled resistor group with the same weight on the other side is connected in series to the circuit. Compared to a scheme that adjusts the resistor only on one side, this dual-sided complementary adjustment method is advantageous for obtaining a larger adjustment range under the same number of adjustment control signals, and the uniformity and linearity of the current change generated by each adjustment step are better. Since the adjustment module (210) is located in the low-voltage domain powered by the low power supply voltage node VL, the power supply voltage of its logic circuit (212) is taken from the low power supply voltage VL, so there is no additional high-voltage device area overhead, which is consistent with the overall architecture design of the voltage limiting loop providing the low-voltage domain operating environment.

[0013] In summary, the modules in the voltage reference circuit of this application are not simply functionally superimposed. The voltage limiting loop provides a low-voltage operating environment globally and forms a common bias relationship with the positive temperature coefficient current source module. While the power supply rejection ratio (PSRR) enhancement module improves the full-band PSRR, it objectively introduces a technical contradiction of reduced startup speed. The startup acceleration module specifically resolves this contradiction with a "pre-charge-automatic exit" closed-loop structure and forms a bidirectional coupling with the voltage limiting loop. The isolation transistor MOSFET eliminates the side effects of the startup capacitor on the mid-frequency PSRR. The tuning module achieves fine tuning of the reference voltage in the low-voltage domain. The tight structural coupling and causal relationship between the above modules enable the voltage reference circuit of this application to achieve corresponding comprehensive technical effects in terms of high power supply voltage applicability, chip area, manufacturing cost, static power consumption, PSRR, startup speed, and reference voltage accuracy.

[0014] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a traditional reference voltage generation circuit suitable for high power supply voltages.

[0016] Figure 2 This is an overall circuit diagram of a voltage reference circuit suitable for high power supply voltage according to an embodiment of this application.

[0017] Figure 3 This is a schematic diagram of the internal circuit structure of the startup acceleration module (140) according to an embodiment of this application.

[0018] Figure 4 This is a schematic diagram of the connection relationship of the voltage reference circuit adjustment scheme (200) according to an embodiment of this application.

[0019] Figure 5 This is a schematic diagram of the specific circuit structure of the adjustment module (210) according to an embodiment of this application. Detailed Implementation

[0020] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0021] Explanation of some concepts: The "positive temperature coefficient current" (PTAT current) mentioned in this application refers to a current whose amplitude increases proportionally with the increase of absolute temperature, where PTAT is an abbreviation for "Proportional To Absolute Temperature".

[0022] The "thermal voltage" VT mentioned in this application refers to a physical quantity equal to kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.

[0023] The term "Native MOS device" as used in this application refers to an NMOS device with a near-zero threshold voltage, also known as a natural threshold MOS transistor or natural threshold MOS transistor, whose threshold voltage is significantly lower than that of a conventional NMOS device. Those skilled in the art will understand that any MOS transistor with a threshold voltage significantly lower than that of the first group of transistors can achieve a similar effect. In specific embodiments of this application, the typical threshold voltage of the second type of NMOS transistor (Native MOS device) is in the range of -100mV to +200mV, while the typical threshold voltage of the first type of NMOS transistor (conventional NMOS device) is in the range of 400mV to 700mV. The threshold voltage difference ΔVth (=Vth1-Vth2) between the two is typically on the order of 300mV to 700mV, and this difference constitutes an important component of the reference voltage VREF. Those skilled in the art will understand that the above numerical ranges are exemplary, and the specific values ​​depend on the process node and device parameters used.

[0024] The "diode connection method" mentioned in this application refers to the connection method in which the gate and drain of a MOS transistor are connected, making the transistor equivalent to a two-terminal device.

[0025] The “subthreshold region” mentioned in this application refers to the operating region of a MOS transistor where the gate-source voltage is lower than its threshold voltage but a weak drain current still flows through it, and the drain current in this region is exponentially related to the gate-source voltage.

[0026] The term "Power Supply Rejection Ratio" (PSRR) used in this application is an abbreviation for Power Supply Rejection Ratio, which characterizes the ability of a circuit's output voltage to suppress power supply voltage fluctuations. The higher the value, the less the output voltage is affected by power supply fluctuations.

[0027] The “linear sensitivity” mentioned in this application refers to the sensitivity of the reference voltage output to changes in the power supply voltage, which is usually characterized by the ratio of the change in reference voltage to the change in power supply voltage.

[0028] The "common source and common gate structure" described in this application refers to a connection method in which two MOS transistors of the same type are stacked in series in the current direction to improve the output impedance and mirroring accuracy of the current mirror.

[0029] The “Ahuja compensation” mentioned in this application refers to a technique that uses a common source cascode node to introduce a compensation capacitor to achieve Miller effect-enhanced frequency compensation, which can effectively separate the frequency of the loop’s dominant pole and secondary pole.

[0030] The "high voltage device" mentioned in this application includes, but is not limited to, LDMOS (laterally diffused metal-oxide-semiconductor transistor) or high voltage PMOS and high voltage NMOS devices, referring to MOS transistors whose rated withstand voltage level is higher than that of conventional devices in the low voltage range.

[0031] The PLDMOS described in this application refers to a laterally diffused P-type metal-oxide-semiconductor transistor, which is a type of high-voltage PMOS device.

[0032] The following is a brief summary of some of the innovative aspects of this application: In general, in the traditional reference voltage generation architecture suitable for high supply voltages, the high supply voltage VIN needs to be stepped down to the low supply voltage VINL by a low-precision pre-regulator (000) containing a Zener diode, resistors and LDMOS, and then the reference voltage VREF is generated by the subsequent voltage reference circuit. However, the Zener diode inherently requires an additional mask layer, which increases the process complexity and manufacturing cost. Under high supply voltage conditions, the extremely large resistance value that must be used to maintain low static power consumption will inevitably increase the chip area significantly. Moreover, the higher the supply voltage, the more difficult it is to reconcile the contradiction between area and power consumption. The voltage reference circuit of this application fundamentally abandons the pre-regulation architecture of Zener diode and high voltage large resistor, and instead replaces it with a voltage limiting loop based on the bias of a positive temperature coefficient current source module (100). In this voltage limiting loop, the source of the high voltage regulating transistor MP5 is connected to the high power supply voltage input terminal VIN, and its gate is controlled by the control node D defined by the drain of the fourth PMOS transistor MP4. Its drain outputs the low power supply voltage node VL, and the gate of the feedback sampling transistor MN0 is connected to this low power supply voltage node VL. The resulting negative feedback loop ensures that no matter how the high power supply voltage VIN fluctuates, the low voltage... The source voltage VL is maintained at a stable low voltage level, so that all subsequent circuit modules, such as the voltage reference core module, current bias module (110), power supply rejection ratio enhancement module (130), and adjustment module (210), can operate safely in this low voltage domain. Most of the voltage difference between the high power supply voltage VIN and the low power supply voltage VL is borne only by the high voltage regulating transistor MP5, the feedback sampling transistor MN0, and the high voltage isolation transistor MN7. This structural isolation mechanism means that when adapting to different power supply voltage ranges, only the withstand voltage level of the above high voltage devices needs to be changed without changing any circuit topology in the low voltage domain.

[0033] Based on the low-voltage domain established by the voltage limiting loop, the voltage reference core module of this application constructs a reference voltage generation structure using two sets of transistors with significantly different threshold voltages—the first set of transistors MN1, MN2, and MN3 are first-type NMOS transistors connected in series in a diode configuration and operating in the saturation region; the second set of transistors MN4, MN5, and MN6 are second-type NMOS transistors with threshold voltages significantly lower than the first type and operating in the subthreshold region—which constitutes a "gate-source voltage addition and subtraction" reference voltage generation structure. The reference voltage VREF is obtained by subtracting the sum of the three gate-source voltages of the three transistors in the second set from the sum of the three gate-source voltages of the first set of transistors. This subtraction method has a significant technical advantage over directly superimposing the gate-source voltages: because similar transistors on the same chip... The threshold voltage deviation of the transistors is highly correlated. The threshold voltage fluctuations between the two sets of transistors can be canceled out in the subtraction operation, thereby significantly reducing the impact of process angle changes on the accuracy of the reference voltage. The bias current required by the reference core module is the first current IPTAT of the positive temperature coefficient current source module (100) in the voltage limiting loop, which is mirrored by the bias transistors MN10, MN11, and MN12 in the current bias module (110) that form a current mirror structure with the third NMOS transistor MN3. The bias reference of the positive temperature coefficient current source module (100) and the control branch of the voltage limiting loop share the same current mirror relationship, so that the voltage limiting loop and the reference core form a main chain of "same source bias - low voltage domain power supply - core output". The two are structurally inseparable coupled together.

[0034] However, it is worth noting that the relationship between the modules in this application is not a simple functional superposition, but a causal chain of "the invention itself introducing technical contradictions, which are then resolved by its own supporting structure". Specifically, in order to improve the power supply rejection ratio across the entire frequency band, the power supply rejection ratio enhancement module (130) is designed to include three sub-modules that work together in different frequency bands: the stacked transistor MN13 is connected between the drain power supply path of the low power supply voltage node VL and the second group of transistors MN6, and its gate is connected to the first node B through the first filter resistor Rp1, so as to enhance the power supply rejection ratio in the low frequency band in a common gate isolation manner; the first-stage low-pass filter composed of the first filter resistor Rp1 and the first filter capacitor Cp1 and the second-stage low-pass filter composed of the second filter resistor Rp2 and the second filter capacitor Cp2 are respectively inserted into the gate bias lines of the second group of transistors MN4 to MN6 and the gate bias lines of the bias transistors MN10 to MN12 in the current bias module (110) to filter out mid-to-high frequency noise and voltage fluctuations. However, the introduction of the aforementioned low-pass filter submodule objectively leads to a new technical contradiction—during the circuit startup process, the filter capacitors Cp1 and Cp2 must first undergo a charging process from zero voltage to near steady-state voltage, while the series-connected filter resistors Rp1 and Rp2 strictly limit the charging current flowing to these two capacitors, thereby significantly extending the charging time and slowing down the startup speed of the entire circuit. To resolve the inherent contradiction introduced by the power supply rejection ratio enhancement module itself, this application specifically designs a startup acceleration module (140). One end of the coupling capacitor Cs2 of the voltage coupling submodule is connected to the low power supply voltage node VL, and the other end is connected to the internal node E. During startup, the rising change of the low power supply voltage node VL is coupled to the internal node E to turn on the transistors M2 and M3 to M5 in the pre-charge submodule. This establishes a fast charging path between the low power supply voltage node VL and the filter capacitors Cp1 and Cp2, bypassing the current limiting effect of the filter resistors Rp1 and Rp2, allowing the filter capacitors to be quickly charged to near the steady-state voltage level. At the same time, the pre-charge current also acts as an additional load for the low power supply voltage node VL, thereby helping to accelerate the stabilization process of the VL node in the voltage limiting loop. This characteristic reflects the bidirectional coupling relationship between the startup acceleration module (140) and the voltage limiting loop: on the one hand, the rise of VL drives the startup acceleration module to turn on through the coupling capacitor Cs2, and on the other hand, the pre-charge current of the startup acceleration module, in turn, acts as a load for the VL node to help VL stabilize faster.Once the core module of the voltage reference is in operation, the voltage of the mirror bias node C reaches a level sufficient to turn on the discharge transistor M1 in the voltage discharge submodule. After M1 is turned on, the voltage of the internal node E is pulled down through the discharge resistor Rs, causing the precharge transistors M2 to M5 to turn off immediately. The acceleration module automatically exits operation without introducing any additional static current or parasitic disturbances, forming a complete closed-loop structure of "precharge-automatic exit".

[0035] Meanwhile, after the startup capacitor Cs1 in the startup circuit (120) completes the startup task of turning on the high-voltage regulating tube MP5 by capacitively pulling down the voltage of the control node D during the power-on process, if it continues to be directly connected in the circuit, its presence will reduce the effective bandwidth of the voltage limiting loop and thus affect the power supply rejection ratio performance in the intermediate frequency band. This constitutes another set of coupling constraints between modules. For this reason, the isolation transistor M0 in the startup capacitor isolation submodule of the power supply rejection ratio enhancement module (130) is connected in series between the startup capacitor Cs1 and ground. During the startup phase, M0 is in the conducting state so that the startup capacitor Cs1 can normally perform the coupling startup function. During the steady state phase, the current flowing through this branch is basically zero, causing M0 to automatically turn to the off state, thereby effectively isolating the path between the startup capacitor Cs1 and ground, eliminating the adverse effects of the startup capacitor on the voltage limiting loop bandwidth and the intermediate frequency power supply rejection ratio. Thus, the stacked transistor MN13 is responsible for the low-frequency band, the low-pass filters Rp1 / Cp1 and Rp2 / Cp2 are responsible for the mid-to-high frequency band, and the isolation transistor M0 eliminates the side effects of the startup capacitor on the mid-frequency band. The three work together in the frequency domain and are structurally inseparable to achieve a significant improvement in the full-band power supply rejection ratio.

[0036] In summary, the technical solution of this application is not a simple physical combination of independent functional modules. Instead, based on the core architecture of the voltage limiting loop providing a low-voltage domain working environment, the working foundation of the reference core is established through the same bias relationship between the positive temperature coefficient current source module (100) and the voltage limiting loop. The power supply rejection ratio enhancement module (130) introduces the problem of reduced startup speed while improving the full-band power supply rejection ratio, which directly leads to the "pre-charge - automatic exit" closed-loop design of the startup acceleration module (140). Furthermore, the startup capacitor isolator is used to... The isolation transistor M0 of the module eliminates the side effect of the startup capacitor Cs1 on the bandwidth of the voltage limiting loop, while the tuning module (210) uses a dual-branch complementary control resistor array (211) structure to finely tune the positive temperature coefficient current IPTAT in the low power supply voltage VL domain, thereby indirectly finely tuning the reference voltage VREF. The tight structural coupling and causal relationship between the above modules make the voltage reference circuit of this application constitute an indivisible structural synergy chain, and its overall technical effect cannot be expected or achieved by the arithmetic superposition of the effects of individual modules.

[0037] More specifically, through long-term in-depth research, the inventors of this application discovered that the technical difficulties faced by traditional reference voltage generation architectures suitable for high power supply voltages are not isolated but rather intrinsically related and mutually restrictive. After a thorough analysis of the principles of existing pre-regulator architectures, the inventors realized that the reason Zener diodes and high-voltage resistors are indispensable in traditional architectures lies in the need for a coarse conversion stage from high to low power supply voltage to protect downstream low-voltage devices. However, this conversion method essentially trades off additional process layers and chip area for voltage isolation—Zener diodes require specialized mask layers to form specific breakdown characteristics, and the large-value resistors required to control the quiescent current of the Zener branch under high power supply voltage conditions experience a dramatic increase in area as power supply voltage and power consumption constraints tighten. The inventors realized that if a method could be used to achieve and maintain the stability of the conversion from high to low power supply voltage without relying on Zener diodes and high-voltage resistors, the aforementioned process complexity and area costs could be fundamentally avoided.

[0038] Further research into the reference voltage generation mechanism revealed that in voltage reference circuits using only MOS transistors, threshold voltage fluctuations caused by process variations are a significant factor affecting the accuracy of the reference voltage. Through repeated analysis and theoretical derivation, the inventors realized that if two sets of transistors with significantly different threshold voltages are used, and the reference voltage is generated by subtracting the gate-source voltages rather than directly superimposing them, the correlation of threshold voltage deviations of similar transistors on the same chip can be utilized to cancel out the fluctuations during the subtraction operation. This provides an effective way to improve the process robustness of the reference voltage.

[0039] While researching the improvement of power supply rejection ratio (PSRR), the inventors discovered a deeper set of technical contradictions. To effectively improve PSRR across the entire frequency band, targeted measures are needed for different frequency bands—in the low-frequency band, the impedance isolation of the signal transmission path needs to be improved, while in the mid-to-high frequency band, low-pass filters need to be installed in the bias circuit to filter out voltage fluctuations and noise. However, the inventors noticed that the filter capacitor in the low-pass filter must undergo a charging process from zero voltage to near steady-state voltage during circuit startup, and the series-connected filter resistor strictly limits the charging current flowing to the capacitor, directly leading to a significant decrease in startup speed. In other words, there is an inherent conflict between improving PSRR and startup speed, introduced by the circuit structure itself, a contradiction that has not yet been effectively resolved in the prior art. The inventors further realized that if the startup capacitor introduced for the startup loop continues to be directly connected in the circuit after completing its startup task, its equivalent capacitance will reduce the effective bandwidth of the voltage-limiting loop, thus affecting the PSRR performance in the mid-frequency band. This constitutes another set of coupling constraints between startup function and steady-state performance.

[0040] Based on the above in-depth research, the inventors of this application propose an innovative voltage reference circuit technology. This solution uses a voltage-limiting loop based on a positive temperature coefficient current source bias as its core architecture to achieve isolation between high and low voltage domains. A reference voltage is generated by subtracting the gate-source voltages of two sets of transistors with different threshold voltages. The aforementioned technical problems are addressed collaboratively through interconnected modules such as a frequency-band coordinated power supply rejection ratio enhancement module, a startup acceleration module with a "pre-charge-automatic exit" closed-loop structure, a startup capacitor isolation mechanism, and a dual-branch complementary control and adjustment module operating in the low-voltage domain. The implementation process of this application is described in detail below through specific embodiments.

[0041] Figure 1 An architecture for a conventional reference voltage generation circuit suitable for high supply voltages is shown. For example... Figure 1 As shown, in the traditional scheme, the high supply voltage VIN obtains the low supply voltage VINL required by the voltage reference circuit through a low-precision pre-regulator 000 composed of a Zener diode, resistors, and an LDMOS, and then the subsequent voltage reference circuit generates the reference voltage VREF. However, the Zener diode requires an additional mask layer, leading to increased process complexity and manufacturing cost; at the same time, to maintain low static power consumption at high supply voltages, extremely large resistors are required, which significantly increases the chip area. The higher the supply voltage, the larger the required resistor, and the more prominent the contradiction between area and power consumption becomes.

[0042] To address the aforementioned problems, this application proposes a voltage reference circuit, the overall architecture of which is as follows: Figure 2 As shown, this voltage reference circuit completely abandons Zener diodes and high-voltage, high-resistance circuits, instead employing a voltage-limiting loop based on a positive temperature coefficient (PTAT) current source bias. It directly generates and stabilizes a low supply voltage VL under a high supply voltage VIN, ensuring safe operation of all subsequent circuit modules within the low-voltage domain. Based on this low-voltage domain, a voltage reference core is constructed using two sets of transistors with different threshold voltages, employing a "gate-source voltage addition and subtraction" mechanism to generate a temperature coefficient-optimized reference voltage VREF. Furthermore, to improve the full-band power supply rejection ratio (PSRR), a power supply rejection ratio enhancement module operating in a frequency band is implemented; to address the startup speed reduction introduced by the low-pass filter in this enhancement module, a startup acceleration module is specifically designed; and to further improve the accuracy of the reference voltage, a trimming module operating in the low-voltage domain is included. These modules are tightly coupled and causally related, forming an inseparable structural collaborative chain.

[0043] Specifically, referring to Figure 2The voltage reference circuit in this embodiment includes a positive temperature coefficient current source module 100, a current bias module 110, a startup circuit 120, a power supply rejection ratio enhancement module 130, and a startup acceleration module 140 (the specific internal structure of which is as follows). Figure 3 As shown), it includes an overvoltage protection module 150, a voltage reference core module, a voltage limiting loop module, and a loop compensation module. Additionally, it includes, for example,... Figure 4 and Figure 5 The adjustment module 210 and its corresponding adjustment scheme 200 are shown below. The specific structure, connection relationship, working principle and cooperation between modules are described in detail below with reference to the attached drawings.

[0044] For ease of subsequent description, the main nodes and signals involved in the circuit are defined uniformly. VIN represents the high power supply voltage input terminal; VL represents the low power supply voltage node at the output of the voltage limiting loop; VREF represents the output reference voltage of the voltage reference circuit; IPTAT represents the positive temperature coefficient current; Node A is located at the source of transistor MN0; Node B is located at the drain of transistor MN1, i.e., the first node; Node C is located at the drain of transistor MN3, i.e., the mirror bias node; Node D is located at the drain of transistor MP4, i.e., the control node, and also the gate control node of the high-voltage regulating transistor MP5 in the voltage limiting loop; Node E is located at the connection point between the internal coupling capacitor Cs2 of the startup acceleration module 140 and the gate of transistor M2, i.e., the internal node. The above node definitions remain consistent throughout the text.

[0045] The following describes the positive temperature coefficient current source module.

[0046] Reference Figure 2 The positive temperature coefficient current source module 100 includes a first current branch and a second current branch. Specifically, the module includes a first resistor R1, a second resistor R2, a third resistor R3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, NMOS transistors MN0 to MN3, and NMOS transistors MN7 to MN9, for generating a first current IPTAT with a positive temperature coefficient.

[0047] The operating principle of this current source utilizes the source voltage difference of the PMOS transistors in the two branches and the size ratio difference of the NMOS transistors. More specifically, the gate voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are equal, and their gates are connected together. The source of MP1 is connected to the high power supply voltage input terminal VIN through the first resistor R1, and the source of MP2 is directly connected to the high power supply voltage input terminal VIN. Since the gate potentials of MP1 and MP2 are the same, the source voltage difference between them is the voltage drop across the first resistor R1. The ratio of this voltage drop to the resistance of the first resistor R1 determines the basic magnitude of the first current IPTAT, and is related to the size ratio of MP1 and MP2, giving the first current IPTAT a positive temperature coefficient characteristic.

[0048] Furthermore, the positive temperature coefficient current source module 100 also includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The gates of MP3 and MP4 are interconnected and form a common-source, common-gate structure with MP1 and MP2 to improve the output impedance and mirroring accuracy of the current mirror. Specifically, the drain of MP1 is connected to the source of MP3, and the drain of MP2 is connected to the source of MP4. The drain of MP3 is connected to the gate of MP3 and the drain of MN0 through a second resistor R2. The drain of MP4 is the control node D. This common-source, common-gate structure effectively suppresses the influence of channel length modulation effect on the matching accuracy of the current mirror, enabling the two current branches to maintain the set current ratio relationship with higher accuracy.

[0049] In the first current branch, the gate of the feedback sampling transistor MN0 is connected to the low power supply voltage node VL, and the source of MN0 is node A. A third resistor R3 is connected between node A and the drain of the first NMOS transistor MN1 (i.e., the first node B). The first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 are connected in series between the first node B and GND. MN1, MN2, and MN3 are all diode-connected, meaning their drains and gates are connected. The drain and gate of MN3 are both connected to the mirror bias node C (MN3 is diode-connected, with its drain and gate shorted). In the basic configuration without the adjustment module connected, the source of MN3 is connected to ground. The third resistor R3 is connected in series between node A and the first node B to help determine the operating point of the feedback sampling transistor MN0.

[0050] In the second current branch, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9 are connected in series. The gates of MN7, MN8, and MN9 are connected to the gates of MN1, MN2, and MN3 in the first current branch, respectively, forming a current mirror relationship with MN1, MN2, and MN3 in the first current branch. The seventh NMOS transistor MN7 is a high-voltage NLDMOS, and its drain is connected to the control node D, used to isolate MN8 and MN9, which are implemented with low-voltage NMOS, from the high voltage.

[0051] In the basic configuration without the adjustment module connected, the source of MN9 is connected to ground. When the adjustment module is connected, the adjustment module 210 is located between the source of MN3, the source of MN9, and GND. Its specific structure will be described in detail later.

[0052] The PTAT current generated by the positive temperature coefficient current source module can be expressed as: Formula 1 In Formula 1, VT is the thermal voltage, which is equal to kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge; R1 is the resistance of the first resistor R1; Kp1 is the width-to-length ratio (W / L) of the first PMOS transistor MP1, Kp2 is the width-to-length ratio of the second PMOS transistor MP2, Kn9 is the width-to-length ratio of the ninth NMOS transistor MN9, and K1 is the width-to-length ratio of the third NMOS transistor MN3; K is a comprehensive constant related to the width-to-length ratios of the above transistors. Since the thermal voltage VT is proportional to the absolute temperature T, IPTAT has a positive temperature coefficient characteristic.

[0053] It should be noted that in the above PTAT current generation mechanism, the NMOS transistors (MN1 to MN3) in the first current branch are connected in series using a diode connection, and the NMOS transistors (MN7 to MN9) in the second current branch are also connected in series accordingly. This causes the source voltage of each transistor in both branches to increase progressively, resulting in different substrate-source voltages (VBS) for each transistor. The body effect leads to differences in the threshold voltages of each stage of the transistors. However, since the transistors at corresponding positions in the two current branches bear the same substrate-source voltage, the body effect has a symmetrical impact on the two branches and does not affect the magnitude of the PTAT current. The expression in Equation 1 remains consistent whether the body effect is considered or not.

[0054] It should be noted that IPTAT plays at least two coupling roles in this circuit: First, as the bias source of the voltage reference core module, it drives the transistors in the first current branch to generate superimposed voltage; Second, it shares the bias reference with the control branch of the voltage limiting loop through the current mirror, so that the voltage limiting loop and the reference core form a main chain of "same source bias - low voltage domain power supply - core output", and the two are structurally inseparable.

[0055] The current bias module is described below.

[0056] Reference Figure 2 The current bias module 110 includes a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12, whose gates are interconnected, forming a bias branch to provide bias current to the second group of transistors in the voltage reference core module. MN10, MN11, and MN12, together with the third NMOS transistor MN3 in the positive temperature coefficient current source module, form a current mirror structure, with the gates of all three connected to the mirror bias node C. The magnitude of each bias current IBIAS is determined by the current mirror ratio, which can be expressed as: Formula 2 In Formula 2, β is the ratio of the width-to-length ratio of MN10 (or MN11, MN12) to MN3. In this embodiment, MN3, MN10, MN11, and MN12 have the same width-to-length ratio, i.e., β equals 1, therefore the bias current IBIAS equals IPTAT. It should be noted that those skilled in the art can adjust the value of β according to actual needs to obtain different magnitudes of bias current.

[0057] The following describes the core module of the voltage reference.

[0058] Reference Figure 2 The core module of the voltage reference includes two sets of transistors. The first set of transistors includes a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. The second set of transistors includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. The two sets of transistors use different types of MOS devices, and their threshold voltages differ significantly. The resulting threshold voltage difference is an important basis for forming the reference voltage.

[0059] More specifically, the first group of transistors MN1, MN2, and MN3 are all Type I NMOS transistors connected in a diode configuration, meaning the drain and gate of each transistor are connected in series. The drain (and gate) of MN1 is connected to the first node B, and the drain of MN3 is connected to the mirror bias node C. Therefore, the superimposed voltage VB generated at the first node B is equal to the sum of the gate-source voltages of the three transistors. The first group of transistors is biased by the first current branch of the positive temperature coefficient current source module; this current is IPTAT.

[0060] The second group of transistors, MN4, MN5, and MN6, are all type II NMOS transistors, with threshold voltages lower than those of type I NMOS transistors. MN4, MN5, and MN6 are driven by bias currents IBIAS provided by MN10, MN11, and MN12 in the current bias module 110, respectively. In terms of connection, the gates of the transistors in the second group are cascaded sequentially: the gate of the first-stage transistor MN4 is connected to the first node B (i.e., the node where the superimposed voltage VB generated by the first group of transistors is located), the gate of MN5 is connected to the source of MN4, and the gate of the last-stage transistor MN6 is connected to the source of MN5. The source of MN6 outputs a reference voltage VREF. Thus, the reference voltage VREF is obtained by subtracting the sum of the gate-source voltages of the second group of transistors from the sum of the gate-source voltages of the first group of transistors. Formula 3 In Formula 3, VGSn1, VGSn2, and VGSn3 are the gate-source voltages of the first group of transistors MN1, MN2, and MN3, respectively, and VGSn4, VGSn5, and VGSn6 are the gate-source voltages of the second group of transistors MN4, MN5, and MN6, respectively.

[0061] In this embodiment, the first type of NMOS transistor (e.g., a 5V NMOS transistor) is configured to operate in the saturation region; the second type of NMOS transistor is a natural threshold MOS transistor (e.g., a 5V native MOS device) with a near-zero threshold voltage, configured to operate in the subthreshold region. Based on this, VREF can be further represented as: Formula 4 In formula 4, and , respectively, are the carrier mobility of the first and second groups of NMOS transistors; Cox1 and Cox2 are the gate oxide capacitance per unit area of ​​the first and second groups of NMOS transistors, respectively; K1 and K2 are the design width-to-length ratios W / L of the first and second groups of NMOS transistors, respectively; Vth1 and Vth2 are the threshold voltages of the first and second groups of NMOS transistors, respectively; m is the subthreshold slope factor; VT is the thermal voltage kT / q.

[0062] Substituting Equation 1 into Equation 4 and simplifying, VREF can be further expressed as: Formula 5 In Formula 5, That is, the difference in threshold voltage between the two sets of transistors. Analyzing the temperature characteristics of Equation 5: In the first term, due to mobility... Since VT has a negative temperature coefficient while PT has a positive temperature coefficient, the first term exhibits an overall positive temperature coefficient (PTAT) characteristic; the temperature characteristic of the second term is affected by the mobility. The combined influence of parameters such as thermal voltage VT; the third item It typically exhibits characteristics complementary to absolute temperature (CTAT). The overall temperature coefficient of a VREF depends on the selection of the composite constant K, the aspect ratios K1 and K2, and the first resistor R1. Therefore, by appropriately selecting the above parameters, the temperature coefficient of the VREF can be made close to zero within the target temperature range, thereby obtaining a reference voltage with a low temperature coefficient.

[0063] It should be noted that this embodiment uses VGS subtraction instead of direct VGS superposition to generate the reference voltage, which has significant technical advantages. In the direct superposition of transistor gate-source voltages, threshold voltage fluctuations caused by process variations are directly reflected in the output voltage. However, by using VGS subtraction, since the threshold voltage deviations of transistors of the same type on the same chip are highly correlated, the threshold voltage fluctuations of the two sets of transistors can cancel each other out to some extent through the subtraction operation, thereby significantly reducing the impact of process corner variations on the reference voltage and improving the circuit's process robustness. Furthermore, selecting two transistor types with significantly different threshold voltages (such as conventional NMOS and Native MOS) can obtain a higher reference voltage value, meeting the amplitude requirements of subsequent circuits. In this embodiment, the channel length of the first type of NMOS transistor is greater than that of the second type of NMOS transistor; that is, the first set of transistors MN1, MN2, and MN3 uses a longer channel length. This helps to reduce the influence of channel length modulation effects, thereby improving the power supply rejection ratio of the output voltage.

[0064] The following describes the voltage limiting loop module.

[0065] The voltage limiting loop module is the core structure of this application for achieving isolation from high power supply voltage to low voltage domain. Its function is to replace the Zener diode and large resistor pre-regulator in the traditional scheme, and provide a safe and stable low power supply voltage VL for all low-voltage devices in the subsequent stage under high power supply voltage VIN.

[0066] Reference Figure 2The voltage limiting loop module includes a high-voltage regulating transistor MP5 and a feedback sampling transistor MN0. MP5 is a high-voltage PMOS transistor (such as an LDMOS or high-voltage PMOS device), with its source connected to the high power supply voltage input terminal VIN and its gate connected to control node D (i.e., the node where the drain of the fourth PMOS transistor MP4 is located). Its drain outputs the voltage of the low power supply voltage node VL. The gate of the feedback sampling transistor MN0 is connected to the low power supply voltage node VL, its drain is connected to the node where the drain of the third PMOS transistor MP3 is located via a second resistor R2, and its source is connected to the first node B via a third resistor R3. Thus, the drain voltage VL of MP5 is fed back to the current branch of the positive temperature coefficient current source module through the gate control of MN0, forming a negative feedback loop.

[0067] The working mechanism of this voltage limiting loop is as follows: When the power supply voltage VIN increases, if VL tends to rise, the gate voltage of MN0 increases, the drain current of MN0 increases, which leads to a decrease in the gate voltages of the second PMOS transistor MP2 and the fourth PMOS transistor MP4. The voltage of control node D is pulled up, the gate-source voltage difference of the high-voltage regulating transistor MP5 decreases, and the output current of MP5 decreases, thereby suppressing the rise of VL. Conversely, when VL tends to fall, the feedback mechanism causes MP5 to provide more current to maintain VL stability. Through this negative feedback mechanism, regardless of how the power supply voltage VIN changes, VL is always maintained at a stable low voltage level, providing a low power supply voltage for subsequent circuits such as the voltage reference core module, current bias module, power supply rejection ratio enhancement module, and trimming module.

[0068] In this embodiment, the typical value of VL is within the safe operating voltage range of the low-voltage devices. The specific value depends on the rated operating voltage of the low-voltage devices, the sum of the threshold voltages from MN0 to MN3, and the circuit design parameters. This voltage range ensures that the low-voltage devices in the positive temperature coefficient current source module 100 and the voltage reference core module operate reliably within their safe operating voltage range.

[0069] The voltage limiting loop itself also provides high power supply rejection ratio and low linear sensitivity. Due to the high-gain negative feedback of the loop, fluctuations in the power supply voltage VIN are significantly attenuated before being transmitted to the VL node. Therefore, VL exhibits extremely low sensitivity to changes in VIN, which is crucial for the accuracy and stability of subsequent circuits. Simultaneously, because the voltage limiting loop is based on current source bias, rather than the large resistor voltage divider used in traditional solutions, it avoids the chip area occupied by high voltage and large resistors, and eliminates the need for an additional Zener diode mask layer, thus simultaneously achieving area reduction and cost reduction.

[0070] The following describes the loop compensation module.

[0071] Reference Figure 2The loop compensation module includes a compensation capacitor Cc. This capacitor is used to compensate the frequency of the voltage-limiting loop, ensuring sufficient phase margin across the entire operating frequency range and thus guaranteeing loop stability. In this embodiment, one end of the compensation capacitor Cc is connected to the drain of the second PMOS transistor MP2, and the other end is connected to the low power supply voltage node VL to form Ahuja compensation, thus separating the dominant pole of the negative feedback loop. The introduction of Cc utilizes the Miller effect to achieve frequency separation between the dominant and secondary poles of the loop, preventing the loop from oscillating due to high gain.

[0072] The function of the compensation capacitor Cc is as follows: In a voltage limiting loop with multiple poles, without proper compensation, the loop's phase margin may be insufficient, leading to oscillations or overshoot in VL. By introducing Cc for Ahuja compensation, the frequency of the dominant pole can be lowered, while the frequency of the secondary pole can be raised. This ensures sufficient phase margin when the open-loop gain crosses 0dB, guaranteeing stable operation of the voltage limiting loop under various operating conditions.

[0073] The starting circuit is described below.

[0074] Reference Figure 2 The startup circuit 120 includes a startup capacitor Cs1. One end of the startup capacitor Cs1 is connected to the control node D (i.e., the node where the gate of the high-voltage regulating transistor MP5 is located), and the other end is connected to ground (GND) via the isolation transistor M0 in the power supply rejection ratio enhancement module 130. The isolation transistor M0 belongs to the startup capacitor isolation submodule, which will be described in detail later. During circuit power-up, the startup capacitor Cs1 is configured to pull down the voltage of the control node D through capacitive coupling in response to the rise in voltage at the high power supply voltage input terminal VIN, thereby increasing the gate-source voltage difference of the high-voltage regulating transistor MP5 and turning it on. When the voltage at the control node D is low enough, MP5 turns on, allowing current to flow from VIN through MP5 to the low power supply voltage node VL, providing the initial current for the establishment of the low power supply voltage node VL. Once VL rises to a level sufficient to turn on MN0 to MN3, current is generated in the current mirror of the positive temperature coefficient current source module 100, and the voltage limiting loop enters the normal negative feedback operating state.

[0075] It should be noted that if the startup capacitor Cs1 remains directly connected in the circuit after completing its startup task, its presence will reduce the effective bandwidth of the voltage limiting loop, thereby affecting the PSRR performance in the mid-frequency range. This design consideration reflects the coupling constraint relationship between the startup circuit 120 and the power supply rejection ratio enhancement module 130: although the startup capacitor Cs1 is necessary for the startup function, its side effects need to be eliminated through an isolation structure; the two must be designed in conjunction and cannot be separated.

[0076] The following describes the power supply rejection ratio enhancement module.

[0077] The power supply rejection ratio (PSRR) enhancement module 130 is one of the key innovations of this application. It achieves a significant improvement in the full-band PRR of the voltage reference circuit through the coordinated operation of three sub-modules working in different frequency bands. This module includes a transistor stacking sub-module, a low-pass filter sub-module, and a startup capacitor isolation sub-module.

[0078] The transistor stacking submodule includes stacked transistors MN13. (See reference...) Figure 2 The stacked transistor MN13 is connected between the low-supply-voltage node VL and the drain power supply path of the sixth NMOS transistor MN6. Specifically, the drain of MN13 is connected to the low-supply-voltage node VL, and the source of MN13 is connected to the drain of the sixth NMOS transistor MN6. The gate of MN13 is connected to the first node B through the first filter resistor Rp1, that is, the gate of MN13 is connected to the connection node of the first filter resistor Rp1 and the first filter capacitor Cp1. MN13 is configured to operate in the saturation region to provide common-gate isolation and increase the power supply rejection ratio in the low-frequency range. As a result, MN13 has a relatively large drain-source resistance during normal operation, providing additional voltage isolation between the low-supply-voltage node VL and the reference core circuit. Low-frequency voltage fluctuations at the VL node need to pass through the high output impedance of MN13 to reach the operating node of the reference core circuit, which is equivalent to adding a stage of common-gate isolation in the signal transmission path, thereby significantly improving the power supply rejection ratio and linear sensitivity of the circuit in the low-frequency range.

[0079] The low-pass filter submodule includes a first-stage low-pass filter and a second-stage low-pass filter. (Refer to...) Figure 2 The first-stage low-pass filter includes a first filter resistor Rp1 and a first filter capacitor Cp1. The first filter resistor Rp1 is connected between the first node B and the gate of the fourth NMOS transistor MN4, and the first filter capacitor Cp1 is connected between the gate of the fourth NMOS transistor MN4 and ground. The second-stage low-pass filter includes a second filter resistor Rp2 and a second filter capacitor Cp2. The second filter resistor Rp2 is connected between the mirror bias node C and the gate of the tenth NMOS transistor MN10, and the second filter capacitor Cp2 is connected between the gate of the tenth NMOS transistor MN10 and ground. By setting a low-pass filter in the bias circuit, the gate voltages of MN4 to MN6 and MN10 to MN12 can be kept stable, filtering out intermediate frequency and high frequency noise and voltage fluctuations, thereby effectively improving the power supply rejection ratio of the circuit in the intermediate frequency and high frequency ranges.

[0080] However, it is important to note that while the introduction of the low-pass filter submodule improves the mid-to-high frequency PSRR, it also introduces a new technical problem—a decrease in startup speed. This is because during startup, the circuit needs to charge the first filter capacitor Cp1 and the second filter capacitor Cp2 to near their steady-state voltage levels before the reference voltage can be correctly established. The first filter resistor Rp1 and the second filter resistor Rp2 limit the charging current flowing to Cp1 and Cp2, significantly extending the charging time and thus slowing down the entire circuit's startup process. This contradiction between "PSRR enhancement and startup speed" is the direct motivation for designing the startup acceleration module 140 in this application. The two modules are closely causally related and structurally coupled, and cannot be separated independently. This logical chain of "inventing itself to introduce a problem → solving it itself" is an important manifestation of the collaborative relationship between the modules in this application.

[0081] The start-up capacitor isolation submodule includes isolation transistor M0. (See reference...) Figure 2 The isolation transistor M0, connected in series with the gate and drain (gate and drain connected), is a diode connected between the startup capacitor Cs1 and ground. This submodule's design also stems from inter-module coupling constraints: during startup, the startup capacitor Cs1 is used to couple and pull down the voltage of control node D to turn on the high-voltage regulating transistor MP5. However, after the circuit reaches steady state, if Cs1 is directly grounded, its equivalent capacitance will reduce the bandwidth of the voltage-limiting loop, thus weakening the mid-frequency power rejection ratio (PSRR). To solve this problem, a diode-connected isolation transistor M0 is inserted between Cs1 and ground. During startup, the current flowing through this branch keeps the isolation transistor M0 in the on state, exhibiting a small equivalent resistance, allowing Cs1 to function normally as a coupling start-up transistor. In the steady-state phase, since the current flowing through this branch is essentially zero, the diode-connected isolation transistor M0 automatically turns off, effectively isolating the path between Cs1 and ground, eliminating the adverse effects of the startup capacitor Cs1 on the negative feedback loop bandwidth and mid-frequency PSRR. This feature of automatically switching between on and off states based on the working status ensures that M0 does not affect the startup function or the steady-state PSRR performance, achieving a synergistic balance of "effective startup and steady-state isolation".

[0082] In summary, the three sub-modules of the power supply rejection ratio (PSRR) enhancement module are responsible for power supply rejection in different frequency bands: the stacked transistor MN13 mainly enhances low-frequency PSRR, the RC low-pass filters (Rp1 / Cp1, Rp2 / Cp2) mainly enhance mid-to-high frequency PSRR, and the isolation transistor M0 eliminates the side effects of the startup capacitor on mid-frequency PSRR. These three components work together to achieve a significant improvement in the full-band power supply rejection ratio.

[0083] The following explains how to start the acceleration module.

[0084] As previously mentioned, the startup acceleration module 140 addresses the startup speed reduction issue caused by the introduction of low-pass filtering devices (Rp1 / Rp2 and Cp1 / Cp2) in the power supply rejection ratio enhancement module 130. The detailed structure of this module is as follows... Figure 3 As shown, it includes a voltage coupling submodule, a precharge submodule, and a voltage discharge submodule.

[0085] The voltage coupling submodule includes coupling capacitor Cs2. (Refer to...) Figure 3 One end of the coupling capacitor Cs2 is connected to the low-supply voltage node VL, and the other end is connected to the internal node E. During circuit startup, as VIN gradually increases from zero, the voltage limiting loop causes VL to gradually build up and rise. When the voltage of the low-supply voltage node VL rises during startup, the coupling capacitor Cs2 couples this voltage change to the internal node E, causing the voltage of the internal node E to rise synchronously with VL.

[0086] The precharge submodule includes a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. (See reference...) Figure 3 The gates of both the second transistor M2 and the third transistor M3 are connected to the internal node E, and their drains are both connected to the low-power supply node VL. The source of the second transistor M2 is connected to the non-grounded terminal of the first filter capacitor Cp1 (i.e., the connection point of Rp1 and Cp1). The source of the third transistor M3 is connected to the non-grounded terminal of the second filter capacitor Cp2 (i.e., the connection point of Rp2 and Cp2) via a series-connected diode configuration of the fourth transistor M4 and the fifth transistor M5. When the voltage of the internal node E is coupled high enough to turn on M2 and M3 through M5, a current path is established between the low-power supply node VL and the filter capacitors in the low-pass filter submodule. The current bypasses the current-limiting effect of the first filter resistor Rp1 and the second filter resistor Rp2, flowing directly from VL to Cp1 and Cp2, allowing the filter capacitors to charge rapidly to near their steady-state voltage level.

[0087] During the startup acceleration process, the first filter capacitor Cp1 is rapidly precharged to a level close to the steady-state voltage of its corresponding gate node, and the second filter capacitor Cp2 is rapidly precharged to a level close to the steady-state voltage of its corresponding gate node. The aforementioned target voltages correspond to the approximate operating voltages of the gates MN4 to MN6 and MN10 to MN12 in steady state, respectively.

[0088] It is worth emphasizing that the pre-charge sub-module, which is turned on during the startup phase, generates a pre-charge current that, while charging the filter capacitor, also acts as an additional load on the low-voltage node VL, accelerating the voltage stabilization process of the voltage limiting loop module. This characteristic reflects the bidirectional coupling between the startup acceleration module and the voltage limiting loop: on the one hand, the rise in VL drives the startup acceleration module to turn on through Cs2 coupling; on the other hand, the pre-charge current of the startup acceleration module, in turn, acts as a load on the VL node, helping VL stabilize more quickly. This bidirectional coupling represents an inseparable structural synergy between the two modules.

[0089] The voltage bleeder submodule includes a bleeder transistor M1 and a bleeder resistor Rs. (Refer to...) Figure 3 The gate of the discharge transistor M1 is connected to the mirror bias node C (i.e., the node where the gate of MN3 is located, reflecting the establishment state of the voltage reference core). The drain of the discharge transistor M1 is connected to the internal node E through the discharge resistor Rs, and the source of the discharge transistor M1 is connected to ground. The discharge resistor Rs is connected between the internal node E and the drain of M1, providing a continuous discharge path for the internal node E during startup and transition, preventing the internal node E from being in an uncertain voltage state due to floating. When the voltage of the mirror bias node C reaches a level sufficient to turn on the discharge transistor M1, M1 conducts, pulling the voltage of the internal node E down to near ground potential. Once the internal node E is pulled down, M2 and M3 to M5 in the precharge submodule are immediately turned off, the precharge path is cut off, and the startup acceleration module 140 automatically exits operation, no longer interfering with the steady-state operation of the circuit.

[0090] This "pre-charge-automatic-exit" closed-loop design is a key feature of the startup acceleration module: during startup, the module automatically turns on to accelerate capacitor charging and VL stabilization; during steady-state operation, the module automatically turns off to avoid introducing additional quiescent current or disturbances to the reference core circuitry. After the startup acceleration module exits operation, M2 to M5 in the pre-charge submodule are completely off, without introducing additional quiescent current or parasitic disturbances—a crucial characteristic for low-power designs. Furthermore, throughout the startup process, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in the overvoltage protection module 150 work together with the voltage limiting loop module to effectively prevent voltage overshoot at control node D and the low-supply-voltage node VL.

[0091] The overvoltage protection module is described below.

[0092] Reference Figure 2The overvoltage protection module 150 includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7. Both MP6 and MP7 are diodes with their drains connected to their gates, and they are connected in series to form a series clamping branch between the high power supply voltage input terminal VIN and the control node D. Under normal operating conditions, due to the negative feedback regulation of the voltage limiting loop, the voltages of each node in the circuit are within a safe range, and the overvoltage protection module does not participate in operation. However, under certain abnormal conditions (such as a momentary overshoot of the power supply voltage or when the voltage limiting loop has not yet fully established), when the drain-source voltage difference of MP6 or MP7 exceeds its threshold voltage, the transistor will automatically turn on to provide clamping protection, limiting the voltage difference from increasing further, thereby preventing damage to internal low-voltage devices due to overvoltage. During circuit startup, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in the overvoltage protection module 150 work together with the voltage limiting loop module to prevent voltage overshoot at the control node D and the low power supply voltage node VL. This module, as a double safety measure in addition to the voltage limiting loop, further enhances the reliability of the circuit under high power supply voltage environments.

[0093] The following describes the adjustment module.

[0094] To further improve the accuracy of the reference voltage, this embodiment also includes a trimming module 210, which operates within the framework of trimming scheme 200 and is located in the low-voltage domain powered by the low-supply voltage node VL. (Refer to...) Figure 4 The adjustment module 210 is positioned between the source (node ​​a) of the third NMOS transistor MN3 and GND, and between the source (node ​​b) of the ninth NMOS transistor MN9 and GND. By fine-tuning the source voltage difference between MN3 and MN9, the mirror ratio of the current mirror can be changed, thereby adjusting the magnitude of the PTAT current IPTAT, ultimately finely adjusting the reference voltage VREF. Since there is a functional relationship between VREF and IPTAT as shown in Equation 5, fine-tuning IPTAT can indirectly achieve precise adjustment of VREF. It should be noted that the adjustment module operates in the low power supply voltage VL domain, which is consistent with the overall architecture design of the voltage limiting loop providing a low-voltage domain operating environment, avoiding the area overhead of high-voltage devices required for high-voltage domain operation.

[0095] Reference Figure 5The trimming module 210 specifically includes a resistor array 211 and a logic circuit 212. The resistor array 211 is divided into a first part of resistors and a second part of resistors: the first part of resistors (side a) is connected in series between the source of MN3 and GND, and the second part of resistors (side b) is connected in series between the source of MN9 and GND. The logic circuit 212 receives the trimming control signal Trim_sel and generates a selection signal sel with corresponding bit width and its inverted selection signal, which complementaryly control the switching transistors connected across the first and second parts of resistors to turn on or off. The power supply voltage of the logic circuit 212 is taken from the low power supply voltage VL.

[0096] More specifically, logic circuit 212 receives the n-bit trimming control signal Trim_sel <n-1:0>This generates an n-bit selection signal sel. <n-1:0>And its inverting selection signal. In resistor array 211, the first part of the resistors (side a) includes one normally connected unit resistor (always connected in series with the circuit) that is not controlled by the switching transistor, and a first controlled resistor group divided into n groups according to binary weights, with the number of resistor units in each group being 2 from the high bit to the low bit. n-1 2 n-2 The numbers 1, 2, ..., 1 form a binary weighting relationship. The second part of the resistor (side b) includes a second controlled resistor group, which is also divided into n groups according to binary weights. The number of resistance units in each group is the same as that in the first controlled resistor group.

[0097] Each of the first and second controlled resistor groups has a switching transistor connected in parallel across its terminals. For the first and second controlled resistor groups with equal weights, their corresponding switching transistors are driven by complementary control signals. This ensures that when one controlled resistor group on one side is short-circuited by the conducting switching transistor, the other controlled resistor group with the same weight is connected in series in the circuit, generating a corresponding voltage drop. The reverse is also true.

[0098] Specifically, in the first part of the resistor (side a), the gate of the switching transistor corresponding to the most significant bit (i.e., the (n-1)th bit) is connected to sel. <n-1>The inverted signal controls the switching transistors, and the gates of the switching transistors corresponding to the remaining bits (bits n-2 to 0) are respectively connected to sel. <n-2>To sel <0> Control; in the second part of the resistor (b side), the gate of the switching transistor corresponding to the most significant bit is connected to sel. <n-1>Control, the gates of the switching transistors corresponding to the other bits are respectively connected to sel <n-2>To sel <0> The inverting signal control. This asymmetric complementary control method ensures that the resistors connected on both sides remain balanced under the initial trim code value (all 0). As the trim code value changes, the total amount of the resistors connected on side a and side b changes in a segmented complementary manner, thereby achieving fine adjustment of IPTAT.

[0099] Through this complementary control method, the logic circuit can precisely control the total resistance of the resistors connected to the circuit on both sides a and b, thereby adjusting the source voltage difference between the third NMOS transistor MN3 and the ninth NMOS transistor MN9 to fine-tune the magnitude of the first current IPTAT, ultimately achieving precise adjustment of the reference voltage VREF. Compared to a scheme that adjusts the resistance on only one side, this dual-sided complementary adjustment method has a larger adjustment range with the same number of bits in the adjustment control signal, and the IPTAT change generated in each adjustment step is more uniform and has better linearity, which is beneficial for achieving high-precision reference voltage adjustment.

[0100] In this embodiment, the controllable number of bits n in the logic circuit 212 is 6, i.e., a 6-bit control signal Trim_sel<5:0> is used. The first and second controlled resistor groups are each divided into 6 groups, with the number of resistance units in each group from the highest to the lowest bit being 32, 16, 8, 4, 2, and 1, respectively. Let R represent the resistance value of a unit resistor. The first part of the resistors (side a) includes one constantly connected unit resistor R that is always connected to the circuit, and switchable resistors divided into 6 groups according to binary weights (from the highest to the lowest bit: 32R, 16R, 8R, 4R, 2R, 1R); the second part of the resistors (side b) is also divided into 6 groups according to binary weights (from the highest to the lowest bit: 32R, 16R, 8R, 4R, 2R, 1R). Through different combinations of the 6-bit control signals, fine-step adjustments to IPTAT can be achieved, thereby enabling high-precision adjustment of VREF. Specifically, in the first part of the resistor (side a), the gate of the switching transistor corresponding to the most significant bit (the 5th bit, with a weight of 32R) is connected to the fifth bit selection signal sel. <5> The inverted signal controls the switching transistor; the gates of the switching transistors corresponding to the remaining bits (bits 4 to 0, with weights of 16R, 8R, 4R, 2R, and 1R respectively) are connected to sel. <4> ,sel <3> ,sel <2> ,sel <1> ,sel <0> Signal control. In the second part of the resistor (b side), the gate of the switching transistor corresponding to the most significant bit (the 5th bit, with a weight of 32R) is connected to sel. <5> Signal control; the gates of the switching transistors corresponding to the remaining bits (bits 4 to 0) are respectively connected to sel <4> ,sel <3> ,sel <2> ,sel <1> ,sel <0> The inverting signal control. The above asymmetric complementary control method ensures that when the trim code value Trim_sel<5:0> is all 0 (i.e., 000000), the number of resistor units connected to side a is 32, and the number of resistor units connected to side b is also 32, guaranteeing the balance on both sides in the initial state. When the trim code value increases from 0 to 31, the number of resistor units connected to side a decreases from 32 to 1, and the number of resistor units connected to side b increases from 32 to 63; when the trim code value increases from 32 to 63, the number of resistor units connected to side a decreases from 63 to 33, and the number of resistor units connected to side b increases from 1 to 31. Through this segmented complementary change method, the source voltage difference between MN3 and MN9 can be finely and controllably adjusted within the entire trim range, which is beneficial for achieving high-precision reference voltage trimming.

[0101] The following describes the three-stage operation of the circuit.

[0102] To fully explain the coordination between the modules of the voltage reference circuit in this application, the complete working process of the circuit is described in detail below according to the three working stages: power-on startup, transition stage, and steady-state stage, combined with the voltage changes and current paths of each node.

[0103] During the power-on startup phase, as the power supply voltage VIN gradually increases from zero, the startup capacitor Cs1 rapidly pulls down the voltage of control node D through capacitive coupling. Because the voltage of control node D is pulled down, the gate-source voltage difference of the high-voltage regulating transistor MP5 increases to exceed its threshold voltage, causing MP5 to conduct. Current flows from VIN through MP5 to the low power supply voltage node VL, and VL begins to gradually increase from zero. During this phase, the isolation transistor M0 in the startup capacitor isolation submodule is in the conducting state (because current flows through the branch from Cs1 to M0), and its equivalent resistance is small, allowing Cs1 to perform its startup coupling function normally. Once VL rises to a voltage level sufficient to turn on MN0 to MN3, the PTAT current begins to build up in the current mirror of the positive temperature coefficient current source module, and the voltage limiting loop enters its initial operating state. Simultaneously, during the rise of VL, the coupling capacitor Cs2 in the startup acceleration module 140 couples the change in VL to the internal node E, causing the voltage of the internal node E to rise accordingly. When the voltage at internal node E is sufficient to activate pre-charge transistors M2 and M3 through M5, a fast charging path is established from VL to filter capacitors Cp1 and Cp2. Current bypasses the current-limiting effect of filter resistors Rp1 and Rp2, directly and rapidly pre-charging Cp1 and Cp2. This pre-charging process not only accelerates the voltage build-up of Cp1 and Cp2, but the resulting pre-charging current also acts as an additional load on node VL, helping the voltage limiting loop stabilize the voltage level of VL more quickly. Throughout the startup process, MP6 and MP7 in the overvoltage protection module 150 work together with the voltage limiting loop to effectively prevent voltage overshoot at control node D and the low-supply-voltage node VL.

[0104] During the transition phase, as the voltage limiting loop enters normal negative feedback regulation, VL is stabilized at the target low voltage level, and the voltage from node A to control node D also stabilizes rapidly. The first and second sets of transistors in the voltage reference core module enter their respective operating regions (saturation and subthreshold regions), and the reference voltage VREF begins to gradually build up. With the assistance of the startup acceleration module, Cp1 and Cp2 have been pre-charged to near their steady-state voltage levels, thus significantly accelerating the reference voltage establishment process without requiring a lengthy RC charging process. Once the voltage reference core is basically established, the voltage at the mirror bias node C reaches a level sufficient to turn on the discharge transistor M1. After M1 turns on, it pulls the voltage of internal node E down to near ground potential, and the pre-charge transistors M2 and M3 to M5 are immediately turned off, cutting off the pre-charge path of the startup acceleration module. The discharge resistor Rs provides an auxiliary discharge path during this process, ensuring a stable decrease in the potential of internal node E. At this point, the startup acceleration module completes its mission and automatically exits, no longer affecting subsequent steady-state operation. It is particularly important to emphasize that the acceleration module does not introduce any additional quiescent current after it exits, a characteristic that is crucial for low-power designs.

[0105] During steady-state operation, the voltage limiting loop continuously maintains VL at a stable low voltage level, exhibiting extremely low linear sensitivity to changes in VIN. The positive temperature coefficient current source module outputs a stable PTAT current IPTAT, the current bias module provides a stable bias current IBIAS, and the voltage reference core module outputs a precise reference voltage VREF. In the power supply rejection ratio (PSRR) enhancement module, the stacking effect of stacked transistors MN13 continuously provides low-frequency power supply rejection capability, while the Rp1 / Cp1 and Rp2 / Cp2 low-pass filters continuously filter out mid-to-high frequency interference, maintaining stable gate voltages for MN4 to MN6 and MN10 to MN12. The isolation transistor M0 is essentially off in steady-state, making the impact of the startup capacitor Cs1 on the voltage limiting loop bandwidth negligible, and the mid-frequency PSRR is not affected by the startup capacitor. In the startup acceleration module, M2 to M5 are completely off, introducing no additional quiescent current or parasitic disturbances. The tuning module operates stably in the low supply voltage (VL) domain, maintaining IPTAT within the target accuracy range through a preset tuning code value without introducing additional power consumption. The entire circuit consumes only the minimal quiescent current required by the positive temperature coefficient current source and bias current in steady state, exhibiting a comprehensive performance of low power consumption, low linear sensitivity, high power supply rejection ratio, and high accuracy.

[0106] The following explains the applicability to high voltage and design flexibility.

[0107] It should be noted that the voltage reference circuit of this application has good high-voltage applicability and design flexibility. Since the high-voltage regulating transistor MP5, the feedback sampling transistor MN0, and the high-voltage isolation transistor MN7 in the second current branch bear most of the voltage difference between the high supply voltage VIN and the low supply voltage VL, all subsequent low-voltage devices operate within the VL supply domain and do not directly bear the high supply voltage. The high-voltage regulating transistor MP5 is a PLDMOS (laterally diffused PMOS) or high-voltage PMOS device, and the feedback sampling transistor MN0 and the seventh NMOS transistor MN7 in the second current branch are high-voltage devices with rated withstand voltage levels higher than those of the first and second groups of transistors located in the low-voltage domain. Therefore, when changing the applicable high supply voltage range, the withstand voltage capability can be improved simply by changing the withstand voltage levels of the high-voltage regulating transistor MP5, the feedback sampling transistor MN0, and the seventh NMOS transistor MN7, or by stacking multiple high-voltage devices, without changing the subsequent circuit topology within the low-voltage domain established by the low supply voltage node VL. This characteristic provides great flexibility and portability for circuit design.

[0108] For example, in this embodiment, the high-voltage regulating transistor MP5 can be a high-voltage-rated PLDMOS, and the feedback sampling transistor MN0 and the seventh NMOS transistor MN7 can be high-voltage-rated NLDMOS. When the power supply voltage range is different, only the voltage rating of the above high-voltage devices needs to be changed accordingly, while the reference core circuit and its supporting modules in the low-voltage domain do not need to be modified.

[0109] The technical effects are explained below.

[0110] Because the above embodiments use a voltage-limiting loop based on PTAT current source bias to replace the Zener diode and high-voltage, high-resistance pre-regulator in the traditional solution, the additional mask layer required for the Zener diode is eliminated, reducing manufacturing costs; at the same time, the high-voltage, high-resistance chip area is avoided, resulting in a smaller chip area. Since the subsequent circuits all operate in the low-voltage domain, the size and power consumption of all low-voltage devices can be maintained at a low level, and the quiescent current is significantly reduced.

[0111] The power rejection ratio (PSRR) enhancement module achieves a significant improvement across the entire frequency band by synergistically optimizing low-frequency, mid-to-high-frequency, and startup capacitor side effects through three sub-modules: transistor stacking, RC low-pass filtering, and startup capacitor isolation. The startup acceleration module, with its closed-loop design of voltage coupling-pre-charge-automatic exit, addresses the startup speed reduction introduced by low-pass filtering devices without sacrificing PSRR performance, thus achieving a balance between fast startup and high PSRR. The tuning module, employing a dual-branch complementary control resistor array structure, operates in the low-voltage domain, enabling fine tuning of the reference voltage without increasing the area overhead of additional high-voltage devices, further improving reference voltage accuracy. The use of a VGS subtraction structure with two transistors of different threshold voltages enhances the process robustness of the voltage reference circuit and reduces the impact of process variations on the output voltage.

[0112] In summary, the modules in the above embodiments are not simply functional superpositions, but rather exhibit tight structural coupling and causal relationships. The voltage limiting loop provides a low-voltage operating environment globally; the power supply rejection ratio (PSRR) enhancement module, while improving PSRR, introduces a startup speed issue; the startup acceleration module specifically addresses this issue and forms a bidirectional coupling with the voltage limiting loop; startup capacitor isolation eliminates the side effects of the startup mechanism on PSRR; and the tuning module improves accuracy in the low-voltage domain. This inseparable structural synergy chain enables the voltage reference circuit in the above embodiments to achieve significant technical benefits in terms of high power supply voltage applicability, small area, low cost, low power consumption, high PSRR, and fast startup.

[0113] The above description is merely a specific implementation of the above embodiments, but the protection scope of the above embodiments is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the above embodiments should be included within the protection scope of the above embodiments. For example, the first group of transistors and the second group of transistors are not limited to the specific device type combination in the above embodiments; a similar reference voltage generation mechanism can be achieved as long as there is a significant difference in the threshold voltages of the two groups of transistors. Furthermore, parameters such as the number of bits in the resistor array and the number of unit resistors can be adjusted according to the actual adjustment accuracy requirements. Therefore, the protection scope of the above embodiments should be determined by the protection scope of this application.

[0114] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0115] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A voltage reference circuit, characterized by, It includes a positive temperature coefficient current source module (100), a current bias module (110), a voltage reference core module, a voltage limiting loop module, and a startup circuit (120). The positive temperature coefficient current source module (100) includes a first current branch and a second current branch, used to generate a first current with a positive temperature coefficient. The voltage reference core module includes a first group of transistors and a second group of transistors. The first group of transistors uses a first type of NMOS transistors, which are connected in series in a diode manner and biased by the first current branch to generate a superimposed voltage of the gate-source voltage at the first node (B). The second group of transistors uses a second type of NMOS transistor with a threshold voltage lower than that of the first type and is biased by the current bias module (110). The gate of the bias transistor of the current bias module (110) is connected to the mirror bias node (C). The gates of the second group of transistors are cascaded in sequence. The gate of the first stage transistor is connected to the first node (B), and the source of the last stage transistor outputs the reference voltage. The gate of each subsequent stage transistor is connected to the source of the previous stage transistor. The reference voltage is obtained by subtracting the sum of the gate-source voltages of the first group of transistors from the sum of the gate-source voltages of the second group of transistors; The voltage limiting loop module includes a high-voltage regulating transistor (MP5) and a feedback sampling transistor (MN0); the source of the high-voltage regulating transistor (MP5) is connected to the high power supply voltage input terminal (VIN), the gate is connected to the control node (D), and the drain outputs a low power supply voltage node (VL); the gate of the feedback sampling transistor (MN0) is connected to the low power supply voltage node (VL), thereby forming a negative feedback loop to maintain the stability of the low power supply voltage node (VL); The startup circuit (120) includes a startup capacitor (Cs1), one end of which is connected to the control node (D) and the other end is connected to ground. When powered on, the high voltage regulating tube (MP5) is turned on through capacitive coupling.

2. The voltage reference circuit of claim 1, wherein, It also includes a power supply rejection ratio enhancement module (130) and a startup acceleration module (140). The power supply rejection ratio enhancement module (130) includes: a stacked transistor (MN13) connected between the low power supply voltage node (VL) and the drain power supply path of the final stage transistor in the second group of transistors; a low-pass filter submodule inserted in the gate bias line of the second group of transistors and the current bias module (110); and an isolation transistor (M0) connected in series between the startup capacitor (Cs1) and ground in a diode connection manner, which is turned on during the startup phase and turned off during the steady state phase to eliminate the influence of the startup capacitor on the loop bandwidth; The startup acceleration module (140) includes a coupling capacitor (Cs2), a pre-charge sub-module, and a discharge transistor (M1). One end of the coupling capacitor (Cs2) is connected to the low power supply voltage node (VL), and the other end is connected to the internal node (E). During startup, it couples voltage changes to the internal node (E) to turn on the pre-charge sub-module. The pre-charge sub-module establishes a current path bypassing the filter resistor between the low power supply voltage node (VL) and the filter capacitor of the low-pass filter sub-module. The gate of the discharge transistor (M1) is connected to the mirror bias node (C). After the circuit is established, it conducts and pulls the internal node (E) low to turn off the pre-charge sub-module, and the startup acceleration module automatically exits.

3. The voltage reference circuit of claim 1, wherein, The positive temperature coefficient current source module (100) includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4); the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are connected together, the source of the first PMOS transistor (MP1) is connected to the high power supply voltage input terminal (VIN) through a first resistor (R1), and the source of the second PMOS transistor (MP2) is directly connected to the high power supply voltage input terminal (VIN); the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are connected together; the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are connected together; the source of the first PMOS transistor (MP1) is connected to the high power supply voltage input terminal (VIN) through a first resistor (R1); the source of the second PMOS transistor (MP2) is directly connected to the high power supply voltage input terminal (VIN); the gates of the third PMOS transistor (MP3) and the second PMOS transistor (MP4) are connected together; the gates of the third PMOS transistor (MP1) and the second PMOS transistor (MP2) are connected together; the gates of the third PMOS transistor (MP1 ... The gates of four PMOS transistors (MP4) are interconnected and form a common-source, common-gate structure with the first PMOS transistor (MP1) and the second PMOS transistor (MP2); the control node (D) is located at the drain of the fourth PMOS transistor (MP4); the drain of the feedback sampling transistor (MN0) is connected to the drain of the third PMOS transistor (MP3) through the second resistor (R2), the gate of the third PMOS transistor (MP3) is connected to the node where the drain of the feedback sampling transistor (MN0) is located, and the source of the feedback sampling transistor (MN0) is connected to the first node (B) through the third resistor (R3).

4. The voltage reference circuit of claim 3, wherein, It also includes a loop compensation module; the loop compensation module includes a compensation capacitor (Cc), one end of which is connected to the drain of the second PMOS transistor (MP2), and the other end is connected to the low power supply voltage node (VL) to form Ahuja compensation so that the primary pole and secondary pole of the negative feedback loop are separated.

5. The voltage reference circuit of claim 2, wherein, The first group of transistors includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a third NMOS transistor (MN3) connected in series, with the mirror bias node (C) located at the gate of the third NMOS transistor (MN3); the second group of transistors includes a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), and a sixth NMOS transistor (MN6); the current bias module (110) includes a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), and a twelfth NMOS transistor, all with their gates connected to the mirror bias node (C). S transistor (MN12) provides bias current to the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the sixth NMOS transistor (MN6), respectively; the low-pass filter submodule includes a first filter resistor (Rp1) connected between the first node (B) and the gate of the fourth NMOS transistor (MN4) and a first filter capacitor (Cp1) connected between the gate and ground, and a second filter resistor (Rp2) connected between the mirror bias node (C) and the gate of the tenth NMOS transistor (MN10) and a second filter capacitor (Cp2) connected between the gate and ground.

6. The voltage reference circuit of claim 5, wherein, The precharge submodule includes a second transistor (M2), a third transistor (M3), a fourth transistor (M4), and a fifth transistor (M5); the gates of the second transistor (M2) and the third transistor (M3) are both connected to the internal node (E), and their drains are both connected to the low power supply voltage node (VL); the source of the second transistor (M2) is connected to the non-grounded terminal of the first filter capacitor (Cp1); the source of the third transistor (M3) is connected to the non-grounded terminal of the second filter capacitor (Cp2) via the fourth transistor (M4) and the fifth transistor (M5) connected in series in a diode configuration; the drain of the discharge transistor (M1) is connected to the internal node (E) through a discharge resistor (Rs), and the source of the discharge transistor (M1) is connected to ground.

7. The voltage reference circuit of claim 6, wherein, During the startup phase, the pre-charge submodule generates a pre-charge current that charges the filter capacitor while simultaneously acting as an additional load on the low power supply voltage node (VL), accelerating the voltage stabilization process of the low power supply voltage node (VL) in the voltage limiting loop module. The discharge resistor (Rs) provides a continuous discharge path for the internal node (E) during startup and transition, preventing the internal node (E) from being in an uncertain voltage state due to floating. After the startup acceleration module (140) exits operation, the transistors in the pre-charge submodule are in a completely off state, without introducing additional quiescent current or parasitic disturbances.

8. The voltage reference circuit of claim 5, wherein, It also includes a trimming module (210), which is located in the low-voltage domain powered by the low power supply voltage node (VL); the second current branch also includes a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), and a ninth NMOS transistor (MN9) connected in series, whose gates are respectively connected to the gates of the first NMOS transistor (MN1), the second NMOS transistor (MN2), and the third NMOS transistor (MN3), forming a current mirror relationship with the first group of transistors; the trimming module (210) includes a resistor array (211) and a logic circuit (212), the first of the resistor array (211) A portion of the resistor is connected in series between the source of the third NMOS transistor (MN3) and ground, and a second portion of the resistor is connected in series between the source of the ninth NMOS transistor (MN9) and ground. The logic circuit (212) receives the adjustment control signal and generates a selection signal and its inverted selection signal to control the switching transistor connected across the first and second portions of the resistor in a complementary manner, thereby adjusting the source voltage difference between the third NMOS transistor (MN3) and the ninth NMOS transistor (MN9) to fine-tune the magnitude of the first current. The power supply voltage of the logic circuit (212) is taken from the low power supply voltage node (VL).

9. The voltage reference circuit of claim 8, wherein, The logic circuit (212) receives the n-bit adjustment control signal, where n is a positive integer; the first part of the resistor includes a normally connected unit resistor that is not controlled by the switching transistor, and a first controlled resistor group divided into n groups according to binary weights; the second part of the resistor includes a second controlled resistor group that is also divided into n groups according to binary weights; for the first controlled resistor group and the second controlled resistor group with the same weights, their corresponding switching transistors are driven by complementary control signals, such that when a controlled resistor group on one side is short-circuited by a switching transistor that is turned on, the controlled resistor group with the same weight on the other side is connected in series to the circuit.

10. The voltage reference circuit of claim 1, wherein, It also includes an overvoltage protection module (150); the overvoltage protection module (150) includes a sixth PMOS transistor (MP6) and a seventh PMOS transistor (MP7), both of which are connected in series with the drain and gate connected in a diode manner. The series clamping branch formed is connected between the high power supply voltage input terminal (VIN) and the control node (D) and is used to automatically turn on to provide clamping protection when the drain-source voltage difference exceeds the threshold voltage.

11. The voltage reference circuit of claim 5, wherein, The first type of NMOS transistor is configured to operate in the saturation region, and the second type of NMOS transistor is a natural threshold MOS transistor with a near-zero threshold voltage and is configured to operate in the subthreshold region; the channel length of the first type of NMOS transistor is greater than the channel length of the second type of NMOS transistor; the gate of the stacked transistor (MN13) is connected to the first node (B) through the first filter resistor (Rp1), the drain is connected to the low power supply voltage node (VL), and the source is connected to the drain of the last stage transistor in the second group of transistors, and is configured to operate in the saturation region to provide common gate isolation.

12. The voltage reference circuit according to claim 1, characterized in that, The high-voltage regulating transistor (MP5) is an LDMOS or high-voltage PMOS device, and the feedback sampling transistor (MN0) and the seventh NMOS transistor (MN7) in the second current branch are high-voltage devices with a rated withstand voltage level higher than that of the first group of transistors and the second group of transistors. This allows the withstand voltage capability to be improved simply by changing the withstand voltage level of the high-voltage devices or by stacking multiple high-voltage devices when changing the applicable high power supply voltage range, without changing the subsequent circuit topology in the low-voltage domain established by the low power supply voltage node (VL).

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