A multi-node AC / DC universal power line carrier circuit for a feeder

Abstract

This utility model proposes a multi-node AC / DC universal power line carrier circuit for a feeder, used to connect a two-core power bus, wherein the two-core power bus includes a first core line and a second core line. The circuit is characterized by comprising: a power line communication chip having a first transceiver channel and a second transceiver channel; the input pin of the first transceiver channel is connected to the first core line via a coupling capacitor C1, and a Zener diode D1 is connected at the input pin; the output pin of the first transceiver channel is connected to the first core line via a resistor R1, an inductor L3, and a coupling capacitor C2, and a Zener diode D2 is connected at the output pin; the input pin of the second transceiver channel is connected to the second core line via a coupling capacitor C4, and a Zener diode D4 is connected at the input pin; the output pin of the second transceiver channel is connected to the second core line via a resistor R2, an inductor L4, and a coupling capacitor C3, and a Zener diode D3 is connected at the output pin; a balancing resistor R4 is connected between the output terminals of the inductors L3 and L4.

Description

Technical Field

[0001] This utility model relates to a multi-node AC / DC universal power line carrier circuit for a feeder. Background Technology

[0002] To obtain the status of the feeders at each node of the feeding system, it is necessary to network the traditional feeders. However, existing feeding systems are generally only configured with power supply lines connecting the nodes. Therefore, power line carrier communication is the preferred solution for networking and upgrading the feeders. This requires consideration of issues such as the large number of feeder nodes in the feeding system and common-mode interference on power lines, as well as adaptability to both DC and AC power lines. Summary of the Invention

[0003] To address the problems mentioned in the background art, this utility model proposes a multi-node AC / DC universal power line carrier circuit for a feeder, the specific technical contents of which include:

[0004] A multi-node AC / DC universal power line carrier circuit for a feeder is used to connect a two-core power bus, the two-core power bus including a first core and a second core. The circuit includes: a power line communication chip for signal transmission and reception, the power line communication chip having a first transceiver channel and a second transceiver channel; the input pin of the first transceiver channel is connected to the first core via a coupling capacitor C1, and a Zener diode D1 is connected at the input pin; the output pin of the first transceiver channel is connected to the first core via a resistor R1, an inductor L3, and a coupling capacitor C2, and a Zener diode D2 is connected at the output pin; the input pin of the second transceiver channel is connected to the second core via a coupling capacitor C4, and a Zener diode D4 is connected at the input pin; the output pin of the second transceiver channel is connected to the second core via a resistor R2, an inductor L4, and a coupling capacitor C3, and a Zener diode D3 is connected at the output pin; a balancing resistor R4 is connected between the output terminals of the inductors L3 and L4.

[0005] Preferably, the first core wire is provided with an isolation inductor L1, and the second core wire is provided with an isolation inductor L2.

[0006] Preferably, the power line communication chip is a power line communication transceiver chip of model XWD1003, and its carrier frequency selection pin is grounded through a variable resistor.

[0007] Compared with the prior art, the advantages of this utility model include at least the following: This circuit can be connected to both DC power lines and AC power lines through capacitive coupling, and adopts a two-terminal differential communication topology to effectively suppress common-mode interference, ensuring the transmission and reception of feeder data. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a power line carrier circuit. Detailed Implementation

[0009] The following description, in conjunction with the accompanying drawings, further illustrates the proposed solution:

[0010] See appendix Figure 1 A multi-node AC / DC universal power line carrier circuit for a feeder is used to connect a two-core power bus. The two-core power bus includes a first core wire and a second core wire. An isolation inductor L1 is provided on the first core wire, and an isolation inductor L2 is provided on the second core wire. In this embodiment, a DC power bus is used as an example. The first core wire is a DC line, and the second core wire is a GND line.

[0011] This circuit specifically includes: a power line communication chip U1 for signal transmission and reception. The power line communication chip U1 is a power line communication transceiver chip of model XWD1003. Its data interaction pins DIN and DOUT are connected to the processor of the feeder. Its carrier frequency selection pin FADJ is grounded through a variable resistor R3. The carrier frequency can be selected by adjusting the resistance value of the variable resistor R3 to ground. The wide range of carrier frequencies allows system designers to flexibly select external inductors and capacitors.

[0012] The power line communication chip U1 is provided with a first transceiver channel and a second transceiver channel, wherein:

[0013] The input pin INA of the first transceiver channel is connected to the DC line via a coupling capacitor C1, and a Zener diode D1 is connected at the input pin; the output pin DRVA of the first transceiver channel is connected to the DC line via a resistor R1, an inductor L3 and a coupling capacitor C2, and a Zener diode D2 is connected at the output pin DRVA.

[0014] The input pin INB of the second transceiver channel is connected to the GND line via coupling capacitor C4, and a Zener diode D4 is connected at the input pin; the output pin DRVB of the second transceiver channel is connected to the GND line via resistor R2, inductor L4 and coupling capacitor C3, and a Zener diode D3 is connected at the output pin DRVB.

[0015] A balancing resistor R4 is connected between the output terminals of inductors L3 and L4. The balancing resistor R4 can match the impedance between the two output lines. As the matching coupling increases, the differential impedance decreases, which helps to suppress interference signals on the lines.

[0016] This circuit uses a topologically equivalent first and second transceiver channel interconnected for two-terminal differential communication, effectively suppressing common-mode interference and ensuring the transmission and reception of feeder data. Furthermore, through capacitive coupling, it can be connected to both DC and AC power lines, facilitating addition or upgrades to existing feeding systems.

[0017] The above preferred embodiments should be regarded as illustrative examples of the embodiments of the present application. Any technical deductions, substitutions, improvements, etc. that are similar to or based on the present application should be considered within the scope of protection of this patent.

Claims

1. A feeder multi-node AC / DC universal power carrier circuit for connecting a two-conductor power bus, the two-conductor power bus comprising a first conductor and a second conductor, characterized by, include: A power line communication chip for signal transmission and reception, wherein the power line communication chip is provided with a first transmission and reception channel and a second transmission and reception channel; The input pin of the first transceiver channel is connected to the first core wire via a coupling capacitor C1, and a Zener diode D1 is connected at the input pin; the output pin of the first transceiver channel is connected to the first core wire via a resistor R1, an inductor L3 and a coupling capacitor C2, and a Zener diode D2 is connected at the output pin. The input pin of the second transceiver channel is connected to the second core wire via a coupling capacitor C4, and a Zener diode D4 is connected at the input pin; the output pin of the second transceiver channel is connected to the second core wire via a resistor R2, an inductor L4 and a coupling capacitor C3, and a Zener diode D3 is connected at the output pin. A balancing resistor R4 is connected between the output terminals of inductors L3 and L4.

2. The feeder multi-node AC / DC universal power carrier circuit of claim 1, wherein, The first core wire is provided with an isolation inductor L1, and the second core wire is provided with an isolation inductor L2.

3. The feeder multi-node AC / DC universal power carrier circuit of claim 1, wherein, The power line communication chip is a power line communication transceiver chip of model XWD1003, and its carrier frequency selection pin is grounded through a variable resistor.

4. The feeder multi-node AC / DC universal power carrier circuit of claim 1, wherein, The two-core power bus is a DC power line, wherein: the first core is a DC line and the second core is a GND line.

5. The feeder multi-node AC / DC universal power carrier circuit of claim 1, wherein, The two-core power bus is an AC power line, wherein: the first core is the L line and the second core is the N line.

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