Scan line driving circuit and display device having the same

Abstract

A scan line driving circuit has a configuration in which a plurality of unit circuits are connected in multiple stages and is formed integrally with a display panel. The unit circuit includes: a first transistor to which a voltage of a first level is applied to one conduction electrode and the other conduction electrode is connected to a first node; a resistor having one end connected to the first node; a second transistor to which a voltage of a second level is applied to one conduction electrode and the other conduction electrode is connected to the other end of the resistor; and an output transistor whose control electrode is connected to the first node and one conduction electrode is connected to an output terminal. The resistor is formed in a semiconductor layer, and an upper electrode is formed above the resistor. Thus, a scan line driving circuit capable of preventing malfunction caused by characteristic variations of the resistor in the unit circuit is provided.

Description

Technical Field

[0001] The present invention relates to a scan line driving circuit, and more particularly to a scan line driving circuit formed integrally with a display panel. Background Art

[0002] Organic electroluminescence (EL) display devices are widely used as thin, lightweight, and high-definition display devices. A typical organic EL display device includes a display unit, a scan line driving circuit, a data line driving circuit, and a light emission control line driving circuit. The display unit is formed on an organic EL panel using thin film transistors (TFTs). The scan line driving circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. In addition, a technique of forming a scan line driving circuit integrally with an organic EL panel (gate driver on-chip technology) has been put into practical use. In addition, a scan line is also referred to as a gate line, and a scan line driving circuit is also referred to as a gate driver.

[0003] Regarding the scan line driving circuit formed integrally with the organic EL panel, various unit circuits have been known heretofore. Figure 24 It is a circuit diagram of a unit circuit of a conventional scan line driving circuit. Figure 24 The shown unit circuit 91 includes a ratio circuit, and the ratio circuit includes TFTs: Q1, Q5, and a resistor R9. The unit circuit 91 performs a set operation of making the voltage of node n9 high and a reset operation of making the voltage of node n9 low.

[0004] When the input signal IN and the clock signal CK1 are at low levels, the TFTs: Q1, Q5 are turned on. At this time, the high-level voltage VGH is applied to node n9 via the TFT: Q1, and the low-level voltage VGL is applied to node n9 via the TFT: Q5 and the resistor R9. Since the resistance value of the resistor R9 is sufficiently larger than the resistance value when the TFT: Q1 is turned on, the voltage of node n9 becomes high. In this way, the unit circuit 91 performs a set operation when the input signal IN and the clock signal CK1 are at low levels.

[0005] When the input signal IN is at a high level and the clock signal CK1 is at a low level, the TFT: Q1 is turned off and the TFT: Q5 is turned on. At this time, the low-level voltage VGL is applied to node n9 via the TFT: Q5 and the resistor R9, so the voltage of node n9 becomes low. In this way, the unit circuit 91 performs a reset operation when the input signal IN is at a high level and the clock signal CK1 is at a low level.

[0006] In order to perform the set operation and the reset operation at high speed, the resistor R9 uses a resistor having a high resistance value of several hundred kΩ to several MΩ. In the case where the scan line drive circuit is formed integrally with the organic EL panel, the unit circuit 91 is formed using a P-channel TFT together with the pixel circuits included in the display unit. In this case, the resistor R9 is formed using a P-type semiconductor having a high resistance value. A scan line drive circuit including a unit circuit having a ratio circuit is described in Patent Documents 1 and 2, for example.

[0007] Prior art documents

[0008] Patent documents

[0009] Patent Document 1: International Publication No. 2016 / 175117

[0010] Patent Document 2: International Publication No. 2016 / 190187 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] However, in the above-described conventional scan line drive circuit, the resistance value of the resistor R9 increases with the passage of time. When the resistance value of the resistor R9 increases, the time required for the voltage of the node n9 to drop becomes longer. Therefore, when the reset operation is performed in the unit circuit 91, a phenomenon occurs in which the voltage of the node n9 does not drop to a low level within a desired time (hereinafter, referred to as reset failure). When reset failure occurs in the scan line drive circuit, display defects such as flickering occur in the display screen.

[0013] Therefore, a problem to be solved is to provide a scan line drive circuit capable of preventing operation failure caused by characteristic variation of a resistor in a unit circuit.

[0014] Solutions for solving the problems

[0015] The above problem can be solved, for example, by a scan line drive circuit having a configuration in which a plurality of unit circuits are connected in multiple stages and formed integrally with a display panel. In the scan line drive circuit, the unit circuit includes: a first transistor having one conduction electrode applied with a voltage of a first level and the other conduction electrode connected to a first node; a resistor having one end connected to the first node; a second transistor having one conduction electrode applied with a voltage of a second level and the other conduction electrode connected to the other end of the resistor; and an output transistor having a control electrode connected to the first node and one conduction electrode connected to an output terminal. The resistor is formed in the same semiconductor layer as the semiconductor portions of the first transistor and the second transistor, and an upper electrode is formed on the resistor.

[0016] Advantages of the invention

[0017] According to the above-described scan line driving circuit, by forming an upper electrode over the resistor, it is possible to prevent the resistor from being affected by charges trapped in an insulating film or the like formed over the resistor, and to reduce characteristic variations of the resistor. Therefore, it is possible to prevent malfunction of the scan line driving circuit caused by characteristic variations of the resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing the configuration of the scan line driving circuit according to the first embodiment.

[0019] Figure 2 is a block diagram showing the configuration of the organic EL display device including the scan line driving circuit Figure 1 shown.

[0020] Figure 3 is Figure 1 the circuit diagram of the unit circuit of the scan line driving circuit shown.

[0021] Figure 4 is Figure 1 the timing chart of the scan line driving circuit shown.

[0022] Figure 5 is Figure 3 the timing chart of the unit circuit shown.

[0023] Figure 6 is a layout diagram showing Figure 3 a part of the unit circuit shown.

[0024] Figure 7 is a layout diagram showing Figure 6 the pattern of the semiconductor layer included in the layout diagram shown.

[0025] Figure 8 is Figure 6 the cross-sectional view taken along the line A-A' of

[0026] Figure 9A is a diagram showing the manufacturing process of the organic EL panel including the scan line driving circuit Figure 1 shown.

[0027] Figure 9B is Figure 9A a continuation of

[0028] Figure 9C is Figure 9B a continuation of

[0029] Figure 9D is Figure 9C a continuation of

[0030] Figure 9E is Figure 9D a continuation diagram of

[0031] Figure 9F is Figure 9E a continuation diagram of

[0032] Figure 9G is Figure 9F a continuation diagram of

[0033] Figure 9H is Figure 9G a continuation diagram of

[0034] Figure 9I is Figure 9H a continuation diagram of

[0035] Figure 9J is Figure 9I a continuation diagram of

[0036] Figure 9K is Figure 9J a continuation diagram of

[0037] Figure 9L is Figure 9K a continuation diagram of

[0038] Figure 9M is Figure 9L a continuation diagram of

[0039] Figure 10 is a diagram for explaining the problems of a conventional scan line driving circuit.

[0040] Figure 11 is for explaining Figure 1 the effects of the scan line driving circuit shown in

[0041] Figure 12 is a cross-sectional view of a unit circuit of a scan line driving circuit according to a modified example of the first embodiment.

[0042] Figure 13 is a block diagram showing the configuration of a scan line driving circuit according to the second embodiment.

[0043] Figure 14 is Figure 13 the circuit diagram of a unit circuit of the scan line driving circuit shown in

[0044] Figure 15 is Figure 14 the timing diagram of the unit circuit shown in

[0045] Figure 16 is the circuit diagram of a unit circuit of a scan line driving circuit according to the third embodiment.

[0046] Figure 17 is Figure 16 the timing diagram of the unit circuit shown in

[0047] Figure 18 the circuit diagram of the unit circuit of the scan line driving circuit according to the fourth embodiment.

[0048] Figure 19 is the block diagram showing the configuration of the scan line driving circuit according to the fifth embodiment.

[0049] Figure 20 is Figure 19 the timing diagram of the scan line driving circuit shown in

[0050] Figure 21 is Figure 19 the timing diagram of the unit circuit of the scan line driving circuit shown in

[0051] Figure 22 is the block diagram showing the configuration of the scan line driving circuit according to the sixth embodiment.

[0052] Figure 23 is Figure 22 the timing diagram of the unit circuit of the scan line driving circuit shown in

[0053] Figure 24 the circuit diagram of the unit circuit of the conventional scan line driving circuit. Detailed Embodiments

[0054] Hereinafter, the scan line driving circuit of each embodiment and the display device including the same will be described with reference to the drawings. In the following description, it is assumed that m and n are integers of 2 or more, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.

[0055] (First Embodiment)

[0056] Figure 1 is the block diagram showing the configuration of the scan line driving circuit 10 according to the first embodiment. Figure 1 The scan line driving circuit 10 shown has a configuration in which (m + 1) unit circuits 11 are connected in multiple stages. The unit circuit 11 has an initialization terminal INIT, clock terminals CK1, CK2, an input terminal IN, a control voltage terminal CV, and an output terminal OUT. A high-level voltage VGH and a low-level voltage VGL are supplied to the unit circuit 11 using wirings (not shown).

[0057] Figure 2 is the block diagram showing the configuration of the organic EL display device including the scan line driving circuit 10. Figure 2The organic EL display device 1 shown includes a display unit 2, a display control circuit 3, a scan line drive circuit 10, a data line drive circuit 4, and a light emission control line drive circuit 5. The display unit 2 is formed on an organic EL panel 8 using TFTs. The scan line drive circuit 10 and the light emission control line drive circuit 5 are formed integrally with the organic EL panel 8 using TFTs. The data line drive circuit 4 is formed separately from the organic EL panel 8. Further, all or part of the data line drive circuit 4 may be formed integrally with the organic EL panel 8 using TFTs, or all or part of the light emission control line drive circuit 5 may be formed separately from the organic EL panel 8.

[0058] The display unit 2 includes (m + 1) scan lines G0 to Gm, n data lines S1 to Sn, m light emission control lines E1 to Em, and (m × n) pixel circuits 6. The scan lines G0 to Gm and the light emission control lines E1 to Em are arranged in parallel with each other. The data lines S1 to Sn are arranged in parallel with each other in a direction orthogonal to the scan lines G0 to Gm. The scan lines G1 to Gm and the data lines S1 to Sn cross at (m × n) positions. The (m × n) pixel circuits 6 are arranged corresponding to the intersections of the scan lines G1 to Gm and the data lines S1 to Sn. The pixel circuit 6 includes an organic EL element 7 as a light emitting element. The pixel circuit 6 in the i-th row and j-th column is connected to the scan lines Gi-1, Gi, the data line Sj, and the light emission control line Ei. Further, the pixel circuit 6 in the i-th row and j-th column may not be connected to the scan line Gi-1, or the pixel circuit 6 in the i-th row and j-th column may be connected to other wirings.

[0059] The display control circuit 3 outputs a control signal CS1 to the scan line drive circuit 10, outputs a control signal CS2 and a video signal DS to the data line drive circuit 4, and outputs a control signal CS3 to the light emission control line drive circuit 5. The scan line drive circuit 10 drives the scan lines G0 to Gm based on the control signal CS1. The data line drive circuit 4 drives the data lines S1 to Sn based on the control signal CS2 and the video signal DS. The light emission control line drive circuit 5 drives the light emission control lines E1 to Em based on the control signal CS3.

[0060] More specifically, the scan line driving circuit 10 sequentially selects one scan line from among the scan lines G0 to Gm based on the control signal CS1, applies a selection voltage (here, a low-level voltage) to the selected scan line, and applies a non-selection voltage (here, a high-level voltage) to the remaining scan lines. Thereby, in the i-th horizontal period, the pixel circuits 6 (n pixel circuits) of the i-th row are selected together. The data line driving circuit 4 applies n voltages corresponding to the video signal DS to the data lines S1 to Sn respectively based on the control signal CS2. Thereby, the n voltages are respectively written into the n selected pixel circuits 6. A current corresponding to the voltage written into the pixel circuit 6 flows through the organic EL element 7, and the organic EL element 7 emits light with a brightness corresponding to the amount of the flowing current.

[0061] A light-emitting period and a non-light-emitting period are set for each row of the pixel circuit 6. The light-emitting control line driving circuit 5 applies a light-emitting voltage (here, a low-level voltage) to the light-emitting control line Ei during the light-emitting period of the pixel circuit 6 of the i-th row, and applies a non-light-emitting voltage (here, a high-level voltage) to the light-emitting control line Ei during the non-light-emitting period of the pixel circuit 6 of the i-th row.

[0062] Hereinafter, the (m + 1) unit circuits 11 are referred to as the 0-th to m-th stage unit circuits in the connection order. The display control circuit 3 outputs an initialization signal INIT, a gate clock GCK1, GCK2, a gate start pulse GSP, and a control voltage CV as the control signal CS1 to the scan line driving circuit 10. The initialization signal INIT is supplied to the initialization terminal INIT of each stage of the unit circuit 11. The gate clock GCK1 is supplied to the clock terminal CK1 of the even-stage unit circuit 11 and the clock terminal CK2 of the odd-stage unit circuit 11. The gate clock GCK2 is supplied to the clock terminal CK2 of the even-stage unit circuit 11 and the clock terminal CK1 of the odd-stage unit circuit 11. The gate start pulse GSP is supplied to the input terminal IN of the 0-th stage unit circuit 11. The control voltage CV is supplied to the control voltage terminal CV of each stage of the unit circuit 11. The output terminal OUT of each stage of the unit circuit 11 is connected to the input terminal IN of the next-stage unit circuit 11 and the corresponding scan line among the scan lines G0 to Gm.

[0063] Figure 3 is a circuit diagram of the unit circuit 11. As Figure 3 shown, the unit circuit 11 includes nine TFTs: M1 to M9, a resistor R1, and two capacitors C1, C2. The TFTs: M1 to M9 are P-channel TFTs. The resistor R1 is formed of P-type semiconductor (P-type polysilicon) in the same semiconductor layer as the semiconductor portions of the TFTs: M1 to M9.

[0064] One end of the resistor R1 (at Figure 3The drain electrodes of TFTs: M1 and M3, the source electrode of TFT: M9, and the gate electrodes of TFTs: M4 and M7 are connected to node n1. The source electrode of TFT: M5 is connected to the other end of resistor R1. One conduction electrode of TFT: M6 (the conduction electrode on the right side in Figure 3 this case) and the gate electrode of TFT: M8 are connected to node n2. The source electrode of TFT: M2 and the drain electrode of TFT: M4 are connected to the other conduction electrode of TFT: M6. The gate electrode of TFT: M9 is connected to the initialization terminal INIT. The gate electrode of TFT: M5 is connected to the clock terminal CK1. The drain electrode of TFT: M8 is connected to the clock terminal CK2. The gate electrodes of TFTs: M1 and M2 are connected to the input terminal IN. The gate electrode of TFT: M3, the drain electrode of TFT: M7, and the source electrode of TFT: M8 are connected to the output terminal OUT. High-level voltage VGH is applied to the source electrodes of TFTs: M1, M3, M4, and M7. Low-level voltage VGL is applied to the drain electrodes of TFTs: M2, M5, and M9 and the gate electrode of TFT: M6. Capacitor C1 is provided between the gate electrode and the source electrode of TFT: M7. Capacitor C2 is provided between the gate electrode and the source electrode of TFT: M8. An upper electrode UE is formed above resistor R1, and the upper electrode UE is connected to the control voltage terminal CV.

[0065] TFT: M1 functions as the first transistor with a high-level voltage VGH applied to the source electrode and the drain electrode connected to node n1. One end of resistor R1 is connected to node n1. TFT: M5 functions as the second transistor with a low-level voltage VGL applied to the drain electrode and the source electrode connected to the other end of resistor R1. TFTs: M1, M5, and resistor R1 form a proportional circuit. TFT: M7 functions as the output transistor with the gate electrode connected to node n1 and the drain electrode connected to the output terminal OUT. Resistor R1 is formed in the same semiconductor layer as the semiconductor portions of the first and second transistors.

[0066] The initialization signal INIT becomes low level during the initialization of the scan line driver circuit 10 and becomes high level during other periods. During the initialization period, TFT: M9 conducts, and the voltage of node n1 is initialized to low level. During periods other than the initialization period, TFT: M9 is cut off. The gate electrode of TFT: M6 is fixedly applied with the low-level voltage VGL, so TFT: M6 always conducts. Therefore, TFTs: M6 and M9 do not affect the normal operation of the unit circuit 11.

[0067] Figure 4 is the timing diagram of the scan line driver circuit 10. As Figure 4As shown, the gate clocks GCK1 and GCK2 are clock signals with a period of two horizontal periods (2H). The length of the high-level period of the gate clocks GCK1 and GCK2 is 3 / 2 horizontal periods, and the length of the low-level period is 1 / 2 horizontal period. The gate clock GCK2 lags behind the gate clock GCK1 by one horizontal period. The gate start pulse GSP becomes low level once when the gate clock GCK1 is low level during one frame period, and becomes high level during other periods. The control voltage CV is a fixed negative voltage slightly higher than the low-level voltage VGL. The control voltage CV is applied to the upper electrode UE in each stage of the unit circuit 11.

[0068] Figure 5 is the timing diagram of the unit circuit 11. At Figure 5 the intervals between times t1 to t6 are all 1 / 2 horizontal period. The voltage of the upper electrode UE is a fixed negative voltage slightly higher than the low-level voltage VGL. Hereinafter, a signal input or output via a certain terminal is referred to by the same name as that terminal. For example, the signal input via the clock terminal CK1 is called the clock signal CK1.

[0069] Just before time t1 (immediately before time t1), the clock signals CK1, CK2, the input signal IN, the voltage of the node n2, and the output signal OUT are high level, and the voltage of the node n1 is low level. Therefore, the TFTs: M1 to M3, M5, M8 are in the cut-off state, and the TFTs: M4, M7 are in the conducting state.

[0070] At time t1, the clock signal CK1 and the input signal IN change to low level. Along with this, the TFTs: M1, M2, M5 turn on. The high-level voltage VGH is applied to the node n1 via the TFT: M1, and the low-level voltage VGL is applied to the node n1 via the TFT: M5 and the resistor R1. The resistance value of the resistor R1 is sufficiently larger than the resistance value when the TFT: M1 is conducting. Therefore, the voltage of the node n1 changes to high level after time t1, and the TFTs: M4, M7 turn off. The low-level voltage VGL is applied to the node n2 via the TFT: M2. Therefore, when the TFT: M4 turns off, the voltage of the node n2 changes to low level, and along with this, the TFT: M8 turns on. Next, at time t2, the clock signal CK1 and the input signal IN change to high level. Along with this, the TFTs: M1, M2, M5 turn off.

[0071] Next, at time t3, the clock signal CK2 changes to a low level. At this time, TFT:M8 is in an on state, so the output signal OUT changes to a low level. A capacitor C2 is provided between the gate electrode and the source electrode of TFT:M8. Therefore, during the period when the output signal OUT is at a low level, the voltage of node n2 becomes a level lower than the normal low level. Therefore, the low-level voltage of the output signal OUT does not increase by the amount of the threshold voltage of TFT:M8 and becomes the same level as the low-level voltage of the clock signal CK2. When the output signal OUT changes to a low level, TFT:M3 turns on. During the period when the output signal OUT is at a low level, TFT:M3 applies a high-level voltage VGH to node n1.

[0072] Next, at time t4, the clock signal CK2 changes to a high level. At this time, TFT:M8 is in an on state, so the output signal OUT changes to a high level. Along with this, the voltage of node n2 changes to the normal low level and TFT:M3 turns off.

[0073] Next, at time t5, the clock signal CK1 changes to a low level. Along with this, TFT:M5 turns on. The low-level voltage VGL is applied to node n1 via TFT:M5 and resistor R1, so the voltage of node n1 changes to a low level. Along with this, TFT:M4 and M7 turn on and the voltage of node n2 changes to a high level. Next, at time t6, the clock signal CK1 changes to a high level. Along with this, TFT:M5 turns off.

[0074] In this way, the unit circuit 11 performs a set operation to make the voltage of node n1 high when the input signal IN and the clock signal CK1 are at a low level, and performs a reset operation to make the voltage of node n1 low when the input signal IN is high and the clock signal CK1 is at a low level. The voltage of node n1 changes to a high level after time t1 when the input signal IN and the clock signal CK1 change to a low level, and changes to a low level after time t5 when the clock signal CK1 changes to a low level during the period when the input signal IN is high. The voltage of node n2 becomes high when the voltage of node n1 is low and becomes low otherwise. The output signal OUT lags behind the input signal IN by 1 horizontal period and becomes low for 1 / 2 horizontal period.

[0075] The output terminals OUT of the unit circuits 11 of the 0th to mth stages are respectively connected to the scan lines G0 to Gm. Therefore, as Figure 4As shown in FIG. 1 , the voltage of the scanning line G0 lags behind the voltage of the gate start pulse GSP by one horizontal period and becomes a low level for 1 / 2 horizontal period. The voltage of the scanning line Gi lags behind the voltage of the scanning line Gi-1 by one horizontal period and becomes a low level for 1 / 2 horizontal period. Therefore, the voltages of the scanning lines G0 to Gm lag behind one horizontal period and become a low level for 1 / 2 horizontal period.

[0076] The resistor R1 and the upper electrode UE will be described below. Figure 6 1 is a layout diagram showing a part of the unit circuit 11 . Figure 6 The layout pattern of TFT: M1, M5, resistor R1 and upper electrode UE is recorded in it. Hereinafter, the wiring layer forming the semiconductor layer of TFT: M1 to M9 is referred to as the semiconductor layer, the wiring layer forming the gate electrode of TFT: M1 to M9 is referred to as the gate wiring layer, the wiring layer forming the wiring connected to the source electrode or drain electrode of TFT: M1 to M9 is referred to as the source wiring layer, and the wiring layer forming the anode electrode of the organic EL element 7 is referred to as the anode electrode layer. The gate wiring layer is located above the semiconductor layer, the source wiring layer is located above the gate wiring layer, and the anode electrode layer is located above the source wiring layer.

[0077] exist Figure 6 In the figure, the area marked with right lower slashes shows the pattern of the semiconductor layer, the area marked with cross-hatching shows the pattern of the gate wiring layer, the area marked with left lower slashes shows the pattern of the source wiring layer, and the rectangle marked with a cross symbol shows the contact hole that electrically connects the semiconductor layer and the source wiring layer. Figure 6 In the diagram, patterns of layers other than the semiconductor layer, the gate wiring layer, and the source wiring layer are omitted, and the voltage applied to the pattern or the name of the terminal to which the pattern is connected is described near the pattern.

[0078] Figure 7 It is shown Figure 6 The layout diagram shown is a diagram of the pattern of the semiconductor layer included in the layout diagram. Figure 7 As shown, at the position of TFT: M5, a p+ region, an n region, and a p+ region are formed. At the position of resistor R1, a p- region is formed. At the position of TFT: M1, a p+ region, a p- region, an n region, a p- region, and a p+ region are formed. In addition, the p+ region is a region containing a relatively large amount of P-type impurities, and the p- region is a region containing a relatively small amount of P-type impurities. The n region functions as a channel region.

[0079] Figure 8 yes Figure 6 A-A' line cross-section diagram. Figure 8As shown, an upper electrode UE is formed on a resistor R1. The upper electrode UE is formed in a source wiring layer. The resistance value of the resistor R1 is, for example, 0.1 MΩ or more and 7 MΩ or less. An insulating film 104 and interlayer insulating films 111 and 112 are interposed between the resistor R1 and the upper electrode UE. The total thickness of these insulating films is, for example, 200 nm or more and 1 μm or less.

[0080] Figures 9A to 9M FIG. is a diagram showing a manufacturing process of the organic EL panel 8 including the scan line driving circuit 10. First, a back coating 102 is deposited on a polyimide substrate 101, amorphous silicon 103 is deposited at a position where a semiconductor layer pattern is to be formed, and an insulating film 104 ( Figure 9A ) is formed using silicon dioxide (SiO2). Next, the amorphous silicon 103 on the substrate is irradiated with excimer laser LS in sequence, so that the amorphous silicon 103 is modified into polycrystalline silicon 105 ( Figure 9B ). Next, a gate electrode 106 of the TFT is formed using molybdenum at a position where the TFT is to be formed ( Figure 9C ). Next, boron ions are implanted into the polycrystalline silicon 105 on the substrate by irradiating boron ions. Through this process, a portion of the polycrystalline silicon 105 on the substrate that is not covered by the gate electrode 106 becomes a p-region 107, and a portion covered by the gate electrode 106 becomes an n-region 108 ( Figure 9D ).

[0081] Next, a resist 109 is applied at a position such as Pos_R1 where the resistor R1 is to be formed, and boron ions are further irradiated. Through this process, a portion of the p-region 107 that is not covered by the resist 109 changes to a p+ region 110 ( Figure 9E ). Next, the resist 109 is peeled off ( Figure 9F ). In the manufactured organic EL panel 8, the p-region 107 at the position Pos_R1 functions as the resistor R1. Next, an interlayer insulating film 111 is formed using silicon nitride (SiN x ), and an interlayer insulating film 112 is formed using silicon nitride and silicon dioxide (SiO x ) ( Figure 9G ). Next, contact holes 113 that penetrate the insulating film 104 and the interlayer insulating films 111 and 112 are formed by opening at positions where drain electrodes and source electrodes of the TFT are to be formed ( Figure 9H ).

[0082] Next, various wirings are formed using titanium / aluminum / titanium at a specified position on the substrate ( Figure 9I)。Through this process, wirings 114 for supplying a high-level voltage VGH, wirings 115 for supplying a low-level voltage VGL, wirings 116 for connecting between electrodes of the TFT, etc. are formed. In addition, the contact hole 113 is filled with the above-mentioned metallic material to form a drain electrode 117 and a source electrode 118 of the TFT. The drain electrode 117 and the source electrode 118 electrically connect the p+ region 110 to the wirings 114 to 116. On top of the resistor R1, an upper electrode UE is formed so as to cover the resistor R1.

[0083] Next, a planarization film 119 is formed using polyimide ( Figure 9J ). Next, a through hole is formed by opening at a prescribed position on the substrate, and a wiring 120 is formed using titanium / aluminum / titanium at a prescribed position on the substrate ( Figure 9K ). Next, a planarization film 121 is formed using polyimide, and an anode electrode 122 is formed using silver at a prescribed position on the substrate ( Figure 9L ). Next, a bank 123 is formed using polyimide at a prescribed position on the substrate ( Figure 9M ).

[0084] Through the above processes, the Figure 8 substrate shown is obtained. For the Figure 8 substrate shown, an organic EL layer, a cathode electrode, and a sealing film are formed in sequence, whereby an organic EL panel 8 including a scan line driving circuit 10 can be manufactured. In addition, the above materials are an example, and materials other than the above can also be used.

[0085] Hereinafter, the effect of the scan line driving circuit 10 of the present embodiment will be described in comparison with a conventional scan line driving circuit having the Figure 24 unit circuit 91 shown. Figure 10 is a diagram for explaining the problems of the conventional scan line driving circuit. Figure 11 is a diagram for explaining the effect of the scan line driving circuit 10. Figure 10 and Figure 11 show cross-sections near the resistor in the unit circuit of the scan line driving circuit. In addition, for easy comparison of the drawings, the same reference numerals are assigned to corresponding components.

[0086] In the conventional scan line driving circuit ( Figure 10) In this case, the upper electrode is not formed over the resistor R9. Therefore, when the charge EC is trapped by the insulating film (planarization films 119 and 121) formed over the resistor R9 or at its interface, the lines of electric force emitted from the charge EC enter the resistor R9 formed in the semiconductor layer. As a result, the carriers induced in the resistor R9 change, and the resistance value of the resistor R9 changes. The resistance value of the resistor R9 increases with the passage of time. In the conventional scan line driving circuit, when the resistance value of the resistor R9 increases, reset failure occurs. Thus, in the organic EL display device having the conventional scan line driving circuit, display defects such as flicker occur in the display screen.

[0087] In contrast, in the scan line driving circuit 10 of the present embodiment ( Figure 11 ), the upper electrode UE is formed over the resistor R1. Therefore, when the charge EC is trapped by the insulating film formed over the resistor R1 or at its interface, the lines of electric force emitted from the charge EC do not enter the resistor R1 due to the action of the upper electrode UE. As a result, the carriers induced in the resistor R1 do not change, and the resistance value of the resistor R1 does not change. Thus, according to the scan line driving circuit 10, reset failure caused by the characteristic change of the resistor R1 can be prevented. In addition, according to the organic EL display device 1 having the scan line driving circuit 10, display defects such as flicker can be prevented from occurring in the display screen.

[0088] In the scan line driving circuit 10, the resistor R1 is formed of a P-type semiconductor, and a fixed negative voltage (control voltage CV) is applied to the upper electrode UE. When the voltage of the upper electrode UE is made lower, the resistance value of the resistor R1 becomes smaller. The smaller the resistance value of the resistor R1, the easier it is for the voltage of the node n1 to change from a high level to a low level. Therefore, the unit circuit 11 can easily perform the reset operation. Thus, reset failure caused by the characteristic change of the resistor R1 can be prevented more effectively. In addition, since the upper electrode UE is formed in the source wiring layer, there is no organic film that easily contains moisture and charges between the resistor R1 and the upper electrode UE. Therefore, the scan line driving circuit 10 can operate more stably.

[0089] As described above, the scan line driving circuit 10 of the present embodiment has a configuration in which a plurality of unit circuits 11 are connected in multiple stages and is formed integrally with a display panel (organic EL panel 8). The unit circuit 11 includes: a first transistor (TFT: M1) to which a voltage of a first level (high-level voltage VGH) is applied to one conduction electrode (source electrode), and the other conduction electrode (drain electrode) is connected to a first node (node n1); a resistor R1 having one end connected to the first node; a second transistor (TFT: M5) to which a voltage of a second level (low-level voltage VGL) is applied to one conduction electrode (drain electrode), and the other conduction electrode (source electrode) is connected to the other end of the resistor R1; and an output transistor (TFT: M7) whose control electrode (gate electrode) is connected to the first node and one conduction electrode (drain electrode) is connected to an output terminal OUT. The resistor R1 is formed in the same semiconductor layer as the semiconductor portions of the first and second transistors, and an upper electrode UE is formed above the resistor R1.

[0090] According to the scan line driving circuit 10, by forming the upper electrode UE above the resistor R1, it is possible to prevent the resistor from being affected by charges trapped in an insulating film or the like formed above the resistor R1, and reduce the characteristic variation of the resistor R1. Therefore, it is possible to prevent malfunction of the scan line driving circuit 10 caused by the characteristic variation of the resistor R1.

[0091] The resistor R1 is formed using a P-type semiconductor (P-type polysilicon). Therefore, it is possible to form the scan line driving circuit 10 including the unit circuit 11 including the resistor R1 integrally with the display panel. The upper electrode UE is formed in a wiring layer above the control electrodes (gate electrodes) of the first and second transistors. Specifically, it is formed in the same wiring layer (source wiring layer) as wirings 114 to 116 connected to the conduction electrodes (source electrodes and drain electrodes) of the first and second transistors. Therefore, there is no organic film that easily contains moisture and charges between the resistor R1 and the upper electrode UE, so that the scan line driving circuit 10 can operate more stably.

[0092] Preferably, the resistance value of the resistor R1 is 0.1 MΩ or more and 7 MΩ or less. By using the resistor R1 having such a resistance value, the unit circuit 11 can perform a setting operation and a reset operation at high speed. Preferably, an insulating film (interlayer insulating films 111, 112) having a thickness of 200 nm or more and 1 μm or less is provided between the resistor R1 and the upper electrode UE. By providing an insulating film having such a thickness, the resistor R1 and the upper electrode UE can be arranged at an appropriate interval.

[0093] The control electrode (gate electrode) of the first transistor is supplied with the output signal OUT of the unit circuit of the previous stage, and the control electrode of the second transistor is supplied with a clock signal (gate clock GCK1 or GCK2). Thereby, the first and second transistors can be turned on at an appropriate timing, and the scan line driving circuit 10 can operate accurately.

[0094] A fixed negative voltage (control voltage CV) is applied to the upper electrode UE, and the negative voltage is, for example, -10V or more and -5V or less. By applying such a negative voltage to the upper electrode UE, the resistance value of the resistor R1 becomes small. Therefore, the unit circuit 11 can easily perform a reset operation.

[0095] Figure 12 is a cross-sectional view of the unit circuit of the scan line driving circuit which is a modified example of the present embodiment. In Figure 12 In the unit circuit shown, the upper electrode UE is not formed on the source wiring layer, but is formed on the same wiring layer as the anode electrode 122 of the organic EL element 7. In this case, the interlayer insulating films 111, 112 and the planarizing films 119, 121 are interposed between the resistor R1 and the upper electrode UE as insulating films. According to the scan line driving circuit of the modified example, similar to the scan line driving circuit 10 of the first embodiment, it is possible to prevent malfunction of the scan line driving circuit caused by characteristic variations of the resistor R1.

[0096] (Second Embodiment)

[0097] Figure 13 is a block diagram showing the configuration of the scan line driving circuit of the second embodiment. Figure 13 The scan line driving circuit 20 shown has a configuration in which (m + 1) unit circuits 21 are connected in multiple stages. The unit circuit 21 has an initialization terminal INIT, clock terminals CK1, CK2, an input terminal IN, and an output terminal OUT. Hereinafter, the differences from the first embodiment will be described.

[0098] Figure 14 is a circuit diagram of the unit circuit 21. In the unit circuit 21, a low-level voltage VGL is fixedly applied to the upper electrode UE formed above the resistor R1. Figure 15 is a timing chart of the unit circuit 21. As Figure 15 shown, the voltage of the upper electrode UE is always equal to the low-level voltage VGL.

[0099] Even if a low-level voltage VGL is applied to the upper electrode UE in this way, it is possible to prevent the resistor R1 from being affected by the charges trapped in the insulating film or the like formed on the resistor R1, and reduce the characteristic variation of the resistor R1. Therefore, it is possible to prevent malfunction of the scan line driving circuit 20 caused by the characteristic variation of the resistor R1. In addition, the scan line driving circuit 20 does not need to be provided with a wiring for supplying the control voltage CV.

[0100] In the scan line driving circuit 20 of the present embodiment, a fixed negative voltage equal to the low-level voltage VGL supplied to the unit circuit 21 is applied to the upper electrode UE. According to the scan line driving circuit 20, without providing a wiring for supplying the control voltage CV, it is possible to prevent malfunction of the scan line driving circuit 10 caused by the characteristic variation of the resistor R1 in the same manner as in the first embodiment.

[0101] (Third Embodiment)

[0102] The scan line driving circuit of the third embodiment is obtained by replacing the unit circuit 21 with another unit circuit in the scan line driving circuit 20 ( Figure 13 ) of the second embodiment. Hereinafter, the differences from the second embodiment will be described.

[0103] Figure 16 It is a circuit diagram of the unit circuit of the scan line driving circuit of the present embodiment. In Figure 16 the unit circuit 31 shown, the upper electrode UE formed on the resistor R1 is connected to the node n1. The node n1 is connected to the drain electrode of the TFT: M1, one end of the resistor R1 (the right end in Figure 16 ), the gate electrode of the TFT: M7, etc. The voltage of the upper electrode UE is equal to the voltage of the node n1.

[0104] Figure 17 It is a timing chart of the unit circuit 31. As Figure 17 shown, the voltage of the upper electrode UE changes in the same manner as the voltage of the node n1. More specifically, the voltage of the upper electrode UE changes to a high level after the time t1 when the input signal IN and the clock signal CK1 change to a low level, and changes to a low level after the time t5 when the clock signal CK1 changes to a low level during the period when the input signal IN is at a high level. The time t1 is the time when the unit circuit 31 starts the set operation, and the time t5 is the time when the unit circuit 31 starts the reset operation.

[0105] In the scanning line driving circuit 10 of the first embodiment, a fixed negative voltage is applied to the upper electrode UE. Therefore, the resistance value of the resistor R1 becomes small, and the unit circuit 11 can easily perform a reset operation. However, when the resistance value of the resistor R1 is decreased, it becomes difficult for the unit circuit 11 to perform a set operation. A small resistance value of the resistor R1 is preferable for performing a reset operation, and a large resistance value of the resistor R1 is preferable for performing a set operation.

[0106] Therefore, in the scanning line driving circuit of the present embodiment, the upper electrode UE is connected to the node n1. When the unit circuit 31 starts a set operation at time t1, the voltage of the upper electrode UE rises together with the voltage of the node n1 and becomes high level. Therefore, during the set operation of the unit circuit 31, a positive voltage is applied to the upper electrode UE, and the resistance value of the resistor R1 becomes large. Therefore, the unit circuit 31 can easily perform a set operation.

[0107] In addition, when the unit circuit 31 starts a reset operation at time t5, the voltage of the upper electrode UE drops together with the voltage of the node n1 and becomes low level. Therefore, during the reset operation of the unit circuit 31, a negative voltage is applied to the upper electrode UE, and the resistance value of the resistor R1 becomes small. Therefore, the unit circuit 31 can easily perform a reset operation.

[0108] In the scanning line driving circuit of the present embodiment, the upper electrode UE is connected to the first node (node n1) connected to the other conduction electrode of the first transistor (the drain electrode of the TFT: M1) and one end of the resistor R1. According to the scanning line driving circuit of the present embodiment, similar to the first embodiment, it is possible to prevent malfunction of the scanning line driving circuit caused by characteristic variations of the resistor R1. In addition, by applying a positive voltage to the upper electrode UE when the unit circuit 31 performs a set operation and applying a negative voltage to the upper electrode UE when the unit circuit 31 performs a reset operation, the unit circuit 31 can easily perform both the reset operation and the set operation.

[0109] (Fourth Embodiment)

[0110] The scanning line driving circuit of the fourth embodiment is obtained by replacing the unit circuit 21 with another unit circuit in the scanning line driving circuit 20 of the second embodiment ( Figure 13 ). Hereinafter, differences from the third embodiment will be described.

[0111] Figure 18 is a circuit diagram of the unit circuit of the scanning line driving circuit of the present embodiment. In Figure 18 In the shown unit circuit 41, the upper electrode UE formed on the resistor R1 is connected to the other end of the resistor R1 (in Figure 18(The left end is in the middle). The other end of the resistor R1 is connected to the source electrode of the TFT: M5.

[0112] When no current flows through the resistor R1, the voltage of the source electrode of the TFT: M5 is equal to the voltage of the node n1. Therefore, the timing diagram of the scan line driving circuit of the present embodiment becomes substantially the same as the Figure 17 timing diagram shown. The unit circuit 41 connecting the upper electrode UE to the other end of the resistor R1 operates in the same manner as the unit circuit 31 of the third embodiment that connects the upper electrode UE to the node n1.

[0113] In the scan line driving circuit of the present embodiment, the upper electrode UE is connected to the other end of the resistor R1 connected to the other conduction electrode of the second transistor (the source electrode of the TFT: M5). According to the scan line driving circuit of the present embodiment, similar to the third embodiment, it is possible to prevent malfunction of the scan line driving circuit caused by characteristic variations of the resistor R1. In addition, the unit circuit 41 can easily perform two operations, a reset operation and a set operation.

[0114] (Fifth Embodiment)

[0115] Figure 19 is a block diagram showing the configuration of the scan line driving circuit of the fifth embodiment. Figure 19 The scan line driving circuit 50 shown has a configuration in which (m + 1) unit circuits 11 are connected in multiple stages. Hereinafter, the differences from the first embodiment will be described. In addition, in the organic EL display device including the scan line driving circuit 50, it is preferable to arrange the scan line driving circuit 50 and the light emission control line driving circuit 5 on the same side of the display unit 2.

[0116] The display control circuit 3 outputs an initialization signal INIT, a gate clock GCK1, GCK2, and a gate start pulse GSP as control signals CS1 to the scan line driving circuit 50. These control signals are supplied to the corresponding terminals of the unit circuit 11 in the same manner as in the first embodiment. The output terminals OUT of the unit circuits 11 at each stage are connected to the input terminals IN of the unit circuits 11 at the next stage and the corresponding scan lines among the scan lines G0 to Gm in the same manner as in the first embodiment.

[0117] The light emission control line driving circuit 5 has a configuration in which (m + 1) unit circuits 9 are connected in multiple stages. The unit circuit 9 has an initialization terminal INIT, clock terminals CK1, CK2, an input terminal IN, and an output terminal OUT. Hereinafter, the (m + 1) unit circuits 9 will be referred to as the 0th to mth stage unit circuits in the connection order, and the wiring to which the output terminal OUT of the 0th stage unit circuit 9 is connected will be referred to as E0.

[0118] The display control circuit 3 outputs an initialization signal INIT, emission clocks EMCK1, EMCK2, and an emission start pulse EMSP as control signals CS3 to the light emission control line drive circuit 5. As Figure 19 shown, these control signals are supplied to the corresponding terminals of the unit circuits 9. The output terminals OUT of the unit circuits 9 at each stage are connected to the input terminals IN of the unit circuits 9 at the next stage, and the corresponding wirings among the wirings E0 and the light emission control lines E1 to Em. The control voltage terminals CV of the unit circuits 11 of the 0th to mth stages are respectively connected to the output terminals OUT of the unit circuits 9 of the 0th to mth stages. Accordingly, the upper electrode UE in the unit circuit 11 of the 0th stage is connected to the wiring E0, and the upper electrode UE in the unit circuit 11 of the ith stage is connected to the light emission control line Ei.

[0119] Figure 20 is a timing chart of the scan line drive circuit 50. In Figure 20 it, n1_0 to n1_4 respectively show the voltages of the nodes n1 of the unit circuits 11 of the 0th to 4th stages. In Figure 20 it, the gate start pulse GSP, the gate clocks GCK1, GCK2, and the voltages of the scan lines G0 to Gm change in the same manner as the Figure 4 shown timing chart.

[0120] The emission clocks EMCK1, EMCK2 are clock signals with a period of 2 horizontal periods. The length of the high level period of the emission clocks EMCK1, EMCK2 is 3 / 2 horizontal periods, and the length of the low level period is 1 / 2 horizontal period. The emission clock EMCK1 lags behind the gate clock GCK1 by 3 / 4 horizontal period. The emission clock EMCK2 lags behind the emission clock EMCK1 by 1 horizontal period. The emission start pulse EMSP becomes high level for 3 horizontal periods starting from a time 9 / 4 horizontal periods earlier than the time when the gate start pulse GSP changes to the low level.

[0121] The unit circuit 9 changes the output signal OUT to high level when the clock signal CK1 changes to low level during the period when the input signal IN is high level, and changes the output signal OUT to low level when the clock signal CK2 changes to low level during the period when the input signal IN is low level. Accordingly, the output signal OUT lags behind the input signal IN by 1 horizontal period and becomes high level for 3 horizontal periods. Accordingly, the voltages of the wiring E0 and the light emission control lines E1 to Em become high level for 3 horizontal periods, lagging behind by 1 horizontal period in sequence. Similarly, the voltages of the upper electrodes UE in the unit circuits 11 of the 0th to mth stages become high level for 3 horizontal periods, lagging behind by 1 horizontal period in sequence.

[0122] Figure 21 is a timing chart of the unit circuit 11 of the present embodiment. As Figure 21As shown, the voltage of the upper electrode UE changes to a high level at time t11 and changes to a low level at time t12. Time t11 is a time that is 5 / 4 horizontal periods earlier than the time t1 when the input signal IN and the clock signal CK1 change to a low level. Time t12 is a time that is 1 / 4 horizontal period earlier than the time t5 when the clock signal CK1 changes to a low level during the period when the input signal IN is at a high level. In this way, a positive voltage and a negative voltage are alternately applied to the upper electrode UE.

[0123] The voltage of the upper electrode UE changes to a high level at time t11, which is earlier than the time t1 when the voltage of node n1 starts to change from a low level to a high level, and changes to a low level at time t12, which is earlier than the time t5 when the voltage of node n1 starts to change from a high level to a low level. Therefore, the voltage of the upper electrode UE is at a high level when the voltage of node n1 changes from a low level to a high level, and is at a low level when the voltage of node n1 changes from a high level to a low level.

[0124] Before the unit circuit 11 starts the set operation at time t1, the voltage of the upper electrode UE is already at a high level. Therefore, during the set operation of the unit circuit 11, a positive voltage is applied to the upper electrode UE, and the resistance value of the resistor R1 becomes larger. Therefore, the unit circuit 11 can easily perform the set operation.

[0125] In addition, before the unit circuit 11 starts the reset operation at time t5, the voltage of the upper electrode UE is already at a low level. Therefore, during the reset operation of the unit circuit 11, a negative voltage is applied to the upper electrode UE, and the resistance value of the resistor R1 becomes smaller. Therefore, the unit circuit 11 can easily perform the reset operation.

[0126] As described above, in the scan line driving circuit 50 of the present embodiment, a plurality of light emission control lines E1 to Em are formed on the display panel (organic EL panel 8), and the upper electrode UE is connected to the corresponding light emission control line among the plurality of light emission control lines E1 to Em. A positive voltage (high-level voltage) and a negative voltage (low-level voltage) are alternately applied to the upper electrode UE. When the voltage of the first node (node n1) changes from the first level (high level) to the second level (low level), a negative voltage is applied to the upper electrode UE. When the voltage of the first node changes from the second level to the first level, a positive voltage is applied to the upper electrode UE.

[0127] The scan line driving circuit 50 according to the present embodiment, similar to the first embodiment, can prevent malfunction of the scan line driving circuit 50 caused by characteristic variations of the resistor R1. Further, by applying a positive voltage to the upper electrode UE before the unit circuit 11 starts the set operation and applying a negative voltage to the upper electrode UE before the unit circuit 11 starts the reset operation, the unit circuit 11 can easily perform both the reset operation and the set operation. Further, by connecting the upper electrode UE to the light emission control line formed in the display panel (organic EL panel 8), the positive voltage and the negative voltage can be alternately applied to the upper electrode UE with a simple configuration.

[0128] (Sixth Embodiment)

[0129] Figure 22 FIG. is a block diagram showing the configuration of the scan line driving circuit according to the sixth embodiment. Figure 22 The shown scan line driving circuit 60 has a configuration in which (m + 1) unit circuits 11 are connected in multiple stages. Hereinafter, the differences from the fifth embodiment will be described.

[0130] Figure 22 The configuration of the shown light emission control line driving circuit 5 is the same as that of the fifth embodiment. The display control circuit 3 outputs an initialization signal INIT, emission clocks EMCK1, EMCK2, and an emission start pulse EMSP as control signals CS3 to the light emission control line driving circuit 5.

[0131] The emission clock EMCK2 output from the display control circuit 3 is supplied to the control voltage terminal CV of the unit circuit 11 of the even stages of the scan line driving circuit 60. The emission clock EMCK1 output from the display control circuit 3 is supplied to the control voltage terminal CV of the unit circuit 11 of the odd stages of the scan line driving circuit 60. Therefore, the voltage of the upper electrode UE in the unit circuit 11 of the even stages changes in the same manner as the emission clock EMCK2, and the voltage of the upper electrode UE in the unit circuit 11 of the odd stages changes in the same manner as the emission clock EMCK1. The timing chart of the scan line driving circuit 60 of the present embodiment is the same as Figure 20 the shown timing chart.

[0132] Figure 23 FIG. is the timing chart of the unit circuit 11 of the present embodiment. As described above, the voltage of the upper electrode UE changes in the same manner as either one of the emission clocks EMCK1 and EMCK2. In Figure 23In this case, the voltage of the upper electrode UE is at a low level during the period from time t21 to time t22 and during the period from time t23 to time t24, and is at a high level during other periods. Time t21 is a time that is 1 / 4 of a horizontal period earlier than time t1 at which the input signal IN and the clock signal CK1 change to a low level. Time t22 is a time that is 1 / 4 of a horizontal period later than time t1. Time t23 is a time that is 1 / 4 of a horizontal period earlier than time t5 at which the clock signal CK1 changes to a low level during the period when the input signal IN is at a high level. Time t24 is a time that is 1 / 4 of a horizontal period later than time t5.

[0133] The voltage of the upper electrode UE changes to a low level at time t23 which is earlier than time t5 at which the voltage of node n1 starts to change from a high level to a low level. Therefore, when the voltage of node n1 changes from a high level to a low level, the voltage of the upper electrode UE is at a low level. Before the unit circuit 11 starts the reset operation at time t5, the voltage of the upper electrode UE is already at a low level. Therefore, during the period when the unit circuit 11 performs the reset operation, a negative voltage is applied to the upper electrode UE, and the resistance value of the resistor R1 becomes smaller. Therefore, the unit circuit 11 can easily perform the reset operation.

[0134] In addition, in the organic EL display device including the scan line driving circuit 60, the light emission control line driving circuit 5 does not necessarily need to be formed integrally with the organic EL panel 8. Even when the light emission control line driving circuit 5 is formed separately from the organic EL panel 8, as long as two wirings for propagating the emission clocks EMCK1 and EMCK2 are formed in the organic EL panel 8, the control voltage terminal CV of the even-numbered unit circuit 11 is connected to the wiring for propagating the emission clock EMCK2, and the control voltage terminal CV of the odd-numbered unit circuit 11 is connected to the wiring for propagating the emission clock EMCK1.

[0135] As described above, in the scan line driving circuit 60 of the present embodiment, a plurality of wirings for propagating a plurality of clock signals (emission clocks EMCK1 and EMCK2) for light emission control are formed in the display panel (organic EL panel 8), and the upper electrode UE is connected to the corresponding wiring among the plurality of wirings.

[0136] According to the scan line driving circuit 60 of the present embodiment, similar to the first embodiment, it is possible to prevent malfunction of the scan line driving circuit 60 caused by characteristic variations of the resistor R1. In addition, by applying a negative voltage to the upper electrode UE before the unit circuit 11 starts the reset operation, the unit circuit 11 can easily perform the reset operation. In addition, by connecting the upper electrode UE to the wiring for propagating the clock signal for light emission control formed in the display panel (organic EL panel 8), it is possible to alternately apply a positive voltage and a negative voltage to the upper electrode UE with a simple configuration.

[0137] Regarding the scan line driving circuit of the above-described embodiment, various modifications can be made. For example, as long as the unit circuit of the modified scan line driving circuit includes the first transistor, resistor, second transistor, and output transistor connected according to the above-described scheme, and an upper electrode is formed on the resistor formed in the semiconductor layer, other configurations can also be adopted. The display device having the modified scan line driving circuit can have any pixel circuit. In the modified scan line driving circuit, the voltage control circuit can also alternately apply a positive voltage and a negative voltage to the upper electrode UE. The voltage control circuit is configured to apply a negative voltage to the upper electrode UE when the voltage at the first node (node n1) changes from the first level (high level) to the second level (low level). More preferably, the voltage control circuit is configured to apply a positive voltage to the upper electrode UE when the voltage at the first node changes from the second level to the first level. Even when such a voltage control circuit is used, the unit circuit of the scan line driving circuit can easily perform a reset operation (or both a reset operation and a set operation).

[0138] So far, as an example of a display device having a pixel circuit including a light-emitting element, an organic EL display device having a pixel circuit including an organic EL element (organic light-emitting diode) has been described. However, an inorganic EL display device having a pixel circuit including an inorganic light-emitting diode, a QLED (Quantum-dot Light Emitting Diode) display device having a pixel circuit including a quantum dot light-emitting diode, and an LED display device having a pixel circuit including a mini LED or a micro LED can also be configured in the same manner. In addition, the features of the above-described display devices can be arbitrarily combined without conflicting with their properties to form a display device having the features of both the above-described embodiment and the modified example.

[0139] Explanation of reference numerals

[0140] 1…Organic EL display device

[0141] 2…Display unit

[0142] 3…Display control circuit

[0143] 4…Data line driving circuit

[0144] 5…Light-emitting control line driving circuit

[0145] 6…Pixel circuit

[0146] 7…Organic EL element

[0147] 8…Organic EL panel

[0148] 10, 20, 50, 60... scan line driver circuits

[0149] 11, 21, 31, 41... unit circuits.

Claims

1. A scan line driving circuit, having a structure that connects multiple unit circuits into multiple stages and is formed integrally with a display panel, characterized in that, The above-mentioned unit circuit includes: A first transistor, whose control electrode is supplied with the output signal of the unit circuit of the previous stage, one conduction electrode is applied with a voltage of the first level, and the other conduction electrode is connected to the first node; A resistor, one end of which is connected to the above-mentioned first node; A second transistor, whose control electrode is supplied with a clock signal, one conduction electrode is applied with a voltage of the second level, and the other conduction electrode is connected to the other end of the above-mentioned resistor; And An output transistor, whose control electrode is connected to the above-mentioned first node, and one conduction electrode is connected to the output terminal, The above-mentioned first node selectively holds the voltage of the first level supplied via the above-mentioned first transistor and the voltage of the second level supplied via the above-mentioned second transistor and the above-mentioned resistor, The above-mentioned output transistor is turned off when the voltage of the first level is supplied to the above-mentioned first node, and is turned on when the voltage of the second level is supplied to the above-mentioned first node, The above-mentioned resistor is formed in the same semiconductor layer as the semiconductor part of the above-mentioned first transistor and the semiconductor part of the above-mentioned second transistor, An upper electrode is formed on the above-mentioned resistor.

2. The scan line driving circuit according to claim 1, characterized in that, The above-mentioned resistor is formed using a P-type semiconductor.

3. The scan line driving circuit according to claim 1 or 2, characterized in that, The above-mentioned upper electrode is formed in a wiring layer higher than the control electrodes of the above-mentioned first transistor and the above-mentioned second transistor.

4. The scan line driving circuit according to claim 3, characterized in that, The above-mentioned upper electrode and the wiring connected to the conduction electrodes of the above-mentioned first transistor and the above-mentioned second transistor are formed in the same wiring layer.

5. The scan line driving circuit according to claim 3, characterized in that, An anode electrode of a light-emitting element is formed on the above-mentioned display panel, The above-mentioned upper electrode and the above-mentioned anode electrode are formed in the same wiring layer.

6. The scan line driving circuit according to claim 1 or 2, characterized in that, The resistance value of the above-mentioned resistor is 0.1 MΩ or more and 7 MΩ or less.

7. The scan line driving circuit according to claim 1 or 2, characterized in that, An insulating film having a thickness of 200 nm or more and 1 μm or less is interposed between the above-mentioned resistor and the above-mentioned upper electrode.

8. The scan line driving circuit according to claim 1 or 2, characterized in that, A fixed negative voltage is applied to the above-mentioned upper electrode.

9. The scan line driving circuit according to claim 8, characterized in that, The above-mentioned negative voltage is -10 V or more and -5 V or less.

10. The scan line driving circuit according to claim 8, characterized in that, The above-mentioned negative voltage is equal to the low-level voltage supplied to the above-mentioned unit circuit.

11. The scan line driving circuit according to claim 1 or 2, characterized in that, The above-mentioned upper electrode is connected to the above-mentioned first node.

12. The scan line driving circuit according to claim 1 or 2, wherein The above-mentioned upper electrode is connected to the other end of the above-mentioned resistor.

13. The scan line driving circuit according to claim 1 or 2, wherein The above-mentioned upper electrode is alternately applied with a positive voltage and a negative voltage, When the voltage at the above-mentioned first node changes from the first level to the second level, the negative voltage is applied to the above-mentioned upper electrode.

14. The scan line driving circuit according to claim 13, wherein When the voltage at the above-mentioned first node changes from the second level to the first level, the positive voltage is applied to the above-mentioned upper electrode.

15. The scan line driving circuit according to claim 13, wherein A plurality of light-emitting control lines are formed on the above-mentioned display panel, The above-mentioned upper electrode is connected to the corresponding light-emitting control line among the above-mentioned plurality of light-emitting control lines.

16. The scan line driving circuit according to claim 13, wherein A plurality of wirings for propagating a plurality of clock signals for light emission control are formed on the above-mentioned display panel, The above-mentioned upper electrode is connected to the corresponding wiring among the above-mentioned plurality of wirings.

17. A display device, wherein It includes the scan line driving circuit according to any one of claims 1 to 16.

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