Memory management method, memory controller and memory storage device

Abstract

The present application belongs to the technical field of storage, and provides a memory management method, a memory controller and a memory storage device. The memory management method comprises the following steps: grouping a plurality of physical units according to the number of erasures of the physical units to obtain a plurality of first groups, each of the first groups corresponding to a read interference threshold value; recording a physical unit whose read number exceeds the read interference threshold value in each of the first groups as a target physical unit; and copying first data in the target physical unit to a physical unit in a memory module with the smallest operation value. In this way, the number of data moving times caused by the read number of the physical units accumulating too quickly can be reduced, and thus the system performance of the memory storage device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage technology, and in particular, to a memory management method, a memory controller and a memory storage device. BACKGROUND

[0002] Rewritable non-volatile memory has the characteristics of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices. The rewritable non-volatile memory has a plurality of physical blocks, each physical block including a plurality of physical pages. Among them, the physical block is the minimum unit of data erasure, and the physical page is the minimum unit of data writing.

[0003] When the host system wants to read the stored data from the memory storage device, the memory storage device reads the data from the physical block according to the read instruction. Generally, when multiple data operations are performed on the physical page, the data operation on other physical pages in the same physical block may cause interference, resulting in read data error.

[0004] How to handle the read interference problem is one of the subjects that the inventors in the field have been trying to study. SUMMARY

[0005] The present application provides a memory management method, a memory controller and a memory storage device, which can solve the technical problem of read interference of physical units in the memory storage device.

[0006] An embodiment of the present application provides a memory management method applied to a memory storage device, wherein the memory storage device includes a memory module, and the memory module includes a plurality of physical units. The method includes: grouping and dividing the plurality of physical units according to the erasing times of the physical units to obtain a plurality of first groups, each of the first groups corresponding to a read interference threshold; recording the physical units in each of the first groups whose read times exceed the read interference threshold as target physical units; copying first data in the target physical units to a first physical unit, the first physical unit being the physical unit with the smallest operation value in the memory module; and updating a logical-to-physical mapping relationship of the first data according to a physical address of the first physical unit.

[0007] In one embodiment, wherein the step of recording the entity units in each of the first groups whose read times exceed the read interference threshold value as target entity units comprises: each of the first groups corresponds to a read interference monitoring value, and the entity units in each of the first groups whose read times exceed the read interference monitoring value are recorded as risk entity units, wherein the read interference monitoring value is less than the read interference threshold value; and the entity units in the risk entity units whose read times exceed the read interference threshold value are recorded as target entity units.

[0008] Further, in another embodiment, wherein the step of recording the entity units in the risk entity units whose read times exceed the read interference threshold value as target entity units comprises: recording the entity units in the risk entity units whose read times exceed the read interference threshold value as second entity units; and obtaining a first read time value of the second entity units, and recording the second entity units whose first read time values are not greater than a first threshold value as target entity units.

[0009] Further, in another embodiment, wherein the steps of obtaining the read times of the plurality of entity units and obtaining the first read time values of the second entity units comprises: establishing a first read time table and a second read time table; the first read time table is used to record the read times that are not greater than the read interference monitoring value, and the entity units in the first read time table are sorted according to the read times, wherein the greater the read time, the higher the sorting of the entity unit; and the second read time table is used to record the read times that exceed the read interference monitoring value and / or the read interference threshold value, and also record the first read time values of the second entity units, wherein the first read time value is the time interval from the last time the second entity unit is read to the present time, and the risk entity units are sorted according to the first read time values, wherein the smaller the first read time value, the higher the sorting of the second entity unit.

[0010] Further, in another embodiment, the step of selecting the target entity units from the second entity units comprises: obtaining a second read time value of a first entity programmed unit of the second entity units, and recording the second entity units whose second read time values are greater than a second threshold value as the target entity units, wherein the second read time value is the time when the data stored in the first entity programmed unit is successfully read in response to a data read instruction.

[0011] Further, in another embodiment, the step of obtaining a second read time value of a first entity-programmed cell of the second entity cell, and recording the second entity cell whose second read time value is greater than a second threshold value as the target entity cell comprises: obtaining a third read time value of a second entity-programmed cell of the second entity cell, and recording the second entity cell whose third read time value is greater than a second threshold value as the target entity cell, the third read time value being a time of successfully reading data stored in the second entity-programmed cell in response to a data read instruction, the first entity-programmed cell and the second entity-programmed cell belonging to the same entity cell.

[0012] Further, in another embodiment, the step of copying data in the target entity cell to the first entity cell comprises: dividing a plurality of entity cells in the memory module into a data area and an idle area; grouping a plurality of entity cells in the idle area according to the number of times of erasing of the entity cells, to obtain a plurality of second groups, each second group corresponding to a different interval of values of the number of times of erasing; selecting a proper number of entity cells from the second group with the smallest interval of values of the number of times of erasing according to the size of the amount of data in the target entity cell as the first entity cell, performing an erasing operation on the first entity cell, and writing the data in the target entity cell into the first entity cell; marking the data in the target entity cell as invalid data or dividing the target entity cell into the idle area; and dividing the first entity cell into the data area.

[0013] Further, in another embodiment, the step of selecting a proper number of entity cells from the second group with the smallest interval of values of the number of times of erasing as the first entity cell comprises: further grouping the second group with the smallest interval of values of the number of times of erasing according to error bit values of the entity cells, to obtain a plurality of subgroups based on having the same interval of values of the number of times of erasing but different intervals of values of error bits; and selecting an entity cell with the smallest number of times of erasing and the smallest error bit value from the subgroup with the smallest interval of values of the number of times of erasing and the smallest interval of values of error bits as the first entity cell.

[0014] An embodiment of the present application also provides a memory controller for controlling a memory module, wherein the memory module comprises a plurality of physical units, and each of the physical units comprises a plurality of physical programming units; the memory controller comprises a host interface connected to a host system, a memory interface connected to the memory module, and a memory control circuit connected to the host interface and the memory interface; wherein the memory control circuit groups the plurality of physical units according to the number of erase times of the physical units to obtain a plurality of first groups, and each of the first groups corresponds to a read disturb threshold value; the memory control circuit records the physical units whose read times exceed the read disturb threshold value in each of the first groups as target physical units; the memory control circuit copies first data in the target physical units to a first physical unit, and the first physical unit is the physical unit with the minimum operation value in the memory module; and the memory control circuit updates the logical-to-physical mapping relationship of the first data according to the physical address of the first physical unit.

[0015] Further, in an embodiment, wherein the operation of the memory control circuit for recording the physical units whose read times exceed the read disturb threshold value in each of the first groups as target physical units comprises: the memory control circuit configures a read disturb monitoring value for each of the first groups, respectively; the memory control circuit records the physical units whose read times exceed the read disturb monitoring value in each of the first groups as risk physical units, and the read disturb monitoring value is less than the read disturb threshold value; and the memory control circuit records the physical units whose read times exceed the read disturb threshold value in the risk physical units as target physical units.

[0016] Further, in another embodiment, wherein the operation of the memory control circuit for recording the physical units whose read times exceed the read disturb threshold value in the risk physical units as target physical units comprises: the memory control circuit records the physical units whose read times exceed the read disturb threshold value in the risk physical units as second physical units; the memory control circuit obtains a first read time value of the second physical units, and the memory control circuit records the second physical units whose first read time values are not greater than a first threshold value as target physical units.

[0017] Further, in another embodiment, the operation of the memory control circuitry obtaining the read counts of the plurality of physical units and obtaining the first read time value of the second physical unit includes the memory control circuitry establishing and maintaining first and second read count tables, the first read count table is used to record read counts that are not greater than the read disturb monitoring value, and the physical units in the first read count table are sorted according to the read counts, wherein the greater the read count, the higher the sorting of the physical unit, the second read count table is used to record read counts that exceed the read disturb monitoring value and / or the read disturb threshold value, and also record the first read time value of the second physical unit, the first read time value is the time interval from the second physical unit being read last time to now, and the risk physical units are sorted according to the first read time value, wherein the smaller the first read time value, the higher the sorting of the second physical unit.

[0018] Further, in another embodiment, the operation of the memory control circuitry selecting the target physical unit from the second physical units includes the memory control circuitry obtaining a second read time value of a first physical programming unit of the second physical unit, and the memory control circuitry records the second physical unit whose second read time value is greater than a second threshold value as the target physical unit, the second read time value is the time of successfully reading data stored in the first physical programming unit in response to a data read instruction.

[0019] Further, in another embodiment, the operation of the memory control circuitry obtaining a second read time value of a first physical programming unit of the second physical unit and recording the second physical unit whose second read time value is greater than a second threshold value as the target physical unit includes the memory control circuitry obtaining a third read time value of a second physical programming unit of the second physical unit, and the memory control circuitry records the second physical unit whose third read time value is greater than a second threshold value as the target physical unit, the third read time value is the time of successfully reading data stored in the second physical programming unit in response to a data read instruction, and the first physical programming unit and the second physical programming unit belong to the same physical unit.

[0020] Further, in another embodiment, the operation of the memory control circuit copying data in the target entity unit to the first entity unit comprises: the memory control circuit dividing a plurality of entity units in the memory module into a data area and an idle area; the memory control circuit grouping a plurality of entity units in the idle area according to the number of erasures of the entity units, to obtain a plurality of second groups, each second group corresponding to a different number of erasure value interval; the memory control circuit selecting a proper number of entity units from the second group with the smallest number of erasure value interval as the first entity unit according to the size of the amount of data in the target entity unit, and performing an erasure operation on the first entity unit and writing data in the target entity unit into the first entity unit; the memory control circuit marking the data in the target entity unit as invalid data or dividing the target entity unit into the idle area; and the memory control circuit dividing the first entity unit into the data area.

[0021] Further, in another embodiment, the operation of the memory control circuit selecting a proper number of entity units from the second group with the smallest number of erasure value interval as the first entity unit comprises: the memory control circuit further grouping the second group with the smallest number of erasure value interval according to the error bit value of the entity units, to obtain a plurality of subgroups based on having the same number of erasure value interval but different error bit value interval; and the memory control circuit selecting the entity unit with the smallest number of erasure and the smallest error bit value from the subgroup with the smallest number of erasure value interval and the smallest error bit value interval as the first entity unit.

[0022] An embodiment of the present application also provides a memory storage device, comprising a connection interface, a memory module and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module comprises a plurality of entity units, and each entity unit comprises a plurality of entity programming units; the memory controller is connected to the connection interface and the memory module; wherein the memory controller groups a plurality of entity units according to the number of erasures of the entity units, to obtain a plurality of first groups, each first group corresponding to a read interference threshold value; the memory controller records the entity units with a read number exceeding the read interference threshold value in each first group as target entity units; the memory controller copies first data in the target entity units to a first entity unit, the first entity unit being the entity unit with the smallest operation value in the memory module; and the memory controller updates the logical-to-physical mapping relationship of the first data according to the physical address of the first entity unit.

[0023] Further, in an embodiment, wherein the operation of the memory controller recording the physical cells in each of the first groups whose read counts exceed the read disturb threshold as target physical cells comprises: the memory controller configuring a read disturb monitoring value for each of the first groups respectively, the memory controller recording the physical cells in each of the first groups whose read counts exceed the read disturb monitoring value as risk physical cells, the read disturb monitoring value being less than the read disturb threshold; and the memory controller recording the physical cells in the risk physical cells whose read counts exceed the read disturb threshold as target physical cells.

[0024] Further, in another embodiment, wherein the operation of the memory controller recording the physical cells in the risk physical cells whose read counts exceed the read disturb threshold as target physical cells comprises: the memory controller recording the physical cells in the risk physical cells whose read counts exceed the read disturb threshold as second physical cells; the memory controller obtaining a first read time value of the second physical cells, and the memory controller recording the second physical cells whose first read time values are not greater than a first threshold as target physical cells.

[0025] Further, in another embodiment, wherein the operation of the memory controller obtaining the read counts of the plurality of physical cells and obtaining the first read time value of the second physical cells comprises: the memory controller establishing and maintaining first and second read count tables; the first read count table is used to record the read counts that are not greater than the read disturb monitoring value, and the physical cells in the first read count table are sorted according to the read counts, wherein the greater the read count, the higher the sorting of the physical cell; and the second read count table is used to record the read counts that exceed the read disturb monitoring value and / or the read disturb threshold, and also record the first read time values of the second physical cells, the first read time value being a time interval from the second physical cell being read last to now, and the risk physical cells are sorted according to the first read time values, wherein the smaller the first read time value, the higher the sorting of the second physical cell.

[0026] Further, in another embodiment, the operation of the memory controller selecting the target physical cells from the second physical cells comprises: the memory controller obtaining a second read time value of a first physical programming cell of the second physical cells, and the memory controller recording the second physical cells whose second read time values are greater than a second threshold as the target physical cells, the second read time value being a time of successfully reading data stored in the first physical programming cell in response to a data read instruction.

[0027] Further, in another embodiment, the operation of the memory controller recording the second physical unit having the second read time value greater than the second threshold value as the target physical unit includes: the memory controller obtaining a third read time value of a second physical programmed unit of the second physical unit, and the memory controller recording the second physical unit having the third read time value greater than the second threshold value as the target physical unit, the third read time value being a time of successfully reading data stored in the second physical programmed unit in response to a data read instruction, the first physical programmed unit and the second physical programmed unit belonging to the same physical unit.

[0028] Further, in another embodiment, the operation of the memory controller copying data in the target physical unit to the first physical unit includes: the memory controller dividing a plurality of physical units in the memory module into a data area and an idle area; the memory controller grouping a plurality of physical units in the idle area according to the number of times of erasing of the physical units, to obtain a plurality of second groups, each second group corresponding to a different interval of values of the number of times of erasing; the memory controller selecting a proper number of physical units from the second group having the smallest interval of values of the number of times of erasing as the first physical unit according to the size of the amount of data in the target physical unit, and the memory controller performing an erasing operation on the first physical unit and writing data in the target physical unit into the first physical unit; the memory controller marking the data in the target physical unit as invalid data or dividing the target physical unit into the idle area; and the memory controller dividing the first physical unit into the data area.

[0029] Further, in another embodiment, the operation of the memory controller selecting a proper number of physical units from the second group having the smallest interval of values of the number of times of erasing as the first physical unit includes: the memory controller further grouping the second group having the smallest interval of values of the number of times of erasing according to error bit values of the physical units, to obtain a plurality of subgroups based on having the same interval of values of the number of times of erasing but different intervals of values of error bits; and the memory controller selecting a physical unit having the smallest number of times of erasing and the smallest error bit value from the subgroup having the smallest interval of values of the number of times of erasing and the smallest interval of values of error bits as the first physical unit.

[0030] Based on the above, the present application provides a memory management method, a memory controller and a memory storage device, which groups the plurality of physical units according to the number of erasures of the physical units, to obtain a plurality of first groups, each of the first groups corresponding to a read interference threshold value; records the physical units in each of the first groups whose read frequency exceeds the read interference threshold value as target physical units; and copies the first data in the target physical units to the physical unit with the smallest operation value in the memory module. In this way, the number of data movement caused by the rapid accumulation of the read frequency of the physical units can be reduced, thereby improving the system performance of the memory storage device.

[0031] In order to make the above technical features and beneficial effects of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present application;

[0033] Figure 2 A structural block diagram of a memory controller according to an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a memory module according to an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a memory module according to an embodiment of the present application;

[0036] Figure 5 A schematic diagram of a first physical unit read frequency according to an embodiment of the present application;

[0037] Figure 6 A schematic diagram of a physical unit erasure frequency table according to an embodiment of the present application;

[0038] Figure 7 A schematic diagram of different erasure frequency value intervals and different read interference threshold values of a physical unit according to an embodiment of the present application;

[0039] Figure 8 A schematic diagram of a memory module according to an embodiment of the present application;

[0040] Figure 9 A schematic diagram of a second physical unit read frequency according to an embodiment of the present application;

[0041] Figure 10 A schematic diagram of a memory module according to an embodiment of the present application;

[0042] Figure 11 A schematic diagram of a bad block table according to an embodiment of the present application;

[0043] Figure 12 A schematic diagram of a second group being divided into subgroups for management according to an embodiment of the present application;

[0044] Figure 13 A flowchart of a memory management method according to an embodiment of the present application DETAILED DESCRIPTION

[0045] The specific structure and implementation scheme of the memory storage device according to the embodiments of the present application will be described in detail below in combination with the accompanying drawings and cases.

[0046] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present application. Please refer to Figure 1 , the storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example, the host system 11 can be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, or various electronic systems. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 can include a solid state disk, a USB flash drive, a memory card, or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCI Express), a universal serial bus (USB), or other types of connection interfaces. Therefore, the host system 11 can store data to and / or read data from the memory storage device 12.

[0047] The memory storage device 12 can include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 can support a SATA, a PCI Express, or a USB connection interface standard. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0048] The memory module 122 is used to store data. The memory module 122 can include a rewritable non-volatile memory module. The memory module 122 includes an array of memory cells. The memory cells in the memory module 122 store data in the form of voltage. For example, the memory module 122 can include a Single Level Cell (SLC) NAND type flash memory module, a Multi Level Cell (MLC) NAND type flash memory module, a Triple Level Cell (TLC) NAND type flash memory module, a Quad Level Cell (QLC) NAND type flash memory module, or other memory modules with similar characteristics.

[0049] Further, SLC (Single Level Cell) is the full name of Single-Level Cell, single-layer electronic structure, each cell can store 1 bit of data, SLC reaches 1 bit / cell, the voltage change interval is small when writing data, the P / E life is longer, and the theoretical erasing times are more than 100,000 times; MLC (Multi-Level Cell) is the full name of Multi-Level Cell, which uses high and low voltage to build different double-layer electronic structures, MLC reaches 2 bits / cell, the P / E life is longer, and the theoretical erasing times are about 3,000-5,000 times; TLC (Trinary-Level Cell) is the full name of Trinary-Level Cell, which is a three-layer storage unit, an extension of MLC flash memory, TLC reaches 3 bits / cell, and since the storage density is higher, the capacity is theoretically 1.5 times that of MLC, and the cost is lower, but the P / E life is relatively lower, and the theoretical erasing times are different, ranging from 1,000 to 3,000 times; QLC (Quad-Level Cell) is the full name of Quad-Level Cell, which is a four-layer storage unit, and QLC flash memory particles have higher storage density than TLC, and the cost is lower than TLC, the advantage is that the capacity can be larger, and the cost is lower, the disadvantage is that the P / E life is shorter, and the theoretical erasing times are only 150 times.

[0050] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 can include a central processing unit (CPU), or other programmable general purpose or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or a combination thereof.

[0051] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access memory cells according to the sequence of instructions.

[0052] Figure 2 is a block diagram of a memory controller according to one embodiment of the present application. Please refer to Figure 2 The memory controller 123 includes a memory control circuit 204, a host interface 202, and a memory interface 206.

[0053] The memory control circuit 204 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 204 has a plurality of control instructions, and these control instructions are executed to perform data write, read, and erase operations, etc. when the memory storage device 12 is operated. The following description of the operation of the memory control circuit 204 is equivalent to the description of the operation of the memory controller 123.

[0054] In the present embodiment, the control instructions of the memory control circuit 204 are operated in firmware. For example, the memory control circuit 204 has a microprocessor unit (not shown in Figure 2 ) and a read-only memory (not shown in Figure 2 ), and the control instructions are burned into the read-only memory. When the memory storage device 12 is operated, the control instructions are executed by the microprocessor unit to perform data write, read, and erase operations, etc.

[0055] In another embodiment, the control instructions of the memory control circuit 204 can also be stored in a program code form in a specific area of the memory module 122 (e.g., a system area of the memory module dedicated for storing system data). In addition, the memory control circuit 204 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory controller 123 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the memory module 122 into the random access memory of the memory control circuit 204. Then, the microprocessor unit executes these control instructions to perform the write, read, and erase operations of data, etc.

[0056] In addition, in another embodiment, the control instructions of the memory control circuit 204 can also be operated in a hardware form. For example, the memory control circuit 204 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of the memory module 122. The memory write circuit is used to issue a write instruction sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a read instruction sequence to the memory module 122 to read data from the memory module 122. The memory erase circuit is used to issue an erase instruction sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit is used to process the data to be written into the memory module 122 and the data read from the memory module 122. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the memory module 122 to perform corresponding write, read, and erase operations, etc. In an embodiment, the memory control circuit 204 can also issue other types of instruction sequences to the memory module 122 to instruct the performance of corresponding operations.

[0057] The host interface 202 is electrically connected to the memory control circuit 204 and is used to receive instructions and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 204 through the host interface 202. In the present embodiment, the host interface 202 is compatible with the SATA standard. However, it must be understood that the present application is not limited thereto, and the host interface 202 can also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0058] The memory interface 206 is electrically connected to the memory control circuit 204 and is used to access the memory module 122. That is, data intended to be written into the memory module 122 is converted into a format acceptable to the memory module 122 via the memory interface 206. Specifically, if the memory control circuit 204 wants to access the memory module 122, the memory interface 206 transmits corresponding instruction sequences. For example, these instruction sequences can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing a read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated, for example, by the memory control circuit 204 and transmitted to the memory module 122 through the memory interface 206. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identifier, a memory address, etc. is included.

[0059] In the present embodiment, the memory controller 123 can perform single-frame encoding for data stored in the same physical program cell, or multi-frame encoding for data stored in multiple physical program cells. According to the encoding algorithm adopted, the memory controller 123 can encode the data to be protected to generate corresponding error correction codes and / or error check codes.

[0060] In one embodiment, the memory controller 123 further includes a buffer memory 210, an error checking and correction circuit 212, and a power management circuit 208. The buffer memory 210 is electrically connected to the memory control circuit 204 and is used to temporarily store data and instructions from the host system 11 or data from the memory module 122. The power management circuit 208 is electrically connected to the memory control circuit 204 and is used to control the power supply to the memory storage device 12. The error checking and correction circuit 212 is electrically connected to the memory control circuit 204 and is used to perform error checking and correction operations to ensure data integrity.

[0061] Specifically, when the memory control circuit 204 receives a write command from the host system 11, the error checking and correction circuit 212 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command. The memory control circuit 204 then writes the data corresponding to the write command along with the corresponding error correcting code and / or error detecting code into the memory module 122. Subsequently, when the memory control circuit 204 reads data from the memory module 122, it simultaneously reads the corresponding error correcting code and / or error detecting code. The error checking and correction circuit 212 then performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0062] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of the present invention. Please refer to... Figure 3 The memory module 122 includes multiple physical units 301(0)--301(A). Each physical unit includes multiple storage cells for non-volatile data storage. For example, a physical unit may include one or more physical blocks. Each physical block may include multiple physical programming units. A physical programming unit may include one or more storage cells. Multiple storage cells in a physical programming unit can be programmed simultaneously to store data. Furthermore, all physical programming units in a physical unit can be erased simultaneously.

[0063] Furthermore, such as Figure 3As shown, the memory control circuit 204 can configure the plurality of logical units 302(0)-302(B) to map the physical units 301(1)-301(A). For example, one logical unit can be composed of one or more logical addresses. The mapping relationship between the logical units and the physical units can be recorded in a logical-to-physical mapping table (L2P). Exemplarily, the mapping of a logical physical unit to a physical physical unit is referred to as block mapping; the mapping of a logical physical programmed unit to a physical physical programmed unit is referred to as physical programmed unit (page) mapping. Hereinafter, the logical-to-physical mapping table can be understood as a logical-to-physical mapping table. When receiving an access instruction from the host system 11, the memory control circuit 204 can access data to the physical units according to the corresponding logical-to-physical mapping table.

[0064] Figure 4 is a schematic diagram of managing a memory module according to an embodiment of the present application. Further, as shown in Figure 4 In an embodiment, the memory control circuit 204 logically groups the physical units 301(0)-301(A) into a data area 506, a spare area 504, a system area 502, and a replacement area 508.

[0065] It must be understood that when describing the operation of the physical units of the memory module 122 in this embodiment, the physical units are operated by means of "extracting", "grouping", "dividing", "associating", etc. in a logical sense. That is, the actual positions of the physical units of the memory module 122 are not changed, but the physical units of the memory module 122 are logically operated.

[0066] The physical units logically belonging to the data area 506 and the spare area 504 are used to store data from the host system 11. Specifically, the physical units of the data area 506 are regarded as physical units having stored data, and the physical units of the spare area 504 are used to replace the physical units of the data area 506. That is, when receiving a write instruction and data to be written from the host system 11, the memory control circuit 204 extracts a physical unit from the spare area 504 to write the data, and the physical unit having written data is then divided from the spare area 504 to the data area 506 and is no longer divided into the spare area 504. When receiving a read instruction and data to be read from the host system 11, the memory control circuit 204 reads data from the physical units in the data area 506 according to the corresponding logical-to-physical mapping table.

[0067] In particular, the data area 506, the spare area 504, the system area 502 and the replacement area 508 each include one or more physical units. The physical units in the data area 506 are physical units that are considered to have stored valid data. The physical units in the spare area 504 also store data, but the data is invalid data. Having data (even invalid data) in the physical units prevents leakage of the physical units and effectively improves the life of the physical units or the memory module 122. When the physical units in the spare area 504 are needed later, the data (invalid data) in the physical units is erased and new data is written into the physical units.

[0068] The physical units logically belonging to the system area 502 are used to record system data. For example, the system data includes information about the manufacturer and model of the memory module 122, the number of physical units of the memory module 122, the number of physical program units of each physical unit, etc. In particular, the system area 502 is used to store a logical-to-physical mapping table, a read count table, an erase count table of the physical units, and a bad block table of the physical units.

[0069] The physical units logically belonging to the replacement area 508 are used in a bad physical unit replacement program to replace damaged physical units. In particular, if there are still normal physical units in the replacement area 508 and the physical units in the data area 506, the spare area 504, and the system area 502 are damaged, the memory control circuit 204 replaces the damaged physical units in the data area 506, the spare area 504, and the system area 502 with normal physical units from the replacement area 508.

[0070] Further, the number of physical units in the data area 506, the spare area 504, the system area 502, and the replacement area 508 varies according to different memory specifications. In addition, it must be understood that the grouping relationship of the physical units associated with the data area 506, the spare area 504, the system area 502, and the replacement area 508 dynamically changes during operation of the memory storage device 12. For example, when the physical units in the spare area 504 are damaged and replaced by physical units from the replacement area 508, the physical units originally in the replacement area 508 are then associated with the spare area 504.

[0071] Furthermore, the physical units in data area 506 are considered to be physical units that have already stored data, while the physical units in idle area 504 are physical units used to store new data. When physical units that have been written with new data are allocated to data area 506, they become physical units in data area 506. That is, when a write command and data to be written are received from the host system 11, the memory control circuit 204 will extract physical units from idle area 504 according to the corresponding logic-to-physical mapping table to write data, and update the area relationship of the physical units, that is, the physical unit that originally belonged to idle area 504 to store new data becomes a physical unit in data area 506. When a read command and data to be read are received from the host system 11, the memory control circuit 204 will read data from the physical units in data area 506 according to the corresponding logic-to-physical mapping table.

[0072] Each physical unit has a threshold limit for the number of reads. As the memory storage device 10 is used, the number of reads for some physical units may reach their read interference threshold limit, requiring data migration operations to be performed on the data in these physical units, i.e., moving it to a new physical unit. This is to ensure the stability of the data stored in the memory module 122.

[0073] Based on this, in one embodiment, the memory control circuit 204 establishes and maintains a physical cell read count table (also referred to as the first read count table, Table 1), such as Figure 5 As shown. Figure 5 This is a schematic representation of the number of times an entity cell is read, as shown in an embodiment of the present invention. Figure 5 In this code, H represents the number of reads for entity cells 301(C)--301(D), where 301(C) represents entity cell number C. Hc represents the number of reads for entity cell number c. After executing a read instruction for a specific entity cell, the memory control circuit 204... Figure 5 The number of reads for the entity unit with that sequence number is incremented by 1 to achieve [the desired result]. Figure 5 Maintenance. Preferably, the table of times the entity unit is accessed can be stored in the system area.

[0074] Preferably, in one embodiment, the memory control circuit 204 sorts the entity units in the read count table according to the number of reads, wherein the entity unit with the higher read count has a higher ranking. Preferably, the entity units with higher rankings are arranged in... Figure 5 The header of the table facilitates the selection of entity units based on the number of reads later. Figure 5 The system uses the header of the read count table to select the required entity unit. This makes the entity unit selection operation faster.

[0075] In one embodiment, the memory control circuit 204 further establishes and maintains a physical block erase count table (P / E table) to record the usage of the physical blocks in the memory module 122. The P / E table records the erase count of all physical blocks in the memory module 122, as shown in Figure 6 Figure 6 In the table, M in 301 (M) represents the serial number of the physical block 301, and N represents the erase count of the physical block 301 (M). The physical block erase count table can be stored in the system area.

[0076] Preferably, in one embodiment, the memory control circuit 204 sorts the plurality of physical blocks according to the erase count of the physical blocks. The memory control circuit 204 arranges the sorted plurality of physical blocks in the erase count table in the order of the serial number of the physical block with the smallest erase count, so as to facilitate the selection of the physical block from the erase count table in the future. This can improve the speed of selection of the physical block. Figure 7

[0077] Further, in one embodiment, the memory control circuit 204 further establishes and maintains an erase count and read disturb threshold table, as shown in Figure 7 . Figure 7 In the table, the relationship between the erase count and the read disturb threshold can be different for different memory blocks. For a single-layer memory block NAND flash memory module, the read disturb threshold decreases as the erase count increases. On the other hand, for a multi-layer memory block NAND flash memory module, the read disturb threshold first increases and then decreases as the erase count increases.

[0078] Further, in one embodiment, the memory control circuit 204 groups the plurality of physical blocks in the data area 506 according to the erase count of the physical blocks, to obtain a plurality of first groups. Each first group corresponds to a different erase count value interval; each first group can include one or more physical blocks, and each physical block can only belong to one first group at a certain time period; and the erase count value interval of each first group is different.

[0079] From Figure 7 ​​As can be seen, the erasing times of the physical units are different, and the corresponding read interference threshold values (K) are also different. The physical units in the memory module 122 are managed in groups, each first group has a corresponding read interference threshold value K, such as K1, K2, K3, … Instead of using one read interference threshold value K to manage all physical units in the memory module 122, this can improve the accuracy of physical unit management and improve the system performance of the memory storage device 12. Specifically, some physical units with small erasing times can have a larger read interference threshold value, reducing the number of data migration operations on such physical units. Some physical units with large erasing times can have a smaller read interference threshold value than physical units with small erasing times, increasing the number of data migration operations on such physical units.

[0080] Further, in an embodiment, the memory control circuit 204 further sets each first group with a read interference monitoring value (W), which is less than the read interference threshold value (K). Each K1 corresponds to a W1. Specifically, the step of recording physical units with read counts greater than K in each first group as target physical units includes: first recording physical units with read counts greater than W1 as risk physical units, and then recording risk physical units with read counts greater than K1 as target physical units. The same applies to each first group.

[0081] For example, referring to Figure 8 As shown, Figure 8 A plurality of different first groups are constructed according to different erasing time value intervals of the physical units, and each first group has a different read interference threshold value. The memory module 122 includes 2000 physical units, B0-B1999. The number of physical units in the first group 41(0) with erasing times of 0-50 is 500, the number of physical units in the first group 41(1) with erasing times of 51-150 is 600, the number of physical units in the first group 41(2) with erasing times of 151-500 is 300, the number of physical units in the first group 41(3) with erasing times of 501-1000 is 400, and the number of physical units in the first group 41(4) with erasing times of 1001-5000 is 200. According to the erasing time interval value, a plurality of first groups are divided, and each first group has a corresponding read interference threshold value K. Figure 8 As can be seen, the read interference threshold value K1 is less than K2, K1 is less than K3, K1 is less than K4, and K1 is greater than K5. The read interference monitoring value W1 is less than W2, W1 is less than W3, W1 is less than W4, and W1 is greater than W5.

[0082] Further, in an embodiment, further,Figure 5 The read counts of the physical units in Table 1 are sorted according to the read counts, and the higher the read count, the higher the rank of the physical unit. However, when the read counts of the physical units reach W (the read interference monitoring value), these physical units are removed from Table 1 in Figure 5 and placed in Table 2 (also referred to as the second read count table) for management, Figure 5 Table 1 in Table 1 is no longer managed. In other words, Table 2 is used to maintain and manage the read counts that exceed W and / or K.

[0083] In an embodiment, the physical units with read counts greater than W are marked as risk physical units and removed from Table 1 in Figure 5 and recorded in Table 2 in Figure 9 Further, the physical units with read counts exceeding the read interference threshold value in the risk physical units are recorded as second physical units. Specifically, Figure 9 Table 2 in Table 2 also records the first read time value T of the second physical units, as shown in Figure 9 Table 2 maintains and manages not only the read counts that exceed W and / or K, but also the first read time value T of the second physical units, T being the time interval from the most recent read to the present, and the second physical units are sorted according to the first read time value, and the smaller the first read time value, the higher the rank of the second physical unit.

[0084] Compared with using one read count table to record and maintain the read counts of all physical units, the embodiment uses two read count tables to record and maintain the read counts of the physical units, and in particular, the physical units in Table 2 are all physical units with read counts exceeding W, so that in subsequent screening of target physical units, the physical units can be selected according to the K value and / or the T value in Table 2, which makes the operation of selecting the target physical units faster.

[0085] In an embodiment, the read disturb threshold is a probability value. Instead of performing data migration on the entity cell whose read count exceeds the read disturb threshold, the entity cell whose read count exceeds the read disturb threshold is recorded as a second entity cell. Then, a first read time value of the second entity cell is obtained. The second entity cell whose first read time value is not greater than a first threshold is recorded as a target entity cell. By adding a judgment of whether the first read time value of the second entity cell is not greater than the first threshold, the selection range of the target entity cell is reduced, and the number of times of performing data migration on the entity cell is reduced. The target entity cell finally selected is the entity cell that really needs to be performed data migration. In an embodiment, the first threshold is a variable threshold, which can be set as 1S, 1M, etc. In another embodiment, the first threshold is an invariable threshold, which can be set as 1S or 1M, etc. In this embodiment, no limitation is made. The purpose of the first threshold is to determine or select the entity cell whose read count exceeds K and is read recently.

[0086] Further, in an embodiment, a method for selecting a target entity cell from the second entity cell and recording the selected entity cell as the target entity cell by the memory control circuit 204 is provided. Specifically, the memory control circuit 204 obtains a second read time value of a first entity program cell of the second entity cell, and records the second entity cell whose second read time value is greater than a second threshold as a target entity cell. The second read time value is a time of successfully reading data stored in the first entity program cell in response to a data read instruction.

[0087] Further, in another embodiment, the step of obtaining the second read time value of the first entity program cell of the second entity cell and recording the second entity cell whose second read time value is greater than the second threshold as the target entity cell further comprises: obtaining a third read time value of a second entity program cell of the second entity cell, and recording the second entity cell whose third read time value is greater than the second threshold as the target entity cell. The third read time value is a time of successfully reading data stored in the second entity program cell in response to a data read instruction. The first entity program cell and the second entity program cell belong to the same entity cell.

[0088] In an embodiment, the second threshold is a variable threshold, which can be set as 0.1mS, 0.01mS, etc. In another embodiment, the second threshold is an invariable threshold, which can be set as 0.1mS, or 0.01mS, etc. In this embodiment, no limitation is made. The purpose of the second threshold is to determine or select the time of reading data in some entity program cells.

[0089] Exemplarily, one entity unit includes 200 entity programing, the first entity programing unit is P0, and the second entity programing unit is P199. By detecting the reading time of two entity programing units in the same risk entity unit, the detection or screening of the target entity unit is more accurate.

[0090] Further, on this basis, the number of entity programing units in the same risk entity unit can be increased, such as a third entity programing unit or more entity programing units.

[0091] In an embodiment, the even or odd numbered entity programing units in the same risk entity unit are detected.

[0092] In another embodiment, the entity programing unit with serial number "0" in the same risk entity unit is detected. For example, P0, P10, P20, and the like.

[0093] The above-mentioned limitation of the first entity programing unit and the second entity programing unit is to improve the representativeness of the target entity unit selected in the second entity unit. That is, the target entity unit that should be executed the data migration operation is selected.

[0094] In another embodiment, the first entity programing unit and the second entity programing unit belong to different word lines.

[0095] Exemplarily, if the number of second entity units is 100 entity units, 20 entity units need to be selected as target entity units from the 100 entity units. The reading time (referred to as the second reading time value) of some entity programing units (referred to as the first entity programing unit) in the 100 entity units is judged. If the reading time of some entity programing units (the first entity programing unit) is greater than the second threshold value, based on the principle of Nand Flash storage data, it can be known that the process of reading data in these entity programing units has undergone a re-reading operation or has undergone a long ECC decoding operation; thereby causing the time spent on reading data in these entity programing units to be longer than that of other entity programing units. It can be judged that the entity unit to which these entity programing units belong can be identified as a target entity unit. The data stored thereon needs to be subjected to a data migration operation. On the one hand, this improves the data reading speed of the memory storage device 12, and on the other hand, it ensures the safety and stability of the data stored in the memory module 122.

[0096] In another embodiment, the first and / or second entity programmed cells are entity programmed cells in the second entity unit that store valid data.

[0097] Further, after the recording or selection of the target entity unit is completed, the memory control circuit 204 needs to perform a data migration operation on the target entity unit. In one embodiment, the data migration operation is to copy valid data (first data) in the target entity unit to the first entity unit, while invalid data (second data) in the entity unit is not subject to the data migration operation. After the data migration operation is performed on the first data, the entity unit that originally stores the first data (i.e., the target entity unit) is marked to indicate that the data stored in one or more entity programmed cells in the entity unit is invalid data. If all the data stored in the entity programmed cells in the entity unit is invalid data, the entity unit is then reclassified from the data area 506 to the spare area 504.

[0098] In one embodiment, the first entity unit is the entity unit with the smallest operation value in the memory module 122. In relation to the first entity unit being the entity unit with the smallest operation value in the memory module 122, in one embodiment, the operation value can be considered as the number of erasures. That is, the entity unit with the smallest operation value can be considered as the entity unit with the smallest number of erasures.

[0099] Preferably, in one embodiment, the target entity unit is an entity unit in the data area 506, and the entity unit with the smallest number of erasures is selected from the spare area 504.

[0100] Further, in another embodiment, a method of managing entity units in the spare area 504 is proposed to provide a first entity unit as required.

[0101] Specifically, the memory control circuit 204 divides multiple physical units in the idle area 504 into groups based on the number of erasures of the physical units, resulting in multiple second groups 51(0)--51(G) [G+1 represents the number of second groups]. Each second group corresponds to a different range of erasure count values. Each second group may contain one or more physical units, and the number of erasures of each physical unit in a certain time period can only belong to one second group. The range of erasure count values ​​for each second group is different. The memory control circuit 204 selects an appropriate number of physical units from the second group with the smallest range of erasure count values ​​to store the first data, based on the amount of first data stored in the target physical unit. Preferably, an appropriate number of physical units with the fewest erasures are selected from the second group with the smallest range of erasure count values ​​to store the first data. Managing the physical units in the memory module 122 by grouping can improve the speed of selecting the first physical units that meet the requirements, thereby improving the speed of data transfer.

[0102] For example, the idle area 504 includes 200 entity units, assuming these 200 entity units are Block 0 to Block 199. These 200 entity units are grouped according to their erase count, resulting in the following... Figure 10 The four groups shown are 51(0), 51(1), 51(2) and 51(3). Figure 10 This is a schematic diagram illustrating how multiple entity units are grouped according to the number of times they are erased, resulting in multiple second groups, each corresponding to a different range of erase count values, as shown in an embodiment of the present invention.

[0103] Specifically, such as Figure 10 As shown, the group number with the smallest range of erasure counts is 51(0). The erasure count range of group 51(0) is 0-200, which includes 50 entity units. The erasure count details of these 50 entity units are as follows: 30 entity units with an erasure count of 80 times, 10 entity units with an erasure count of 120 times, and 10 entity units with an erasure count of 180 times. If the number of first entity units is 2, then 2 entity units are selected from the 30 entity units with an erasure count of 80 times as the first entity units.

[0104] Furthermore, in another embodiment, the selection operation of the first entity unit further includes: the memory control circuit 204 selecting the entity unit with the smallest number of erases and the smallest error bit value from the subgroup with the smallest number of erases and the smallest error bit value as the first entity unit.

[0105] Specifically, the memory control circuit 204 further groups the second group with the minimum erasing number value interval according to the error bit value of the physical unit, to obtain a plurality of subgroups based on having the same erasing number value interval but different error bit value intervals; wherein each subgroup can contain one or more physical units and each physical unit can only belong to a certain subgroup in a certain time period; each subgroup can belong to the same erasing number value interval but correspond to different error bit value intervals respectively; the number of physical units contained in each subgroup can be the same or different; the memory control circuit 204 selects the physical unit with the minimum erasing number and the minimum error bit value from the subgroup with the minimum erasing number value interval and the minimum error bit value interval as the first physical unit.

[0106] For example, the error bit number of the physical unit can be obtained from the bad block table (saved in the system area), as shown in Figure 11 . Figure 11 In the table, F in 301(F) represents the serial number of the physical unit 301, and S represents the error bit number of the physical unit 301(F).

[0107] For example, the memory control circuit 204 obtains the error bit number of each physical unit in the group 51(0), and further groups the group 51(0) according to the error bit number of each physical unit, to obtain a plurality of subgroups based on having the same erasing number value interval but different error bit value intervals, as shown in Figure 12 . Figure 12 The schematic diagram of further grouping the second group with the minimum erasing number value interval according to the error bit value of the physical unit to obtain a plurality of subgroups based on having the same erasing number value interval but different error bit value intervals according to an embodiment of the present application.

[0108] Specifically, Figure 11 In the table, the erasing number of Block 15 and Block 17 is the minimum, and the error bit value is also the minimum. Therefore, Block 15 and Block 17 are selected as the first physical unit.

[0109] Further, in another embodiment, the memory control circuit 204 selects a proper number of physical units as the first physical unit according to the size of the first data. Specifically, the memory control circuit 204 selects a proper number of physical units as the first physical unit from the second group with the smallest number of erasing times according to the size of the first data. Further, the memory control circuit 204 selects a physical unit with the smallest number of erasing times and the smallest number of error bits from the sub-group with the smallest number of erasing times and the smallest number of error bits as the first physical unit according to the size of the first data.

[0110] It should be noted that the above-mentioned operation of the physical units in the memory module in the description of the operation of the physical units in the memory module is a logical concept. That is, the actual positions of the physical units in the memory module 122 are not changed, but the physical units in the memory module 122 are logically operated.

[0111] In an embodiment, the above-mentioned sorting algorithm can be any one of the insertion sort, the hill sort, the selection sort, the bubble sort, the quick sort, the merge sort, the counting sort, and the bucket sort.

[0112] In an embodiment, the logical-to-physical mapping relationship of the first data is updated according to the physical address of the first physical unit. Since the data migration operation is performed on the target physical unit, the physical address of the first data is changed from the physical address of the original target physical unit to the physical address of the first physical unit. That is, the physical address of the first data is changed. For example, the first logical address is mapped to the first physical address, the first physical address is the original physical address of the first data, and the physical address of the first data is now the second physical address. Then, the memory control circuit 204 removes the mapping relationship between the first logical address and the first physical address, and the memory control circuit 204 re-establishes the mapping relationship between the first logical address and the second physical address. The second physical address is the new physical address of the first data. It is also the physical address of the first physical unit.

[0113] In an embodiment, after the memory control circuit 204 selects the first physical unit, the memory control circuit 204 further copies the first data in the target physical unit to the first physical unit.

[0114] The memory control circuit 204 first performs an erasing operation on the first physical unit, erases the data (invalid data) in the first physical unit, and then writes the first data into the first physical unit.

[0115] Figure 13 is a flowchart of a memory management method according to an embodiment of the present application.

[0116] Please refer to Figure 13 In step S100, the plurality of physical units are grouped according to the erase times of the physical units, and a plurality of first groups are obtained, each of the first groups corresponding to a read disturb threshold. In step S200, the physical units whose read times exceed the read disturb threshold in each of the first groups are recorded as target physical units. In step S300, the first data in the target physical units are copied to a first physical unit, and the first physical unit is the physical unit with the minimum operation value in the memory module.

[0117] However, Figure 13 The steps in the above embodiment have been described in detail, and will not be repeated here. It is worth noting that, Figure 13 The steps in the above embodiment can be implemented as a plurality of codes or circuits, and the present application is not limited thereto. In addition, Figure 13 The method can be used in combination with the above example embodiments, or can be used alone, and the present application is not limited thereto.

[0118] In summary, the present application provides a memory management method, a memory controller, and a memory storage device. The plurality of physical units are grouped according to the erase times of the physical units, and a plurality of first groups are obtained, each of the first groups corresponding to a read disturb threshold. The physical units whose read times exceed the read disturb threshold in each of the first groups are recorded as target physical units. After the target physical units are selected, a data migration operation is performed on the first data. A method for selecting a first physical unit from the idle area 504 of the memory module 122 to store the first data is also proposed. Specifically, the first physical unit is the physical unit with the minimum operation value in the memory module 122. Further, the physical unit with the minimum operation value can be understood as the physical unit with the minimum erase time. Since the smaller the erase time of the physical unit is, the larger the read disturb threshold is, the number of times that the first data is subjected to the data migration operation can be reduced, thereby reducing the erase times of the physical unit storing the first data, and further improving the service life of the memory storage device.

[0119] Further, the physical unit with the minimum operation value can be understood as the physical unit with the minimum erase time and the minimum error bit value selected from the sub-group with the minimum erase time and the minimum error bit value. The first data is migrated (copied) to the physical unit with the smaller error bit value, which on the one hand improves the safety and stability of data storage in the memory storage device, and on the other hand improves the speed of reading the first data, thereby improving the system performance of the memory storage device.

[0120] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method applied to a memory storage device, characterized in that, The memory storage device includes a memory module, the memory module includes a plurality of physical units, the physical units include a plurality of physical programming units, and the method includes: Dividing a plurality of physical units in the memory module into a data area and an idle area, grouping a plurality of physical units in the data area and the idle area according to the number of erasures of the physical units, obtaining a plurality of first groups and a plurality of second groups, each of the first groups corresponding to a read interference threshold value, each of the first groups and the second groups corresponding to different erasure value intervals, and further grouping the second group with the smallest erasure value interval according to the error bit value of the physical unit to obtain a plurality of subgroups based on the same erasure value interval but different error bit value intervals; Recording the physical units in each of the first groups with the number of readings exceeding the read interference monitoring value as risk physical units, recording the physical units in the risk physical units with the number of readings exceeding the read interference threshold value as second physical units, obtaining a first reading time value of the second physical units, and recording the second physical units with the first reading time value not greater than a first threshold value as target physical units, wherein the step of selecting the target physical units from the second physical units includes: obtaining the reading time values of at least two physical programming units belonging to the same physical unit, recording the second physical units with the reading time values all greater than a second threshold value as the target physical units, and selecting two physical programming units from the same physical unit according to any of the following logical standards: selecting the physical programming units with serial numbers at the beginning and end positions in the physical unit, selecting the physical programming unit with a serial number of "0", or selecting the physical programming unit with an even or odd serial number; According to the size of the data amount in the target physical unit, selecting the physical unit with the smallest number of erasures and the smallest error bit value from the subgroups as a first physical unit, performing an erasure operation on the first physical unit, and copying the first data in the target physical unit to the first physical unit, wherein the first physical unit is the physical unit with the smallest operation value in the memory module.

2. The memory management method of claim 1, wherein, Further comprising: The read interference monitoring value is less than the read interference threshold value.

3. The memory management method of claim 1, wherein, The steps of obtaining the number of readings of the plurality of physical units and obtaining the first reading time value of the second physical units include: Establishing a first reading frequency table and a second reading frequency table; The first reading frequency table is used to record the number of readings not greater than the read interference monitoring value, and the physical units in the first reading frequency table are sorted according to the number of readings, wherein the greater the number of readings, the higher the sorting of the physical units; The second read number table is used to record the read number exceeding the read disturb monitoring value and / or the read disturb threshold value, and also record the first read time value of the second entity unit, the first read time value being the time interval from the last time the second entity unit is read to the present time, and the risk entity unit is sorted according to the first read time value, wherein the smaller the first read time value is, the higher the sorting of the second entity unit is.

4. The memory management method of claim 1, wherein, Further comprising: The read time value of the at least two entity programmed entity units is the time of successfully reading the data stored in the at least two entity programmed units in response to the data read instruction.

5. The memory management method of claim 1, wherein, Further comprising: Marking the data in the target entity unit as invalid data or dividing the target entity unit into the idle area; Dividing the first entity unit into the data area.

6. A memory controller for controlling a memory module, wherein the memory module comprises a plurality of physical units, the physical units comprising a plurality of physical program units; the memory controller comprising: A host interface connected to a host system; a memory interface connected to the memory module; A memory control circuit connected to the host interface and the memory interface; characterized in that the memory control circuit is used to execute each step in the memory management method of any one of claims 1 to 5.

7. A memory storage device, the memory storage device comprising a connection interface, a memory module and a memory controller; the connection interface is configured to connect the memory storage device to a host system; the memory module comprises a plurality of physical units, the physical units comprise a plurality of physical program units; the memory controller is connected to the connection interface and the memory module; characterized in that, The memory controller is used to execute each step in the memory management method of any one of claims 1 to 5.

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