Critical path replication method and apparatus

Abstract

The application discloses a kind of critical path replication method and device, wherein the method comprises: according to the critical path timing report of chip, determine the critical path information of chip;According to critical path information, construct critical path topology structure;By inserting inverter in each node of critical path topology structure, the fan-out of each node in critical path topology structure is calibrated, and first critical path copy is obtained;By inserting NAND gate at the end of first critical path copy, the timing of first critical path copy is calibrated, and second critical path copy is obtained;The NAND gate inserted at the end of second critical path copy is increased or decreased until the delay of the layout of second critical path copy is greater than or equal to the delay of critical path information.The application can improve the tracking accuracy of critical path copy, reduce the delay error of critical path copy, improve the accuracy of chip critical path replication, and more accurately track the timing state of chip.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and in particular to a critical path replication method and apparatus. Background Technology

[0002] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] With the advent of the era of ubiquitous intelligence, various smart devices have entered people's lives. Many of these portable devices are limited by their operating environment and battery capacity, making energy consumption one of the most critical indicators. Designing highly energy-efficient chips has become a goal pursued by chip designers. A chip's energy efficiency is strictly dependent on its operating voltage and clock frequency. In practical applications, chips typically need to operate over a wide voltage range, and it is desirable to minimize the chip's timing margin to maximize its performance.

[0004] In practical chip applications, in order to accurately track the timing status of the chip, it is usually necessary to build a copy of the chip's critical timing path to monitor and track the chip's timing status.

[0005] Traditional methods for constructing critical timing paths in chips include inverter chaining and buffer chaining. However, the critical path replicas obtained using these methods often fail to track the critical path effectively due to significant topological differences from the actual critical path, exhibiting drawbacks such as low tracking accuracy and narrow voltage adaptability. Summary of the Invention

[0006] This invention provides a critical path replication method to improve the tracking accuracy of critical path replicas, reduce the delay error of critical path replicas, and improve the accuracy of chip critical path replication. It can more accurately track the timing status of the chip and has a wider voltage adaptability range. The method includes:

[0007] Based on the chip's critical path timing report, the chip's critical path information is determined; the critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node.

[0008] Construct the critical path topology based on the critical path information;

[0009] By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain a first critical path replica; the fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information.

[0010] By inserting a NOR gate at the end of the first critical path copy, the timing of the first critical path copy is calibrated to obtain the second critical path copy; the NOR gates inserted at the end of the second critical path copy are added or removed until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information.

[0011] This invention also provides a critical path replication device to improve the tracking accuracy of critical path copies, reduce the delay error of critical path copies, improve the accuracy of chip critical path replication, and more accurately track the timing status of the chip. It also has a wider voltage adaptability range. The device includes:

[0012] The critical path information determination module is used to determine the critical path information of the chip based on the chip's critical path timing report; the critical path information includes the logic gates traversed by the critical path and the fan-out value of the output node of each logic gate.

[0013] The critical path topology construction module is used to construct the critical path topology based on the critical path information.

[0014] The first calibration module is used to calibrate the fan-out value of each node in the critical path topology by inserting inverters into each node of the critical path topology to obtain a first critical path replica; the fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information.

[0015] The second calibration module is used to calibrate the timing of the first critical path copy by inserting a NOR gate at the end of the first critical path copy to obtain a second critical path copy; the NOR gate inserted at the end of the second critical path copy is added or removed until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information.

[0016] This invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described critical path copying method.

[0017] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described critical path copying method.

[0018] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described critical path copying method.

[0019] In this embodiment of the invention, the critical path information of the chip is determined based on the chip's critical path timing report. The critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. A critical path topology is constructed based on the critical path information. By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. By inserting NOR gates at the end of the first critical path replica, the timing of the first critical path replica is calibrated to obtain a second critical path replica. The NOR gates inserted at the end of the second critical path replica are then adjusted. Until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information, compared with the existing technical solutions where the topology of the critical path copy differs greatly from that of the real critical path, by constructing a critical path topology structure and inserting inverters and NOR gates into the critical path topology structure, the tracking accuracy of the critical path copy can be improved, the delay error of the critical path copy can be reduced, and thus the accuracy of chip critical path replication can be improved, enabling more accurate tracking of the chip's timing state. At the same time, by completely replicating the critical path topology structure and the fan-out values ​​of each node in the critical path, the obtained critical path copy can be made closer to the real critical path, thus obtaining more complete critical path information than traditional methods, giving it a wider voltage adaptation range. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0021] Figure 1 This is a flowchart illustrating a critical path replication method according to an embodiment of the present invention.

[0022] Figure 2 This is a specific example diagram of a critical path replication method in an embodiment of the present invention;

[0023] Figure 3 This is a specific example diagram of a critical path replication method in an embodiment of the present invention;

[0024] Figure 4 This is a specific example diagram of a critical path replication method in an embodiment of the present invention;

[0025] Figure 5This is a schematic diagram of a critical path replication device according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the system composition structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0028] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0029] In the description of this specification, the terms "comprising," "including," "having," and "containing" are open-ended terms, meaning that they include but are not limited to. The terms "an embodiment," "a specific embodiment," "some embodiments," and "for example," etc., refer to specific features, structures, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. The order of steps involved in the various embodiments is used to illustrate the implementation of this application, and the order of steps is not limited and can be adjusted appropriately as needed.

[0030] The acquisition, storage, use, and processing of data in this application all comply with the relevant provisions of national laws and regulations.

[0031] With the advent of the era of ubiquitous intelligence, various smart devices have entered people's lives. Many of these portable devices are limited by their operating environment and battery capacity, making energy consumption one of the most critical indicators. Designing highly energy-efficient chips has become a goal pursued by chip designers. A chip's energy efficiency is strictly dependent on its operating voltage and clock frequency. In practical applications, chips typically need to operate over a wide voltage range, and it is desirable to minimize the chip's timing margin to maximize its performance.

[0032] In practical chip applications, in order to accurately track the timing status of the chip, it is usually necessary to build a copy of the chip's critical timing path to monitor and track the chip's timing status.

[0033] Traditional methods for constructing critical timing paths in chips include inverter chaining and buffer chaining. However, the critical path replicas obtained using these methods often fail to track the critical path effectively due to significant topological differences from the actual critical path, exhibiting drawbacks such as low tracking accuracy and narrow voltage adaptability.

[0034] To address the aforementioned issues, this invention provides a critical path replication method to improve the tracking accuracy of critical path copies, reduce the delay error of critical path copies, and enhance the accuracy of chip critical path replication. This method can more accurately track the timing status of the chip and also has a wider voltage adaptability range. (See [link to previous document]). Figure 1 The method may include:

[0035] Step 101: Determine the critical path information of the chip based on the chip's critical path timing report; the critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node.

[0036] Step 102: Construct the critical path topology based on the critical path information;

[0037] Step 103: By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain the first critical path replica; the fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information.

[0038] Step 104: By inserting a NOR gate at the end of the first critical path copy, the timing of the first critical path copy is calibrated to obtain the second critical path copy; the NOR gates inserted at the end of the second critical path copy are added or removed until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information.

[0039] In this embodiment of the invention, the critical path information of the chip is determined based on the chip's critical path timing report. The critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. A critical path topology is constructed based on the critical path information. By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. By inserting NOR gates at the end of the first critical path replica, the timing of the first critical path replica is calibrated to obtain a second critical path replica. The NOR gates inserted at the end of the second critical path replica are added or removed until the second critical path replica is obtained. The delay of the key path replica layout is greater than or equal to the delay of the critical path information. Compared with existing technologies where the topology of the obtained key path replica differs greatly from that of the real key path, constructing a key path topology structure and inserting inverters and NOR gates into it can improve the tracking accuracy of the key path replica, reduce the delay error of the key path replica, and thus improve the accuracy of chip key path replication, enabling more accurate tracking of the chip's timing state. At the same time, by completely replicating the key path topology structure and the fan-out values ​​of each node in the key path, the obtained key path replica can be closer to the real key path, thus achieving more complete key path information than traditional inverter chains and buffer chains, giving it a wider voltage adaptability range.

[0040] In practice, the critical path information of the chip is first determined based on the chip's critical path timing report. The critical path information includes the logic gates that the critical path passes through and the fan-out value of each logic gate's output node.

[0041] In this embodiment, high-precision circuit simulation tools such as Hspice can be used to simulate the critical path and obtain more accurate delay values ​​for the critical path. The timing report of the critical path can provide the logic gates traversed by the critical path and the fan-out value of each logic gate's output node.

[0042] In one embodiment, before determining the critical path information of the chip based on the chip's critical path timing report, the above method may further include:

[0043] Parasitic parameters are extracted from the chip layout to obtain the chip's parasitic parameter file;

[0044] Static timing analysis is performed based on the chip's back-end netlist and parasitic parameter file to obtain the chip's critical path timing report.

[0045] In one specific embodiment, extracting parasitic parameters from the chip layout to obtain a parasitic parameter file for the chip may include: using a parasitic parameter extraction tool such as StarRC to extract parasitic parameters from the chip layout to obtain a parasitic parameter SPEF file.

[0046] In one specific embodiment, static timing analysis is performed based on the chip's back-end netlist and parasitic parameter file to obtain a critical path timing report for the chip, which may include:

[0047] Import the backend netlist and parasitic parameter files into a transistor-level static timing analysis tool such as NanoTime to perform static timing analysis and obtain a critical path report.

[0048] In the above embodiments, NanoTime has SPICE simulation-level analysis accuracy, which can accurately identify the critical path and export the critical path timing report and the critical path SPICE deck simulation file.

[0049] In practice, the critical path information of the chip is determined based on the chip's critical path timing report. The critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. Based on the critical path information, the critical path topology is constructed.

[0050] In this embodiment, a critical path topology can be constructed using a custom script program based on the critical path information in the time series report.

[0051] In practice, after constructing the critical path topology based on the critical path information, inverters are inserted into each node of the critical path topology to calibrate the fan-out value of each node in the critical path topology, thus obtaining a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information.

[0052] In one embodiment, after constructing the critical path topology, a corresponding number of inverters can be inserted into each node to make the fan-out value (i.e., fan-out load) of each node in the extracted critical path replica the same as the actual critical path.

[0053] See Figure 2 The fan-out value Ni of each node in the intermediate key path replica can be associated with the addition of Ni inverters. Specifically, the number of inverters to be added can be determined based on the fan-out value of each node in the intermediate key path replica.

[0054] In practice, after inserting inverters into each node of the critical path topology to calibrate the fan-out value of each node and obtain the first critical path copy, a NOR gate is inserted at the end of the first critical path copy to calibrate its timing and obtain the second critical path copy. The NOR gates inserted at the end of the second critical path copy are added or removed until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information.

[0055] In one embodiment, the above method may further include:

[0056] Import the copy of the second critical path into the automatic placement and routing tool to obtain the layout of the copy of the second critical path;

[0057] SPICE simulations were performed on the parasitic parameters extracted from the layout of the second critical path replica to determine the delay difference between the layout of the second critical path replica and the critical path information.

[0058] In the above embodiment, after calibrating the timing of the first critical path copy to obtain the second critical path copy, the obtained second critical path copy is only a gate-level netlist. This gate-level netlist can then be imported into an automatic placement and routing tool to obtain the layout of the second critical path copy. Afterwards, parasitic parameters can be extracted from the layout of the obtained second critical path copy, and then SPICE simulation can be performed. After checking the placement and routing, the delay of the critical path copy can be compared with the previously obtained actual critical path delay. Due to the difference in physical information, there will inevitably be a small delay difference between the actual critical path and the critical path after placement and routing.

[0059] In one embodiment, adding or removing NOR gates at the end of the second critical path replica until the layout latency of the second critical path replica is greater than or equal to the latency of the critical path information may include:

[0060] Based on the delay difference, add or remove the NOR gates at the end of the second critical path copy to obtain the modified critical path copy; repeat the above process of obtaining the modified critical path copy until the delay of the modified critical path copy is greater than or equal to the delay of the critical path information.

[0061] In one embodiment, the netlist of the second critical path copy can be modified according to the above-mentioned delay difference, and the new netlist can be imported into the ICC (IC Compiler) for ECO (Engineering Change Order) to rearrange the routing and obtain the modified critical path copy; and the above process can be repeated until the delay of the critical path copy is greater than or equal to the delay of the real critical path.

[0062] In the above embodiments, the logic gates (i.e., the inverters and NOR gates mentioned above) added for calibration and design margins need to be selected. The selection requirements are: the delay of the logic gates is more sensitive to PVT (Process Voltage Temperature) fluctuations, so as to ensure that the critical path copy is always the most critical path in the chip throughout the entire wide voltage operating range.

[0063] The following is a specific embodiment to illustrate the application of the method of the present invention; this embodiment particularly relates to near-threshold / subthreshold digital circuits and adaptive voltage regulation technology. In this embodiment, the core of synchronous digital circuit timing monitoring is accurately monitoring the timing status of critical timing paths in the chip. Accurate identification and extraction of critical paths are the core issues. As shown below, this embodiment of the present invention proposes a method for accurately extracting and copying timing paths, the design flow of which is as follows: Figure 2 As shown. First, the main logic of the target circuit is synthesized and placed and routed to obtain its back-end netlist and layout. Then, the following steps can be performed:

[0064] 1. Use parasitic parameter extraction tools, such as StarRC, to extract parasitic parameters from the layout to obtain parasitic parameter SPEF files.

[0065] 2. Import the backend netlist and parasitic parameter files into the transistor-level static timing analysis tool NanoTime to perform static timing analysis and obtain a critical path report.

[0066] 3. NanoTime has SPICE simulation-level analysis accuracy, which can accurately identify the critical path and export the critical path timing report and the critical path SPICE deck simulation file.

[0067] 4. Use high-precision circuit simulation tools such as Hspice to simulate the critical path and obtain more accurate delay values ​​for the critical path. The timing report of the critical path can provide the logic gates traversed by the critical path and the fan-out value of each logic gate's output node.

[0068] 5. Based on the critical path information in the time series report, use a custom script to construct the critical path topology and insert the appropriate number of inverters into each node, ensuring that the fan-out value of each node in the extracted critical path replica is the same as that of the actual critical path. An example of the appropriate number of inverters to insert can be found in [reference needed]. Figure 3 .

[0069] 6. At this point, having obtained a preliminary copy of the critical path, the difference in delay between the copy and the actual critical path is compared using HSPICE simulation. Then, the critical path copy is calibrated by inserting several NOR2 (two-input NOR gates) at the end, ensuring that the delay of the copy equals the delay of the actual critical path. Examples of the inserted NOR2 gates can be found in [reference needed]. Figure 3 .

[0070] 7. At this point, the critical path copy is only a gate-level netlist. Then, the obtained gate-level netlist is imported into the automatic placement and routing tool to obtain the layout of the critical path copy.

[0071] 8. Then, after extracting parasitic parameters from the obtained critical path copy layout, perform SPICE simulation to check the delay of the critical path copy after placement and routing and compare it with the delay of the real critical path obtained earlier. Due to the difference in physical information, there will inevitably be a small delay difference between the real critical path and the critical path after placement and routing.

[0072] 9. Based on the delay difference, modify the critical path copy netlist and import the new netlist into ICC to perform ECO (Engineering Change Command), rearrange the routing, and obtain a new critical path copy layout.

[0073] 10. Repeat the above process until the delay of the critical path replica is greater than or equal to the delay of the actual critical path. The logic gates added for calibration and design margins need to be carefully selected. Their delays should be more sensitive to PVT fluctuations to ensure that the critical path replica remains the most critical path on the chip throughout the entire wide voltage operating range.

[0074] A specific example is provided to compare the method of this invention with several traditional methods for constructing critical path replicas:

[0075] Figure 4 This paper presents a comparison between the method of this invention and several conventional methods for constructing critical path replicas.

[0076] Comparative experiments using SPICE simulations show that the proposed method in this invention yields a more accurate and efficient critical path replica (proposed). Figure 4 Midline 1), compared to the traditional inverter chain (inv, i.e. Figure 4 2) Midline 2) Buffer chain (UDL, i.e. Figure 4 Midline 3) and mixed logic gate chains (mix, i.e. Figure 4 The center line 4) has a smaller delay error. Figure 4 The "Failed point" refers to the point where the delay matching fails; the horizontal axis represents voltage; and the vertical axis represents relative delay error.

[0077] This demonstrates that the critical path copy obtained using the method provided in the embodiments of the present invention can more accurately track the chip timing state.

[0078] Of course, it is understood that there may be other variations of the above detailed process, and all such variations should fall within the protection scope of this invention.

[0079] In this embodiment of the invention, the critical path information of the chip is determined based on the chip's critical path timing report. The critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. A critical path topology is constructed based on the critical path information. By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. By inserting NOR gates at the end of the first critical path replica, the timing of the first critical path replica is calibrated to obtain a second critical path replica. The NOR gates inserted at the end of the second critical path replica are added or removed until the second critical path replica is obtained. The delay of the key path replica layout is greater than or equal to the delay of the critical path information. Compared with existing technologies where the topology of the obtained key path replica differs greatly from that of the real key path, constructing a key path topology structure and inserting inverters and NOR gates into it can improve the tracking accuracy of the key path replica, reduce the delay error of the key path replica, and thus improve the accuracy of chip key path replication, enabling more accurate tracking of the chip's timing state. At the same time, by completely replicating the key path topology structure and the fan-out values ​​of each node in the key path, the obtained key path replica can be closer to the real key path, thus achieving more complete key path information than traditional inverter chains and buffer chains, giving it a wider voltage adaptability range.

[0080] This invention also provides a critical path replication apparatus, as described in the following embodiments. Since the principle by which this apparatus solves the problem is similar to that of the critical path replication method, the implementation of this apparatus can be referred to the implementation of the critical path replication method, and repeated details will not be elaborated further.

[0081] This invention provides a critical path replication device to improve the tracking accuracy of critical path copies, reduce the delay error of critical path copies, and improve the accuracy of chip critical path replication. It can more accurately track the timing state of the chip and also has a wider voltage adaptability range. Figure 5 As shown, the device includes:

[0082] The critical path information determination module 501 is used to determine the critical path information of the chip based on the chip's critical path timing report; the critical path information includes the logic gates traversed by the critical path and the fan-out value of the output node of each logic gate.

[0083] Critical path topology construction module 502 is used to construct the critical path topology based on critical path information;

[0084] The first calibration module 503 is used to calibrate the fan-out value of each node in the critical path topology by inserting inverters into each node of the critical path topology to obtain a first critical path copy; the fan-out value of each node in the first critical path copy is the same as the fan-out value of the corresponding node in the critical path information.

[0085] The second calibration module 504 is used to calibrate the timing of the first critical path copy by inserting a NOR gate at the end of the first critical path copy to obtain a second critical path copy; and to increase or decrease the NOR gate inserted at the end of the second critical path copy until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information.

[0086] In one embodiment, it may further include:

[0087] The critical path timing report determination module is used for:

[0088] Parasitic parameters are extracted from the chip layout to obtain the chip's parasitic parameter file;

[0089] Static timing analysis is performed based on the chip's back-end netlist and parasitic parameter file to obtain the chip's critical path timing report.

[0090] In one embodiment, it may further include:

[0091] The delay difference determination module is used for:

[0092] Import the copy of the second critical path into the automatic placement and routing tool to obtain the layout of the copy of the second critical path;

[0093] SPICE simulations were performed on the parasitic parameters extracted from the layout of the second critical path replica to determine the delay difference between the layout of the second critical path replica and the critical path information.

[0094] In one embodiment, the second calibration module is specifically used for:

[0095] Based on the delay difference, add or remove the NOR gates at the end of the second critical path copy to obtain the modified critical path copy; repeat the above process of obtaining the modified critical path copy until the delay of the modified critical path copy is greater than or equal to the delay of the critical path information.

[0096] Based on the same inventive concept, this invention also provides a computer device embodiment for implementing all or part of the above-described critical path replication method. This computer device specifically includes the following:

[0097] The system includes a processor, memory, a communications interface, and a bus; wherein the processor, memory, and communications interface communicate with each other via the bus; the communications interface is used to realize information transmission between related devices; the computer device can be a desktop computer, tablet computer, or mobile terminal, etc., and this embodiment is not limited to these. In this embodiment, the computer device can be implemented with reference to the embodiments for implementing the above-mentioned critical path replication method and the embodiments for implementing the above-mentioned critical path replication apparatus, the contents of which are incorporated herein by reference, and repeated details will not be described again.

[0098] Figure 6 This is a schematic diagram of the system composition structure of a computer device provided in an embodiment of the present invention. Figure 6 As shown, the computer device 70 may include a processor 701 and a memory 702; the memory 702 is coupled to the processor 701. It is worth noting that... Figure 6 This is an example; other types of structures can also be used to supplement or replace this structure to achieve telecommunications functions or other functions.

[0099] In one embodiment, the functionality implemented by the critical path replication method can be integrated into the processor 701. The processor 701 can be configured to perform the following controls:

[0100] Based on the chip's critical path timing report, the chip's critical path information is determined. This critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. A critical path topology is constructed based on this information. Inverters are inserted into each node of the critical path topology to calibrate the fan-out value of each node, resulting in a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. A NOR gate is inserted at the end of the first critical path replica to calibrate its timing, resulting in a second critical path replica. The NOR gates inserted at the end of the second critical path replica are added or removed until the delay of the second critical path replica's layout is greater than or equal to the delay of the critical path information.

[0101] As can be seen from the above, the computer device provided in the embodiments of the present invention can improve the tracking accuracy of the critical path copy and reduce the delay error of the critical path copy by constructing a critical path topology and inserting inverters and NOR gates into the critical path topology, thereby improving the accuracy of the chip critical path replication and enabling more accurate tracking of the chip's timing state. At the same time, by completely replicating the critical path topology and the fan-out values ​​of each node in the critical path, the obtained critical path copy can be closer to the real critical path, thereby achieving more complete critical path information than traditional inverter chains and buffer chains, and enabling it to have a wider voltage adaptation range.

[0102] In another embodiment, the critical path replication device can be configured separately from the processor 701. For example, the critical path replication device can be configured as a chip connected to the processor 701, and the function of the critical path replication method can be implemented through the control of the processor.

[0103] like Figure 6 As shown, the computer device 70 may also include: a communication module 703, an input unit 704, an audio processing unit 705, a display 706, and a power supply 707. It is worth noting that the computer device 70 does not necessarily need to include these components. Figure 6 All components shown; in addition, computer device 70 may also include Figure 6 For components not shown, please refer to existing technologies.

[0104] like Figure 6 As shown, processor 701, sometimes also referred to as controller or operation control, may include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of various components of computer device 70.

[0105] The memory 702 may be, for example, one or more of a cache, flash memory, hard drive, removable media, volatile memory, non-volatile memory, or other suitable device. It may store the aforementioned failure-related information, and also store a program for executing that information. The processor 701 may execute the program stored in the memory 702 to perform information storage or processing, etc.

[0106] Input unit 704 provides input to processor 701. This input unit 704 may be, for example, a keypad or touch input device. Power supply 707 provides power to computer device 70. Display 706 displays images and text, etc. This display may be, for example, an LCD display, but is not limited thereto.

[0107] The memory 702 can be a solid-state memory, such as a read-only memory (ROM), random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and contains more data; examples of this type of memory are sometimes referred to as EPROMs. The memory 702 can also be some other type of device. The memory 702 includes a buffer memory 7021 (sometimes referred to as a buffer). The memory 702 may include an application / function storage unit 7022 for storing application programs and function programs or processes for executing operations of the computer device 70 via the processor 701.

[0108] The memory 702 may also include a data storage unit 7023 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the computer device. The driver storage unit 7024 of the memory 702 may include various drivers for the computer device for communication functions and / or for performing other functions of the computer device (such as messaging applications, address book applications, etc.).

[0109] The communication module 703 is a transmitter / receiver that transmits and receives signals via the antenna 708. The communication module (transmitter / receiver) 703 is coupled to the processor 701 to provide input signals and receive output signals, which is the same as in a conventional mobile communication terminal.

[0110] Based on different communication technologies, multiple communication modules 703 can be configured in the same computer device, such as cellular network modules, Bluetooth modules, and / or wireless LAN modules. The communication module (transmitter / receiver) 703 is also coupled to a speaker 709 and a microphone 710 via an audio processing unit 705 to provide audio output via the speaker 709 and receive audio input from the microphone 710, thereby realizing typical telecommunications functions. The audio processing unit 705 may include any suitable buffer, decoder, amplifier, etc. Additionally, the audio processing unit 705 is also coupled to a processor 701, enabling on-device recording via the microphone 710 and on-device playback of stored audio via the speaker 709.

[0111] In embodiments of the present invention, a computer-readable storage medium is also provided for implementing all steps of the critical path replication method in the above embodiments. The computer-readable storage medium stores a computer program that, when executed by a processor, implements all steps of the critical path replication method in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0112] Based on the chip's critical path timing report, the chip's critical path information is determined. This critical path information includes the logic gates traversed by the critical path and the fan-out value of each logic gate's output node. A critical path topology is constructed based on this information. Inverters are inserted into each node of the critical path topology to calibrate the fan-out value of each node, resulting in a first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. A NOR gate is inserted at the end of the first critical path replica to calibrate its timing, resulting in a second critical path replica. The NOR gates inserted at the end of the second critical path replica are added or removed until the delay of the second critical path replica's layout is greater than or equal to the delay of the critical path information.

[0113] As can be seen from the above, the computer device provided in the embodiments of the present invention can improve the tracking accuracy of the critical path copy and reduce the delay error of the critical path copy by constructing a critical path topology and inserting inverters and NOR gates into the critical path topology, thereby improving the accuracy of the chip critical path replication and enabling more accurate tracking of the chip's timing state. At the same time, by completely replicating the critical path topology and the fan-out values ​​of each node in the critical path, the obtained critical path copy can be closer to the real critical path, thereby achieving more complete critical path information than traditional inverter chains and buffer chains, and enabling it to have a wider voltage adaptation range.

[0114] Embodiments of the present invention also provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the above-described critical path copying method.

[0115] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0116] While this invention provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual device or client product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0118] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0120] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0121] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0122] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0123] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0124] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention is not limited to any single aspect, nor to any single embodiment, nor to any combination and / or substitution of these aspects and / or embodiments. Each aspect and / or embodiment of the present invention can be used alone, or in combination with one or more other aspects and / or other embodiments.

[0125] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0126] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A critical path replication method, characterized in that, include: Based on the chip's critical path timing report, determine the chip's critical path information; The critical path information includes the logic gates traversed by the critical path and the fan-out value of the output node of each logic gate. Construct the critical path topology based on the critical path information; By inserting inverters into each node of the critical path topology, the fan-out value of each node in the critical path topology is calibrated to obtain the first critical path replica. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. By inserting a NOR gate at the end of the first critical path replica, the timing of the first critical path replica is calibrated to obtain the second critical path replica; the delay of the inverter and NOR gate is more sensitive to PVT fluctuations, so that the critical path replica is always the most critical path in the chip throughout the entire wide voltage operating range. Import the copy of the second critical path into the automatic placement and routing tool to obtain the layout of the copy of the second critical path; SPICE simulations were performed on the parasitic parameters extracted from the layout of the second critical path replica to determine the delay difference between the layout of the second critical path replica and the critical path information. Based on the delay difference, add or remove the NOR gates at the end of the second critical path copy to obtain the modified critical path copy; repeat the above process of obtaining the modified critical path copy until the delay of the modified critical path copy is greater than or equal to the delay of the critical path information.

2. The method as described in claim 1, characterized in that, Also includes: Parasitic parameters are extracted from the chip layout to obtain the chip's parasitic parameter file; Static timing analysis is performed based on the chip's back-end netlist and parasitic parameter file to obtain the chip's critical path timing report.

3. A critical path replication device, characterized in that, include: The critical path information determination module is used to determine the critical path information of the chip based on the chip's critical path timing report. The critical path information includes the logic gates traversed by the critical path and the fan-out value of the output node of each logic gate. The critical path topology construction module is used to construct the critical path topology based on the critical path information. The first calibration module is used to calibrate the fan-out value of each node in the critical path topology by inserting inverters into each node of the critical path topology, so as to obtain a copy of the first critical path. The fan-out value of each node in the first critical path replica is the same as the fan-out value of the corresponding node in the critical path information. The second calibration module is used to calibrate the timing of the first critical path copy by inserting a NOR gate at the end of the first critical path copy to obtain a second critical path copy; the NOR gate inserted at the end of the second critical path copy is added or removed until the delay of the layout of the second critical path copy is greater than or equal to the delay of the critical path information; the delay of the inverter and NOR gate is more sensitive to PVT fluctuations, so that the critical path copy is always the most critical path in the chip throughout the entire wide voltage operating range. The delay difference determination module is used to: import the copy of the second critical path into the automatic placement and routing tool to obtain the layout of the copy of the second critical path; SPICE simulations were performed on the parasitic parameters extracted from the layout of the second critical path replica to determine the delay difference between the layout of the second critical path replica and the critical path information. The second calibration module is specifically used to: add or remove the NOR gate at the end of the second critical path copy according to the delay difference to obtain the modified critical path copy; repeat the above process of obtaining the modified critical path copy until the delay of the modified critical path copy is greater than or equal to the delay of the critical path information.

4. The apparatus as described in claim 3, characterized in that, Also includes: The critical path timing report determination module is used for: Parasitic parameters are extracted from the chip layout to obtain the chip's parasitic parameter file; Static timing analysis is performed based on the chip's back-end netlist and parasitic parameter file to obtain the chip's critical path timing report.

5. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 2.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 2.

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