Data transfer circuit, method and storage device

Abstract

The application relates to a data transmission circuit, a method and a storage device. A comparison module is used for comparing bus data on a data bus and global data on a global data line, and outputting a comparison result of whether the number of bits of the bus data different from the global data exceeds a preset threshold; a first data conversion module is used for providing the bus data after inversion to a data bus buffer module in the case that the comparison result exceeds the preset threshold, and providing the bus data to the data bus buffer module in the case that the comparison result does not exceed the preset threshold; the data bus buffer module is used for generating a data polarity identification signal according to the comparison result, and transmitting the bus data or the data after inversion of the bus data to the global data line; and a write circuit module is used for transmitting the global data on the global data line or the data after inversion to a local data line according to the data polarity identification signal. The application effectively reduces the power consumption of the write data in the process of writing the write data into a storage unit array via the data bus.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor storage, and particularly relates to a data transmission circuit, a data transmission method and a storage device. BACKGROUND

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements for the storage capacity and power saving performance of semiconductor storage devices, which puts forward higher requirements for the power saving performance of the peripheral circuit area of the control circuit for controlling reading and writing and the storage array area in the semiconductor storage device.

[0003] However, due to the increase of the density and quantity of storage units in the storage unit array, the power consumption in the process of writing data into the semiconductor storage device via the data bus to the storage unit array increases, and the data transmission rate decreases.

[0004] If the power consumption in the process of writing data into the semiconductor storage device via the data bus to the storage unit array can be reduced without reducing the density and quantity of storage units in the storage unit array, the possibility of further improving the storage capacity and reducing the power consumption of the semiconductor storage device can be increased. SUMMARY

[0005] Therefore, it is necessary to provide a data transmission circuit, a data transmission method and a storage device to effectively reduce the power consumption in the process of writing data into the semiconductor storage device via the data bus to the storage unit array.

[0006] To achieve the above object and other objects, one aspect of the present application provides a data transmission circuit, comprising a comparison module, a first data conversion module, a data bus buffer module and a write circuit module. The comparison module is configured to receive bus data on a data bus and global data on a global data line, and compare the bus data and the global data to output a comparison result of whether the number of bits of the bus data and the global data that are not the same exceeds a preset threshold, wherein the bus data and the global data have the same preset bit width. The first data conversion module is electrically connected with the data bus, the comparison module and the global data line, and is configured to output the bus data after inversion in the case that the comparison result exceeds the preset threshold, and output the bus data in the case that the comparison result does not exceed the preset threshold. The data bus buffer module is electrically connected with the first data conversion module, the comparison module and the global data line, and is configured to generate a data polarity identification signal according to the comparison result, and further configured to transmit the bus data or the data after inversion of the bus data to the global data line. The write circuit module is electrically connected with the global data line, a local data line and a complementary local data line, and is configured to transmit the global data on the global data line or the data after inversion to the local data line according to the data polarity identification signal, wherein the local data line and the complementary local data line transmit signals with opposite phases.

[0007] In the data transmission circuit in the above embodiment, the comparison module is configured to receive bus data on the data bus and global data on the global data line, and compare the bus data and the global data to output a comparison result indicating whether the number of bits in which the bus data is different from the global data exceeds a preset threshold, wherein the bus data and the global data have the same preset bit width, so that the first data conversion module outputs the bus data after inversion when the comparison result exceeds the preset threshold, and outputs the bus data when the comparison result does not exceed the preset threshold; the data bus buffer module is configured to generate a data polarity identification signal according to the comparison result, and transmit the bus data or the data after inversion of the bus data to the global data line, so that the write circuit module can transmit the global data on the global data line or the data after inversion to the local data line according to the data polarity identification signal, wherein the local data line and the complementary local data line transmit signals having opposite phases, so as to reduce the number of times of inversion of data during transmission via the data bus, the global data line, the local data line, or the data bus, the global data line and the complementary local data line, thereby effectively reducing the power consumption during transmission of data via the data bus, the global data line and the local data line, or the data bus, the global data line and the complementary local data line. Thus, the energy consumption of the semiconductor storage device is reduced without reducing the density and the number of storage units in the storage unit array.

[0008] In one embodiment, the write circuit module includes a write conversion circuit electrically connected to the data bus buffer module, the global data line, the local data line and the complementary local data line, and configured to transmit the global data on the global data line to the complementary local data line when the comparison result indicated by the data polarity identification signal exceeds the preset threshold, and transmit the global data on the global data line to the local data line when the comparison result does not exceed the preset threshold.

[0009] In the data transmission circuit in the above embodiment, the write conversion circuit is configured to transmit the global data on the global data line to the complementary local data line when the comparison result indicated by the data polarity identification signal exceeds the preset threshold, and transmit the global data on the global data line to the local data line when the comparison result does not exceed the preset threshold, so as to accurately transmit the bus data on the data bus to the local data line or the complementary local data line, and reduce the number of times of inversion of data during transmission, thereby effectively reducing the power consumption during transmission of data via the data bus, the global data line and the local data line, or the data bus, the global data line and the complementary local data line.

[0010] In one of the embodiments, the preset threshold is half of the preset bit width; the comparison module comprises a comparison unit and a state recognition unit, the comparison unit is configured to compare the bus data and the global data bit by bit and output comparison state data of each bit, and the state recognition unit is electrically connected to the comparison unit and configured to count the comparison state data of each bit and output the comparison result according to a counting result.

[0011] In one of the embodiments, the first data conversion module comprises a first transmission unit, a first inverter unit, a second transmission unit and a second inverter unit, the first transmission unit is electrically connected to the data bus, the data bus buffer module, and the output end of the state recognition unit through the first inverter unit, and is configured to transmit the bus data to the data bus buffer module when the comparison result does not exceed the preset threshold; the second transmission unit is electrically connected to the data bus buffer module, the output end of the state recognition unit, and the data bus through the second inverter unit, and is configured to transmit the bus data to the data bus buffer module after inversion when the comparison result exceeds the preset threshold.

[0012] In one of the embodiments, the write conversion circuit comprises a write enable module and a write driving circuit, the write enable module is configured to generate a write enable signal and a write enable inverse signal according to the data polarity identification signal and an initial write enable signal; and the write driving circuit is configured to generate third data according to the write enable signal, the write enable inverse signal and the global data, and transmit the third data to the local data line or the complementary local data line.

[0013] In one of the embodiments, the write enable module comprises a first inverter, a first NOR gate, a second inverter and a second NOR gate, the first inverter is configured to have an input end electrically connected to an initial write enable signal and an output end outputting a first write enable inverse signal; the first NOR gate is configured to have an input end electrically connected to the data polarity identification signal and the output end of the first inverter and an output end outputting a write enable signal; the second inverter is configured to have an input end electrically connected to the data polarity identification signal and an output end outputting a data polarity identification inverse signal; and the second NOR gate is configured to have an input end electrically connected to the output end of the second inverter and the output end of the first inverter and an output end outputting a write enable inverse signal.

[0014] In one of the embodiments, the write driving circuit comprises a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit and a sixth switch unit. The first switch unit is configured to electrically connect the complementary local data line and the global data line according to the write enable inverse signal. The second switch unit is configured to have a control end electrically connected to the global data line, a first end electrically connected to the local data line and a second end electrically connected to a first node. The third switch unit is configured to electrically connect the first node and the ground according to the write enable inverse signal. The fourth switch unit is configured to electrically connect the local data line and the global data line according to the write enable signal. The fifth switch unit is configured to have a control end electrically connected to the global data line, a first end electrically connected to the complementary local data line and a second end electrically connected to a second node. The sixth switch unit is configured to electrically connect the second node and the ground according to the write enable signal.

[0015] In one of the embodiments, the data transmission circuit further comprises an encoding module electrically connected to the global data line and the data bus, configured to generate check code data according to the bus data on the data bus during a write operation and transmit the check code data to the global data line.

[0016] In one of the embodiments, the encoding module comprises an ECC encoding unit.

[0017] In one of the embodiments, the data transmission circuit further comprises a reading unit and a correction module. The reading unit is configured to read the global data on the global data line and the check code data on the global data line. The correction module is electrically connected to the reading unit and the data bus, configured to receive the global data on the global data line and the check code data on the global data line, perform error detection and / or error correction on the global data according to the check code data, generate corrected data and transmit the corrected data to the data bus.

[0018] In one of the embodiments, the data transmission circuit further comprises a second data conversion module. The second data conversion module comprises a third transmission unit, a third inverting unit, a fourth transmission unit and a fourth inverting unit. The third transmission unit is electrically connected to the data bus, the correction module and the output end of the comparison module through the third inverting unit, configured to transmit the corrected data to the data bus when the comparison result does not exceed the preset threshold. The fourth transmission unit is electrically connected to the data bus, the output end of the comparison module and the correction module through the fourth inverting unit, configured to transmit the inverted corrected data to the data bus when the comparison result exceeds the preset threshold.

[0019] In one of the embodiments, the data transmission circuit further comprises a recovery module electrically connected with the comparison module, the data bus and the serial-parallel conversion module, configured to transmit the data on the data bus or the inverted data to the serial-parallel conversion module according to the comparison result.

[0020] Another aspect of the present application provides a storage device comprising the data transmission circuit described in any of the embodiments of the present application, configured to store and transmit data of a read operation or a write operation.

[0021] Still another aspect of the present application provides a data transmission method, comprising:

[0022] comparing bus data on a data bus with global data on a global data line and outputting a comparison result of whether a number of bits different between the bus data and the global data exceeds a preset threshold, wherein the bus data and the global data have a same preset bit width;

[0023] if the comparison result exceeds the preset threshold, providing the bus data inverted to a data bus buffer module; otherwise, providing the bus data to the data bus buffer module, wherein the data bus buffer module is configured to generate a data polarity identification signal according to the comparison result and to transmit the bus data or the bus data inverted to the global data line;

[0024] transmitting the global data on the global data line or inverted to a local data line according to the data polarity identification signal.

[0025] In one of the embodiments, the preset threshold is half of the preset bit width, and the transmitting the global data on the global data line or inverted to a local data line according to the data polarity identification signal comprises:

[0026] in a case where the comparison result indicated by the data polarity identification signal exceeds the preset threshold, transmitting the global data on the global data line to a complementary local data line, and in a case where the comparison result does not exceed the preset threshold, transmitting the global data to the local data line, wherein the local data line and the complementary local data line transmit signals in opposite phases. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0028] Figure 1 A circuit principle schematic diagram of a data transmission circuit provided in a first embodiment of the present application;

[0029] Figure 2 A circuit principle schematic diagram of a data transmission circuit provided in a second embodiment of the present application;

[0030] Figure 3 A circuit principle schematic diagram of a data transmission circuit provided in a third embodiment of the present application;

[0031] Figure 4a A circuit principle schematic diagram of a data transmission circuit provided in a fourth embodiment of the present application;

[0032] Figure 4b A circuit principle schematic diagram of a data transmission circuit provided in a fifth embodiment of the present application; Figure 4a A circuit principle schematic diagram of a data transmission circuit provided in a sixth embodiment of the present application;

[0033] Figure 5 A circuit principle schematic diagram of a data transmission circuit provided in a seventh embodiment of the present application;

[0034] Figure 6 A circuit schematic diagram of a write enable module in a data transmission circuit provided in an embodiment of the present application;

[0035] Figure 7 A circuit schematic diagram of a write driving circuit in a data transmission circuit provided in an embodiment of the present application;

[0036] Figure 8 A circuit principle schematic diagram of a data transmission circuit provided in an eighth embodiment of the present application;

[0037] Figure 9 A circuit principle schematic diagram of a data transmission circuit provided in a ninth embodiment of the present application;

[0038] Figure 10 A circuit principle schematic diagram of a data transmission circuit provided in a tenth embodiment of the present application;

[0039] Figure 11 A circuit principle schematic diagram of a data transmission circuit provided in an eleventh embodiment of the present application;

[0040] Figure 12 A flow schematic diagram of a data transmission method provided in an embodiment of the present application;

[0041] Figure 13 A flow schematic diagram of a data transmission method provided in another embodiment of the present application.

[0042] BRIEF DESCRIPTION OF THE DRAWINGS

[0043] 100, data transmission circuit; 10, comparison module; 20, first data conversion module; 30, data bus buffer module; 40, write circuit module; 41, write conversion circuit; 11, comparison unit; 12, state recognition unit; 21, first transmission unit; 22, first inverting unit; 23, second transmission unit; 24, second inverting unit; 411, write enable module; 412, write driving circuit; 4121, first switching unit; 4122, second switching unit; 4123, third switching unit; 4124, fourth switching unit; 4125, fifth switching unit; 4126, sixth switching unit; 50, encoding module; 60, read unit; 70, correction module; 81, third transmission unit; 82, third inverting unit; 83, fourth transmission unit; 84, fourth inverting unit; 90, recovery module; 200, serial-parallel conversion module. DETAILED DESCRIPTION

[0044] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the figures. The preferred embodiments of the application are illustrated in the figures. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used in the description herein and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood by those within the art that, in general, terms used herein, and especially

[0046] Reference will now be made to Figure 1In an embodiment of the present application, a data transmission circuit 100 is provided, comprising a comparison module 10, a first data conversion module 20, a data bus buffer module 30 and a write circuit module 40. The comparison module 10 is configured to receive bus data on a data bus Data bus and global data on a global data line YIO, and compare the bus data and the global data to output a comparison result indicating whether the number of bits in which the bus data and the global data are different exceeds a preset threshold, wherein the bus data and the global data have a same preset bit width. The first data conversion module 20 is electrically connected to the data bus Data bus, the comparison module 10 and the global data line YIO, and is configured to output the bus data after inversion in a case where the comparison result exceeds the preset threshold, and output the bus data in a case where the comparison result does not exceed the preset threshold. The data bus buffer module 30 is electrically connected to the first data conversion module 20, the comparison module 10 and the global data line YIO, and is configured to generate a data polarity identification signal pl according to the comparison result, and transmit the bus data or the bus data after inversion to the global data line YIO. The write circuit module 40 is electrically connected to the data bus buffer module 30, the global data line YIO, a local data line LIO and a complementary local data line LIO_, and is configured to transmit the global data on the global data line YIO or the global data after inversion to the local data line LIO according to the data polarity identification signal pl, wherein the local data line LIO and the complementary local data line LIO_ transmit signals in opposite phases.

[0047] In particular, please continue to refer to Figure 1, the bus data on the data bus and the global data on the global data line YIO are received by setting a comparison module 10, and the bus data and the global data are compared to output a comparison result of whether the number of bits that the bus data is different from the global data exceeds a preset threshold, wherein the bus data and the global data have the same preset bit width, so that the first data conversion module 20 outputs the bus data after inversion in the case that the comparison result exceeds the preset threshold, and outputs the bus data in the case that the comparison result does not exceed the preset threshold; by setting a data bus buffer module 30, a data polarity identification signal pl is generated according to the comparison result, and the global data or the data after inversion of the global data is transmitted to the global data line YIO, so that the write circuit module 40 can transmit the global data on the global data line YIO or the inverted data to the local data line LIO according to the data polarity identification signal pl, wherein the local data line LIO and the complementary local data line LIO_ transmit signals with opposite phases, so as to reduce the number of times of data inversion in the process of data transmission via the data bus Data bus, the global data line YIO and the local data line LIO, or data transmission via the data bus Data bus, the global data line YIO and the complementary local data line LIO_, so as to effectively reduce the power consumption in the process of data transmission via the data bus Data bus, the global data line YIO and the local data line LIO, or data transmission via the data bus Data bus, the global data line YIO and the complementary local data line LIO_. Thus, the energy consumption of the semiconductor storage device is reduced without reducing the density and the number of storage units in the storage unit array.

[0048] Please refer to Figure 2 In an embodiment of the present application, the write circuit module 40 includes a write conversion circuit 41 electrically connected with the data bus buffer module 30, the global data line YIO, the local data line LIO and the complementary local data line LIO_, for transmitting the data on the global data line YIO to the complementary local data line LIO_ in the case that the comparison result indicated by the data polarity identification signal pl exceeds the preset threshold, and transmitting the data on the global data line YIO to the local data line LIO in the case that the comparison result indicated by the data polarity identification signal pl does not exceed the preset threshold.

[0049] Please continue to refer to Figure 2In a case where the comparison result indicated by the data polarity identification signal pl exceeds a preset threshold, the global data on the global data line YIO is transmitted to the complementary local data line LIO_, and in a case where the comparison result indicated by the data polarity identification signal pl does not exceed the preset threshold, the global data on the global data line YIO is transmitted to the local data line LIO, so that the bus data on the data bus Data bus can be accurately transmitted to the local data line LIO or the complementary local data line LIO_, and the number of times of flipping in the data transmission process is reduced, so as to effectively reduce the power consumption in the data transmission process via the data bus Data bus, the global data line YIO and the local data line LIO, or the data transmission process via the data bus Data bus, the global data line YIO and the complementary local data line LIO_.

[0050] Please refer to Figure 3 In an embodiment of the present application, the preset threshold can be set as half of the preset bit width; the comparison module 10 comprises a comparison unit 11 and a state recognition unit 12, the comparison unit 11 is used for bit-by-bit comparison of the bus data on the data bus Data bus and the global data on the global data line YIO, and outputs the comparison state data of each bit; the state recognition unit 12 is electrically connected to the comparison unit 11, and is used for counting the comparison state data of each bit, and outputs the comparison result according to the counting result.

[0051] Please refer to Figure 4a and Figure 4b In an embodiment of the present application, the first data conversion module 20 comprises a first transmission unit 21, a first inversion unit 22, a second transmission unit 23 and a second inversion unit 24, the first transmission unit 21 is electrically connected to the data bus Data bus, the data bus buffer module 30, and is electrically connected to the output end of the state recognition unit 12 through the first inversion unit 22, and is used for transmitting the bus data to the data bus buffer module 30 in a case where the comparison result does not exceed the preset threshold; the second transmission unit 23 is electrically connected to the data bus buffer module 30 and the output end of the state recognition unit 12, and is electrically connected to the data bus Data bus through the second inversion unit 24, and is used for transmitting the inverted bus data to the data bus buffer module 30 in a case where the comparison result exceeds the preset threshold.

[0052] Please refer to Figure 5In an embodiment of the present application, the write conversion circuit 41 comprises a write enable module 411 and a write driving circuit 412. The write enable module 411 generates a write enable signal WrEn and a write enable inverse signal WrEn_ according to the data polarity identification signal pl and the initial write enable signal we. The write driving circuit 412 is configured to generate a third data according to the write enable signal WrEn, the write enable inverse signal WrEn_ and global data on the global data line YIO, and transmit the third data to the local data line LIO or the complementary local data line LIO_. For example, the write conversion circuit 41 can be configured to transmit the global data on the global data line YIO to the complementary local data line LIO_ when the comparison result indicated by the data polarity identification signal pl exceeds a preset threshold, and transmit the global data on the global data line YIO to the local data line LIO when the comparison result indicated by the data polarity identification signal pl does not exceed the preset threshold.

[0053] For reference Figure 6 In an embodiment of the present application, the write enable module 411 comprises a first inverter Inv1, a first NOR gate Nor1, a second inverter Inv2 and a second NOR gate Nor2. The first inverter Inv1 is configured to have an input end electrically connected to the initial write enable signal we, and an output end outputting a first write enable inverse signal We1_. The first NOR gate Nor1 is configured to have an input end electrically connected to the data polarity identification signal pl and the output end of the first inverter Inv1, and an output end outputting the write enable signal WrEn. The second inverter Inv2 is configured to have an input end electrically connected to the data polarity identification signal pl, and an output end outputting a data polarity identification inverse signal Pl_. The second NOR gate Nor2 is configured to have an input end electrically connected to the output end of the second inverter Inv2 and the output end of the first inverter Inv1, and an output end outputting the write enable inverse signal WrEn_.

[0054] For reference Figure 7In one embodiment of this application, the write drive circuit 412 includes a first switch unit 4121, a second switch unit 4122, a third switch unit 4123, a fourth switch unit 4124, a fifth switch unit 4125, and a sixth switch unit 4126. The first switch unit 4121 is configured to electrically connect the complementary local data line LIO_ and the global data line YIO according to the write enable inverse signal WrEn_. The second switch unit 4122 is configured such that its control terminal is electrically connected to the global data line YIO, and its first terminal is electrically connected to the local data line LIO. The second terminal is electrically connected to the first node; the third switch unit 4123 is used to electrically connect the first node a and ground according to the write enable inverse signal WrEn_; the fourth switch unit 4124 is used to electrically connect the local data line LIO and the global data line YIO according to the write enable signal WrEn; the fifth switch unit 4125 is configured such that: the control terminal is electrically connected to the global data line YIO, the first terminal is electrically connected to the complementary local data line LIO_, and the second terminal is electrically connected to the second node; the sixth switch unit 4126 is used to electrically connect the second node b and ground according to the write enable signal WrEn.

[0055] Please refer to Figure 8 In one embodiment of this application, the data transmission circuit 100 further includes an encoding module 50, which is electrically connected to both the global data line YIO and the data bus. The encoding module 50 is used to generate check code data Check_data based on the bus data on the data bus during a write operation, and to transmit the check code data Check_data to the global data line YIO.

[0056] Please refer to Figure 9 In one embodiment of this application, the data transmission circuit 100 further includes a reading unit 60 and a correction module 70. The reading unit 60 is used to read global data and check code data on the global data line YIO. The correction module 70 is electrically connected to both the reading unit 60 and the data bus, and is used to receive the global data and check code data Check_data on the global data line YIO, perform error detection and / or error correction on the global data on the global data line YIO according to the check code data Check_data, generate corrected data, and transmit the corrected data to the data bus.

[0057] As an example, please continue to refer to Figure 9In one embodiment, the encoding module 50 includes an ECC encoding unit, which verifies the global data on the global data line YIO and generates an ECC checksum. This enables the correction module 70 to perform error detection and / or error correction on the global data on the global data line YIO based on the ECC checksum and generate corrected data to ensure the accuracy of the read data.

[0058] Please refer to Figure 10 In one embodiment of this application, the data transmission circuit 100 further includes a second data conversion module (not shown). The second data conversion module includes a third transmission unit 81, a third inverting unit 82, a fourth transmission unit 83, and a fourth inverting unit 84. The third transmission unit 81 is electrically connected to the data bus and the correction module 70, and is electrically connected to the output terminal of the comparison module 10 through the third inverting unit 82. It is used to transmit the corrected data to the data bus when the comparison result does not exceed the preset threshold. The fourth transmission unit 83 is electrically connected to the data bus and the output terminal of the comparison module 10, and is electrically connected to the correction module 70 through the fourth inverting unit 84. It is used to invert the corrected data and transmit it to the data bus when the comparison result exceeds the preset threshold. This reduces the number of times the data is flipped during transmission via the global data line and the data bus while ensuring the accuracy of the read data, thereby effectively reducing the power consumption during data transmission via the global data line and the data bus.

[0059] Please refer to Figure 11 In one embodiment of this application, the data transmission circuit 100 further includes a recovery module 90, which is electrically connected to the comparison module 10, the data bus, and the serial-to-parallel conversion module 200. The recovery module 90 is used to transmit the data on the data bus or the inverted data to the serial-to-parallel conversion module 200 according to the comparison result output by the comparison module 10, so as to restore the data flipped by the second data conversion module and ensure the accuracy of the read data.

[0060] Furthermore, in one embodiment of this application, a storage device is provided, including the data transmission circuit 100 described in any embodiment of this application, for storing and transmitting data for read or write operations.

[0061] For specific limitations of the storage device in the above embodiments, please refer to the specific limitations of the data transmission circuit 100 above, which will not be repeated here.

[0062] Further, please refer to Figure 12 In one embodiment of this application, a data transmission method is provided, comprising:

[0063] Step 102, comparing bus data on a data bus with global data on a global data line, and outputting a comparison result of whether a number of bits of the bus data that is not identical to the global data exceeds a preset threshold, wherein the bus data and the global data have a same preset bit width;

[0064] Step 104, if the comparison result exceeds the preset threshold, providing the bus data after being inverted to a data bus buffer module; otherwise, providing the bus data to the data bus buffer module, wherein the data bus buffer module is configured to generate a data polarity identification signal according to the comparison result, and configured to transmit the bus data or data after the bus data being inverted to the global data line;

[0065] Step 106, transmitting the global data on the global data line or after being inverted to a local data line according to the data polarity identification signal.

[0066] Specifically, please continue to refer to Figure 12 , by comparing bus data on a data bus with global data on a global data line, and outputting a comparison result of whether a number of bits of the bus data that is not identical to the global data exceeds a preset threshold, wherein the bus data and the global data have a same preset bit width; in the case that the comparison result exceeds the preset threshold, providing the bus data after being inverted to a data bus buffer module; otherwise, providing the bus data to the data bus buffer module, wherein the data bus buffer module is configured to generate a data polarity identification signal according to the comparison result, and configured to transmit the bus data or data after the bus data being inverted to the global data line; and a write circuit module can be configured to transmit the global data on the global data line or after being inverted to a local data line according to the data polarity identification signal, wherein a local data line and a complementary local data line transmit signals with opposite phases. Since the transmitted data generally includes a data string composed of 0 and 1, by applying a power saving algorithm to the number of times of inversion in the process of writing data from the data bus to the memory cell array, the power consumption in the process of writing data from the data bus to the memory cell array can be effectively reduced. Thus, the energy consumption of the semiconductor storage device is reduced without reducing the density and number of memory cells in the memory cell array.

[0067] Further, please refer to Figure 13 In an embodiment of the present application, the preset threshold is half of the preset bit width, and the transmitting the global data on the global data line or after being inverted to a local data line according to the data polarity identification signal comprises:

[0068] Step 1061, transmitting the global data on the global data line to the complementary local data line if the comparison result indicated by the data polarity identification signal exceeds the preset threshold, and transmitting the global data to the local data line if the comparison result does not exceed the preset threshold, wherein the local data line and the complementary local data line transmit signals in opposite phases.

[0069] As an example, please continue to refer to Figure 13 , by applying the power saving algorithm to the number of times of data inversion during the transmission of data via the data bus, the global data line, the local data line, or the transmission of write data via the data bus, the global data line and the complementary local data line, the power consumption during the transmission of write data via the data bus, the global data line and the local data line, or the transmission of data via the data bus, the global data line and the complementary local data line is effectively reduced. Thus, the energy consumption of the semiconductor storage device during the write data process is reduced without reducing the density and number of memory cells in the memory cell array.

[0070] In an embodiment of the present application, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the data transmission method described in any embodiment of the present application.

[0071] It should be understood that, although Figure 12 , Figure 13 the steps in the flowcharts are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 12 , Figure 13 At least part of the steps in

[0072] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0073] Please note that the above embodiments are only for illustrative purposes and do not mean to limit the present application.

[0074] The technical features of the above-mentioned embodiments can be combined in any way. In order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0075] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A data transmission circuit, characterized by The application relates to a data bus write circuit, comprising: a comparison module for receiving bus data on a data bus and global data on a global data line and comparing the bus data and the global data to output a comparison result of whether the number of bits of the bus data different from the global data exceeds a preset threshold, wherein the bus data and the global data have a same preset bit width; a first data conversion module electrically connected with the data bus, the comparison module and the global data line, for outputting the bus data after inversion in the case that the comparison result exceeds the preset threshold, and outputting the bus data in the case that the comparison result does not exceed the preset threshold; a data bus buffer module electrically connected with the first data conversion module, the comparison module and the global data line, for generating a data polarity identification signal according to the comparison result and transmitting the bus data or the data after inversion of the bus data to the global data line; a write circuit module electrically connected with the data bus buffer module, the global data line, a local data line and a complementary local data line, for transmitting the global data or the data after inversion on the global data line to the local data line according to the data polarity identification signal, wherein the local data line and the complementary local data line transmit signals in opposite phases; an encoding module electrically connected with the global data line and the data bus, for generating check code data according to bus data on the data bus during a write operation and transmitting the check code data to the global data line; wherein the write circuit module comprises: a write conversion circuit electrically connected with the data bus buffer module, the global data line, the local data line and the complementary local data line, for transmitting the global data to the complementary local data line in the case that the comparison result indicated by the data polarity identification signal exceeds the preset threshold, and transmitting the global data to the local data line in the case that the comparison result does not exceed the preset threshold; the write conversion circuit comprises: a write enable module for generating a write enable signal and a write enable inversion signal according to the data polarity identification signal and an initial write enable signal; a write drive circuit for generating third data according to the write enable signal, the write enable inversion signal and the global data and transmitting the third data to the local data line or the complementary local data line.

2. The data transmission circuit of claim 1, wherein, The preset threshold is half of the preset bit width; the comparison module comprises: a comparison unit for comparing the bus data and the global data bit by bit and outputting comparison state data of each bit; a state identification unit electrically connected with the comparison unit, for counting the comparison state data of each bit and outputting the comparison result according to the counting result.

3. The data transmission circuit of claim 2, wherein, the first data conversion module comprises: The first transmission unit is electrically connected with the data bus, the data bus buffer module, and the output terminal of the state identification unit through a first inverter unit, and is configured to transmit the bus data to the data bus buffer module when the comparison result does not exceed the preset threshold value. The second transmission unit is electrically connected with the data bus buffer module, the output terminal of the state identification unit, and the data bus through a second inverter unit, and is configured to transmit the inverted bus data to the data bus buffer module when the comparison result exceeds the preset threshold value.

4. The data transmission circuit of claim 1, wherein, The write enable module comprises: The first inverter is configured to have an input terminal electrically connected with an initial write enable signal and an output terminal outputting a first write enable inverse signal. The first NOR gate is configured to have an input terminal electrically connected with the data polarity identification signal and the output terminal of the first inverter, and an output terminal outputting a write enable signal. The second inverter is configured to have an input terminal electrically connected with the data polarity identification signal and an output terminal outputting a data polarity identification inverse signal. The second NOR gate is configured to have an input terminal electrically connected with the output terminal of the second inverter and the output terminal of the first inverter, and an output terminal outputting a write enable inverse signal.

5. The data transmission circuit of claim 1, wherein, The write driving circuit comprises: The first switch unit is configured to electrically connect the complementary local data line and the global data line according to the write enable inverse signal. The second switch unit is configured to have a control terminal electrically connected with the global data line, a first terminal electrically connected with the local data line, and a second terminal electrically connected with a first node. The third switch unit is configured to electrically connect the first node and the ground according to the write enable inverse signal. The fourth switch unit is configured to electrically connect the local data line and the global data line according to the write enable signal. The fifth switch unit is configured to have a control terminal electrically connected with the global data line, a first terminal electrically connected with the complementary local data line, and a second terminal electrically connected with a second node. The sixth switch unit is configured to electrically connect the second node and the ground according to the write enable signal.

6. The data transmission circuit of claim 1, wherein, The encoding module comprises an ECC encoding unit.

7. The data transmission circuit of claim 1, wherein, Further comprising: The read unit is configured to read the global data on the global data line and the check code data on the global data line. The correction module is electrically connected with the read unit and the data bus, and is configured to receive the global data on the global data line and the check code data on the global data line, perform error detection and / or error correction on the global data according to the check code data, and generate corrected data.

8. The data transmission circuit of claim 7, wherein, Further comprising a second data conversion module, which comprises: The third transmission unit is electrically connected with the data bus, the correction module, and the output terminal of the comparison module through a third inverter unit, and is configured to transmit the corrected data to the data bus when the comparison result does not exceed the preset threshold value. The fourth transmission unit is electrically connected with the data bus, the output terminal of the comparison module, and the correction module through a fourth inverter unit, and is configured to transmit the inverted corrected data to the data bus when the comparison result exceeds the preset threshold value.

9. The data transmission circuit of claim 8, wherein, Also included are: A recovery module, electrically connected with the comparison module, the data bus and the serial-parallel conversion module, for transmitting the data on the data bus or the inverted data to the serial-parallel conversion module according to the comparison result.

10. A memory device, comprising: Included are: The data transmission circuit according to any one of claims 1-9, for storing and transmitting data of a read operation or a write operation.

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