Predicting and compensating for degradation of memory cells

Abstract

The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. Embodiments include a memory having a group of memory cells, and circuitry configured to, when a quantity of sensing operations performed on the group of memory cells meets or exceeds a threshold quantity: perform a sensing operation on the group of memory cells using a positive sense voltage, and perform a sensing operation on the group of memory cells using a negative sense voltage; and perform an operation to program the memory cells of the group that are determined to be in a reset data state by both of the sensing operations to the reset data state.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to predicting and compensating for the degradation of memory cells. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, etc.

[0003] Memory devices can be used as volatile and non-volatile memory in a variety of electronic applications that require high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players and video players such as MP3 players, and other electronic devices.

[0004] Variable resistance memory devices may include variable resistance memory cells capable of storing data based on the resistance state of a storage element (e.g., a memory element with variable resistance). Thus, a variable resistance memory cell can be programmed to store data corresponding to a target data state by changing the resistance level of the memory element. A variable resistance memory cell can be programmed to a target data state (e.g., corresponding to a specific resistance state) by applying an electric field or energy source (e.g., positive or negative electrical pulses (e.g., positive or negative voltage or current pulses)) to the cell (e.g., to the memory element of the cell) for a specific duration. The state of the cell can be determined by sensing the current through the variable resistance memory cell in response to an applied interrogation voltage. The sensed current, varying based on the resistance level of the cell, indicates the state of the cell.

[0005] Various memory arrays can be organized into a crosspoint architecture, where memory cells (e.g., variable-resistance cells) are located at the intersection of a first signal line and a second signal line for accessing the cell (e.g., the intersection of a word line and a bit line). Some variable-resistance memory cells may include a selection element (e.g., a diode, transistor, or other switching device) connected in series with a storage element (e.g., a phase-change material, a metal oxide material, and / or some other material programmable to different resistance levels). Some variable-resistance memory cells, which may be called self-selecting memory cells, may contain a single material that can serve as both the selection element and the storage element of the memory cell. Summary of the Invention

[0006] This disclosure relates to a memory device comprising: a memory having a group of memory cells; and a circuit system configured to perform the following operations when the amount of a sensing operation performed on the group of memory cells meets or exceeds a threshold amount: performing a sensing operation on the group of memory cells using a positive sensing voltage and performing a sensing operation on the group of memory cells using a negative sensing voltage; and performing an operation to program the memory cells of the group that are determined to be in a reset data state by the two sensing operations to the reset data state.

[0007] Another aspect of this disclosure relates to a method of operating a memory, comprising: determining that an amount of sensing operation performed on a group of memory cells has met or exceeded a threshold amount; and, upon determining that the amount of sensing operation has met or exceeded the threshold amount, performing the following operations: sensing the group of memory cells using a positive sensing voltage to determine a data state of each of the memory cells; sensing the group of memory cells using a negative sensing voltage to determine a data state of each of the memory cells; and programming the memory cells of the group that have been determined by the two sensing operations to be in a reset data state to the reset data state.

[0008] Another aspect of this disclosure relates to a memory device comprising: a memory having a group of memory cells; and a circuit system configured to perform the following operations when the amount of a sensing operation performed on the group of memory cells meets or exceeds a threshold amount: performing a sensing operation on the group of memory cells using a positive sensing voltage, the magnitude of which has been adjusted according to the magnitude of a positive sensing voltage used to determine a data state of the memory cells of the group during the sensing operation of the amount performed on the group; performing a sensing operation on the group of memory cells using a negative sensing voltage; and performing an operation to program the memory cells of the group, which have been determined by the two sensing operations to be in a reset data state, to a reset data state.

[0009] Another aspect of this disclosure relates to a method of operating a memory, comprising: determining that an amount of sensing operation performed on a group of memory cells has met or exceeded a threshold amount; and, upon determining that the amount of sensing operation has met or exceeded the threshold amount, performing the following operations: sensing the group of memory cells using a positive sensing voltage to determine a data state of each of the memory cells; sensing the group of memory cells using a negative sensing voltage to determine a data state of each of the memory cells; and programming the memory cells of the group determined by the two sensing operations to be in a reset data state to a reset data state, wherein the operation includes applying a reset voltage pulse to the memory cells of the group determined by the two sensing operations to be in a reset data state. Attached Figure Description

[0010] Figure 1 A three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

[0011] Figure 2A This describes the distribution of threshold voltages associated with various states of memory cells according to embodiments of the present disclosure.

[0012] Figure 2B For the embodiments of this disclosure corresponding to Figure 2A An example of a current-voltage curve for memory states.

[0013] Figure 2C For the embodiments of this disclosure corresponding to Figure 2A Another example of the current-voltage curve for a memory state.

[0014] Figure 3 A block diagram illustration of an example device according to an embodiment of the present disclosure.

[0015] Figure 4 This document describes an example method for predicting and compensating for the degradation of memory cells according to embodiments of the present disclosure.

[0016] Figures 5A to 5B This section describes conceptual examples of predicting and compensating for the degradation of memory cells according to embodiments of the present disclosure. Detailed Implementation

[0017] This disclosure includes apparatus, methods, and systems for predicting and compensating for degradation of memory cells. Embodiments include: a memory having a group of memory cells; and a circuit system configured to, when the amount of a sensing operation performed on the group of memory cells meets or exceeds a threshold amount, perform the following operations: perform a sensing operation on the group of memory cells using a positive sensing voltage and a negative sensing voltage; and perform an operation to program the memory cells of a group determined by the two sensing operations to be in a reset data state to the reset data state.

[0018] During the sensing of a variable resistance memory cell, such as a self-select memory cell, a voltage can be applied to the memory cell, and the data state of the cell can be determined based on the amount of current flowing through the cell in response to the applied voltage. For example, when a voltage is applied to the memory cell, the amount of current obtained on the signal lines (e.g., bit lines or word lines) to which the memory cell is coupled can be compared with a reference current, and the state of the memory cell can be determined based on the comparison. For example, if the comparison indicator signal line current is less than the reference current, then the cell can be determined to be in a first (e.g., reset) data state, and if the comparison indicator signal line current is greater than the reference current, then the cell can be determined to be in a second (e.g., set) data state.

[0019] However, because such sensing operations are performed on memory cells during memory operation, the voltage applied to the memory cells during each sensing operation can cause the memory cells to gradually degrade over time. For example, the voltage applied to the memory cells can cause the cell's threshold voltage to drift (e.g., change) to a higher or lower value over time, which can ultimately cause the memory cell to be determined (e.g., sensed) to be in a data state different from the state to which the cell was actually programmed. For example, this threshold voltage drift can cause a memory cell programmed to a first (e.g., reset) data state to be incorrectly determined to be in a second (e.g., set) data state. This phenomenon can be called read interference (e.g., read interference to reset) and can reduce memory performance and / or lifetime.

[0020] This read interference in the memory cell can be compensated for by performing an operation that refreshes the cell to its originally programmed data state (e.g., a write refresh operation). In some prior methods, the timing of this refresh operation can be determined based on the error rate of sensing operations performed on the memory (e.g., the raw bit error rate) (e.g., triggering a refresh operation once the error rate reaches a certain threshold). However, this error rate may not be an accurate indicator of the read interference actually occurring in the memory cell. For example, the memory cell may deteriorate faster than reflected by the error rate, and / or a deteriorated memory cell may not necessarily lead to erroneous data reads. Furthermore, some error correction operations may have low error tolerance and therefore may fail before triggering a refresh operation. Therefore, the error rate may not always provide a reliable indicator of when to perform a refresh operation on the memory cell to compensate for read interference.

[0021] In contrast, embodiments of this disclosure can reliably (e.g., accurately) predict when read disturbances in a memory cell have occurred and / or will occur, and therefore provide a reliable indicator of when to perform a refresh operation on the memory cell to compensate for read disturbances. For example, embodiments of this disclosure can use sensing operations performed on the memory cell (e.g., the cell's read workload) to determine when to trigger an evaluation of whether a refresh operation is needed to compensate for read disturbances. The evaluation may include performing two sensing operations on the memory cell using sensing voltages of opposite polarities (e.g., a dual read operation), and the results of the two sensing operations can be used to determine whether a refresh operation should be performed on the memory cell. Therefore, embodiments of this disclosure can increase the memory performance and / or lifetime of the memory cell compared to previous methods (e.g., methods using error rates to determine when to perform a refresh operation).

[0022] As used herein, “a / an” or “a plurality of” can refer to one or more of something, and “a plurality of” can refer to two or more of such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, the designations “N” and “M” as used herein, especially with respect to reference numerals in the drawings, indicate that several specific features so specified may be included with several embodiments of this disclosure.

[0023] The diagrams in this document follow a numbering convention, where the first one or more numbers correspond to the diagram number, and the remaining numbers identify elements or components within the diagram. Similar elements or components between different diagrams can be identified by using similar numbers.

[0024] Figure 1This is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to an embodiment of the present disclosure. The memory array 100 may include a plurality of first signal lines (e.g., first access lines) that intersect each other (e.g., intersect in different planes), and a plurality of second signal lines (e.g., second access lines) that intersect each other (e.g., intersect in different planes), referred to as word lines 110-0 to 110-N, and a plurality of second signal lines (e.g., second access lines) that are referred to as bit lines 120-0 to 120-M. For example, each of the word lines 110-0 to 110-N may pass through the bit lines 120-0 to 120-M. Memory cells 125 may be located between the bit lines and word lines (e.g., at each bit line / word line intersection).

[0025] For example, memory cell 125 may be a variable-resistance memory cell. Memory cell 125 may include a material programmable to different data states. In some instances, each of memory cells 125 may include a single material between a top electrode (e.g., a top plate) and a bottom electrode (e.g., a bottom plate) that can act as both a selection element (e.g., a switching material) and a storage element, such that each memory cell 125 can act as both a selector device and a memory element. This memory cell may be referred to herein as a self-selecting memory cell. For example, each memory cell may include a chalcogenide material that can be formed from various doped or undoped materials, may or may not be a phase-change material, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. Chalcogenide materials may be materials or alloys comprising at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Examples of chalcogenide materials may also include SAG-based glass-non-phase change materials, such as SeAsGe. Hyphenated chemical composition symbols used herein indicate elements included in a particular compound or alloy and are intended to represent all stoichiometric quantities involving the indicated element. For example, Ge-Te may include Ge x Te y , where x and y can be any positive integers.

[0026] In various embodiments, the threshold voltage of memory cell 125 may buck back in response to an applied voltage difference exceeding its threshold voltage. These memory cells may be referred to as buck-back memory cells. For example, memory cell 125 may change (e.g., buck back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., low impedance) state in response to an applied voltage difference exceeding its threshold voltage. For example, a memory cell buck back may refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to an applied voltage difference greater than the memory cell's threshold voltage. For example, the threshold voltage of a buck-back memory cell may be referred to as a buck-back event.

[0027] The architecture of memory array 100 can be called a cross-point architecture, in which memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 1 As explained in [the document], this crossover architecture can provide relatively high-density data storage at a lower production cost compared to other memory architectures. For example, the crossover architecture can have memory cells with a smaller area and therefore a higher memory cell density compared to other architectures.

[0028] However, the embodiments disclosed herein are not limited to Figure 1 The example memory array architecture described herein. For example, embodiments of this disclosure may include a three-dimensional memory array having a plurality of vertically oriented (e.g., vertical) access lines and a plurality of horizontally oriented (e.g., horizontal) access lines. The vertical access lines may be bit lines arranged in a columnar architecture, and the horizontal access lines may be word lines arranged in a plurality of conductive planes or stacks separated (e.g., insulated) from each other by a dielectric material. The chalcogenide material of the respective memory cell of this memory array may be located at the intersection of the respective vertical bit line and horizontal word line.

[0029] Furthermore, in some architectures (not shown), multiple first access lines may be formed on a parallel plane or layer parallel to the substrate. The multiple first access lines may be configured to include multiple vias to allow multiple second access lines to be formed orthogonally to the plane of the first access lines, such that each of the multiple second access lines passes through a vertically aligned set of vias (e.g., second access lines positioned perpendicular to the plane of the first access lines and the horizontal substrate). Memory cells including memory elements (e.g., self-select memory cells comprising chalcogenide materials) may be formed at the intersection of the first and second access lines (e.g., the space between the first and second access lines in the vertically aligned set of vias). Memory cells (e.g., self-select memory cells comprising chalcogenide materials) may be operated (e.g., read and / or programmed) by selecting a corresponding access line and applying a voltage or current pulse.

[0030] Figure 2AThe description of the memory cell (e.g., according to embodiments of the present disclosure) is illustrated. Figure 1 The threshold distribution associated with various states of the memory cell 125 described herein. For example, as Figure 2A As shown, the memory cells can be programmed to one of two possible data states (e.g., state 0 or state 1). That is, Figure 2A This describes the threshold voltage distribution associated with two possible data states that the memory cell can be programmed to.

[0031] exist Figure 2A In this context, the voltage VCELL can correspond to the voltage difference applied to (e.g., on) a memory cell, such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL - VWL). Threshold voltage distributions (e.g., ranges) 201-1, 201-2, 202-1, and 202-2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a particular state. Figure 2A The distribution described corresponds to a further explanation of the asymmetry of sudden reversion associated with the assigned data state. Figure 2B and 2C The described current-voltage curve.

[0032] In some instances, the threshold voltage of memory cell 125 in a particular state may be asymmetrical for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of memory cell 125 programmed to a reset state (e.g., state 0) or a set state (e.g., state 1) may have a different value in one polarity than in the opposite polarity. For example, in Figure 2A In the example described, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) where the magnitude is greater for negative polarity than positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 202-1 and 202-2) where the magnitude is greater for positive polarity than negative polarity. In this example, it is sufficient to cause the applied voltage magnitude of the memory cell 125 to suddenly return to a value that is different (e.g., higher or lower) for one applied voltage polarity than for the other applied voltage polarity.

[0033] Figure 2AThe dividing voltages VDM1 and VDM2 are explained, which can be used to determine the state of a memory cell (e.g., to distinguish between states as part of a read operation). In this example, VDM1 is a positive voltage used to distinguish cells in state 0 (e.g., in threshold voltage distribution 201-2) from cells in state 1 (e.g., threshold voltage distribution 202-2). Similarly, VDM2 is a negative voltage used to distinguish cells in state 1 (e.g., threshold voltage distribution 202-1) from cells in state 0 (e.g., threshold voltage distribution 201-1). Figures 2A to 2C In the example, memory cell 125 in positive state 1 does not suddenly return in response to the application of VDM1; memory cell 125 in positive state 0 suddenly returns in response to the application of VDM1; memory cell 125 in negative state 1 suddenly returns in response to the application of VDM2; and memory cell 125 in negative state 0 does not suddenly return in response to the application of VDM2.

[0034] Examples are not limited to Figure 2A Examples are shown in the document. For instance, the indications of state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be designated as state 1 and distributions 202-1 and 202-2 can be designated as state 0). Furthermore, in some instances, the value of VDM1 can be adjusted (e.g., increased) to eliminate threshold voltage drift that can occur in memory cells, as will be further described herein.

[0035] Figure 2B and 2C For the embodiments of this disclosure corresponding to Figure 2A An example of the current-voltage curve for the memory state. Therefore, in this example, Figure 2B and 2C The curves in the diagram correspond to the cells where state 1 is designated as a higher threshold voltage state in a specific polarity (positive polarity direction in this example) and state 0 is designated as a higher threshold voltage state in the opposite polarity (negative polarity direction in this example). As mentioned above, the state indications are interchangeable, such that state 0 can correspond to a higher threshold voltage state in the positive polarity direction, while state 1 corresponds to a higher threshold voltage state in the negative polarity direction.

[0036] Figure 2B and 2C This describes a memory cell failover as described herein. VCELL can represent the voltage applied to the memory cell. For example, VCELL can be the voltage applied to the top electrode corresponding to the cell minus the voltage applied to the bottom electrode corresponding to the cell (e.g., via the corresponding word line and bit line). Figure 2BAs shown, in response to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 200-2) is in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be called a backsliding event, which occurs when the voltage applied to the cell (in a particular polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be called the backsliding voltage. Figure 2B In this context, voltage Vtst01 corresponds to the sudden return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 202-1). That is, as... Figure 2B As shown, when VCELL moves beyond Vtst01 in the negative polarity direction, the memory cell switches (e.g., transposes) to a conductive state.

[0037] Similarly, such as Figure 2C As shown, in response to an applied negative polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 201-1) is in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly returns to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the sudden return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown in the figure, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell suddenly returns from a high impedance non-conductive state to a lower impedance conductive state.

[0038] In various situations, a backslip event can cause a memory cell to switch states. For example, if a VCELL exceeding Vtst02 is applied to a state 1 cell, the resulting backslip event can reduce the cell's threshold voltage to a level below VDM1, causing the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Therefore, in several embodiments, a backslip event can be used to write a cell to the opposite state (e.g., from state 1 to state 0, and vice versa).

[0039] When memory cell 125 is repeatedly sensed (e.g., read), the magnitudes of its surge voltages (e.g., Vtst 01, Vtst 02, Vtst 11, and Vtst 12) can drift (e.g., change) due to the stress caused by the continuous application of boundary voltages (e.g., VDM1 and VDM2) to the cell, which may in turn make the cell more or less prone to surge. If this degradation of the memory cell (e.g., read interference) is not compensated for in a manner that will be further described herein, then the cell may be sensed as being in a data state different from the state to which the cell is actually programmed. For example, if this degradation is not compensated for in a manner that will be further described herein, then a memory cell programmed to a reset state (e.g., state 0) may be erroneously sensed as being in a set state (e.g., state 1).

[0040] Figure 3 This is a block diagram illustration of an example device (e.g., electronic memory system 300) according to an embodiment of the present disclosure. Memory system 300 may include devices, such as memory device 302, and a controller 304, such as a memory controller (e.g., a host controller). Controller 304 may include, for example, a processor. Controller 304 may be coupled to, for example, a host and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

[0041] Memory device 302 includes a memory array 306 of memory cells. For example, memory array 306 may include one or more memory arrays of memory cells disclosed herein (e.g., a crosspoint array). Memory device 302 may include an address circuitry 308 to latch address signals provided via I / O connection 310 through an I / O circuitry 312. The address signals may be received and decoded by row decoder 314 and column decoder 316 to access memory array 306. For example, row decoder 314 and / or column decoder 316 may include drivers.

[0042] Memory device 302 may use a sensing / buffer circuitry system to sense (e.g., read) data in memory array 306 by sensing voltage and / or current changes in the memory array columns. In some instances, the sensing / buffer circuitry system may include a read / latch circuitry system 320 and / or a sensing circuitry system 305. Read / latch circuitry system 320 may read and latch data from memory array 306. Sensing circuitry system 305 may include several sensing amplifiers coupled to memory cells of memory array 306, which may operate in combination with read / latch circuitry system 320 to sense (e.g., read) memory state from target memory cells. I / O circuitry system 312 may be included for bidirectional data communication with controller 304 via I / O connection 310. Write circuitry system 322 may be included for writing data to memory array 306.

[0043] The control circuitry 324 can decode signals provided from the controller 304 via the control connection 326. These signals may include chip signals, write enable signals, and address latch signals for controlling operations on the memory array 306, including data read and data write operations.

[0044] Control circuitry 324 may be included, for example, in controller 304. Controller 304 may include other circuitry, firmware, software, etc., individually or in combination. Controller 304 may be an external controller (e.g., in a die separate from memory array 306, whether fully or partially) or an internal controller (e.g., included in the same die as memory array 306). For example, an internal controller may be a state machine or a memory sequencer.

[0045] In some instances, controller 304 may be configured to predict and compensate for degradation (e.g., read interference) of memory cells in memory array 306. For example, controller 304 may reliably (e.g., accurately) predict when read interference has occurred and / or will occur in memory cells programmed to a reset data state (e.g., state 0), and thus provide a reliable indicator of when to perform a refresh operation on the memory cells to compensate for read interference. For example, controller 304 may use sensing operations performed on the memory cells (e.g., read workload of the cells) to determine when to trigger an evaluation of whether a refresh operation on the memory cells is needed to compensate for read interference. The evaluation may include performing two sensing operations (e.g., dual read operations) on the memory cells using sensing voltages of opposite polarities, and the results of the two sensing operations may be used by controller 304 to determine whether a refresh operation on the memory cells should be performed.

[0046] For example, controller 304 may determine when the amount of sensing (e.g., read) operations performed on a group of memory cells of memory array 306 has met or exceeded a threshold amount. In some instances, controller 304 may determine when the amount of sensing operations has met or exceeded a threshold amount within a specific (e.g., a shorter) time period. The threshold amount may be, for example, every 10,000 sensing operations (e.g., 10,000 sensing operations in 1 second). For example, controller 304 may use a counter (e.g., a counter that counts the sensing operations performed on a group of memory cells) to determine when the amount of sensing operations has met or exceeded the threshold amount.

[0047] A group of memory cells may be a page of storage codeword data patterns of memory cells in, for example, memory array 306. For instance, memory array 306 may be divided into addressable groups of memory cells that can be programmed in response to a programming (e.g., write) command addressing the group and sensed in response to a sensing (e.g., read) command addressing the group. In some instances, a group of memory cells may have physical addresses corresponding to logical addresses received from the host. Controller 304 may include a logic-to-physical (L2P) mapping component that maps logical addresses from the host to physical addresses of groups of memory cells. A group of memory cells may be a page corresponding to a logical address. For example, each group may store a data pattern (e.g., a data structure) that may be called a management unit (e.g., a codeword).

[0048] When it is determined that the amount of sensing operation performed on a group of memory cells has met or exceeded a threshold amount, the controller 304 may perform two sensing operations (e.g., a double read operation) on the memory cells using sensing voltages of opposite polarities. For example, the controller 304 may perform a sensing operation on the group of memory cells using a positive sensing voltage to determine the data state of each of the cells (e.g., set or reset), and perform a sensing operation on the group of memory cells using a negative sensing voltage to determine the data state of each of the cells. However, these two sensing operations (e.g., the double read operation) may only be performed by the controller 304 if it is determined that the amount of sensing operation has met or exceeded the threshold amount (e.g., if the threshold amount is not met or exceeded, then the double read operation is not performed).

[0049] The magnitude of the negative sensing voltage in a dual read operation can be equal to the magnitude of the negative sensing voltage used to determine the data state of a memory cell during a sensing operation of the amount performed on the group (e.g., to distinguish cells in a set data state from cells in a reset data state). For example, the magnitude of the negative sensing voltage in a dual read operation can be equal to... Figure 2A VDM2 as described herein (e.g., the negative sensing voltage may be VDM2).

[0050] The magnitude of the positive sensing voltage for the dual read operation can be a magnitude that has been adjusted according to (e.g., relative to) the magnitude of the positive sensing voltage used to determine the data state of the memory cell during a sensing operation performed on the group (e.g., by controller 304). For example, the magnitude of the positive sensing voltage for the dual read operation can be greater than [amount missing]. Figure 2A VDM1 as described in the document. Adjusting the magnitude of the positive sensing voltage for the dual read operation in this manner can take into account any threshold voltage drift that may have occurred in the memory cells of the group (e.g., cells programmed to the reset data state).

[0051] For example, in some instances, controller 304 may increase the magnitude of the positive sensing voltage used to determine the data state of memory cells during a sensing operation of the amount performed on the group, based on VDM1, to eliminate any threshold voltage drift that may have occurred in memory cells programmed to reset the data state. That is, the increased magnitude can be used to eliminate threshold voltage drift, and the sensing voltage with this increased magnitude may be referred to herein as the drift elimination sensing voltage. In such instances, the magnitude of the positive sensing voltage for a dual read operation may be less than the increased magnitude of the positive drift elimination sensing voltage (e.g., reduced by controller 304 based on the increased magnitude), but still greater than VDM1. Reducing the magnitude of the positive sensing voltage for a dual read operation in this way, based on the increased magnitude of the positive drift elimination sensing voltage, allows controller 304 to predict memory cells in the group where read interference has occurred, and also to predict which memory cells in the group are susceptible to read interference (e.g., which memory cells in the group may experience read interference), even if read interference has not yet occurred in those cells.

[0052] For example, the amount by which the positive sensing voltage of the dual read operation is less than the increase in the positive drift elimination sensing voltage (e.g., according to its decrease) can be based on the expected threshold voltage drift of the group of memory cells (e.g., the estimated rate of threshold voltage drift). For example, this amount can be predetermined (e.g., during the manufacture of memory device 302) and decoded into the firmware of controller 304. As an example, this amount could be 280 millivolts (mV). However, embodiments of this disclosure are not limited to this example.

[0053] As an additional example, the amount by which the magnitude of the positive sensing voltage of a dual read operation decreases based on the increase in the positive drift elimination sensing voltage can be based on the magnitude of the sensing operations performed on a group of memory cells (e.g., their read workloads). For instance, controller 304 can determine and tune this amount during operation of memory device 302 of a previously decoded adjustment.

[0054] As an additional example, the amount by which the magnitude of the positive sensing voltage of the dual read operation decreases according to the increase in the positive drift elimination sensing voltage can be based on an error rate (e.g., bit error rate) associated with an error correction operation performed on the data sensed during the sensing operation of said amount performed on a group of memory cells. For example, controller 304 may determine and tune this amount of adjustment of the previous decoding during operation of memory device 302. For example, controller may tune this amount of adjustment of the previous decoding when the error rate meets or exceeds a certain threshold. For example, this amount may be 200mV. However, embodiments of this disclosure are not limited to this example.

[0055] Error rate (e.g., bit error rate) can refer to the amount of erroneous data corresponding to the data sensed during the sensing operation of the quantity divided by the amount of erroneous bits of the total amount of data sensed during the sensing operation of the quantity (e.g., sample size). Therefore, the error rate associated with an error correction operation can be determined by dividing the amount of erroneous bits to be corrected during the error correction operation by the total amount of data sensed during the sensing operation.

[0056] When any memory cell in a group is determined (e.g., sensed) to be in a reset data state (e.g., state 0) by two sensing operations of a double read operation, controller 304 may perform an operation to program the cells in the group that are determined to be in a reset data state by the two sensing operations of the double read operation to the reset data state. For example, the operation may be a refresh operation (e.g., a write refresh operation) to refresh the memory cells in the group programmed to the reset data state back to their original reset data state to compensate for read interference in the cells. However, the refresh operation may be performed by controller 304 only when any one of the memory cells in the group is determined to be in a reset data state by two sensing operations of the double read operation (e.g., if no one of the memory cells in the group is determined to be in a reset data state by two sensing operations of the double read operation, then no refresh operation is performed). Furthermore, the refresh operation may be performed only on those cells in the group that are determined to be in a reset data state by two sensing operations of the double read operation (e.g., no refresh operation is performed on cells in the group that are not determined to be in a reset data state by two sensing operations).

[0057] In some instances, a refresh operation may include applying a set voltage pulse to memory cells that are identified as being in a reset data state by two sensing operations of a dual read operation, and then applying a reset voltage pulse to those memory cells after (e.g., immediately following) (e.g., before) the set voltage pulse. The set and reset voltage pulses may have opposite polarities. For example, the set voltage pulse may be negative and the reset voltage pulse may be positive. Furthermore, the set and reset voltage pulses may have the same magnitude and the same duration.

[0058] In some instances, the refresh operation may include applying a reset voltage pulse only to memory cells that are identified as being in a reset data state by two sensing operations of a dual read operation (e.g., in some instances, a set pulse may not be applied to those cells before the reset pulse). The reset voltage pulse may be positive and may have the same magnitude and duration as the reset voltage pulse in the previous instances.

[0059] Figure 4 This describes an example method 430 for predicting and compensating for memory cell degradation according to embodiments of the present disclosure. Method 430 can be implemented, for example, through previously combined... Figure 3 The described controller 304 is executed.

[0060] At box 432, the amount of sensing operation performed on the group of memory cells is determined. The group of memory cells can be, for example, the previously combined Figure 3 The memory array 306 described is a group of memory cells (e.g., pages). A counter can be used, for example, to determine the amount of sensing operation performed on the group of memory cells, as previously described herein (e.g., in conjunction with...). Figure 3 ).

[0061] At box 434, it is determined whether the amount of sensing operations performed on the group of memory cells meets or exceeds a threshold amount for the sensing operations. For example, it can be determined whether the amount of sensing operations meets or exceeds a threshold amount within a specific time period, as previously described herein (e.g., in conjunction with...). Figure 3 If it is determined that the amount of the sensing operation does not meet or exceeds the threshold amount, then method 430 proceeds to block 442. If it is determined that the amount of the sensing operation meets or exceeds the threshold amount, then method 430 proceeds to block 436.

[0062] At box 436, a sensing operation is performed on a group of memory cells using a positive sensing voltage to determine the data state of each cell in the group, and a sensing operation is performed on a group of memory cells using a negative sensing voltage to determine the data state of each cell in the group. These two sensing operations can be performed as part of a dual read operation to assess whether a refresh operation is needed on the memory cell to compensate for read interference in the cell, as previously described herein (e.g., in conjunction with...). Figure 3 ).

[0063] At block 438, it is determined whether any memory cell in the group is determined (e.g., sensed) to be in a reset data state (e.g., state 0) by the two sensing operations performed at block 436. If it is determined that none of the memory cells in the group are determined to be in a reset data state by the two sensing operations, then method 430 proceeds to block 442. If it is determined that any one (e.g., one or more) of the memory cells in the group are determined to be in a reset data state by the two sensing operations, then method 430 proceeds to block 440.

[0064] At box 440, an operation is performed to program the memory cells of the group determined by two sensing operations to be in a reset data state to the reset data state. This operation may be a refresh operation to refresh the memory cells of the group programmed to the reset data state back to their original reset data state in order to compensate for read interference in the cells, as previously described herein (e.g., in conjunction with...). Figure 3 Method 430 then proceeds to box 442.

[0065] At box 442, the next operation to be performed on the group of memory cells is executed. This operation can be, for example, a programming (e.g., writing), sensing (e.g., reading), or erasing operation. For example, this operation can be the next read, write, or erase operation in a sequence of operations performed on the group of memory cells.

[0066] Figures 5A to 5B This section illustrates conceptual examples of predicting and compensating for memory cell degradation according to embodiments of the present disclosure. For example, Figure 5A Explanation regarding positive polarity and memory cells (e.g., Figure 1 This is a conceptual example of the threshold voltage distribution associated with the reset data state of the memory cell 125 described herein, and Figure 5B This section illustrates a conceptual example of a threshold voltage distribution associated with the reset data state of a memory cell for negative polarity.

[0067] For example, in Figure 5A In the diagram, threshold voltage distribution 550 represents the magnitude of the threshold voltage previously programmed to a memory cell of positive polarity, which can correspond to... Figure 2A The threshold voltage distribution described in 201-2. Figure 5B In the diagram, threshold voltage distribution 556 represents the magnitude of the threshold voltage previously programmed to a memory cell of negative polarity, which can correspond to... Figure 2A The threshold voltage distribution described in document 201-1. Furthermore, Figure 5A and 5B The threshold voltage distributions 552 and 558 shown represent the current actual threshold voltage of the memory cell that has drifted over time (e.g., due to read interference occurring in the cell). Furthermore, if the memory cell is not refreshed to compensate for read interference according to this disclosure, then... Figure 5A and 5B The threshold voltage distributions 554 and 560 shown represent the threshold voltages of memory cells that the cell may (e.g., potentially) drift to in the future (e.g., due to additional read interference occurring in the cell). Furthermore, Figure 5A The VDM DRIFT shown in the diagram corresponds to the previously combined... Figure 3 The described positive drift cancellation sensing voltage, Figure 5A The VDM POS shown in the diagram corresponds to the previously combined Figure 3 The positive sensing voltage used during the described dual read operation Figure 5B The VDM NEG shown in the figure corresponds to the previously combined Figure 3 The negative sensing voltage used during the described dual readout operation, and Figure 5B The VDM WRITE shown in the image can correspond to Figure 2A VWRITE0 as described in the document.

[0068] like Figure 5A and 5B As explained, if the operation of refreshing memory cells to compensate for read interference according to this disclosure is not performed, the threshold voltages of some memory cells will be sensed in the future as being greater than VDM DRIFT and VDM WRITE, respectively (e.g., a portion of distribution 554 is greater than VDM DRIFT, and a portion of distribution 560 is greater than VDM WRITE). Therefore, if the operation of refreshing memory cells to compensate for read interference according to this disclosure is not performed, some memory cells (e.g., cells whose threshold voltages are sensed as being greater than VDM DRIFT or VDM WRITE) will be incorrectly determined in the future to be in a data state (e.g., a set data state) different from their programmed state (e.g., a reset data state).

[0069] like Figure 5A and 5B As explained in the document, if the current execution (e.g., triggering) previously combined Figure 3In the described dual read operation, the threshold voltage of some memory cells will be sensed as greater than VDM POS and VDM NEG by the dual read operation (e.g., a portion of distribution 552 is greater than VDM POS, and all distributions 558 are greater than VDM NEG). These memory cells (e.g., cells whose threshold voltage is sensed as greater than VDM POS and VDM NEG) will be sensed as being in a reset data state by the two sensing operations of the dual read operation, and will therefore be memory cells for which an operation to refresh the memory cell to compensate for read interference will be performed (e.g., such that the cell can be refreshed before the read interference causes the threshold voltage distribution to drift to distributions 554 and 560).

[0070] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description has been carried out in an illustrative rather than restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art after reviewing the above description. The scope of several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined by reference to the full scope of the appended claims together with the equivalents claimed by such claims.

[0071] In the foregoing detailed description, some features have been grouped together in a single embodiment for the purpose of brevity. This approach of the present disclosure should not be construed as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is, in itself, a separate embodiment.

Claims

1. A memory device (300) comprising: Memory (302), having a group of memory cells (125); and A circuit system (304) is configured to perform the following operations when the amount of a sensing operation performed on the group of memory cells (125) meets or exceeds a threshold amount: A sensing operation is performed on the group of memory cells (125) using a positive sensing voltage, and a sensing operation is performed on the group of memory cells (125) using a negative sensing voltage; and The operation of programming the memory cell (125) of the group that is determined to be in a reset data state by the two sensing operations to the reset data state is performed.

2. The device of claim 1, wherein the magnitude of the positive sensing voltage is less than the magnitude of the positive sensing voltage used to determine the data state of the memory cell of the group during a sensing operation of the amount performed on the group.

3. The device of claim 2, wherein the magnitude of the positive sensing voltage being less than the magnitude of the positive sensing voltage used to determine the data state of the memory cell of the group during a sensing operation of the amount performed on the group is based on a predicted drift of the threshold voltage of the memory cell of the group.

4. The device of claim 1, wherein the magnitude of the negative sensing voltage is equal to the magnitude of the negative sensing voltage used to determine the data state of the memory cell of the group during a sensing operation of the amount performed on the group.

5. The device of claim 1, wherein the circuitry is configured to perform the operation of programming the memory cells of the group determined by the two sensing operations to be in the reset data state to the reset data state by: A set voltage pulse is applied to the memory cell of the group determined to be in the reset data state; and After the set voltage pulse is applied, a reset voltage pulse is applied to the memory cell of the group that is determined to be in the reset data state.

6. The device of claim 1, wherein each of the memory cells in the group is a self-selecting memory cell that serves as both a selection element and a storage element of a single material.

7. The device according to claim 6, wherein the single material is a chalcogenide material.

8. A method for operating a memory (302), comprising: Determine whether the amount of sensing operation performed on the group of memory cells (125) has met or exceeded a threshold amount; and When it is determined that the amount of the sensing operation has met or exceeded the threshold amount, the following operations are performed: The group of memory cells (125) is sensed using a positive sensing voltage to determine the data state of each of the memory cells (125); The group of memory cells (125) is sensed using a negative sensing voltage to determine the data state of each of the memory cells (125); as well as The operation of programming the memory cells (125) of the group that are determined to be in a reset data state by the two sensing operations to the reset data state.

9. The method of claim 8, wherein the method comprises: Determine whether the amount of sensing operations performed on the group of memory cells has met or exceeded the threshold amount within a specific time period; as well as When it is determined that the amount of sensing operation performed on the group of memory cells has met or exceeded the threshold amount within the specific time amount, the sensing operation is performed on the group of memory cells using the positive sensing voltage, the sensing operation is performed on the group of memory cells using the negative sensing voltage, and the operation of programming the memory cells of the group determined to be in the reset data state is performed.

10. The method of claim 8, wherein the operation of programming the memory cells of the group determined to be in a reset data state is a refresh operation.

11. The method of claim 8, wherein the method includes performing the sensing operation on the group of memory cells using the positive sensing voltage only when it is determined that the amount of the sensing operation has been satisfied or exceeded the threshold amount, and performing the sensing operation on the group of memory cells using the negative sensing voltage.

12. The method of claim 8, wherein the method includes performing the operation of programming the memory cells of the group that are determined to be in the reset data state by the two sensing operations to the reset data state only when any memory cell of the group is determined to be in the reset data state by the two sensing operations.

13. A memory device (300) comprising: Memory (302), having a group of memory cells (125); and A circuit system (304) is configured to perform the following operations when the amount of a sensing operation performed on the group of memory cells (125) meets or exceeds a threshold amount: A sensing operation is performed on the group of memory cells (125) using a positive sensing voltage, the magnitude of which is adjusted according to the magnitude of a positive sensing voltage used to determine the data state of the memory cells (125) of the group during the sensing operation performed on the group. A sensing operation is performed on the group of memory cells (125) using a negative sensing voltage; as well as The operation of programming the memory cell (125) of the group that is determined to be in a reset data state by the two sensing operations to the reset data state is performed.

14. The device of claim 13, wherein the magnitude of the positive sensing voltage for determining the data state of the memory cell of the group during a sensing operation of the amount performed on the group is configured to eliminate drift of the threshold voltage of the memory cell of the group.

15. The device of claim 13, wherein the adjustment of the magnitude of the positive sensing voltage based on the magnitude of the positive sensing voltage used to determine the data state of the memory cells of the group during the sensing operation of the amount performed on the group is based on the expected drift of the threshold voltage of the memory cells of the group.

16. The device of claim 13, wherein the circuitry is configured to determine, based on a sensing operation of the amount performed on the group of memory cells, the adjustment of the magnitude of the positive sensing voltage according to the magnitude of the positive sensing voltage used to determine the data state of the memory cells of the group during the sensing operation of the amount performed on the group.

17. The device of claim 13, wherein the circuitry is configured to determine, based on an error rate associated with an error correction operation performed on data, the adjustment of the magnitude of the positive sensing voltage according to the magnitude of the positive sensing voltage used to determine the data state of the memory cells of the group during a sensing operation of the amount performed on the group, the data being sensed during the sensing operation of the amount performed on the group of memory cells.

18. A method for operating a memory (302), comprising: Determine whether the amount of sensing operation performed on the group of memory cells (125) has met or exceeded a threshold amount; and When it is determined that the amount of the sensing operation has met or exceeded the threshold amount, the following operations are performed: The group of memory cells (125) is sensed using a positive sensing voltage to determine the data state of each of the memory cells (125); The group of memory cells (125) is sensed using a negative sensing voltage to determine the data state of each of the memory cells (125); as well as The operation of programming the memory cell (125) of the group determined to be in the reset data state by the two sensing operations to the reset data state, wherein the operation includes applying a reset voltage pulse to the memory cell (125) of the group determined to be in the reset data state by the two sensing operations.

19. The method of claim 18, wherein the operation of programming the memory cells of the group determined to be in the reset data state by the two sensing operations to the reset data state includes applying a setting voltage pulse to the memory cells of the group determined to be in the reset data state before applying the reset voltage pulse to the memory cells of the group determined to be in the reset data state.

20. The method of claim 18, wherein the reset data state is associated with an asymmetric threshold voltage distribution, the asymmetric threshold voltage distribution having a greater magnitude for negative polarity than for positive polarity.

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