Multi-fast charging protocol control circuit, control method, related chip and electronic device

Abstract

This application provides a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmitting module, a VOOC transmitting module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, and switches G1, G2, and G3. The charging logic control module controls the voltage detection modules to detect the voltages of the DP and DM interfaces, performs timing through the timer module, controls the on / off state of each switch based on the voltage detection results, timing results, and VBUS interface current, communicates with the load device using the corresponding communication protocol, and charges the load device through the VBUS interface. The multi-fast charging protocol control circuit provided in this application can realize fast charging of multiple fast charging protocols. When applied to a fast charging protocol chip, a single chip can support multiple fast charging protocols, offering flexible application and cost savings.

Description

Technical Field

[0001] This application relates to the field of fast charging technology, and in particular to a multi-fast charging protocol control circuit, control method, related chips and electronic devices. Background Technology

[0002] With the rapid popularization of fast charging technology, more and more mobile phone manufacturers are launching their own proprietary fast charging protocols. Currently, the mainstream protocols on the market include Quick Charge (QC) 3.0 / 2.0, Dedicated Charging Ports (DCP), Fast Charge Protocol (FCP), Super Fast Charge (SCP), and Adaptive Fast (AFC), among others. However, traditional fast charging protocol chips typically only support a single fast charging protocol and cannot support multiple protocols with a single chip. This results in some mobile phones or electronic devices being unable to fast charge, leading to protocol compatibility issues. Summary of the Invention

[0003] This application provides a multi-fast charging protocol control circuit, control method, chip, and electronic device, aiming to solve the protocol compatibility problem caused by the inability of a single fast charging protocol chip to support multiple fast charging protocols in traditional fast charging protocol chips.

[0004] In a first aspect, embodiments of this application provide a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmitting module, a VOOC transmitting module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, and switches G1, G2, and G3.

[0005] The charging logic control module is connected to the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module, the first port of the AFSCP transmitting module, the first port of the VOOC transmitting module, the control port of switch G1, the control port of switch G2, and the control port of switch G3. The second port of the first voltage detection module is combined with the first port of switch G1 and then connected to the DP interface and the first port of switch G2. The second port of switch G1 is connected to the second port of the VOOC transmitting module. The second port of the second voltage detection module is combined with the first port of switch G3 and then connected to the DM interface and the second port of switch G2. The second port of switch G3 is connected to the second port of the AFSCP transmitting module.

[0006] The DP interface, DM interface, VBUS interface, and GND interface are used to connect to the load device. The VOOC transmitting module is used to communicate with the load device via the VOOC protocol under the control of the charging logic control module. The AFSCP transmitting module is used to communicate with the load device via the AFC / SCP / FCP protocol under the control of the charging logic control module. The charging logic control module is used to control the first voltage detection module to detect the voltage of the DP interface, control the second voltage detection module to detect the voltage of the DM interface, and use the timer module to perform timing. Based on the voltage detection results, timing results, and the current of the VBUS interface, the module controls the on / off state of switches G1, G2, and G3 to adjust the path state of the multi-fast charging protocol control circuit, and uses the corresponding communication protocol to communicate with the load device, and charges the load device through the VBUS interface.

[0007] Secondly, this application provides a control method for a multi-fast charging protocol control circuit, wherein the multi-fast charging protocol control circuit includes the multi-fast charging protocol control circuit described in the first aspect, and the control method includes the following steps:

[0008] When communicating with the load device via the multi-fast charging protocol control circuit, the charging logic control module defaults to using the DCP fast charging protocol and controls the path state of the multi-fast charging protocol control circuit to the first state.

[0009] When the charging logic control module determines the voltage change of the DP interface or DM interface based on the voltage detection results of the first voltage detection module or the second voltage detection module, the timer module starts timing for time t1.

[0010] If the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the time t1, then after the time t1, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the second state, the switch G2 is closed, and the DP interface and the DM interface are short-circuited.

[0011] When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is within the preset voltage range based on the voltage detection result of the first voltage detection module, then the timer module starts timing for time t2.

[0012] If, within the time t2, the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the voltage of the DP interface is always within the preset voltage range;

[0013] Then, after time t2, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the third state, the switch G2 is opened, and the short circuit between the DP interface and the DM interface is broken.

[0014] The charging logic control module controls the closing of switches G1 and G3, and determines whether the DM interface is less than the first preset voltage value based on the voltage detection result of the second voltage detection module.

[0015] If so, the timer module starts timing for time t3;

[0016] If, within the time interval t3, the charging logic control module determines, based on the voltage detection result of the second voltage detection module, that the voltage of the DM interface is always less than the first preset voltage value, then the QC handshake is successful; otherwise, the QC handshake fails.

[0017] If the QC handshake is successful, then after time t3, check whether an AFC / SCP / FCP data packet is received on the DM interface;

[0018] If received, the device communicates with the load device via the AFSCP sending module using the AFC / SCP / FCP protocol.

[0019] If no signal is received, the charging logic control module adopts the QC fast charging protocol and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module.

[0020] If the QC handshake fails, the charging logic control module will detect whether the current of the VBUS interface is greater than the preset current value after the t3 time.

[0021] If so, the timer module will start timing for time t4;

[0022] If, within the time period t4, the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value, then it communicates with the load device via the VOOC sending module using the VOOC protocol.

[0023] Thirdly, this application provides a multi-fast charging protocol control chip, including the multi-fast charging protocol control circuit as described in the first aspect.

[0024] Fourthly, this application provides an electronic device including a multi-fast charging protocol control chip as described in the third aspect.

[0025] As can be seen, this application provides a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmitting module, a VOOC transmitting module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, and switches G1, G2, and G3. The charging logic control module is used to control the first and second voltage detection modules to detect the voltage of the DP and DM interfaces respectively, to perform timing through the timer module, and to control the on / off state of switches G1, G2, and G3 based on the voltage detection results, timing results, and the current of the VBUS interface. It also communicates with the load device using the corresponding communication protocol and charges the load device through the VBUS interface. Therefore, the multi-fast charging protocol control circuit provided in this application can realize fast charging of multiple fast charging protocols. When applied to fast charging protocol chips, a single chip can support multiple fast charging protocols, offering flexible application and cost savings. Attached Figure Description

[0026] Figure 1 This is a circuit schematic diagram of a multi-fast charging protocol control circuit provided in this application;

[0027] Figure 2 This is a circuit schematic diagram of a voltage detection module provided in this application;

[0028] Figure 3 This is a circuit schematic diagram of another multi-fast charging protocol control circuit provided in this application;

[0029] Figure 4 This is a circuit schematic diagram of a data voltage output module provided in this application;

[0030] Figure 5 This is a circuit schematic diagram of another multi-fast charging protocol control circuit provided in this application;

[0031] Figure 6 This is a circuit schematic diagram of another multi-fast charging protocol control circuit provided in this application;

[0032] Figure 7 This is a flowchart illustrating a control method for a multi-fast charging protocol control circuit provided in this application;

[0033] Figure 8 This is a flowchart illustrating another control method for a multi-fast charging protocol control circuit provided in this application.

[0034] The present application will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] It should be noted that the terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0037] Example 1:

[0038] Reference Figure 1 This embodiment provides a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmission module (i.e., an FCP / SCP / AFC protocol transmission module), a flash charging VOOC transmission module, a data positive signal (DP) interface, a data negative signal (DM) interface, a voltage positive terminal VBUS interface, a voltage negative terminal GND interface, a timer module, and switches G1, G2, and G3.

[0039] The charging logic control module is connected to the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module, the first port of the AFSCP transmitting module, the first port of the VOOC transmitting module, the control port of switch G1, the control port of switch G2, and the control port of switch G3. The second port of the first voltage detection module is combined with the first port of switch G1 and then connected to the DP interface and the first port of switch G2. The second port of switch G1 is connected to the second port of the VOOC transmitting module. The second port of the second voltage detection module is combined with the first port of switch G3 and then connected to the DM interface and the second port of switch G2. The second port of switch G3 is connected to the second port of the AFSCP transmitting module.

[0040] The DP interface, DM interface, VBUS interface, and GND interface are used to connect to the load device. The VOOC transmitting module is used to communicate with the load device via the VOOC protocol under the control of the charging logic control module. The AFSCP transmitting module is used to communicate with the load device via the AFC / SCP / FCP protocol under the control of the charging logic control module. The charging logic control module is used to control the first voltage detection module to detect the voltage of the DP interface, control the second voltage detection module to detect the voltage of the DM interface, and use the timer module to perform timing. Based on the voltage detection results, timing results, and the current of the VBUS interface, the module controls the on / off state of switches G1, G2, and G3 to adjust the path state of the multi-fast charging protocol control circuit, and uses the corresponding communication protocol to communicate with the load device, and charges the load device through the VBUS interface.

[0041] The multi-fast charging protocol control circuit described in the embodiments of this application can be applied to the fast charging protocol control chip at the power adapter end.

[0042] Specifically, in terms of communicating with the load device using the corresponding fast charging protocol, the charging logic control module can be used to control the VOOC transmitting module to communicate with the load device via the DP interface using the VOOC protocol, and to control the AFSCP transmitting module to communicate with the load device via the DM interface using the AFC / SCP / FCP protocol.

[0043] The charging logic control module controls two voltage detection modules (the first voltage detection module and the second voltage detection module) to detect the voltage of the DP interface and the DM interface. It can include configuring the voltage detection modules to detect voltages of different value ranges through the same voltage detection module.

[0044] In practice, when the multi-fast charging protocol circuit is fast charging the load device, the charging logic control module can default to using one fast charging protocol as the initial fast charging protocol. Subsequently, it can determine whether to switch to other fast charging protocols based on the protocol communication with the load device. For example, the charging logic control module can default to using the DCP protocol. After connecting to the load device, it can adjust the path state of the multi-fast charging protocol control circuit and perform a protocol handshake with the load device to confirm whether to switch fast charging protocols.

[0045] For example, when the DCP fast charging protocol is used by default, after the charging logic control module confirms the connection with the load device based on the voltage detection result of the voltage detection module (for example, based on the voltage detection result of the first voltage detection module or the second voltage detection module, it determines that the voltage of the DP interface or DM interface changes and is maintained for a period of time), the charging logic control module can control the switch G2 to close, so that the DP interface and DM interface are short-circuited, and notify the load device that the DCP protocol is used.

[0046] After the load device detects a short circuit between the DP and DM interfaces, it can determine that the power adapter uses the DCP fast charging protocol. If the load device needs to use other fast charging protocols, it can control the voltage output to the DP and DM interfaces accordingly. The charging logic control module can determine whether to switch to the fast charging protocol based on the voltage detection results.

[0047] For example, based on the voltage detection results of the first voltage detection module, if the charging logic control module determines that the voltage value on the DP interface has remained within a preset voltage range for a specific time, it can control the disconnect switch G2 to disconnect the short circuit between the DP interface and the DM interface, and enable switches G1 and G3 to perform a QC protocol handshake with the load device. Specifically, it can detect whether the voltage on the DM interface meets the preset conditions to determine whether the QC handshake is successful. Since switches G1 and G3 are enabled, the AFSCP transmitting module and the VOOC transmitting module can communicate with the load device through the DP interface and the DM interface under the control of the charging logic control module, according to the corresponding fast charging protocol. If the QC handshake is successful, it can further determine whether to use the AFC / SCP / FCP fast charging protocol or the QC fast charging protocol based on whether the DM interface receives AFC / SCP / FCP data packets. Alternatively, if the QC handshake fails, it can determine whether to use the VOOC fast charging protocol based on the current value on the VBUS. After determining the fast charging protocol to be used, the charging logic control module can adjust the output voltage on VBUS according to the voltage detection results, and then realize fast charging that supports multiple fast charging protocols through the above-mentioned multi-fast charging logic control circuit.

[0048] Specifically, when communicating with the load via VOOC protocol or AFC / SCP / FCP protocol, the AFSCP transmitting module and the VOOC transmitting module are used to transmit signals (specifically, the charging logic control module can control the AFSCP transmitting module to output a specific voltage signal to the DM interface and control the VOOC transmitting module to output a specific voltage signal to the DP interface). The charging logic control module is used to determine the signal from the load device based on the voltage detection result.

[0049] In one possible example, refer to Figure 2The first voltage detection module includes voltage comparators CMP1, CMP2, and CMP3; the second voltage detection module includes voltage comparators CMP4, CMP5, and CMP6. The first input terminals of voltage comparators CMP1, CMP2, and CMP3, and the first port of switch G1 are combined and connected to the DP interface and the first port of switch G2. The first input terminals of voltage comparators CMP4, CMP5, and CMP6, and the first port of switch G3 are combined and connected to the DM interface and the second port of switch G2. The output terminals of voltage comparators CMP1, CMP2, CMP3, CMP4, CMP5, and CMP6 are connected to the charging logic control module.

[0050] Among them, voltage comparators CMP1, CMP2, and CMP3 are used to detect the voltage on the DP interface, and voltage comparators CMP4, CMP5, and CMP6 are used to detect the voltage on the DM interface. The charging logic control module can determine the voltage on the DP interface and the DM interface respectively based on the voltage detection results of the above comparators.

[0051] Continue to refer to Figure 2 In this example, the first voltage detection module further includes: data selector D1 and data selector D2, and the second voltage detection module further includes: data selector D3 and data selector D4.

[0052] The second input terminal of voltage comparator CMP1 is connected to the output terminal of data selector D1, the second input terminal of voltage comparator CMP2 is connected to the output terminal of data selector D2, the input voltage of the second input terminal of voltage comparator CMP3 is the first input voltage, the input voltage of the first input terminal of data selector D1 is the second input voltage, the input voltage of the second input terminal of data selector D1 is the third input voltage, the input voltage of the first input terminal of data selector D2 is the fourth input voltage, and the input voltage of the second input terminal of data selector D2 is the fifth input voltage.

[0053] The second input terminal of voltage comparator CMP4 is connected to the output terminal of data selector D3; the second input terminal of voltage comparator CMP5 is connected to the output terminal of data selector D4; the input voltage of the second input terminal of voltage comparator CMP6 is the sixth input voltage; the input voltage of the first input terminal of data selector D3 is the seventh input voltage; the input voltage of the second input terminal of data selector D3 is the eighth input voltage; the input voltage of the first input terminal of data selector D4 is the ninth input voltage; and the input voltage of the second input terminal of data selector D4 is the tenth input voltage.

[0054] The first and sixth input voltages can be 0.325V, the second and seventh input voltages can be 2.9V, the third, fourth, eighth and ninth input voltages can be 2.0V, the fifth input voltage can be 1.2V, and the tenth input voltage can be 1.5V.

[0055] In this system, one input terminal of the voltage comparator is connected to the output terminal of a data selector. The two input terminals of the data selector have different voltage values. In other words, one input terminal of the voltage comparator can be connected to different input voltages, thus enabling the detection of voltages in different voltage ranges through the same voltage detection module.

[0056] For example, when the input voltage at the second input terminal of voltage comparator CMP2 is 2.0V (i.e., data selector D2 selects 2.0V) and the input voltage at the second input terminal of voltage comparator CMP3 is 0.325V, the first voltage detection module can detect voltages less than 0.325V, voltages between 0.325V and 2.0V, and voltages greater than 2.0V (determined by the outputs of voltage comparators CMP2 and CMP3). When the input voltage at the second input terminal of voltage comparator CMP2 is 1.2V (i.e., data selector D2 selects 1.2V), the first voltage detection module can also detect voltages less than 0.325V, voltages between 0.325V and 1.2V, and voltages greater than 1.2V.

[0057] In practice, the voltage selected at the input terminal of the voltage comparator may differ when using different fast charging protocol modes to quickly charge the load device. For example, when using the DCP fast charging protocol, the input voltage at the second input terminal of voltage comparator CMP1 and voltage comparator CMP4 can be 2.9V, while the input voltage at the second input terminal of voltage comparator CMP2 and voltage comparator CMP5 can be 2.0V.

[0058] Once the charging logic module successfully hands over the QC interface with the load device and confirms the need for the QC fast charging protocol, the input voltages of voltage comparators CMP1 and CMP4 can be set to 2.0V. The charging logic control module can then control the output voltage of the VBUS interface based on the voltage detection results from the first and second voltage detection modules. The relationship between the DP and DM interface voltages and the VBUS output voltage is shown in Table 1 below.

[0059] The adapter voltage is the VBUS output voltage. The first input terminal of each voltage comparator is the non-inverting input terminal, and the second input terminal is the inverting input terminal. When the voltage at the non-inverting input terminal of a voltage comparator is greater than the voltage at the inverting input terminal, the signal at the output terminal of the voltage comparator is 0, and vice versa.

[0060] For example, when the output signals of voltage comparators CMP1 and CMP3 are 0 and 1 respectively, and the output information of voltage comparators CMP4 and CMP6 is both 1, the charging logic control module adjusts the output voltage of the VBUS interface to 5V. When both the DP interface voltage and the DM interface voltage are 0V, the adapter voltage is in default mode. When the DP interface voltage is 0.6V and the DM interface voltage is 3.3V, the adapter voltage is in continuous mode, i.e., QC3.0 mode.

[0061] Table 1 QC Protocol Output Voltage Control Logic Table

[0062]

[0063] In one possible example, refer to Figure 3 The multi-fast charging protocol control circuit further includes: a first data voltage output module and a second data voltage output module;

[0064] The charging logic control module is connected to the control port of the first data voltage output module and the control port of the second data voltage output module. The first port of the first data voltage output module, the second port of the first voltage detection module, and the first port of the switch G1 are combined and then connected to the DP interface and the first port of the switch G2. The first port of the second data voltage output module, the second port of the second voltage detection module, and the first port of the switch G3 are combined and then connected to the DM interface and the second port of the switch G2.

[0065] The first data voltage output module is used to provide the output voltage of the DP interface, the second data voltage output module is used to provide the output voltage of the DM interface, and the charging logic control module is also used to control the output voltage of the first data voltage output module and the second data voltage output module.

[0066] In a specific implementation, the charging logic control module can control the output voltage of the two data voltage output modules to output a specific voltage value to the DP interface or DM interface, or control the two data voltage output modules not to output voltage.

[0067] Specifically, in the multi-fast charging protocol control circuit, DCP mode is used for charging. The charging logic control module can control the output voltage of the two data voltage output modules to notify the load device of the specific fast charging mode. For example, controlling the first data voltage output module and the second data voltage output module to output voltages to the DP interface and DM interface to be 2.7V respectively will notify the load device to use the APPLE 2.4A mode.

[0068] In this example, refer to Figure 4 The first data voltage output module includes a data selector D5 and an analog switch OP1, and the second data voltage output module includes a data selector D6 and an analog switch OP2.

[0069] The input voltage at the first input terminal of the data selector D5 is the eleventh input voltage, and the input voltage at the second input terminal of the data selector D5 is the twelfth input voltage. The output terminal of the data selector D5 is connected to the first port of the analog switch OP1. The second port of the analog switch OP1, the second port of the first voltage detection module, and the first port of the switch G1 are combined and connected to the DP interface and the first port of the switch G2. The charging logic control module is connected to the control port of the data selector D5 and the control port of the analog switch OP1.

[0070] The input voltage at the first input terminal of the data selector D6 is the thirteenth input voltage, and the input voltage at the second input terminal of the data selector D6 is the fourteenth input voltage. The output terminal of the data selector D6 is connected to the first port of the analog switch OP2. The second port of the analog switch OP2, the second port of the second voltage detection module, and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2. The charging logic control module is connected to the control port of the data selector D6 and the control port of the analog switch OP2.

[0071] The eleventh and thirteenth input voltages can be 2.7V, and the twelfth and fourteenth input voltages can be 2.0V.

[0072] In practical implementation, the charging logic control module can control whether the first data voltage output module and the second voltage output module output data voltage through the control ports of two analog switches. Furthermore, it can control the output voltage values ​​of the two data voltage output modules by controlling two data selectors D5 and D6. For example, if the charging logic control module controls data selector D5 to select 2.7V and controls analog switch OP1 to open, the first data voltage output module can output 2.7V to the DP interface. When using the DCP fast charging protocol, the charging logic control module can control the output voltage values ​​of the two data voltage output modules according to the specific fast charging mode adopted. Specifically, the correspondence between the output voltage values ​​of the two data voltage output modules and the fast charging mode can be as follows: the first data voltage output module outputs a voltage of 2.0V and the second data voltage output module outputs a voltage of 2.7V, corresponding to the APPLE 1A fast charging mode; the first data voltage output module outputs a voltage of 2.7V and the second data voltage output module outputs a voltage of 2.0V, corresponding to the APPLE 2A fast charging mode; the first data voltage output module outputs a voltage of 2.7V and the second data voltage output module outputs a voltage of 2.7V, corresponding to the APPLE 2.4A fast charging mode.

[0073] In one possible example, refer to Figure 5 The multi-fast charging protocol control circuit also includes: resistor R1, resistor R2, NMOS transistor N1, and NMOS transistor N2;

[0074] The first port of resistor R1, the second port of the first voltage detection module, and the first port of switch G1 are combined and connected to the DP interface and the first port of switch G2. The second port of resistor R1 is connected to the drain of NMOS transistor N1, and the source of NMOS transistor N1 is grounded.

[0075] The first port of resistor R2, the second port of the second voltage detection module, and the first port of switch G3 are combined and connected to the DM interface and the second port of switch G2. The second port of resistor R2 is connected to the drain of NMOS transistor N2, and the source of NMOS transistor N2 is grounded.

[0076] The charging logic control module is connected to the gate of the NMOS transistor N1 and the gate of the NMOS transistor N2;

[0077] The charging logic control module is also used to control the gate voltage of the NMOS transistor N1 and the gate voltage of the NMOS transistor N2.

[0078] Among them, resistors R1 and R2 can be used as bleed resistors. By setting resistors R1 and R2, the impedance requirements of the DP or DM interface in the charging specifications corresponding to the DCP fast charging protocol can be matched.

[0079] In a specific implementation, the charging logic control module can control the conduction state of NMOS transistors N1 and N2 by controlling their gate voltages, thereby enabling control over whether resistors R1 and R2 are grounded.

[0080] For example, when it is necessary to pull down the DM resistor, that is, when it is necessary to ground the resistor R2, the charging logic control module can control the gate voltage of the NMOS transistor N2 to turn on the NMOS transistor N2.

[0081] In one possible example, the charging logic control module includes an S0 port, an S1 port, and an S2 port;

[0082] The S0 port is connected to the control port of the switch G1, the S1 port is connected to the control port of the switch G2, and the S2 port is connected to the control port of the switch G3.

[0083] The charging logic control module is used to control the on / off state of switch G1 through the S0 port, control the on / off state of switch G2 through the S1 port, and control the on / off state of switch G3 through the S2 port.

[0084] In one possible example, the charging logic control module includes ports S3, S4, S5, and S6.

[0085] The S3 port is connected to the control port of the data selector D1, the S4 port is connected to the control port of the data selector D2, the S5 port is connected to the control port of the data selector D3, and the S6 port is connected to the control port of the data selector D4.

[0086] The charging logic control module is used to control the data selector D1 to select the input voltage through the S3 port, control the data selector D2 to select the input voltage through the S4 port, control the data selector D3 to select the input voltage through the S5 port, and control the data selector D4 to select the input voltage through the S6 port.

[0087] In one possible example, the charging logic control module includes ports S7, S8, S9, and S10.

[0088] The S7 port is connected to the control port of the data selector D5, the S8 port is connected to the control port of the analog switch OP1, the S9 port is connected to the control port of the data selector D6, and the S10 port is connected to the control port of the analog switch OP2.

[0089] The charging logic control module is used to control the data selector D5 to select the input voltage through the S7 port, to control the data selector D6 to select the input voltage through the S9 port, and to control the on / off state of the analog switch OP1 through the S8 port and the on / off state of the analog switch OP2 through the S10 port.

[0090] In one possible example, the charging logic control module includes an S11 port and an S12 port;

[0091] The S11 port is connected to the gate of the NMOS transistor N1, and the S12 port is connected to the gate of the NMOS transistor N2.

[0092] The charging logic control module is used to control the gate voltage of the NMOS transistor N1 through the S11 port and to control the gate voltage of the NMOS transistor N2 through the S12 port.

[0093] Specifically, refer to Figure 6 In practical applications, the multi-fast charging protocol control circuit can be specifically as follows: Figure 6 As shown, the multi-fast charging protocol control circuit includes: a charging logic control module, analog switches OP1, OP2, G1, G2, G3, data selectors D1, D2, D3, D4, D5, D6, voltage comparators CMP1, CMP2, CMP3, CMP4, CMP5, CMP6, an AFSCP transmitting module, a VOOC transmitting module, resistors R1 and R2, NMOS transistors N1 and N2, a DP interface, a DM interface, a VBUS interface, a GND interface, and a timer module; the charging logic control module includes ports S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, and S12.

[0094] The charging logic module is connected to the output terminals of voltage comparators CMP1, CMP2, CMP3, CMP4, CMP5, and CMP6, as well as a VBUS interface, a GND interface, a timer module, the first port of the VOOC transmitting module, and the first port of the AFSCP transmitting module.

[0095] The charging logic control module's S3 port is connected to the control port of switch G1, S4 port is connected to the control port of switch G2, S8 port is connected to the control port of switch G3, S9 port is connected to the control port of data selector D1, S10 port is connected to the control port of data selector D2, S11 port is connected to the control port of data selector D3, S12 port is connected to the control port of data selector D4, S0 port is connected to the control port of data selector D5, S1 port is connected to the control port of analog switch OP1, S5 port is connected to the control port of data selector D6, S6 port is connected to the control port of analog switch OP2, S2 port is connected to the gate of NMOS transistor N1, and S7 port is connected to the gate of NMOS transistor N2.

[0096] The input voltage of the first input terminal of data selector D5 is 2.7V, the input voltage of the second input terminal of data selector D5 is 2.0V, and the output terminal of data selector D5 is connected to the first port of analog switch OP1; the input voltage of the first input terminal of data selector D6 is 2.7V, the input voltage of the second input terminal of data selector D6 is 2.0V, and the output terminal of data selector D6 is connected to the first port of analog switch OP2.

[0097] The second port of analog switch OP1, the first input terminal of voltage comparator CMP1, the first input terminal of voltage comparator CMP2, the first input terminal of voltage comparator CMP3, the first port of resistor R1, and the first port of switch G1 are combined and then connected to the DP interface and the first port of switch G2. The second port of analog switch OP2, the first input terminal of voltage comparator CMP4, the first input terminal of voltage comparator CMP5, the first input terminal of voltage comparator CMP6, the first port of resistor R2, and the first port of switch G3 are combined and then connected to the DM interface and the second port of switch G2.

[0098] The second input terminal of voltage comparator CMP1 is connected to the output terminal of data selector D1, the second input terminal of voltage comparator CMP2 is connected to the output terminal of data selector D2, the input voltage of the second input terminal of voltage comparator CMP3 is 0.325V, the input voltage of the first input terminal of data selector D1 is 2.9V, the input voltage of the second input terminal of data selector D1 is 2.0V, the input voltage of the first input terminal of data selector D2 is 2.0V, and the input voltage of the second input terminal of data selector D2 is 1.2V. The second input terminal of voltage comparator CMP4 is connected to the output terminal of data selector D3. The second input terminal of voltage comparator CMP5 is connected to the output terminal of data selector D4. The input voltage of the second input terminal of voltage comparator CMP6 is 0.325V. The input voltage of the first input terminal of data selector D3 is 2.9V. The input voltage of the second input terminal of data selector D3 is 2.0V. The input voltage of the first input terminal of data selector D4 is 2.0V. The input voltage of the second input terminal of data selector D4 is 1.5V.

[0099] The second terminal of resistor R1 is connected to the drain of NMOS transistor N1, and the source of NMOS transistor N1 is grounded; the second terminal of resistor R2 is connected to the drain of NMOS transistor N2, and the source of NMOS transistor N2 is grounded.

[0100] The second port of switch G1 is connected to the second port of the VOOC transmitting module, and the second port of switch G3 is connected to the second port of the AFSCP transmitting module.

[0101] The charging logic control module can adjust the path state of the multi-fast charging protocol control circuit based on the voltage detection results of the voltage detection module, the timing results of the timer module, and the current on the VBUS interface. For example, it can control the on / off state of each switch, the output of each selector, and the gate voltage of the NMOS transistor. By adjusting the path state, it can communicate with the load device via protocol (for example, by shorting the DP and DM interfaces to notify the load device to use the DCP protocol, by detecting the voltage values ​​on the DP and DM to perform a protocol handshake with the load device to determine the fast charging protocol to be used, and by controlling the VOOC transmitting module or AFSCP transmitting module to communicate with the load device via the VOOC protocol or AFC / SCP / FCP protocol). Furthermore, it can use the corresponding fast charging protocol to quickly charge the load device through the VBUS interface.

[0102] As can be seen, the multi-fast charging protocol control circuit provided in this application includes a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmitting module, a VOOC transmitting module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, and switches G1, G2, and G3. The charging logic control module is used to control the first and second voltage detection modules to detect the voltage of the DP and DM interfaces, and to perform timing through the timer module. Based on the voltage detection results, timing results, and the current of the VBUS interface, the module controls the on / off state of switches G1, G2, and G3, and communicates with the load device using the corresponding communication protocol, and charges the load device through the VBUS interface. Therefore, the multi-fast charging protocol control circuit provided in this application can realize fast charging of multiple fast charging protocols. When applied to fast charging protocol chips, a single chip can support multiple fast charging protocols, offering flexible application and cost savings. This helps solve the device compatibility problem caused by the inability of a single chip to support multiple fast charging protocols.

[0103] Example 2:

[0104] Reference Figure 7 This embodiment provides a control method for a multi-fast charging protocol control circuit, applied to the multi-fast charging protocol control circuit in Embodiment 1 above. The method includes:

[0105] S201, the charging logic control module defaults to the DCP fast charging protocol and controls the path state of the multi-fast charging protocol control circuit to the first state.

[0106] In specific implementation, when communicating with the load device via the multi-fast charging protocol control circuit, the charging logic control module can default to using the DCP fast charging protocol. The first state of the multi-fast charging protocol control circuit is the circuit state when using the DCP protocol to fast charge the load device.

[0107] S202, when the charging logic control module determines the voltage change of the DP interface or DM interface based on the voltage detection results of the first voltage detection module and the second voltage detection module, the timer module starts timing for time t1.

[0108] S203, if the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the time t1, then after the time t1, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the second state.

[0109] In the second state, switch G2 is closed, and the DP interface and the DM interface are short-circuited.

[0110] In S202 and 203, the charging logic control module determines that the voltage of the DP interface or DM interface has changed based on the voltage detection result. This indicates that a load device has been connected, and the module can then control switch G2 to close, short-circuiting the DP interface and DM interface, and notifying the load device that the fast charging protocol used is the DCP fast charging protocol.

[0111] S204, when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is within the preset voltage range based on the voltage detection result of the first voltage detection module, then the timer module starts timing for time t2.

[0112] S205, if within the time t2, the charging logic control module determines that the voltage of the DP interface is always within the preset voltage range based on the voltage detection result of the first voltage detection module.

[0113] In S204 and S205, the load device can notify the charging logic control module on the charging adapter side of the supported fast charging protocol by applying a preset voltage value to the DP or DM interface. Based on the voltage detection result, the charging logic control module determines whether the voltage applied to the DP interface by the load device is within the preset voltage range, and thus determines whether to continue the subsequent fast charging protocol handshake steps. This preset voltage range can be determined by the QC fast charging protocol. If the charging logic control module determines that the voltage value on the DP interface is within the preset voltage range, it can continue to execute the subsequent QC protocol handshake steps. Furthermore, since the DP and DM interfaces are short-circuited at this time, the voltage of the DM interface actually changes with the voltage of the DP interface; the voltages of the DP and DM interfaces are the same.

[0114] S206, after the time t2, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the third state.

[0115] In the third state, switch G2 is disconnected, breaking the short circuit between the DP interface and the DM interface.

[0116] S207, the charging logic control module controls the switches G1 and G3 to close, and determines whether the DM interface is less than the first preset voltage value based on the voltage detection result of the second voltage detection module.

[0117] The first preset voltage value can be 0.325V.

[0118] In the actual implementation, since the short circuit between the DP interface and the DM interface is disconnected, the voltage of the DM interface will no longer change with the voltage of the DM interface. The NMOS transistor N2 is turned on, and the voltage value of the DM interface decreases.

[0119] S208, if so, then the timer module starts timing for time t3.

[0120] S209, if within the time period t3, the charging logic control module determines that the voltage of the DM interface is always less than the first preset voltage value based on the voltage detection result of the second voltage detection module, then the QC handshake is successful; otherwise, the QC handshake fails.

[0121] S210, if the QC handshake is successful, then after time t3, check whether AFC / SCP / FCP data packets are received on the DM interface.

[0122] In specific implementation, AFC data packets, SCP data packets, and FCP data packets correspond to different voltage pulse sequences. The charging logic module can detect whether AFC / SCP / FCP data packets have been received on the DM interface by determining the voltage pulse sequence on the DM interface based on the voltage detection result of the second voltage detection module, and then decoding the voltage pulse sequence to determine whether AFC / SCP / FCP data packets have been received.

[0123] S211, if received, then communicate with the load device via the AFSCP sending module using the AFC / SCP / FCP protocol.

[0124] In practice, since the voltage applied to the DM interface by the load device is different when using the three fast charging protocols AFC / SCP / FCP, the charging logic control module can determine which fast charging protocol to communicate with the load device based on the detected data packets.

[0125] S212, if not received, the charging logic control module adopts the QC fast charging protocol and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module.

[0126] S213, if the QC handshake fails, then after time t3, the charging logic control module detects whether the current of the VBUS interface is greater than the preset current value.

[0127] S214, if yes, then the timer module starts timing for time t4.

[0128] S215, if the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value within the time t4, then it communicates with the load device via the VOOC sending module using the VOOC protocol.

[0129] In one possible example, the method further includes: when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the DP interface voltage is not within the preset voltage range; or, if, within the time t2, the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the DP interface voltage is not within the preset voltage range; then the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the second state.

[0130] In practice, if the voltage applied to the DP interface by the load device does not meet the relevant requirements of the QC fast charging protocol, the charging logic control module can control the path state of the multi-fast charging protocol control circuit to return to the state of short connection between the DP interface and the DM interface, and re-detect the voltage of the DP interface. When the voltage of the DP interface is detected to meet the relevant requirements of the QC fast charging protocol, the subsequent steps can continue.

[0131] In one possible example, when determining the voltage change of the DP interface or the DM interface, after the timer module starts timing for time t1, the method further includes: if the voltage detection results of the first voltage detection module and the second voltage detection module change during time t1, then the timer module is reset to zero and the timing for time t1 is restarted.

[0132] In one possible example, the charging logic control module employs the QC fast charging protocol and adjusts the output voltage of the VBUS interface based on the voltage detection result of the voltage detection module, including:

[0133] The charging logic control module determines whether the voltage of the DM interface is greater than the second preset voltage value based on the voltage detection result of the second voltage detection module.

[0134] If not, adjust the output voltage of the VBUS interface to the first output voltage value;

[0135] If so, then determine whether the voltage of the DP interface is greater than the third preset voltage value based on the voltage detection result of the first voltage detection module;

[0136] If not, adjust the output voltage of the VBUS interface to the second output voltage value;

[0137] If so, then determine whether the voltage of the DM interface is greater than the fourth preset voltage value based on the voltage detection result of the second voltage detection module;

[0138] If so, adjust the output voltage of the VBUS interface to the third output voltage value;

[0139] If not, adjust the output voltage of the VBUS interface to the fourth output voltage value;

[0140] After each adjustment of the output voltage of the VBUS interface, the voltage of the DP interface is determined to be greater than the fifth preset voltage value based on the voltage detection result of the first voltage detection module.

[0141] If so, then execute the step of determining whether the voltage of the DM interface is greater than the second preset voltage value based on the voltage detection result of the second voltage detection module;

[0142] If not, the charging logic control module adopts the DCP fast charging protocol and controls the path state of the multi-fast charging protocol circuit to the first state.

[0143] In specific implementation, the second and fifth preset voltage values ​​can be 0.325V, the third and fourth preset voltage values ​​can be 2V, the first output voltage value can be 5V, the second output voltage value can be 12V, the third output voltage value can be 20V, and the fourth output voltage value can be 9V.

[0144] In practical applications, refer to Figure 8 The control method of the multi-fast charging protocol control circuit of this application may specifically include the following steps, and can be applied to, for example... Figure 6 In the multi-fast charging protocol control circuit shown:

[0145] Step 1: Begin, proceed to Step 2.

[0146] Step 2: The default APPLE 2.4A mode is used. Proceed to Step 3.

[0147] When the APPLE 2.4A mode is used by default, the input voltage of analog switches OP1 and OP2 is set to 2.7V by default, the second input voltage of voltage comparators CMP1 and CMP4 is set to 2.9V, the second input voltage of voltage comparator CMP5 is set to 1.5V, and analog switches OP1 and OP2 are turned on.

[0148] When the analog switch is on, controlling data selectors D5 and D6 allows voltage to be output to either the DP or DM interface. When the analog switch is off, no voltage is output to either the DP or DM interface. The charging logic module controls each component through its corresponding port. For example, it controls data selectors D1 and D3 through ports S9 and S11, ensuring that the second input voltages of voltage comparators CMP1 and CMP4 are both set to 2.9V. In practical applications, the second input voltage of voltage comparator CMP5 can also be 2.0V. By setting the input voltages of the voltage comparators, the charging logic control module can determine whether a load device is plugged in based on the output signals of each voltage comparator.

[0149] When using the DCP fast charging protocol for fast charging, the multi-fast charging protocol control module can specifically notify the load device of the fast charging mode by controlling the voltage output to the DP interface and DM interface by controlling the two analog switches. For example, if the voltage output to the DP interface and DM interface by the analog switches OP1 and OP2 is 2.7V, it means that the load device is notified to use the APPLE 2.4A fast charging mode.

[0150] Step 3: If a voltage change is detected at the DP or DM interface, proceed to step 4.

[0151] In practice, the charging logic control module detects voltage changes at the DP or DM interface by the output signals of each voltage comparator. When a voltage change at the DP or DM interface is detected, i.e., as long as the output signal of one voltage comparator jumps, it can be determined that a load device is connected.

[0152] Step 4: Start the timer module to begin timing for time t1, then proceed to step 5.

[0153] In the specific implementation, when the output signal of any voltage comparator jumps, the timer module is set to 0 and the timing t1 is restarted.

[0154] Step 5: Determine whether the timer module has finished timing t1. If yes, proceed to step 6; otherwise, continue with step 5.

[0155] Step 6: Adjust the path status of the multi-fast charging protocol control circuit, short-circuit the DP interface and DM interface, and then proceed to step 7.

[0156] In the specific implementation, the charging logic control module controls switch G2 to close, short-circuit the DP interface and DM interface, and also controls analog switches OP1 and OP2 to close, controls the voltage at the second input terminal of voltage comparator CMP2 to select 1.2V, the voltage at the second input terminal of voltage comparator CMP4 to select 2.0V, and the voltage at the second input terminal of voltage comparator CMP5 to select 1.5V.

[0157] In addition, in step 6, the charging logic control module can also control the gate voltage of NMOS transistor N1 to turn on NMOS transistor N1, enable the DP resistor pull-down, and ground one end of resistor R1.

[0158] The selection of the second input voltage of voltage comparators CMP4 and CMP5 can be used to detect whether FCP / SCP / AFC data packets are received on the DM interface. This is because the voltage applied to the DM interface by the load device is different when using the three fast charging protocols FCP, SCP and AFC. Therefore, different fast charging protocols can be identified by voltage comparators CMP4 and CMP5.

[0159] Step 7: Determine if the DP interface voltage is greater than 0.325V and less than 2V. If yes, proceed to step 8; otherwise, return to step 6.

[0160] In this example, step 7 is performed when a voltage jump is detected at the DP or DM interface.

[0161] Step 8: Start the timer module to start timing for 1.25 seconds, then proceed to step 9.

[0162] Step 9: Determine if the DP interface voltage is greater than 0.325V and less than 2V. If yes, proceed to step 10; otherwise, return to step 6.

[0163] Step 10: Determine if the timer module has reached the set time of 1.25 seconds. If yes, proceed to step 11; otherwise, return to step 9.

[0164] Specifically, steps 7 to 10 above determine whether the voltage of the DP interface is greater than 0.325V and less than 2V for 1.25S. If the DP voltage detected within the 1.25S timed by the timer module is always greater than 0.325V and less than 2.0V, then after the timer module reaches the timing time of 1.25S, the subsequent step 11 is executed.

[0165] In the specific implementation, the charging adapter short-circuits the DP interface and DM interface to notify the load device of the DCP protocol used. The load device can also communicate with the charging adapter through the voltage on the DP interface and DM interface. In steps 7 to 10 above, it can be determined that the voltage applied by the load device on the DP interface is greater than 0.325V and less than 2.0V. Since the DP interface and DM interface are short-circuited, the voltages of the DP interface and DM interface are the same.

[0166] Step 11: Disconnect the short circuit between the DP interface and the DM interface, turn on the NMOS transistor N2, turn on the DM resistor pull-down, and proceed to step 12.

[0167] In the specific implementation, in step 11, the charging logic control module controls the switch G2 to open, that is, to disconnect the short circuit between the DP interface and the DM interface. Then the voltage of the DM interface will no longer change with the voltage of the DM interface. The charging logic control module controls the gate voltage of the NMOS transistor N2 to turn on the NMOS transistor N2, and the resistor R2 is grounded. The detected voltage value of the DM interface is maintained at a low level.

[0168] Step 12: Determine if the DM interface voltage is less than 0.325V. If so, proceed to step 13.

[0169] Step 13: Determine if the QC protocol handshake was successful. If yes, proceed to step 14; otherwise, proceed to step 23.

[0170] Specifically, determining whether the QC protocol handshake is successful can include: starting the timer module to start timing for 10ms, checking whether the voltage of the DM interface is less than 0.325V during the 10ms timing period, if so, then after the timer timing t3 ends, it is determined that the QC protocol handshake is successful; otherwise, it is identified as a QC protocol handshake failure.

[0171] Step 14: Determine whether AFC / SCP / FCP data packets have been received on the DM interface. If yes, proceed to step 27; otherwise, proceed to step 15.

[0172] In the specific implementation, steps 15 to 21 are the process of communicating with the load device to determine the VBUS output voltage when using the QC fast charging protocol to quickly charge the load device.

[0173] Step 15: Determine if the DM interface voltage is greater than 0.325V. If yes, proceed to step 17; otherwise, proceed to step 16.

[0174] Step 16: Confirm that a QC fast charging request has been received from the load device, requesting a 5V charging voltage, and proceed to step 22.

[0175] In practice, the charging logic control module can determine the charging voltage requested by the load device based on the detected voltage values ​​on the DP and DM interfaces. Furthermore, it can control the VBUS to output the requested charging voltage to quickly charge the load device.

[0176] Step 17: Determine if the DP interface voltage is greater than 2V. If yes, proceed to step 19; otherwise, proceed to step 18.

[0177] Step 18: Confirm that a QC fast charging request has been received from the load device, requesting a 12V charging voltage, and proceed to step 22.

[0178] Step 19: Determine if the DM interface voltage is greater than 2V. If yes, proceed to step 20; otherwise, proceed to step 21.

[0179] Step 20: Confirm that a QC fast charging request has been received from the load device, requesting a 20V charging voltage, and proceed to step 22.

[0180] Step 21: Confirm that a QC fast charging request has been received from the load device, requesting a 9V charging voltage, and proceed to step 22.

[0181] Step 22: Determine if the DP interface voltage is greater than 0.325V. If yes, proceed to step 15; otherwise, return to step 1.

[0182] In practice, if the charging logic control module determines that the voltage of the DP interface is not greater than 0.325V based on the voltage detection result, it will exit the QC fast charging mode and control the path state of the multi-fast charging protocol control circuit back to the initial APPLE2.4A mode.

[0183] Step 23: Determine if the VBUS interface current is greater than 1A. If yes, proceed to step 24; otherwise, continue with step 23.

[0184] Step 24: Start the timer module to start timing for 2 seconds, then proceed to step 25.

[0185] Step 25: Determine if the timer module has reached the timing time of 2 seconds. If yes, proceed to step 26; otherwise, continue with step 25.

[0186] Step 26: Communicate with the load device via the VOOC sending module using the VOOC protocol.

[0187] Step 27: Communicate with the load device via the AFSCP sending module using the AFC / SCP / FCP protocol.

[0188] Therefore, the control method of the multi-fast charging protocol control circuit provided in this application can be applied to the design of charging chips, enabling a single protocol chip to be compatible with multiple fast charging protocols, thereby saving chip design costs and chip application costs.

[0189] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A multi-fast charging protocol control circuit, characterized in that, include: Charging logic control module, first voltage detection module, second voltage detection module, AFSCP protocol module, VOOC protocol module, DP interface, DM interface, VBUS interface, GND interface, timer module, switch G1, switch G2, switch G3; The charging logic control module is connected to the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module, the first port of the AFSCP protocol module, the first port of the VOOC protocol module, the control port of switch G1, the control port of switch G2, and the control port of switch G3. The second port of the first voltage detection module is combined with the first port of switch G1 and then connected to the DP interface and the first port of switch G2. The second port of switch G1 is connected to the second port of the VOOC protocol module. The second port of the second voltage detection module is combined with the first port of switch G3 and then connected to the DM interface and the second port of switch G2. The second port of switch G3 is connected to the second port of the AFSCP protocol module. The DP interface, DM interface, VBUS interface, and GND interface are used to connect to the load device. The VOOC protocol module is used to communicate with the load device via the VOOC protocol under the control of the charging logic control module. The AFSCP protocol module is used to communicate with the load device via the AFC / SCP / FCP protocol under the control of the charging logic control module. The charging logic control module is used to control the first voltage detection module to detect the voltage of the DP interface, control the second voltage detection module to detect the voltage of the DM interface, and use the timer module to keep track of time. Based on the voltage detection results, timing results, and the current of the VBUS interface, the module controls the on / off state of switches G1, G2, and G3 to adjust the path state of the multi-fast charging protocol control circuit, communicates with the load device using the corresponding communication protocol, and charges the load device via the VBUS interface.

2. The multi-fast charging protocol control circuit according to claim 1, characterized in that, The first voltage detection module includes voltage comparators CMP1, CMP2, and CMP3, and the second voltage detection module includes voltage comparators CMP4, CMP5, and CMP6. The first input terminal of voltage comparator CMP1, the first input terminal of voltage comparator CMP2, the first input terminal of voltage comparator CMP3, and the first port of switch G1 are combined and then connected to the DP interface and the first port of switch G2. The first input terminals of voltage comparator CMP4, voltage comparator CMP5, and voltage comparator CMP6, and the first port of switch G3 are combined and then connected to the DM interface and the second port of switch G2. The output terminals of voltage comparators CMP1, CMP2, CMP3, CMP4, CMP5, and CMP6 are connected to the charging logic control module.

3. The multi-fast charging protocol control circuit according to claim 2, characterized in that, The first voltage detection module further includes: data selector D1 and data selector D2; the second voltage detection module further includes: data selector D3 and data selector D4. The second input terminal of voltage comparator CMP1 is connected to the output terminal of data selector D1, the second input terminal of voltage comparator CMP2 is connected to the output terminal of data selector D2, the input voltage of the second input terminal of voltage comparator CMP3 is the first input voltage, the input voltage of the first input terminal of data selector D1 is the second input voltage, the input voltage of the second input terminal of data selector D1 is the third input voltage, the input voltage of the first input terminal of data selector D2 is the fourth input voltage, and the input voltage of the second input terminal of data selector D2 is the fifth input voltage. The second input terminal of voltage comparator CMP4 is connected to the output terminal of data selector D3; the second input terminal of voltage comparator CMP5 is connected to the output terminal of data selector D4; the input voltage of the second input terminal of voltage comparator CMP6 is the sixth input voltage; the input voltage of the first input terminal of data selector D3 is the seventh input voltage; the input voltage of the second input terminal of data selector D3 is the eighth input voltage; the input voltage of the first input terminal of data selector D4 is the ninth input voltage; and the input voltage of the second input terminal of data selector D4 is the tenth input voltage.

4. The multi-fast charging protocol control circuit according to claim 1, characterized in that, The multi-fast charging protocol control circuit also includes: a first data voltage output module and a second data voltage output module; The charging logic control module is connected to the control port of the first data voltage output module and the control port of the second data voltage output module. The first port of the first data voltage output module, the second port of the first voltage detection module, and the first port of the switch G1 are combined and then connected to the DP interface and the first port of the switch G2. The first port of the second data voltage output module, the second port of the second voltage detection module, and the first port of the switch G3 are combined and then connected to the DM interface and the second port of the switch G2. The first data voltage output module is used to provide the output voltage of the DP interface, the second data voltage output module is used to provide the output voltage of the DM interface, and the charging logic control module is also used to control the output voltage of the first data voltage output module and the second data voltage output module.

5. The multi-fast charging protocol control circuit according to claim 4, characterized in that, The first data voltage output module includes a data selector D5 and an analog switch OP1; the second data voltage output module includes a data selector D6 and an analog switch OP2. The input voltage at the first input terminal of the data selector D5 is the eleventh input voltage, and the input voltage at the second input terminal of the data selector D5 is the twelfth input voltage. The output terminal of the data selector D5 is connected to the first port of the analog switch OP1. The second port of the analog switch OP1, the second port of the first voltage detection module, and the first port of the switch G1 are combined and connected to the DP interface and the first port of the switch G2. The charging logic control module is connected to the control port of the data selector D5 and the control port of the analog switch OP1. The input voltage at the first input terminal of the data selector D6 is the thirteenth input voltage, and the input voltage at the second input terminal of the data selector D6 is the fourteenth input voltage. The output terminal of the data selector D6 is connected to the first port of the analog switch OP2. The second port of the analog switch OP2, the second port of the second voltage detection module, and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2. The charging logic control module is connected to the control port of the data selector D6 and the control port of the analog switch OP2.

6. The multi-fast charging protocol control circuit according to claim 1, characterized in that, The multi-fast charging protocol control circuit also includes: resistor R1, resistor R2, NMOS transistor N1, and NMOS transistor N2; The first port of resistor R1, the second port of the first voltage detection module, and the first port of switch G1 are combined and connected to the DP interface and the first port of switch G2. The second port of resistor R1 is connected to the drain of NMOS transistor N1, and the source of NMOS transistor N1 is grounded. The first port of resistor R2, the second port of the second voltage detection module, and the first port of switch G3 are combined and connected to the DM interface and the second port of switch G2. The second port of resistor R2 is connected to the drain of NMOS transistor N2, and the source of NMOS transistor N2 is grounded. The charging logic control module is connected to the gate of the NMOS transistor N1 and the gate of the NMOS transistor N2; The charging logic control module is also used to control the gate voltage of the NMOS transistor N1 and the gate voltage of the NMOS transistor N2.

7. A control method for a multi-fast charging protocol control circuit, characterized in that, The method includes the following steps: When communicating with the load device via the multi-fast charging protocol control circuit, the charging logic control module defaults to using the DCP fast charging protocol and controls the path state of the multi-fast charging protocol control circuit to the first state. When the charging logic control module determines the voltage change of the DP interface or DM interface based on the voltage detection results of the first voltage detection module or the second voltage detection module, the timer module starts timing for time t1. If the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the time t1, then after the time t1, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the second state, the switch G2 is closed, and the DP interface and the DM interface are short-circuited. When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is within the preset voltage range based on the voltage detection result of the first voltage detection module, then the timer module starts timing for time t2. If, within the time t2, the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the voltage of the DP interface is always within the preset voltage range; Then, after time t2, the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the third state, the switch G2 is opened, and the short circuit between the DP interface and the DM interface is broken. The charging logic control module controls switches G1 and G3 to close, and determines whether the DM interface is less than the first preset voltage value based on the voltage detection result of the second voltage detection module. If so, the timer module starts timing for time t3; If, within the time interval t3, the charging logic control module determines, based on the voltage detection result of the second voltage detection module, that the voltage of the DM interface is always less than the first preset voltage value, then the QC handshake is successful; otherwise, the QC handshake fails. If the QC handshake is successful, then after time t3, check whether an AFC / SCP / FCP data packet is received on the DM interface; If received, it communicates with the load device via the AFSCP protocol module using the AFC / SCP / FCP protocol. If no signal is received, the charging logic control module adopts the QC fast charging protocol and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module. If the QC handshake fails, the charging logic control module will detect whether the current of the VBUS interface is greater than the preset current value after the t3 time. If so, the timer module will start timing for time t4; If, within the time period t4, the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value, then it communicates with the load device via the VOOC protocol module using the VOOC protocol.

8. The method according to claim 7, characterized in that, The method further includes: When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the DP interface voltage is not within the preset voltage range; or... If, within the time period t2, the charging logic control module determines, based on the voltage detection result of the first voltage detection module, that the voltage of the DP interface is not within the preset voltage range; Then the charging logic control module controls the path state of the multi-fast charging protocol control circuit to the second state.

9. A multi-fast charging protocol control chip, characterized in that, Includes the multi-fast charging protocol control circuit as described in any one of claims 1-6.

10. An electronic device, characterized in that, The electronic device includes the multi-fast charging protocol control chip as described in claim 9.

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