A resonant converter and a delay compensation circuit thereof

Abstract

This invention discloses a resonant converter and its delay compensation circuit. The delay compensation circuit generates a compensation signal by reverse-modulating the primary-side sampling signal that characterizes the resonant current of the resonant circuit in the resonant converter. This compensation signal is then used to control the power switch, thereby achieving adaptive delay power compensation, improving the stability of the output power, and enhancing the flexibility and convenience of the circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and more specifically, to a resonant converter and its delay compensation circuit. Background Technology

[0002] When using current-mode controlled LLC and LCC resonant converters, the controllers are designed with full-load point, over-power protection load point, and operating mode switching load point according to application requirements. Due to the delays of the internal comparators of the controller, the transmission delay of the PWM control signal, the drive delay of the PWM control signal to the driver, and the rise or fall delay of the midpoint voltage of the half-bridge or full-bridge, the actual power point will be higher than the design value. When the switching frequency is higher, the proportion of the sum of all delays to the switching cycle is higher, and the deviation between the actual power point and the design value will be greater, causing the system to fail to operate at its required design point. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a resonant converter and its delay compensation circuit to achieve adaptive delay power compensation, thereby improving the stability of output power and the flexibility and convenience of the circuit.

[0004] In a first aspect, embodiments of the present invention provide a delay compensation circuit for a resonant converter. The delay compensation circuit is configured to reverse-modulate a primary-side sampling signal characterizing the resonant current of the resonant circuit in the resonant converter to generate a compensation signal, thereby controlling the adjustment of a power switch based on the compensation signal to achieve delay compensation.

[0005] Optionally, the delay compensation circuit is further configured to reverse-modulate the primary-side sampling signal during the delay time of each switching cycle to generate a compensation signal.

[0006] Optionally, the delay compensation circuit is configured to, in response to receiving a control signal that controls the power switches in the resonant converter to turn off, begin to reverse-modulate the primary-side sampling signal to adjust the output power of the resonant converter transmitted from the primary side to the secondary side.

[0007] Optionally, the delay compensation circuit is configured to stop reverse modulation of the primary-side sampling signal before receiving a control signal that controls the conduction of each power switch in the resonant converter.

[0008] Optionally, the delay compensation circuit is configured to invert the primary-side sampled signal and generate the compensation signal based on the inverted primary-side sampled signal.

[0009] Optionally, the primary-side sampling signal is used to characterize the current signal of the resonant circuit;

[0010] The delay compensation circuit is configured to be controlled by the control signals of each of the power switches, to reverse the primary side sampling signal, and to integrate the reverse-controlled primary side sampling signal to generate the compensation signal.

[0011] Optionally, the delay compensation circuit includes:

[0012] An electrical signal processing unit is configured to be controlled by the control signals of each of the power switches to reverse the primary-side sampling signals and obtain the target electrical signal.

[0013] An integration unit is configured to integrate the target electrical signal to obtain a compensation signal.

[0014] Optionally, the delay compensation circuit further includes:

[0015] The conversion unit is configured to perform voltage-to-current conversion on the primary-side sampled signal to obtain the primary-side current signal.

[0016] Optionally, the electrical signal processing unit is configured to reverse-modulate the primary-side sampling signal in response to a control signal that controls the power switches to turn on or off, thereby acquiring the target electrical signal.

[0017] Optionally, the electrical signal processing unit includes a current source;

[0018] The coefficient of the current source is determined according to the control signal that controls the on or off time of each power switch.

[0019] Optionally, the coefficient of the current source is negative in response to the control signal when the control power switch is turned off, and the coefficient of the current source is positive in response to the control signal when the control power switch is turned on.

[0020] Optionally, the electrical signal processing unit includes:

[0021] The trigger module is configured to generate transformation coefficients in response to a control signal that controls the on or off times of each of the power switches;

[0022] An electrical signal generation unit is configured to generate the target electrical signal based on the transformation coefficients and the primary-side sampled signal.

[0023] Optionally, the triggering module includes:

[0024] The first trigger circuit is configured to generate a negative coefficient in response to a control signal that controls the turn-off time of each of the power switches;

[0025] The second trigger circuit is configured to generate a positive coefficient in response to a control signal that controls the on-time of each of the power switches.

[0026] Optionally, the resonant converter is a half-bridge resonant converter, and the control signal includes the upper MOSFET control signal and the lower MOSFET control signal;

[0027] The first trigger circuit includes:

[0028] The first trigger is configured to be set in response to the lower control signal when the lower power switch is turned off, and to be reset in response to the rise of the intermediate voltage corresponding to each power switch, wherein the intermediate voltage is the voltage of the common terminal of the upper power switch and the lower power switch.

[0029] The second trigger is configured to be set in response to the upper transistor control signal at the moment when the upper power switch is turned off, and to be reset in response to the drop in the intermediate voltage.

[0030] Optionally, the second trigger circuit includes:

[0031] The third trigger is configured to be set in response to the lower transistor control signal when the controlled power switch is turned on, and to be reset in response to the lower transistor control signal when the controlled power switch is turned off.

[0032] The fourth trigger is configured to be set in response to the upper transistor control signal when the upper power switch is turned on, and to be reset in response to the upper transistor control signal when the upper power switch is turned off.

[0033] Optionally, the integration unit includes an energy storage element.

[0034] The energy storage element is configured to integrate the target electrical signal to obtain the compensation signal.

[0035] Optionally, the resonant converter is a full-bridge resonant converter, and the control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal;

[0036] The triggering module is configured to generate negative coefficients in response to the first and fourth control signals controlling the first and fourth power switches to turn off, or the second and third control signals controlling the second and third power switches to turn off, and to generate positive coefficients in response to the first and fourth control signals controlling the first and fourth power switches to turn on, or the second and third control signals controlling the second and third power switches to turn on.

[0037] In a second aspect, embodiments of the present invention provide a resonant converter, the resonant converter comprising:

[0038] The primary-side control circuit transmits electrical signals to the secondary-side control circuit; and

[0039] The secondary-side control circuit is configured to receive and process the electrical signal transmitted by the primary-side control circuit to obtain the output electrical signal of the resonant converter;

[0040] The primary-side control circuit includes the delay compensation circuit described above.

[0041] This invention discloses a resonant converter and its delay compensation circuit. The delay compensation circuit generates a compensation signal by reverse-modulating the primary-side sampling signal that characterizes the resonant current of the resonant circuit in the resonant converter. This compensation signal is then used to control the power switch, thereby achieving adaptive delay power compensation, improving the stability of the output power, and enhancing the flexibility and convenience of the circuit. Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0043] Figure 1 This is a control principle diagram of a resonant converter based on related technologies;

[0044] Figure 2 This is a waveform diagram of the resonant converter of the relevant technology;

[0045] Figure 3 This is a circuit diagram of a resonant converter according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of the delay compensation circuit according to an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of an electrical signal processing unit according to an embodiment of the present invention;

[0048] Figure 6 This is a schematic diagram of another electrical signal processing unit according to an embodiment of the present invention;

[0049] Figure 7 This is a circuit diagram of another resonant converter according to an embodiment of the present invention;

[0050] Figure 8 This is a waveform diagram of the resonant converter in an embodiment of the present invention;

[0051] Figure 9 This is a circuit diagram of another resonant converter according to an embodiment of the present invention. Detailed Implementation

[0052] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0053] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0054] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0055] Unless the context explicitly requires it, words such as "including" or "contains" in the instruction manual should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0056] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0057] Figure 1 This is a control principle diagram of a resonant converter based on related technologies. Figure 2 This is a waveform diagram of a resonant converter based on related technologies. This embodiment uses a half-bridge LLC resonant converter as an example to describe the principle of power error caused by transmission and drive delays. Figure 1 As shown, the resonant converter 1 includes a primary-side control circuit 11 and a secondary-side control circuit 12.

[0058] The primary-side control circuit 11 includes an input capacitor Ci1, a power switch Q1, a power switch Q2, and a resonant inductor L. R Resonant capacitor C R Primary coil L M Sampling circuit 111 and driving circuit 112.

[0059] Among them, sampling circuit 111 is used to sample resonant capacitor C. RThe voltage signal VCR. The drive circuit 112 is used to generate control signals PWMH and PWML for power switches Q1 and Q2 based on the resonant capacitor voltage VCR and the reference signal, so as to control and adjust the switching state of power switches Q1 and Q2, thereby adjusting the output signal of the primary control circuit 11, and further adjusting the output signal of the secondary control circuit.

[0060] Furthermore, the driving circuit 112 includes comparator A2, comparator A3, and PWM logic circuit 112a. Comparator A2 is used to compare the first reference signal (V... CM -Vfb1) and the resonant capacitor voltage VCR, comparator A3 is used to compare the second reference signal (V CM The PWM logic circuit 112a generates control signals PWMH and PWML for power switches Q1 and Q2 based on the outputs of comparators A2 and A3, using the resonant capacitor voltage VCR and Vfb1. Vfb1 characterizes the error between the output signal of the secondary control circuit and the desired output value Vref1. The drive circuit 112 also includes a driver 112b, which receives the control signals PWMH and PWML and generates drive signals GATEH and GATEL to directly drive the control terminals of power switches Q1 and Q2, thereby enhancing the drive capability.

[0061] The secondary control circuit 12 includes a secondary coil Ls1, a secondary coil Ls2, diodes D1 and D2, an output capacitor Co1, an output impedance Ro1, and an error generation circuit 121. The error generation circuit 121 is used to calculate the error between the output signal of the secondary control circuit and the desired value Vref1.

[0062] Furthermore, the error generation circuit 121 includes a comparator A1. The comparator A1 uses the sampled value VO of the output signal of the secondary control circuit and the expected value Vref1 to determine the error signal Vfb1.

[0063] It should be understood that Figure 1 The control principle diagram of the LLC resonant converter in this example is merely illustrative; other types of resonant converters will not be described in detail here.

[0064] like Figure 2 As shown, Figure 1 The working principle of the LLC resonant converter in the image is as follows:

[0065] The resonant capacitor voltage VCR sampled by sampling circuit 111 is compared with VH_DESIRE(VCM+Vfb1) and VL_DESIRE(VCM-Vfb1). When the resonant capacitor voltage VCR is less than VL_DESIRE, the PWML signal goes low after a delay time t0 of comparator A2. Symmetrically, when the resonant capacitor voltage VCR is greater than VH_DESIRE, the PWMH signal goes low after a delay time of t0 of comparator A3. After the PWML signal goes low, the drive signal GATEL goes low after a total delay time of t1, including the PWML signal's propagation delay and drive delay. Similarly, after the PWMH signal goes low, the drive signal GATEH goes low after a total delay time of t1, including the PWMH signal's propagation delay and drive delay. It should be understood that this embodiment uses complementary PWML and PWMH signals, and complementary drive signals GATEL and GATEH, as an example.

[0066] When the drive signal GATEL goes low (that is, when the drive signal GATEH goes high), the upper power transistor Q1 turns on, and the voltage VHB at the midpoint HB of the half-bridge starts to rise. The time for VHB to rise to half the input voltage is t2. When the drive signal GATEH goes low (that is, when the drive signal GATEL goes high), the lower power transistor Q2 turns on, and the voltage VHB at the midpoint HB of the half-bridge starts to fall. The time for the symmetrical VHB to fall to half the input voltage is also t2.

[0067] It should be understood that the difference ΔVHL_D between the reference signals VH_DESIRE and VL_DESIRE is proportional to the desired output power Pout_DESIRE. However, due to the introduction of component processing delay, transmission delay, and drive delay, the actual power Pout_REAL is clearly higher than the desired output power Pout_DESIRE. Specifically, in the negative half-cycle of the signal, the desired comparison point is when the resonant capacitor voltage VCR is less than VL_DESIRE, but due to the introduction of delay (t0+t1+t2), the actual comparison point of the resonant converter is when VCR is less than VL_REAL. Symmetrically, in the positive half-cycle of the signal, the desired comparison point is when the resonant capacitor voltage VCR is greater than VH_DESIRE, but due to the introduction of delay (t0+t1+t2), the actual comparison point of the resonant converter is when VCR is greater than VH_REAL. Therefore, the expected reference signal difference VHL_D is obviously smaller than the actual reference signal difference VHL_R. Since the reference signal difference is proportional to the output power, the actual output power Pout_REAL is obviously higher than the expected output power Pout_DESIRE. This will lead to certain errors in the design of the subsequent full load point, overpower protection load point, and operating mode switching load point. Therefore, it is necessary to adjust the power error caused by the delay time to make it basically consistent with the expected value.

[0068] As mentioned above, the delay can be mainly divided into two parts: inherent delay and system delay. The inherent delay consists of the delay of the comparator inside the controller and the transmission delay of the PWM control signal. It is generally determined by the characteristics of the controller and is not affected by changes in external parameters. The system delay generally consists of the drive delay and the rise or fall time of the midpoint voltage of the half-bridge or full-bridge. The system delay is affected by external parameters (such as drive resistor, MOSFET characteristics, etc.) and will change.

[0069] For power errors caused by inherent delays and system delays, a common approach is to treat the sum of all the aforementioned delays as a fixed delay during the design phase, taking into account the power point deviation caused by this fixed delay before designing. This method can compensate for the power point deviation caused by delays to a certain extent, but it lacks flexibility, the accuracy of compensation is not high, and it cannot adapt well to various operating states of the system. When the external parameters of the system change, it is necessary to re-evaluate the relevant delays and redesign. Therefore, this invention provides a resonant converter and its delay compensation circuit to achieve adaptive delay power compensation, improving output power stability and the flexibility and convenience of the circuit.

[0070] This invention provides a delay compensation circuit for reverse modulation of the primary-side sampling signal characterizing the resonant current of the resonant circuit in a resonant converter, generating a compensation signal, and enabling a control signal generated based on the compensation signal to control the power switch, thereby achieving adaptive output power compensation.

[0071] Figure 3 This is a circuit diagram of the resonant converter according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the delay compensation circuit according to an embodiment of the present invention. Figure 3 As shown, this embodiment will still use a half-bridge LLC resonant converter as an example for description. Figure 3 As shown, the resonant converter 3 includes a primary-side control circuit 31 and a secondary-side control circuit 32.

[0072] The primary-side control circuit 31 includes an input capacitor Ci1, a power switch Q1, a power switch Q2, and a resonant inductor L. R Resonant capacitor C R Primary coil L M The circuit consists of a sampling circuit 311, a delay compensation circuit 312, and a driving circuit 313. The resonant inductor L... R Resonant capacitor C R Primary coil L M An LLC resonant circuit is formed. In this embodiment, the output signal of the primary control circuit 31 is adjusted by controlling the switching frequency and duty cycle of power switches Q1 and Q2, thereby adjusting the output signal of the secondary control circuit 32.

[0073] The secondary-side control circuit 32 includes a secondary-side adjustment circuit and an error generation circuit 321. The secondary-side adjustment circuit includes a secondary-side coil, a diode, an output capacitor, and an output impedance, as detailed in the above embodiment, and will not be repeated here. The error generation circuit 321 calculates the error between the output signal Vo of the secondary-side control circuit and the desired value Vref. Based on this error, the power switch in the primary-side control circuit 31 can be adjusted so that the output signal Vo of the secondary-side control circuit tends towards the desired value Vref. Further, the error generation circuit 321 includes a comparator A4. The comparator A4 compares the sampled value Vo of the output signal of the secondary-side control circuit with the desired value Vref to determine the error signal Vfb.

[0074] In this embodiment, the sampling circuit 311 is configured to sample the resonant current flowing through the resonant circuit to generate a primary-side sampling signal characterizing the resonant current. In this embodiment, the sampling circuit 311 is a current sampling circuit used to sample the current signal of the resonant circuit and obtain a current sampling signal Vsen. Optionally, the sampling circuit 311 includes a sampling resistor Rsen to sample and obtain the current sampling signal Vsen of the resonant circuit. It should be understood that in other optional implementations, the sampling circuit 311 may also include a voltage-to-current conversion circuit to convert the current sampling signal Vsen into a current signal. The sampling circuit 311 may also directly sample and obtain the current signal of the resonant circuit; this embodiment does not limit this.

[0075] The delay compensation circuit 312 is used to reverse the primary-side sampling signal that characterizes the resonant current of the resonant circuit to generate a compensation signal, and then use the control signal generated based on the compensation signal to control the power switch, thereby achieving adaptive output power compensation.

[0076] Furthermore, in this embodiment, the delay compensation circuit changes the trend of the compensation signal by inverting the primary-side sampling signal, thereby controlling the power switch to change the power transmitted from the primary side to the secondary side of the resonant converter, thus compensating for the additional output power caused by the delay time. Specifically, the delay compensation circuit 312 inverts the primary-side sampling signal within a predetermined time to increase the compensation signal during the falling phase and decrease it during the rising phase. For example, the delay compensation circuit 312 inverts the primary-side sampling signal during the delay time to generate the compensation signal, or it generates a reverse signal with opposite polarity and a larger value than the primary-side sampling signal during the delay time, and then superimposes the primary-side sampling signal and the reverse signal to generate the compensation signal. Optionally, the delay compensation circuit 312 is configured to invert the primary-side sampling signal during the delay time to generate the compensation signal. The delay time mentioned therein is the transmission delay and the drive delay (inherent delay). For example, when the PWML signal goes low, after the transmission delay and drive delay of the PWML signal, the drive signal GATEL goes low. Similarly, when the PWMH signal goes low, after the transmission delay and drive delay of the PWMH signal, the drive signal GATEH goes low.

[0077] In one optional implementation, the delay compensation circuit 312, controlled by the control signals of each power switch, reverse-modulates the primary-side sampled signal Vsen and integrates the reverse-modulated primary-side sampled signal to generate the compensation signal. Further optionally, the delay compensation circuit 312, controlled by the control signals controlling the turn-off of each power switch, reverse-modulates the primary-side sampled signal during the delay time to change the output power transmitted from the primary side to the secondary side.

[0078] Optionally, in this embodiment, the delay compensation circuit 312 is configured to begin reverse modulation of the primary-side sampling signal Vsen in response to receiving a control signal that controls the power switch Q1 or Q2 to turn off, so as to adjust the output power of the resonant converter 3 transmitted from the primary side to the secondary side. Further, the delay compensation circuit 312 is configured to stop reverse modulation of the primary-side sampling signal Vsen before receiving a control signal that controls the power switch Q1 or Q2 to turn on, so as to adjust the output power of the resonant converter 3 transmitted from the primary side to the secondary side.

[0079] In one alternative implementation, such as Figure 4 As shown, if the sampling circuit 311 outputs a primary-side current signal Is1, the delay compensation circuit 312 includes an electrical signal processing unit 42 and an integration unit 43. The electrical signal processing unit 42 is configured to be controlled by the control signals of each power switch, and to reverse-regulate the primary-side current signal Is1 to obtain a target electrical signal Is2. The integration unit 43 is configured to integrate the target electrical signal Is2 to obtain a compensation signal Vcharge, so that the drive circuit 313 generates control signals for each power switch based on the compensation signal Vcharge.

[0080] In another alternative implementation, if the sampling circuit 311 outputs a voltage signal characterizing the current signal of the resonant circuit, the delay compensation circuit 312 may further include a conversion unit 41. The conversion unit 41 is configured to perform voltage-to-current conversion on the primary-side sampling signal Vsen to obtain the primary-side current signal Is1. It should be understood that this embodiment does not limit the type of voltage-to-current conversion circuit, as long as it can achieve voltage-to-current conversion.

[0081] In one alternative implementation, the integration unit 43 includes an energy storage element configured to integrate the target electrical signal to obtain a compensation signal. Further optionally, the energy storage element can be a capacitor or other energy storage element.

[0082] In one alternative implementation, the drive circuit 313 generates control signals PWMH and PWML for power switches Q1 and Q2 based on the compensation signal Vcharge and the reference signal, so as to control and adjust the switching states of power switches Q1 and Q2, thereby adjusting the output signal of the primary control circuit 31 and further adjusting the output signal of the secondary control circuit 32.

[0083] Furthermore, the driving circuit 313 includes comparator A5, comparator A6, PWM logic circuit 313a, and driver 313b. Comparator A5 is used to compare the first reference signal (V... CM -Vfb) and compensation signal Vcharge, comparator A6 is used to compare the second reference signal (V) and compensation signal Vcharge.CM The PWM logic circuit 313a generates control signals PWMH and PWML for power switches Q1 and Q2 based on the outputs of comparators A5 and A6, along with a compensation signal Vcharge. The driver 313b receives the control signals PWMH and PWML and generates drive signals GATEH and GATEL to directly drive the control terminals of power switches Q1 and Q2, thereby enhancing their drive capability. Here, Vfb characterizes the error between the output signal Vo of the secondary control circuit and the desired output value Vref.

[0084] In one alternative implementation, the electrical signal processing unit 42 of this embodiment is controlled by a control signal that controls the on or off times of each power switch. It reverse-modulates the primary-side sampling signal to obtain a target electrical signal, and then generates control signals for each power switch based on the target electrical signal to control and adjust the switching state of each power switch, thereby achieving adaptive power compensation.

[0085] In one optional implementation, the electrical signal processing unit 42 includes a current source. The coefficient of this current source is determined based on the control signal controlling the on / off states of each power switch. Further optionally, the coefficient of this current source is negative in response to the control signal controlling the power switch to turn off (e.g., controlled by the falling edge of the control signal) and positive in response to the control signal controlling the power switch to turn on (e.g., controlled by the rising edge of the control signal). That is, when the control signal of power switch Q1 or power switch Q2 in the primary-side control circuit 31 becomes low, the current source in the electrical signal processing unit 42 is negative, so as to reverse the current signal of the resonant cavity circuit through this current source to achieve reverse regulation, and integration is performed based on the integration unit 43. This embodiment uses the example of controlling the corresponding power switch to turn off when the falling edge of the control signal and controlling the corresponding power switch to turn on when the rising edge of the control signal is used for explanation; the type of control signal is not limited, as long as it can control the power switch to turn off.

[0086] Figure 5 This is a schematic diagram of an electrical signal processing unit according to an embodiment of the present invention. In an optional implementation, the electrical signal processing unit 42 includes a trigger module 51 and an electrical signal generation unit 52. The trigger module 51 is configured to generate a transformation coefficient K in response to a control signal (e.g., the falling edge or rising edge of each control signal) controlling the on or off times of each power switch. The electrical signal generation unit 52 is configured to generate a target electrical signal Is2 based on the transformation coefficient K and the primary current signal Is1.

[0087] Optionally, the trigger module 51 includes a first trigger circuit 511 and a second trigger circuit 512. The first trigger circuit 511 is configured to generate a negative coefficient, such as K = -1, in response to a control signal (e.g., the falling edge of the control signal) at the moment the control power switch is turned off. The second trigger circuit 512 is configured to generate a positive coefficient, such as K = 1, in response to a control signal (e.g., the rising edge of the control signal) at the moment the control power switch is turned on. It should be understood that this embodiment only limits the sign of the coefficient, and does not limit its specific value. The specific value can be adjusted according to the actual application scenario.

[0088] by Figure 3 Taking the half-bridge resonant converter shown as an example, it includes power switches Q1 and Q2. Power switch Q1 has a corresponding control signal PWMH, and power switch Q2 has a corresponding control signal PWML. When the control signal PWMH switches from high level to low level (e.g., the falling edge of the control signal), it controls power switch Q1 to turn off, and when it switches from low level to high level (e.g., the rising edge of the control signal), it controls power switch Q1 to turn on. When the control signal PWML switches from high level to low level (e.g., the falling edge of the control signal), it controls power switch Q2 to turn off, and when it switches from low level to high level (e.g., the rising edge of the control signal), it controls power switch Q2 to turn on.

[0089] Figure 6 This is a schematic diagram of another electrical signal processing unit according to an embodiment of the present invention. Figure 6 As shown, the electrical signal processing unit 42 includes a first flip-flop RS1, a second flip-flop RS2, a third flip-flop RS3, and a fourth flip-flop RS4.

[0090] In this implementation, the first flip-flop RS1 is configured to be set in response to the control signal PWML (e.g., the falling edge of the control signal PWML) when the upper power switch Q2 is turned off, and to be reset in response to the rise of the intermediate voltage VHB corresponding to power switches Q1 and Q2. The intermediate voltage VHB is the voltage at the common terminal HB of the upper power switch Q1 and the lower power switch Q2. The second flip-flop RS2 is configured to be set in response to the falling edge of the control signal PWML (e.g., the control signal PWMH) when the upper power switch Q1 is turned off, and to be reset in response to the fall of the intermediate voltage VHB. In another implementation, the first flip-flop RS1 is configured to be reset in response to the intermediate voltage VHB rising to a predetermined value, and the second flip-flop RS2 is configured to be reset in response to the intermediate voltage VHB falling to a predetermined value.

[0091] In one optional implementation, the electrical signal processing unit 42 further includes an OR gate circuit 61, the input of which is connected to the output of the first flip-flop RS1 and the second flip-flop RS2. That is, when either the first flip-flop RS1 or the second flip-flop RS2 is set, the corresponding transformation coefficient is controlled to be negative; when either the first flip-flop RS1 or the second flip-flop RS2 is reset, the electrical signal processing unit 42 is controlled not to draw current.

[0092] The third flip-flop RS3 is configured to be set in response to the control signal PWML (e.g., the rising edge of the control signal PWML) when the power switch Q2 is turned on, and reset in response to the control signal PWML (e.g., the falling edge of the control signal PWML) when the power switch Q2 is turned off. The fourth flip-flop RS4 is configured to be set in response to the control signal PWMH (e.g., the rising edge of the control signal PWMH) when the power switch Q1 is turned on, and reset in response to the control signal PWMH (e.g., the falling edge of the control signal PWMH) when the power switch Q1 is turned off.

[0093] In one optional implementation, the electrical signal processing unit 42 further includes an OR gate circuit 62, the input of which is connected to the output of the third flip-flop RS3 and the fourth flip-flop RS4. That is, when either the third flip-flop RS3 or the fourth flip-flop RS4 is set, the corresponding transformation coefficient is controlled to be positive; when either the third flip-flop RS3 or the fourth flip-flop RS4 is reset, one of the first flip-flop RS1 and the second flip-flop RS2 is set, and the corresponding transformation coefficient is controlled to be negative.

[0094] In an alternative implementation, the electrical signal processing unit 42 further includes an electrical signal generation unit 63. The electrical signal generation unit 63 is configured to generate a target electrical signal Is2 based on the transformation coefficient K and the primary current signal Is1.

[0095] It should be understood that this embodiment does not show the circuit structure of the electrical signal processing unit 42, and other circuit structures can also be applied to this embodiment, and this embodiment does not limit them. For example, an OR gate circuit can be set first and then a flip-flop can be set. Specifically, an OR gate circuit is set at the set input terminal of a flip-flop to determine whether PWML or PWMH becomes low, and another OR gate circuit is set at the reset input terminal of the flip-flop to determine whether the intermediate voltage VHB rises or falls. In this way, the number of flip-flops can be reduced.

[0096] It should be understood that the electrical signal processing unit in this embodiment is described using a half-bridge as an example. Similarly, this embodiment can also be applied to a full-bridge circuit, and the principle is similar to that described above, so it will not be repeated here.

[0097] As can be seen, this embodiment performs reverse regulation based on the current in the primary side resonant circuit during the delay time, and adjusts the power switch based on the primary side sampling signal after reverse regulation. Thus, adaptive delay compensation of output power can be achieved, improving the compensation accuracy and flexibility of the circuit.

[0098] Figure 7 This is a circuit diagram of another resonant converter according to an embodiment of the present invention. Figure 8 This is a waveform diagram of the resonant converter in an embodiment of the present invention. Figure 7 As shown, the primary-side control circuit 71 includes an input capacitor Ci1, a power switch Q1, a power switch Q2, and a resonant inductor L. R Resonant capacitor C R Primary coil L M The circuit consists of a sampling circuit 711, a delay compensation circuit 712, and a driving circuit 713. The resonant inductor L... R Resonant capacitor C R Primary coil L M An LLC resonant circuit is formed. In this embodiment, the output signal of the primary-side control circuit 71 is adjusted by controlling the switching frequency and duty cycle of power switches Q1 and Q2, thereby adjusting the output signal of the secondary-side control circuit. The secondary-side control circuit in this embodiment is similar to that in the above embodiments and will not be described again here.

[0099] In this embodiment, the sampling circuit 711 is a current sampling circuit used to sample the current signal of the resonant circuit and obtain the primary-side sampling signal Vsen. Optionally, the sampling circuit 711 includes a sampling resistor Rsen to sample the current of the resonant circuit and generate the primary-side sampling signal Vsen.

[0100] The delay compensation circuit 712 includes a conversion unit 712a, an electrical signal processing unit 712b, and an integration unit 712c.

[0101] The conversion unit 712a is configured to perform voltage-to-current conversion on the primary-side sampled signal Vsen to obtain the primary-side current signal Is1. The electrical signal processing unit 712b is controlled by the control signals of each power switch (i.e., the control signals PWMH and PWML of power switches Q1 and Q2), and reverses the primary-side current signal Is1 to obtain the target electrical signal Is2. The integration unit 712c is configured to integrate the target electrical signal Is2 to obtain the compensation signal Vcharge, so that the drive circuit 713 generates the control signals of each power switch based on the compensation signal Vcharge.

[0102] Optionally, in this embodiment, the integrator 712c includes an energy storage element Ccharge to integrate the target electrical signal Is2 and obtain a compensation signal Vcharge. In this embodiment, it is readily understood that the integrator 712c performs integration based on the current signal of the resonant circuit. Therefore, the charge decrease and increase on the energy storage element Ccharge reflects the power transmitted from the primary-side control circuit to the secondary-side control circuit. Thus, this embodiment can compensate the output power of the resonant converter using the compensation signal Vcharge, making it approach the desired power.

[0103] The drive circuit 713 is used to generate control signals PWMH and PWML for power switches Q1 and Q2 based on the compensation signal Vcharge and the reference signal, so as to control and adjust the switching state of power switches Q1 and Q2, thereby adjusting the output signal of the primary control circuit 71, and further adjusting the output signal of the secondary control circuit.

[0104] Furthermore, the drive circuit 713 includes comparator A7, comparator A8, PWM logic circuit 713a, and driver 713b. Comparator A7 is used to compare the first reference signal (V... CM -Vfb) and compensation signal Vcharge, comparator A8 is used to compare the second reference signal (V) and compensation signal Vcharge. CM The PWM logic circuit 713a generates control signals PWMH and PWML for power switches Q1 and Q2 based on the outputs of comparators A7 and A8, using the +Vfb) and compensation signal Vcharge. The driver 713b receives the control signals PWMH and PWML and generates drive signals GATEH and GATEL to directly drive the control terminals of power switches Q1 and Q2, thereby enhancing their drive capability. Here, Vfb characterizes the error between the output signal Vo of the secondary control circuit and the desired output value Vref, V... CM This is the bias voltage.

[0105] This invention compensates for the additional output power caused by the extra integration during the delay time by reverse-modulating the current signal of the resonant circuit during the delay time. For example... Figure 8 As shown in the figure, the curve of the compensation signal VCR does not use the delay compensation circuit of this embodiment, as indicated by the dashed line. The compensation signal Vcharge, representing the input charge, uses the delay compensation circuit of this embodiment, as indicated by the solid line. The working principle of the resonant converter in this embodiment is as follows:

[0106] At time t0, the compensation signal Vcharge drops to the reference signal V. CMAfter a delay by comparator A7, at time t1, the control signal PWML of the lower power switch Q2 goes low. At this time, the first flip-flop RS1 in the electrical signal processing unit 712b is set in response to the control signal PWML going low, making the corresponding current coefficient negative for reverse regulation, i.e., the target electrical signal Is2 = -k*Is1. Thus, the electrical signal processing unit 712b draws current in reverse from the energy storage element Ccharge until, after the drive delay and transmission delay, at time t2, the drive signal GATEL of the lower power switch Q2 goes low, the lower power switch Q2 is turned off, the intermediate voltage VHB begins to rise, the first flip-flop RS1 in the electrical signal processing unit 712b is reset in response to the intermediate voltage VHB rising, and the electrical signal processing unit 712b stops charging and discharging the energy storage element Ccharge, so that the compensation voltage Vcharge on the energy storage element Ccharge remains unchanged. Therefore, during the turn-off process of the lower power switch Q2, the reverse control time is the sum of the transmission delay and drive delay of the control signal PWML of the lower power transistor Q2 (i.e., time t1-t2).

[0107] In this embodiment, the PWM logic circuit 713a causes the control signal PWMH of the upper power switch Q1 to go high after the control signal PWML has been at a low level for a predetermined time. It should be understood that after the drive signal GATEL of the lower power switch Q2 is at a low level, the lower power switch Q2 is turned off. At this time, even if the upper power switch is not yet turned on, the intermediate voltage VFB will gradually rise because the voltage in the primary LLC circuit is greater than 0.

[0108] At time t3, the control signal PWMH of the upper power switch Q1 goes high. The fourth flip-flop RS4 in the electrical signal processing unit 712b responds to the PWMH going high and is set, making the corresponding current coefficient positive, i.e., the target electrical signal Is2 = k*Is1. Therefore, the electrical signal processing unit 712b performs positive regulation by charging and discharging the energy storage element Ccharge. Thus, at time t3', when the drive signal GATEH of the upper power switch Q1 goes high, the upper power switch Q1 is turned on, and the trend of the compensation signal Vcharge is the same as the primary input signal.

[0109] At time t4, the compensation signal Vcharge rises to the reference signal V. CMAfter a delay by comparator A8, at time t5, the control signal PWMH of the upper power switch Q1 goes low. At this time, the second flip-flop RS2 in the electrical signal processing unit 712b is set in response to the control signal PWMH going low, making the corresponding current coefficient negative for reverse regulation, i.e., the target electrical signal Is2 = -k*Is1. Thus, the electrical signal processing unit 712b draws current in reverse from the energy storage element Ccharge until, after a transmission delay and a drive delay, at time t6, the drive signal GATEH of the upper power switch Q1 goes low, the upper power switch Q1 is turned off, the intermediate voltage VHB begins to drop, and the second flip-flop RS2 in the electrical signal processing unit 712b is reset in response to the drop in the intermediate voltage VHB, stopping the charging and discharging of the energy storage element Ccharge, thus keeping the compensation voltage Vcharge on the energy storage element Ccharge constant. Therefore, during the turn-off process of the upper power switch Q1, the reverse control time is the sum of the transmission delay and drive delay of the control signal PWMH of the upper power switch Q1 (i.e., time t5-t6).

[0110] In this embodiment, the PWM logic circuit 713a causes the control signal PWML of the lower power switch Q2 to go high after the control signal PWMH has been at a low level for a predetermined time. At time t7, the control signal PWML of the lower power switch Q2 goes high, and the third flip-flop RS3 in the electrical signal processing unit 712b is set in response to the control signal PWML going high, making the corresponding current coefficient positive, i.e., the target electrical signal Is2 = k*Is1. Therefore, the electrical signal processing unit 712b performs positive regulation by charging and discharging the energy storage element Ccharge. Thus, at time t7', when the drive signal GATEL of the lower power switch Q2 goes high, the lower power switch Q2 is turned on, and the change trend of the compensation signal Vcharge is the same as that of the primary input signal.

[0111] It should be understood that this embodiment stops reverse regulation when the intermediate voltage begins to rise or fall. In other optional implementations, reverse regulation may also stop when the intermediate voltage rises to a predetermined value or falls to a predetermined value. Further optionally, the predetermined value may be half of the maximum intermediate voltage value Vfbm or the maximum intermediate voltage value Vfbm. In another optional implementation, reverse regulation may also stop when the control signal or drive signal of the corresponding upper or lower power switch becomes high; this can be determined based on the actual application scenario.

[0112] like Figure 8As shown, due to symmetry, the integral of the rising process of the intermediate voltage VHB during the time interval t2-t3 cancels out the integral of the falling process during the time interval t6-t7, having almost no impact on the output power of the resonant converter. Furthermore, the comparator delay times (times t0-t1 and t4-t5) are very small and can be ignored. Therefore, this embodiment of the invention, by incorporating a delay compensation circuit in the resonant converter, can adaptively compensate for changes in output power caused by variations in the switching frequency, the drive speed due to optimized external parameters, or the rise or fall time of the intermediate voltage VHB during operation. This improves the accuracy of output power delay compensation, making the output power tend towards the desired power, and also enhances the flexibility of the circuit.

[0113] The delay compensation circuit of the resonant converter in this embodiment generates a compensation signal by reverse-modulating the primary-side sampling signal that characterizes the resonant current of the resonant circuit in the resonant converter. This compensation signal is then used to control the power switch, thereby achieving adaptive delay power compensation, improving the stability of the output power and the flexibility and convenience of the circuit.

[0114] Figure 9 This is a circuit diagram of another resonant converter according to an embodiment of the present invention. Most of the above embodiments are described using a half-bridge resonant converter as an example; however, it should be understood that this embodiment can also be applied to a full-bridge resonant converter. Figure 9 As shown, the resonant converter in this embodiment includes a primary-side control circuit 91 and a secondary-side control circuit 92. Both the primary-side control circuit 91 and the secondary-side control circuit 92 employ full-bridge rectifier circuits.

[0115] The primary-side control circuit 91 includes a full-bridge rectifier circuit 911 and an inductor L. r Capacitor element C r and primary coil L p An LLC resonant circuit is constructed. The full-bridge rectifier circuit 911 is used to rectify the input power supply U. in The input current signal i is obtained by rectification. r and input voltage signal V in The full-bridge rectifier circuit 911 includes power switches S1-S4. Power switches S1 and S2 have a common terminal A, and power switches S3 and S4 have a common terminal B.

[0116] The secondary control circuit 92 includes a full-bridge rectifier circuit 921, an output capacitor, and an output impedance R. L The full-bridge rectifier circuit 921 is used to rectify the secondary-side input signal to obtain the output signal.

[0117] In this embodiment, the primary-side control circuit 91 further includes a delay compensation circuit 912 and a drive circuit 913. The delay compensation circuit 912 reverse-modulates the primary-side sampling signal characterizing the resonant current in the LLC resonant circuit to generate a compensation signal, which is then used to control the power switch to achieve delay compensation. Further, the delay compensation circuit 912 is configured to reverse-modulate the primary-side sampling signal during the delay time to generate the compensation signal.

[0118] Specifically, such as Figure 9 As shown, the delay compensation circuit 912 includes a conversion unit 912a, an electrical signal processing unit 912b, and an integration unit 912c.

[0119] The conversion unit 912a is configured to perform voltage-to-current conversion on the primary-side sampled signal Vsen' to obtain the primary-side current signal Is1. The electrical signal processing unit 912b is controlled by the control signals of each power switch (i.e., the control signals PWMS and PWMS' of power switches S1-S4), and reverses the primary-side current signal Is1 to obtain the target electrical signal Is2. The integration unit 912c is configured to integrate the target electrical signal Is2 to obtain the compensation signal Vcharge, so that the drive circuit 913 generates the control signals of each power switch according to the compensation signal Vcharge.

[0120] Optionally, in this embodiment, the integrator 912c includes an energy storage element Ccharge to integrate the target electrical signal Is2 and obtain a compensation signal Vcharge. In this embodiment, it is readily understood that the integrator 912c performs integration based on the current signal of the resonant circuit. Therefore, the charge decrease and increase on the energy storage element Ccharge reflects the power transmitted from the primary-side control circuit to the secondary-side control circuit. Thus, this embodiment can compensate the output power of the resonant converter using the compensation signal Vcharge, making it approach the desired power.

[0121] The drive circuit 913 is used to generate control signals PWMS and PWMS' for power switches S1-S4 based on the compensation signal Vcharge and the reference signal, so as to control and adjust the switching state of power switches S1-S4, thereby adjusting the output signal of the primary control circuit 91, and further adjusting the output signal of the secondary control circuit 92.

[0122] Furthermore, the drive circuit 913 includes comparator A9, comparator A10, and PWM logic circuit 913a. Comparator A9 is used to compare the first reference signal (V... CMfb1 The comparator A10 is used to compare the second reference signal (V) with the compensation signal Vcharge. CMfb2The PWM logic circuit 913a generates control signals PWMS and PWMS' for power switches S1-S4 based on the outputs of comparators A9 and A10, and the compensation signal Vcharge. CMfb1 and V CMfb2 The error between the output signal of the secondary control circuit and the expected output value Vref is determined. The drive circuit 913 also includes a driver 913b, which receives control signals PWMS and PWMS' and generates drive signals GATE1, GATE2, GATE3 and GATE4 to directly drive the control terminals of power switches S1-S4 to enhance the drive capability.

[0123] In the full-bridge rectifier circuit 911, power switches S1 and S4 are simultaneously on and off, meaning they share the same control signal PWMS, and power switches S2 and S3 are simultaneously on and off, meaning they share the same control signal PWMS'. Optionally, the electrical signal processing unit 912b includes a trigger module and an electrical signal generation unit. The electrical signal generation unit acts as a current source, transforming the current signal of the resonant circuit based on corresponding transformation coefficients to obtain the target electrical signal. The integration unit 912c integrates this target electrical signal to obtain the compensation signal Vcharge. Optionally, the trigger module is configured to generate a negative coefficient in response to the first and fourth control signals (e.g., the falling edge of PWMS) when the power switches S1 and S4 are turned off, or the second and third control signals (e.g., the falling edge of PWMS') when the power switches S2 and S3 are turned off, and to generate a positive coefficient in response to the first and fourth control signals (e.g., the rising edge of PWMS) when the power switches S1 and S4 are turned on, or the second and third control signals (e.g., the rising edge of PWMS') when the power switches S2 and S3 are turned on. Thus, this embodiment can generate a negative coefficient during the delay time, causing the electrical signal processing unit 712b to reverse-draw current, achieving reverse regulation and thus delay power compensation.

[0124] It should be understood that the control principles of both half-bridge resonant converters and full-bridge resonant converters are basically similar, and will not be elaborated here.

[0125] The delay compensation circuit of the resonant converter in this embodiment generates a compensation signal by reverse modulation of the primary side sampling signal that characterizes the primary side resonant current. This compensation signal is then used to control the power switch, thereby achieving adaptive delay power compensation, improving the stability of the output power, as well as the flexibility and convenience of the circuit.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A delay compensation circuit for a resonant converter, characterized in that, The delay compensation circuit is configured to reverse the primary-side sampling signal characterizing the resonant current of the primary-side resonant circuit in the resonant converter to generate a compensation signal, so that the power switch is controlled based on the compensation signal to achieve delay compensation. The delay compensation circuit is configured to reverse the original side sampling signal during the delay time of each switching cycle to generate a compensation signal. The delay compensation circuit is configured to adjust the primary-side sampling signal in reverse during the delay time so that the compensation signal increases during the falling phase and decreases during the rising phase. The delay time is determined based on the moment when each power switch is turned on or off.

2. The delay compensation circuit according to claim 1, characterized in that, The delay compensation circuit is configured to, in response to receiving a control signal that controls the power switches in the resonant converter to turn off, begin to reverse-modulate the primary-side sampling signal to adjust the output power of the resonant converter transmitted from the primary side to the secondary side.

3. The delay compensation circuit according to claim 1, characterized in that, The delay compensation circuit is configured to stop reverse modulation of the primary-side sampling signal before receiving a control signal that controls the conduction of each power switch in the resonant converter.

4. The delay compensation circuit according to claim 1, characterized in that, The delay compensation circuit is configured to invert the primary side sampled signal and generate the compensation signal based on the inverted primary side sampled signal.

5. The delay compensation circuit according to claim 1, characterized in that, The primary-side sampling signal is used to characterize the current signal of the primary-side resonant circuit; The delay compensation circuit is configured to be controlled by the control signals of each of the power switches, to reverse the primary side sampling signal, and to integrate the reverse-controlled primary side sampling signal to generate the compensation signal.

6. The delay compensation circuit according to claim 1, characterized in that, The delay compensation circuit includes: An electrical signal processing unit is configured to be controlled by the control signals of each of the power switches to reverse the primary-side sampling signals and obtain the target electrical signal. An integration unit is configured to integrate the target electrical signal to obtain a compensation signal.

7. The delay compensation circuit according to claim 6, characterized in that, The delay compensation circuit further includes: The conversion unit is configured to perform voltage-to-current conversion on the primary-side sampled signal to obtain the primary-side current signal.

8. The delay compensation circuit according to claim 6, characterized in that, The electrical signal processing unit is configured to reverse-modulate the primary-side sampling signal in response to a control signal that controls the power switches to turn on or off, thereby acquiring the target electrical signal.

9. The delay compensation circuit according to claim 6, characterized in that, The electrical signal processing unit includes a current source; The coefficient of the current source is determined according to the control signal that controls the on or off time of each power switch.

10. The delay compensation circuit according to claim 9, characterized in that, The coefficient of the current source is negative in response to the control signal when the control power switch is turned off, and positive in response to the control signal when the control power switch is turned on.

11. The delay compensation circuit according to claim 6, characterized in that, The electrical signal processing unit includes: The trigger module is configured to generate transformation coefficients in response to a control signal that controls the on or off times of each of the power switches; An electrical signal generation unit is configured to generate the target electrical signal based on the transformation coefficients and the primary-side sampled signal.

12. The delay compensation circuit according to claim 11, characterized in that, The triggering module includes: The first trigger circuit is configured to generate a negative coefficient in response to a control signal that controls the turn-off time of each of the power switches; The second trigger circuit is configured to generate a positive coefficient in response to a control signal that controls the on-time of each of the power switches.

13. The delay compensation circuit according to claim 12, characterized in that, The resonant converter is a half-bridge resonant converter, and the control signals include the upper MOSFET control signal and the lower MOSFET control signal; The first trigger circuit includes: The first trigger is configured to be set in response to the lower control signal when the lower power switch is turned off, and to be reset in response to the rise of the intermediate voltage corresponding to each power switch, wherein the intermediate voltage is the voltage of the common terminal of the upper power switch and the lower power switch. The second trigger is configured to be set in response to the upper transistor control signal at the moment when the upper power switch is turned off, and to be reset in response to the drop in the intermediate voltage.

14. The delay compensation circuit according to claim 13, characterized in that, The second trigger circuit includes: The third trigger is configured to be set in response to the lower transistor control signal when the controlled power switch is turned on, and to be reset in response to the lower transistor control signal when the controlled power switch is turned off. The fourth trigger is configured to be set in response to the upper transistor control signal when the upper power switch is turned on, and to be reset in response to the upper transistor control signal when the upper power switch is turned off.

15. The delay compensation circuit according to claim 6, characterized in that, The integrator unit includes an energy storage element. The energy storage element is configured to integrate the target electrical signal to obtain the compensation signal.

16. The delay compensation circuit according to claim 11, characterized in that, The resonant converter is a full-bridge resonant converter, and the control signals include a first control signal, a second control signal, a third control signal, and a fourth control signal; The triggering module is configured to generate negative coefficients in response to the first and fourth control signals controlling the first and fourth power switches to turn off, or the second and third control signals controlling the second and third power switches to turn off, and to generate positive coefficients in response to the first and fourth control signals controlling the first and fourth power switches to turn on, or the second and third control signals controlling the second and third power switches to turn on.

17. A resonant converter, characterized in that, The resonant converter includes: The primary-side control circuit transmits electrical signals to the secondary-side control circuit; and The secondary-side control circuit is configured to receive and process the electrical signal transmitted by the primary-side control circuit to obtain the output electrical signal of the resonant converter; The primary-side control circuit includes a delay compensation circuit as described in any one of claims 1-16.

Images