Gate drive circuit and display panel

Abstract

The present disclosure provides a gate drive circuit and a display panel. The gate drive circuit includes multiple cascaded shift register units. The display panel includes multiple pixel circuits, which form multiple circuit rows. The multiple shift register units are connected to the multiple circuit rows in a one-to-one correspondence. The shift register units include storage subcircuits, and the storage subcircuits in adjacent shift register units are staggered. The present disclosure can improve resolution.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] A gate drive circuit is an important auxiliary circuit in an active matrix organic light-emitting diode (AMOLED) display. Existing gate drive circuits include multiple cascaded shift register units. However, display devices equipped with such gate drive circuits have low resolution. Summary of the Invention

[0003] The present disclosure aims to provide a gate driving circuit and a display panel, which can improve the resolution.

[0004] According to one aspect of the present disclosure, a gate drive circuit is provided for a display panel, wherein the gate drive circuit includes a plurality of cascaded shift register units, the display panel includes a plurality of pixel circuits, the plurality of pixel circuits constitute a plurality of circuit rows, the plurality of shift register units are connected to the plurality of circuit rows in a one-to-one correspondence, the shift register units include storage sub-circuits, and the storage sub-circuits in adjacent shift register units are staggered.

[0005] Furthermore, the storage sub-circuit includes a plurality of capacitors, and the plurality of capacitors are distributed along an extension direction of the circuit row.

[0006] Furthermore, the storage subcircuit includes a first capacitor and a second capacitor; the shift register unit includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor is connected to the signal input end, the gate of the first transistor is connected to the first clock signal end, the first electrode of the second transistor is connected to the second electrode of the first transistor, the gate of the second transistor is connected to the first power supply end, the gate of the third transistor is connected to the second electrode of the second transistor, the first electrode of the third transistor is connected to the second clock signal end, and the second electrode of the third transistor is connected to the signal output end; the first capacitor is connected between the signal output end and the gate of the third transistor.

[0007] Furthermore, the shift register unit also includes a fourth transistor, a fifth transistor and a sixth transistor, the first electrode of the fourth transistor is connected to the first clock signal end, the gate of the fourth transistor is connected to the second electrode of the first transistor, the gate of the fifth transistor is connected to the second electrode of the fourth transistor, the first electrode of the fifth transistor is connected to the second power supply end, the second electrode of the fifth transistor is connected to the signal output end, the first electrode of the sixth transistor is connected to the first power supply end, the second electrode of the sixth transistor is connected to the second electrode of the fourth transistor, and the gate of the sixth transistor is connected to the first clock signal end; the second capacitor is connected between the second power supply end and the gate of the fifth transistor.

[0008] Furthermore, the capacitor includes a first plate and a second plate, the first plate of the first capacitor and the first plate of the second capacitor are arranged on the same layer, and the second plate of the first capacitor and the second plate of the second capacitor are arranged on the same layer.

[0009] Furthermore, the first transistor and the sixth transistor are distributed along a direction perpendicular to the circuit row; the gate of the first transistor and the gate of the sixth transistor are arranged in the same layer and are an integrated structure.

[0010] Furthermore, the gate drive circuit also includes a seventh transistor and an eighth transistor, the first electrode of the seventh transistor is connected to the second power supply terminal, the control electrode of the seventh transistor is connected to the control electrode of the fifth transistor, the control electrode of the eighth transistor is connected to the second clock signal terminal, the first electrode of the eighth transistor is connected to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is connected to the second electrode of the first transistor.

[0011] Furthermore, the first transistor, the eighth transistor and the seventh transistor are distributed along the extension direction of the circuit row; the second pole of the first transistor and the second pole of the eighth transistor are arranged on the same layer and are an integrated structure; the first pole of the eighth transistor and the second pole of the seventh transistor are arranged on the same layer and are an integrated structure.

[0012] Furthermore, the shift register unit further includes a first auxiliary transistor, wherein the first auxiliary transistor and the third transistor are distributed along a direction perpendicular to the circuit row and are connected in parallel; and / or

[0013] The shift register unit further includes a second auxiliary transistor, and the second auxiliary transistor and the fifth transistor are distributed along a direction perpendicular to the circuit row and connected in parallel.

[0014] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0015] a plurality of pixel circuits, wherein the plurality of pixel circuits constitute a plurality of circuit rows;

[0016] In the gate driving circuit, the plurality of shift register units are connected to the plurality of circuit rows in a one-to-one correspondence.

[0017] In the gate drive circuit and display panel disclosed herein, multiple shift register units are connected to multiple circuit rows in a one-to-one correspondence, and the storage sub-circuits in adjacent shift register units are staggered, thereby increasing the distance between adjacent storage sub-circuits, solving the problem of a small number of circuit rows caused by the spacing limitations of the storage sub-circuits, and improving the resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of a gate drive circuit and circuit rows in an embodiment of the present disclosure.

[0019] Figure 2 is a circuit diagram of a shift register in an embodiment of the present disclosure.

[0020] Figure 3 yes Figure 2 The working timing diagram of the shift register is shown.

[0021] Figure 4 is a schematic diagram of a capacitor in an embodiment of the present disclosure.

[0022] Figure 5 Schematic diagram of the first electrode plate in an embodiment of the present disclosure.

[0023] Figure 6 Schematic diagram of the first capacitor and the second capacitor in an embodiment of the present disclosure.

[0024] Figure 7 Schematic diagram of the gate layer and the source-drain electrode layer in an embodiment of the present disclosure.

[0025] Figure 8 2 is another schematic diagram of the gate layer and the source-drain electrode layer in an embodiment of the present disclosure.

[0026] Figure 9 Schematic diagram of a gate drive circuit in an embodiment of the present disclosure.

[0027] Description of the accompanying drawings: 1. storage sub-circuit; 2. source-drain electrode layer; 201. first source-drain region; 202. second source-drain region; 203. third source-drain region; 204. fourth source-drain region; 205. fifth source-drain region; 206. sixth source-drain region; 207. seventh source-drain region; 208. eighth source-drain region; 209. ninth source-drain region; 210. tenth source-drain region; 211. eleventh source-drain region; 212. twelfth source-drain region; 21 3. 13th source / drain region; 214. 14th source / drain region; 215. 15th source / drain region; 216. 16th source / drain region; 217. 17th source / drain region; 218. 18th source / drain region; 219. 19th source / drain region; 220. 20th source / drain region; 3. Gate electrode layer; 301. First gate region; 302. Second gate region; 303. Third gate region; 304. Fourth gate region; 305. Fifth gate region; 306. Sixth gate region; 3 07, seventh gate region; 308, eighth gate region; 309, ninth gate region; 310, tenth gate region; 311, eleventh gate region; 4, lead hole; 5, first electrode plate; 6, second electrode plate; 7, top metal; 8, tungsten hole; 9, repeating unit; 100, shift register unit; 200, circuit row; SIN, signal input terminal; SCK1, first clock signal terminal; SCK2, second clock signal terminal; GOUTn, signal output terminal; VGL, first power supply terminal; VGH, second power supply terminal; BS, reverse scan terminal; FS, forward scan terminal; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; C1, first capacitor; C2, second capacitor. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0029] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar words used in this disclosure and the claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, the terms "a" or "an" and similar words do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "plurality" or "several" mean two or more. The terms "include" or "comprising" and similar words mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar words are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0030] In related art, a gate drive circuit includes multiple cascaded shift register units, a display panel includes multiple pixel circuits, the multiple pixel circuits forming multiple circuit rows, and the multiple shift register units are connected to the multiple circuit rows in a one-to-one correspondence. The shift register units include storage subcircuits, and the storage subcircuits of adjacent shift register units are distributed along a direction perpendicular to the circuit rows. For the gate drive circuit to function properly, the spacing between adjacent storage subcircuits needs to be greater than or equal to a certain distance. This results in too few shift register units being arranged in a direction perpendicular to the circuit rows, which in turn results in a small number of circuit rows and reduced resolution.

[0031] The present disclosure provides a gate drive circuit. The gate drive circuit is used for a display panel. Figure 1 As shown, the gate drive circuit includes multiple cascaded shift register units 100. The display panel includes multiple pixel circuits. The multiple pixel circuits constitute multiple circuit rows 200. The multiple shift register units 100 are connected to the multiple circuit rows 200 in a one-to-one correspondence. The shift register units 100 include storage sub-circuits 1, and the storage sub-circuits 1 in adjacent shift register units 100 are staggered.

[0032] In the gate drive circuit of the embodiment of the present disclosure, multiple shift register units 100 are connected to multiple circuit rows 200 in a one-to-one correspondence, and the storage sub-circuits 1 in adjacent shift register units 100 are staggered, thereby increasing the distance between adjacent storage sub-circuits 1, solving the problem of a small number of circuit rows 200 due to the spacing limitation of the storage sub-circuits 1, and improving the resolution.

[0033] The following describes in detail the various components of the gate drive circuit according to the embodiment of the present disclosure:

[0034] like Figure 2 As shown, the shift register unit 100 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first electrode of the first transistor M1 is connected to the signal input terminal SIN, and the gate of the first transistor M1 is connected to the first clock signal terminal SCK1. The first electrode of the second transistor M2 is connected to the second electrode of the first transistor M1, and the gate of the second transistor M2 is connected to the first power supply terminal VGL. The first power supply terminal VGL can output a constant low voltage. The gate of the third transistor M3 is connected to the second electrode of the second transistor M2, the first electrode of the third transistor M3 is connected to the second clock signal terminal SCK2, and the second electrode of the third transistor M3 is connected to the signal output terminal GOUTn. The first electrode of the fourth transistor M4 is connected to the first clock signal terminal SCK1, and the gate of the fourth transistor M4 is connected to the second electrode of the first transistor M1. The gate of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4. The first electrode of the fifth transistor M5 is connected to the second power supply terminal VGH, and the second electrode of the fifth transistor M5 is connected to the signal output terminal GOUTn. The second power supply terminal VGH is capable of outputting a constant high voltage. The first electrode of the sixth transistor M6 is connected to the first power supply terminal VGL, the second electrode of the sixth transistor M6 is connected to the second electrode of the fourth transistor M4, and the gate of the sixth transistor M6 is connected to the first clock signal terminal SCK1. Of course, the gate drive circuit of the disclosed embodiment may also include a seventh transistor M7 and an eighth transistor M8. The first electrode of the seventh transistor M7 is connected to the second power supply terminal VGH, and the control electrode of the seventh transistor M7 is connected to the control electrode of the fifth transistor M5. The control electrode of the eighth transistor M8 is connected to the second clock signal terminal SCK2, the first electrode of the eighth transistor M8 is connected to the second electrode of the seventh transistor M7, and the second electrode of the eighth transistor M8 is connected to the second electrode of the first transistor M1. In addition, each of the above-mentioned transistors can be a P-type thin-film transistor, i.e., a PMOS transistor, or an N-type thin-film transistor, i.e., an NMOS transistor.

[0035] The shift register unit 100 includes a storage subcircuit 1, and the storage subcircuits 1 in adjacent shift register units 100 are staggered. The storage subcircuits 1 in adjacent shift register units 100 are staggered in a direction perpendicular to the circuit row 200. In one embodiment of the present disclosure, the storage subcircuit 1 may include a capacitor. In another embodiment of the present disclosure, the storage subcircuit 1 may include multiple capacitors, and the multiple capacitors are distributed along the extension direction of the circuit row 200. Figure 4 As shown, each capacitor may include a first plate 5 and a second plate 6. The first plate 5 may be a lower plate, and the second plate 6 may be an upper plate. In addition, each capacitor may further include a top metal 7, and the top metal 7 may be provided on the side of the second plate 6 facing away from the first plate 5, and the top metal 7 and the second plate 6 are electrically connected via a tungsten via 8.

[0036] For example, the storage sub-circuit 1 includes multiple capacitors, such as Figure 1 and Figure 2 As shown, the storage sub-circuit 1 may include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be connected between the signal output terminal GOUTn and the gate of the third transistor M3, that is, the first plate 5 of the first capacitor C1 is connected to the signal output terminal GOUTn, and the second plate 6 of the first capacitor C1 is connected to the gate of the third transistor M3. The second capacitor C2 is connected between the second power supply terminal VGH and the gate of the fifth transistor M5, that is, the first plate 5 of the second capacitor C2 is connected to the second power supply terminal VGH, and the second plate 6 of the second capacitor C2 is connected to the gate of the fifth transistor M5. As shown Figure 5 As shown, the first plate 5 of the first capacitor C1 can be provided on the same layer as the first plate 5 of the second capacitor C2, and distributed along the extension direction of the circuit row 200; the second plate 6 of the first capacitor C1 can be provided on the same layer as the second plate 6 of the second capacitor C2, and distributed along the extension direction of the circuit row 200; Figure 6 As shown, the top metal layer 7 of the first capacitor C1 and the top metal layer 7 of the second capacitor C2 can be provided in the same layer and distributed along the extension direction of the circuit row 200 .

[0037] Figure 3 yes Figure 2The shift register unit 100 shown in the operating timing diagram takes all transistors as P-type thin-film transistors as an example. The conduction level of all transistors is low. In the first phase S1, the signal input terminal SIN and the first clock signal terminal SCK1 input a low level, the second clock signal terminal SCK2 input a high level, and all first transistors M1 are turned on except for the eighth transistor M8, which is turned off. The signal output terminal GOUTn outputs a high level. In the second phase S2, the signal input terminal SIN and the first clock signal terminal SCK1 input a high level, the second clock signal terminal SCK2 input a low level, the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off, the remaining transistors are turned on, and the signal output terminal GOUTn outputs a low level. In the second phase S3, the signal input terminal SIN and the second clock signal terminal SCK2 input a high level, the first clock signal terminal SCK1 input a low level, the fourth transistor M4, the eighth transistor M8, and the third transistor M3 are turned off, the remaining transistors are turned on, and the signal output terminal GOUTn outputs a high level.

[0038] The first transistor M1 and the sixth transistor M6 can be arranged in a direction perpendicular to the circuit row 200. The gate of the first transistor M1 can be arranged in the same layer as the gate of the sixth transistor M6, and the gate of the first transistor M1 and the gate of the sixth transistor M6 are an integrated structure. In other words, the first transistor M1 and the sixth transistor M6 share a common gate. The first transistor M1, the eighth transistor M8, and the seventh transistor M7 are arranged along the extension direction of the circuit row 200. The second electrode of the first transistor M1 can be arranged in the same layer as the second electrode of the eighth transistor M8, and the second electrode of the first transistor M1 and the second electrode of the eighth transistor M8 are an integrated structure. The first electrode of the eighth transistor M8 can be arranged in the same layer as the second electrode of the seventh transistor M7, and the first electrode of the eighth transistor M8 can be an integrated structure.

[0039] Specifically, if Figure 7As shown, the gate drive circuit of the present disclosure may include a gate electrode layer 3 and a source-drain electrode layer 2. The gate electrode layer 3 may include a first gate region 301, a second gate region 302, and a third gate region 303. The source-drain electrode layer 2 may include a first source-drain region 201, a second source-drain region 202, a third source-drain region 203, a fourth source-drain region 204, a fifth source-drain region 205, and a sixth source-drain region 206. The first gate region 301 serves as both the gate of the first transistor M1 and the gate of the sixth transistor M6. A lead hole 4 is provided in the first gate region 301 for electrical connection to an external circuit. The first source-drain region 201 and the second source-drain region 202 serve as the first and second electrodes of the sixth transistor M6, respectively. The second gate region 302 serves as the gate of the eighth transistor M8. The third gate region 303 serves as the gate of the seventh transistor M7. The third source-drain region 203 serves as the first electrode of the first transistor M1. The fourth source-drain region 204 serves as both the second electrode of the first transistor M1 and the second electrode of the eighth transistor M8. The fifth source-drain region 205 serves as both the first electrode of the eighth transistor M8 and the second electrode of the seventh transistor M7. The sixth source-drain region 206 serves as the first electrode of the seventh transistor M7.

[0040] The shift register unit 100 of the embodiment of the present disclosure may further include a first auxiliary transistor. The first auxiliary transistor may be distributed along a direction perpendicular to the circuit row 200 with the third transistor M3. The first auxiliary transistor may be connected in parallel with the third transistor M3. The gate of the first auxiliary transistor is provided on the same layer as the gate of the third transistor M3 and is electrically connected; the first electrode of the first auxiliary transistor is provided on the same layer as the first electrode of the third transistor M3 and is electrically connected; the second electrode of the first auxiliary transistor is provided on the same layer as the second electrode of the third transistor M3 and is an integrated structure. Specifically, as Figure 7 As shown, the gate electrode layer 3 may further include a fourth gate region 304 and a fifth gate region 305. The source-drain electrode layer 2 may include a seventh source-drain region 207, an eighth source-drain region 208, and a ninth source-drain region 209. The fourth gate region 304 serves as the gate of the third transistor M3, the fifth gate region 305 serves as the gate of the first auxiliary transistor, and the fourth gate region 304 and the fifth gate region 305 are electrically connected. The seventh source-drain region 207 serves as the first electrode of the first transistor M1, the ninth source-drain region 209 serves as the first electrode of the first auxiliary transistor, and the seventh source-drain region 207 and the ninth source-drain region 209 are electrically connected. The eighth source-drain region 208 serves as both the second electrode of the third transistor M3 and the second electrode of the first auxiliary transistor.

[0041] The shift register unit 100 of the embodiment of the present disclosure further includes a second auxiliary transistor. The second auxiliary transistor and the fifth transistor M5 are distributed along a direction perpendicular to the circuit row 200 and are connected in parallel. The gate of the second auxiliary transistor is provided on the same layer as the gate of the fifth transistor M5 and is electrically connected; the first electrode of the second auxiliary transistor is provided on the same layer as the first electrode of the fifth transistor M5 and is electrically connected; the second electrode of the second auxiliary transistor is provided on the same layer as the second electrode of the fifth transistor M5 and is an integrated structure. Specifically, as Figure 8 As shown, the gate electrode layer 3 may further include a sixth gate region 306 and a seventh gate region 307. The source-drain electrode layer 2 may include a tenth source-drain region 210, an eleventh source-drain region 211, and a twelfth source-drain region 212. The sixth gate region 306 serves as the gate of the fifth transistor M5, the seventh gate region 307 serves as the gate of the second auxiliary transistor, and the sixth gate region 306 is electrically connected to the seventh gate region 307. The tenth source-drain region 210 serves as the first electrode of the fifth transistor M5, the twelfth source-drain region 212 serves as the first electrode of the second auxiliary transistor, and the tenth source-drain region 210 is electrically connected to the twelfth source-drain region 212. The eleventh source-drain region 211 serves as both the second electrode of the fifth transistor M5 and the second electrode of the second auxiliary transistor. The present disclosure regards the fifth transistor M5 and the second auxiliary transistor connected in parallel as a repeating unit 9, which may include two, three, four, or more repeating units 9. Multiple repeating units 9 are distributed along the direction of the circuit row 200. For any two adjacent repeating units 9, the tenth source and drain regions 210 in the two repeating units 9 are electrically connected, the eleventh source and drain regions 211 in the two repeating units 9 are electrically connected, the twelfth source and drain regions 212 in the two repeating units 9 are electrically connected, the sixth gate regions 306 in the two repeating units 9 are electrically connected, and the seventh gate regions 307 in the two repeating units 9 are electrically connected.

[0042] like Figure 8 As shown, the gate electrode layer 3 may further include an eighth gate region 308 and a ninth gate region 309. The source-drain electrode layer 2 may include a thirteenth source-drain region 213, a fourteenth source-drain region 214, a fifteenth source-drain region 215, and a sixteenth source-drain region 216. The eighth gate region 308 serves as the gate of the second transistor M2, and the ninth gate region 309 serves as the gate of the fourth transistor M4. The thirteenth source-drain region 213 and the fourteenth source-drain region 214 serve as the first and second electrodes of the second transistor M2, respectively. The fifteenth source-drain region 215 and the sixteenth source-drain region 216 serve as the first and second electrodes of the fourth transistor M4, respectively.

[0043] like Figure 9As shown, the shift register unit 100 may further include a ninth transistor M9 and a tenth transistor M10. For the adjacent nth shift register unit 100 and the (n+1)th shift register unit 100, the first electrode of the ninth transistor M9 is connected to the signal input terminal SIN of the nth shift register unit 100, the second electrode of the ninth transistor M9 is connected to the signal output terminal GOUTn of the (n+1)th shift register unit 100, and the control electrode of the ninth transistor M9 is connected to the reverse scan terminal BS; the first electrode of the tenth transistor M10 is connected to the signal output terminal GOUTn of the nth shift register unit 100, the second electrode of the tenth transistor M10 is connected to the signal input terminal SIN of the (n+1)th shift register unit 100, and the control electrode of the tenth transistor M10 is connected to the forward scan terminal FS. Wherein, n is an integer greater than or equal to 1. Forward scanning is scanning from top to bottom line by line. The forward scanning terminal FS outputs a low level, and the tenth transistor M10 connected to the forward scanning terminal FS is turned on. From top to bottom, the output of each row serves as the input of the next row, and the OUT signal is output line by line. Similarly, the reverse scanning is from bottom to top.

[0044] like Figure 8 As shown, the gate layer may further include a tenth gate region 310 and an eleventh gate region 311. The source-drain electrode layer 2 may include a seventeenth source-drain region 217, an eighteenth source-drain region 218, a nineteenth source-drain region 219, and a twentieth source-drain region 220. The tenth gate region 310 is the gate of the ninth transistor M9, and the eleventh gate region 311 is the gate of the tenth transistor M10. The seventeenth source-drain region 217 and the eighteenth source-drain region 218 are the first electrode and the second electrode of the ninth transistor M9, respectively. The nineteenth source-drain region 219 and the twentieth source-drain region 220 are the first electrode and the second electrode of the tenth transistor M10, respectively. The shift register unit 100 of the present disclosure may have a size of 6.3 μm in a direction perpendicular to the circuit row 200, and the present disclosure may drive a pixel circuit with a PPI of 4032.

[0045] The present disclosure also provides a display panel. The display panel may include a plurality of pixel circuits and the gate drive circuit described in any of the above embodiments. The plurality of pixel circuits constitute a plurality of circuit rows 200. The plurality of shift register units 100 are connected to the plurality of circuit rows 200 in a one-to-one correspondence.

[0046] The display panel and gate driving circuit provided in the embodiments of the present disclosure belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0047] The above description is merely a preferred embodiment of the present disclosure and does not constitute any form of limitation to the present disclosure. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not intended to limit the present disclosure. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A gate drive circuit for a display panel, the gate drive circuit comprising a plurality of cascaded shift register units, the display panel comprising a plurality of pixel circuits, the plurality of pixel circuits constituting a plurality of circuit rows, the plurality of shift register units being connected in a one-to-one correspondence with the plurality of circuit rows, characterized in that: The shift register unit includes a storage sub-circuit, and the storage sub-circuits in adjacent shift register units are staggered; The shift register unit includes a first transistor, a second transistor, and a third transistor, wherein a first electrode of the first transistor is connected to a signal input terminal, a gate of the first transistor is connected to a first clock signal terminal, a first electrode of the second transistor is connected to a second electrode of the first transistor, a gate of the second transistor is connected to a first power supply terminal, a gate of the third transistor is connected to a second electrode of the second transistor, a first electrode of the third transistor is connected to a second clock signal terminal, and a second electrode of the third transistor is connected to a signal output terminal; The shift register unit further includes a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first electrode of the fourth transistor is connected to the first clock signal terminal, a gate of the fourth transistor is connected to the second electrode of the first transistor, a gate of the fifth transistor is connected to the second electrode of the fourth transistor, a first electrode of the fifth transistor is connected to the second power supply terminal, a second electrode of the fifth transistor is connected to the signal output terminal, a first electrode of the sixth transistor is connected to the first power supply terminal, a second electrode of the sixth transistor is connected to the second electrode of the fourth transistor, and a gate of the sixth transistor is connected to the first clock signal terminal; The shift register unit further includes a first auxiliary transistor, wherein the first auxiliary transistor and the third transistor are distributed along a direction perpendicular to the circuit row and connected in parallel; The shift register unit further includes a second auxiliary transistor, and the second auxiliary transistor and the fifth transistor are distributed along a direction perpendicular to the circuit row and connected in parallel.

2. The gate drive circuit according to claim 1, wherein: The storage sub-circuit includes a plurality of capacitors, and the plurality of capacitors are distributed along an extension direction of the circuit row.

3. The gate drive circuit according to claim 2, wherein: The storage sub-circuit includes a first capacitor and a second capacitor; the first capacitor is connected between the signal output terminal and the gate of the third transistor.

4. The gate driving circuit according to claim 3, wherein: The second capacitor is connected between the second power supply terminal and the gate of the fifth transistor.

5. The gate driving circuit according to claim 4, wherein: The capacitor includes a first plate and a second plate. The first plate of the first capacitor and the first plate of the second capacitor are arranged on the same layer. The second plate of the first capacitor and the second plate of the second capacitor are arranged on the same layer.

6. The gate driving circuit according to claim 4, wherein: The first transistor and the sixth transistor are distributed along a direction perpendicular to the circuit row; the gate of the first transistor and the gate of the sixth transistor are arranged in the same layer and are an integrated structure.

7. The gate driving circuit according to claim 4, wherein: The gate drive circuit also includes a seventh transistor and an eighth transistor, the first electrode of the seventh transistor is connected to the second power supply end, the control electrode of the seventh transistor is connected to the control electrode of the fifth transistor, the control electrode of the eighth transistor is connected to the second clock signal end, the first electrode of the eighth transistor is connected to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is connected to the second electrode of the first transistor.

8. The gate driving circuit according to claim 7, wherein: The first transistor, the eighth transistor and the seventh transistor are distributed along the extension direction of the circuit row; the second electrode of the first transistor and the second electrode of the eighth transistor are arranged on the same layer and are an integrated structure; the first electrode of the eighth transistor and the second electrode of the seventh transistor are arranged on the same layer and are an integrated structure.

9. A display panel, characterized in that: include: a plurality of pixel circuits, wherein the plurality of pixel circuits constitute a plurality of circuit rows; The gate drive circuit according to any one of claims 1 to 8, wherein the plurality of shift register units are connected to the plurality of circuit rows in a one-to-one correspondence.

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