Semiconductor structure and method of manufacturing, memory and method of manufacturing, storage system

Abstract

The embodiment of the present application provides a semiconductor structure and a manufacturing method, a memory and a manufacturing method, and a storage system, wherein the semiconductor structure comprises: an active pillar group located in a semiconductor layer; the active pillar group comprises: a first active pillar and a second active pillar; a first air gap isolation structure is located between adjacent active pillar groups; and a second air gap isolation structure is located between adjacent first active pillars and second active pillars.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and manufacturing method, a memory and manufacturing method, and a memory system. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell. The basic memory cell structure of DRAM consists of a transistor and a storage capacitor. Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0003] However, transistors in related technologies still have many problems that need to be improved. Summary of the Invention

[0004] To address the related technical issues, embodiments of this application propose a semiconductor structure and manufacturing method, a memory and manufacturing method, and a storage system.

[0005] This application provides a semiconductor structure, including:

[0006] An active pillar group is located in a semiconductor layer; the active pillar group includes: a first active pillar and a second active pillar;

[0007] The first air gap isolation structure is located between adjacent active column groups;

[0008] The second air gap isolation structure is located between the adjacent first active column and the second active column.

[0009] In the above scheme, the active pillar groups are arranged in an array along the first direction and the second direction respectively; both the first direction and the second direction are perpendicular to the direction of the semiconductor layer thickness.

[0010] The first active post and the second active post are arranged side by side along the first direction;

[0011] The semiconductor structure also includes:

[0012] The first gate structure is located between the second air gap isolation structure and the first active pillar;

[0013] The second gate structure is located between the second air gap isolation structure and the second active pillar.

[0014] In the above scheme, the dimension of the second air gap isolation structure along the first direction is larger than the dimension of the first air gap isolation structure along the first direction.

[0015] In the above scheme, the semiconductor structure further includes: an insulating layer located between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the active pillar group;

[0016] A protective layer is located above the active column group and the first air gap isolation structure;

[0017] A capping layer is located above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the capping layer is flush with the top of the protective layer.

[0018] In the above scheme, the semiconductor structure further includes:

[0019] A support layer is located between the first active pillar and the second active pillar, and below the first gate structure and the second gate structure.

[0020] In the above scheme, both the first active post and the second active post include:

[0021] Channel area;

[0022] The source electrode is located at the first end of the channel region;

[0023] The drain is located at the second end of the channel region; the first end and the second end are opposite ends in the extension direction of the channel region; the extension direction is parallel to the direction of the semiconductor layer thickness.

[0024] In the above scheme, the angle between the first direction and the second direction ranges from 0 to 90 degrees.

[0025] This application provides a memory, including: the semiconductor structure described in the above embodiments;

[0026] A memory cell, wherein the memory cell is connected to one of the source and drain terminals of an active pillar in the semiconductor structure; and

[0027] Bit lines are connected to the remaining one of the source and drain of each active pillar in a row of active pillars in the semiconductor structure.

[0028] This application provides a storage system, including: a memory as described in the above embodiments; and,

[0029] A memory controller, connected to the memory and used to control the memory.

[0030] This application provides a method for manufacturing a semiconductor structure, including:

[0031] Provides a semiconductor layer;

[0032] Forming the first and second trenches;

[0033] A third trench is formed; the second trench and the third trench divide the semiconductor layer into an active pillar group; the active pillar group includes a first active pillar and a second active pillar separated by the first trench; a protective layer is formed on the second trench to form a first air gap isolation structure in the second trench;

[0034] A first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar are formed on the sidewall of the first trench, and a fourth trench is formed between the first gate structure and the second gate structure.

[0035] A capping layer is formed on the fourth groove to form a second air gap isolation structure in the fourth groove.

[0036] In the above scheme, the first trench and the second trench penetrate the semiconductor layer and are alternately arranged along the first direction; the third trench penetrates the semiconductor layer and is arranged along the second direction;

[0037] The active pillar groups are arranged in an array along a first direction and a second direction, respectively; both the first direction and the second direction are perpendicular to the direction of the semiconductor layer thickness.

[0038] The first active post and the second active post are arranged side by side along the first direction.

[0039] In the above scheme, after the first trench and the second trench are formed, an insulating layer is formed on the sidewall of each of the first trench and the second trench.

[0040] The step of forming a protective layer on the second trench includes:

[0041] A protective layer in contact with the insulating layer is formed on top of the second trench where the insulating layer is formed;

[0042] The method further includes:

[0043] When a protective layer is formed on the second trench, a protective layer covering the insulating layer is formed in the first trench where the insulating layer is formed.

[0044] The method in the above scheme further includes:

[0045] Before forming the first gate structure covering one side of the first active pillar and the second gate structure covering one side of the second active pillar, an insulating material is filled in the first trench where the protective layer is formed, and a portion of the protective layer, a portion of the insulating layer and a portion of the insulating material located in the first trench are removed to form a support layer at the bottom of the first trench.

[0046] In the above solution, providing the semiconductor layer includes:

[0047] A substrate is provided; the substrate includes silicon on insulator, the silicon on insulator including a bottom silicon layer, an intermediate silicon oxide layer on the bottom silicon layer, and a top silicon layer on the intermediate silicon oxide layer; the top silicon layer is the semiconductor layer;

[0048] The first trench and the second trench penetrate the top silicon layer.

[0049] In the above scheme, the first gate structure includes a first gate oxide layer and a first gate; the second gate structure includes a second gate oxide layer and a second gate.

[0050] The step of forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on the sidewall of the first trench includes:

[0051] A first gate oxide layer is formed on one side of the first active pillar; a first gate is formed covering the first gate oxide layer; and

[0052] A second gate oxide layer is formed on one side of the second active pillar; a second gate is formed covering the second gate oxide layer.

[0053] This application provides a method for manufacturing a memory, the method comprising:

[0054] A semiconductor structure is formed; the semiconductor structure is manufactured by the semiconductor structure manufacturing method provided in the above embodiments.

[0055] A memory cell is formed, wherein the memory cell is connected to one of the source and drain of an active pillar in the semiconductor structure;

[0056] A bit line is formed, which is connected to the remaining one of the source and drain of the active pillar in the semiconductor structure.

[0057] This application provides a semiconductor structure and manufacturing method, a memory and manufacturing method, and a memory system. The semiconductor structure includes: an active pillar group located in a semiconductor layer; the active pillar group includes: a first active pillar and a second active pillar; a first air gap isolation structure located between adjacent active pillar groups; and a second air gap isolation structure located between adjacent first and second active pillars. In various embodiments of this application, a first air gap isolation structure is provided between active pillar groups, and a second air gap isolation structure is provided between the first and second active pillars within an active pillar group. This allows adjacent active pillar groups in the semiconductor structure, as well as the first and second active pillars within an active pillar group, to be separated by the air gap isolation structure. This reduces the coupling capacitance between transistors formed using the active pillars and between transistor groups formed using the active pillar groups, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this application;

[0059] Figure 2 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment;

[0060] Figures 3a-3j This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application.

[0061] Explanation of reference numerals in the attached figures:

[0062] 300 - Substrate; 301 - Bottom silicon; 302 - Intermediate silicon oxide layer; 303 - Top silicon (semiconductor layer); 304 - First trench; 305 - Second trench; 306 - Third trench; 307 - Active pillar group; 3071 - First active pillar; 3072 - Second active pillar; 308 - Insulating layer; 309 - Protective layer; 310 - First air gap isolation structure; 311 - Insulating material; 312 - Support layer; 313 - Gate structure; 3131 - First gate structure; 3132 - Second gate structure; 314 - Fourth trench; 315 - Capping layer; 316 - Second air gap isolation structure.

[0063] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0064] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0065] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0066] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0067] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0070] The semiconductor structures involved in the embodiments of this application are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM in the embodiments are for illustrative purposes only and are not intended to limit the scope of this application.

[0071] It is understandable that dynamic random access memory (DRAM) consists of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0072] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this application; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0073] However, with the miniaturization of memory, the spacing between multiple transistors formed in the semiconductor layer gradually decreases, causing the coupling capacitance between two adjacent transistors to increase gradually, which in turn affects the performance of the memory.

[0074] Based on this, in order to solve one or more of the above problems, this application provides a semiconductor structure and a method for manufacturing the same, as well as a memory and a method for manufacturing the same, to reduce the coupling capacitance between two adjacent transistors and thereby improve the performance of the memory. Figure 2 This is a schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in an embodiment of this application. Figure 2 As shown, the method for manufacturing the semiconductor structure includes the following steps:

[0075] Step S201: Provide a semiconductor layer;

[0076] Step S202: Form the first trench and the second trench;

[0077] Step S203, forming a third trench; the second trench and the third trench divide the semiconductor layer into an active pillar group; the active pillar group includes a first active pillar and a second active pillar separated by the first trench;

[0078] Step S204: A protective layer is formed on the second trench to form a first air gap isolation structure in the second trench;

[0079] Step S205: A first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar are formed on the sidewall of the first trench, and a fourth trench is formed between the first gate structure and the second gate structure.

[0080] Step S206: A capping layer is formed on the fourth groove to form a second air gap isolation structure in the fourth groove.

[0081] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. Figures 3a to 3j This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application. The following is in conjunction with... Figure 2 , Figures 3a to 3j The method for fabricating the semiconductor structure provided in the embodiments of this application will be described in detail.

[0082] It should be noted that in this embodiment, the first direction intersects the second direction, meaning the angle between the first direction and the second direction ranges from 0 to 90 degrees. In some specific embodiments, the first direction may be perpendicular to the second direction. It is understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of multiple active pillars along the first direction and the second direction.

[0083] For ease of description, in this embodiment and herein, the first direction and the second direction are represented as two orthogonal directions parallel to the substrate surface; wherein, the substrate surface can be understood as a plane perpendicular to the extension direction of the active pillar. Exemplarily, the first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the extension direction of the active pillar can be represented as the Z direction in the figures. It is understood that in some other embodiments, the first direction can be represented as the Y direction in the figures; and the second direction can be represented as the X direction in the figures.

[0084] Perform steps S201 and S202, refer to Figure 3a , Figure 3b , Figure 3c , Figure 3a This is a sectional view of the XOZ plane. Figure 3b This is a top view of the XOY plane. Figure 3c This is a top view of the XOY plane; where, Figure 3b for Figure 3a Top view along section AA, Figure 3c Figure 3b The enlarged view corresponding to the dashed box shown.

[0085] In some embodiments, providing the semiconductor layer includes: providing a substrate 300; the substrate 300 includes silicon-on-insulator (SOI), the SOI including a bottom silicon 301, an intermediate silicon oxide 302 located on the bottom silicon, and a top silicon 303 located on the intermediate silicon oxide 302; the top silicon 303 is the semiconductor layer.

[0086] In some embodiments, the substrate may also be germanium-on-insulator (GOI).

[0087] Next, refer to Figure 3a , Figure 3b , Figure 3c A first trench 304 and a second trench 305 are formed, wherein the first trench 304 and the second trench 305 penetrate the semiconductor layer 303 (i.e., the top silicon layer). The plurality of first trenches 304 and the plurality of second trenches 305 are spaced apart and alternately arranged along a first direction. Here, the first trenches 304 and the second trenches 305 extend to the surface of the intermediate silicon oxide layer 302; in other words, the intermediate silicon oxide layer 302 can serve as an etch stop layer for the first trenches 304 and the second trenches 305.

[0088] In other embodiments, the width of the first groove 304 along the first direction may be greater than or equal to the width of the second groove 305 along the first direction; preferably, the width of the first groove 304 along the first direction is greater than the width of the second groove 305 along the first direction.

[0089] In some embodiments, the first trench 304 and the second trench 305 are formed using photolithography (hereafter understood as lithography-etching (LE)) and self-aligned double patterning (SADP) processes. Here, the SADP process includes first depositing a sacrificial layer on the surface of the semiconductor layer, then performing photolithography and etching to transfer the pattern from the mask onto the sacrificial layer. Atomic layer deposition (ALD) is then used to deposit a relatively uniform thin film on the surface and sides of the sacrificial layer as an isolation structure. The isolation structure is then removed by etching back. Due to the geometric effects of the sidewalls of the sacrificial layer, material deposited on both sides of the pattern on the sacrificial layer remains, forming the isolation structure. A highly selective etchant is used to remove the sacrificial layer, leaving only the isolation structure on the substrate surface. The period of the isolation structure pattern is half that of the photolithographic pattern, achieving a doubling of spatial pattern density. Finally, plasma etching is used to transfer the isolation structure pattern onto a hard mask in the substrate, thus transferring the preset pattern of the active pillars onto the surface of the semiconductor layer.

[0090] refer to Figure 3b Step S203 is executed to form a third trench 306. A plurality of the third trenches 306 are arranged along a second direction, and each third trench 306 penetrates the semiconductor layer 303 and extends along the first direction.

[0091] In some embodiments, after forming the first trench 304 and the second trench 305, the method further includes: filling the first trench 304 and the second trench 305 with an insulating material, such as silicon oxide. Then, the third trench 306 is formed, and after forming the third trench 306, any remaining insulating material in the first trench 304 and the second trench 305 is removed.

[0092] In some specific embodiments, the method for forming the third trench 306 may include: forming a mask layer on the surface of the semiconductor layer 303, developing and exposing the mask layer to form a preset pattern of the third trench 306, and then forming the third trench 306 by an etching process.

[0093] It should be noted that steps S202 and S203 do not have a specific execution order. The first and second trenches can be formed first, then filled, and finally the third trench formed in the semiconductor layer. Alternatively, the third trench can be formed first, filled, and then the first and second trenches formed in the semiconductor layer. A mesh-like mask layer can also be formed, creating the first, second, and third trenches all at once. In other words, the formation order of the first, second, and third trenches can be selected and set according to the actual situation.

[0094] Here, the second trench 305 and the third trench 306 divide the semiconductor layer into a plurality of active pillar groups 307 arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the thickness direction of the semiconductor layer. (Reference) Figure 3b , Figure 3c Each active post group 307 includes a first active post 3071 and a second active post 3072. The first active post 3071 and the second active post 3072 are arranged side by side along a first direction, and the first active post 3071 and the second active post 3072 are isolated by a first groove 304. In other words, the first groove 304 is located between the first active post 3071 and the second active post 3072. The second groove 305 is located between two adjacent active post groups 307.

[0095] Here, the methods for forming the first trench 304, the second trench 305, and the third trench 306 include, but are not limited to, plasma dry etching processes.

[0096] refer to Figure 3d , Figure 3e In some embodiments, the method further includes forming an insulating layer 308 on the sidewall of each of the first trenches 304 and the second trenches 305 after forming the third trench 306. The insulating layer 308 can be used to couple dangling bonds (such as silicon dangling bonds) to the sidewalls of the first trenches 304 and the second trenches 305.

[0097] In some specific embodiments, the material of the insulating layer 308 includes, but is not limited to, silicon oxide; the method of forming the insulating layer 308 includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), ALD, and other processes.

[0098] here, Figure 3d This is a sectional view of the XOZ plane. Figure 3e This is a top view of the XOY plane, where... Figure 3e for Figure 3d Top view along section BB.

[0099] refer to Figure 3d , Figure 3e Step S204 is executed to form a protective layer 309 on the second trench 305.

[0100] In some specific embodiments, forming a protective layer on the second trench 305 includes:

[0101] A protective layer 309 is formed on the top of the second trench 305 where the insulating layer 308 is formed, and in contact with the insulating layer 308; and a protective layer 309 is formed on the surface of the active pillar assembly; wherein the surface of the protective layer located on the top of the second trench 305 is substantially flush with the surface of the protective layer located on the surface of the active pillar assembly, in other words, the height of the surface of the protective layer 309 in the Z-axis direction is greater than the height of the surface of the active pillar assembly in the Z-axis direction.

[0102] The method further includes:

[0103] When a protective layer 309 is formed on the second trench 305, a protective layer 309 covering the insulating layer 308 is formed in the first trench 304 where the insulating layer 308 is formed.

[0104] refer to Figure 3d The protective layer 309 contacts the insulating layer 308 on the sidewall of the second trench 305 to form a first air gap isolation structure 310 in the second trench 305. The protective layer 309 is located above the active pillars (the first active pillar and the second active pillar) and the first air gap isolation structure 310. It should be noted that each active pillar is used to form a corresponding transistor, and the group of active pillars forms a corresponding transistor group in subsequent processes. Here, the first air gap isolation structure 310 can be used to reduce the coupling capacitance between two adjacent transistor groups.

[0105] It should be noted that in some embodiments, a solid isolation structure (such as silicon oxide) is filled in the second trench to separate two adjacent active pillars used to form transistors; in this embodiment, an air gap isolation structure is used to separate two adjacent active pillars used to form transistors; here, the air gap isolation structure may include gases such as nitrogen and air. Preferably, the air gap isolation structure includes air; it should be understood that air is a good dielectric with a significantly smaller relative permittivity (approximately 1), resulting in a smaller coupling capacitance between two transistors separated by the air gap isolation structure; while the relative permittivity of a solid isolation structure is relatively large (such as silicon oxide, with a relative permittivity of approximately 4), resulting in a larger coupling capacitance between two transistors separated by the solid isolation structure; therefore, in this embodiment, using an air gap isolation structure can reduce the coupling capacitance between two adjacent transistor groups compared to a solid isolation structure.

[0106] It should be noted that the height of the insulating layer 308 in the Z-axis direction can be higher than the surface of the active post, as shown in the reference. Figure 3d The formation process may include first forming a first protective layer on the surface of the active post, then forming an insulating layer 308 on the sidewall and bottom of the second trench 305 of the active post, the surface of the insulating layer 308 being substantially flush with the surface of the first protective layer, and finally forming a second protective layer on the surfaces of the insulating layer 308 and the first protective layer. Here, the protective layer 309 includes the first protective layer and the second protective layer.

[0107] It should be noted that during the formation of the protective layer 309, since the diameter of the second trench 305 along the first direction is small, the protective layer 309 is only formed at the opening of the second trench, so that a first air gap isolation structure 310 is formed in the second trench 305; here, the protective layer 309 located at the opening of the second trench 305 can be used to protect the first air gap isolation structure 310 from being etched or filled in subsequent etching processes.

[0108] The material of the protective layer 309 includes, but is not limited to, silicon nitride; the method of forming the protective layer 309 includes, but is not limited to, PVD process, CVD process or ALD process.

[0109] Here, since the first trench 304 has a large dimension along the first direction, the protective layer 309 is also located on the sidewall and bottom surface of the first trench 304 on which the insulating layer 308 is formed.

[0110] Next, refer to Figure 3f , Figure 3gAn insulating material 311 is filled into the first trench 304 where the protective layer 309 is formed, and a portion of the protective layer 309, a portion of the insulating layer 308, and a portion of the insulating material 311 located in the first trench 304 are removed to form a support layer 312 at the bottom of the first trench 304.

[0111] The insulating material 311 is composed of materials including, but not limited to, silicon oxide; the methods for forming the insulating material 311 include, but are not limited to, PVD and CVD processes; the removal process includes, but is not limited to, etching processes; the support layer 312 can serve a supporting function and can also make the gate structure formed in the first trench shorter in subsequent process steps, thereby further reducing parasitic capacitance; Reference Figure 3f The support layer 312 is Figure 3f The corresponding structure is shown in the dashed box.

[0112] here, Figure 3f This is a sectional view of the XOZ plane. Figure 3g This is a top view of the XOY plane, where... Figure 3g for Figure 3f Top view along section CC.

[0113] It should be noted that during the process of removing part of the protective layer 309, part of the insulating layer 308 and part of the insulating material 311 located in the first trench 304, part of the protective layer 309 located at the top of the active column group and the second trench is also removed; wherein, the protective layer 309 located at the top of the second trench is used to protect the first air gap isolation structure 310 from being damaged.

[0114] refer to Figure 3h , Figure 3i , Figure 3j Step S205 is executed to form a gate structure 313; wherein, the gate structure 313 includes a first gate structure 3131 and a second gate structure 3132, wherein the first gate structure 3131 covers one side of the first active pillar 3071; and the second gate structure 3132 covers one side of the second active pillar 3072.

[0115] Here, the method of forming the gate structure 313 includes forming a first gate structure 3131 covering one side of the first active pillar 3071 and a second gate structure 3132 covering one side of the second active pillar 3072 on the sidewall of each of the first trenches 304. Here, the first gate structure and the second gate structure in each group of active pillars are confined in the same trench (first trench).

[0116] The methods for forming the first gate structure 3131 and the second gate structure 3132 include, but are not limited to, PVD process, CVD process or ALD process.

[0117] here, Figure 3h This is a sectional view of the XOZ plane. Figure 3i This is a top view of the XOY plane. Figure 3j This is a top view of the XOY plane, where... Figure 3i for Figure 3h Top view along section DD. Figure 3j for Figure 3i The enlarged view corresponding to the dashed box shown in the image.

[0118] In some embodiments, the first gate structure 3131 includes a first gate oxide layer and a first gate; the second gate structure 3132 includes a second gate oxide layer and a second gate.

[0119] The step of forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on the sidewall of the first trench includes:

[0120] A first gate oxide layer is formed on one side of the first active pillar; a first gate is formed covering the first gate oxide layer; and

[0121] A second gate oxide layer is formed on one side of the second active pillar; a second gate is formed covering the second gate oxide layer.

[0122] In other words, the first gate oxide layer ( Figure 3h (Not shown in the image) The insulating layer 308 located between the first active pillar sidewall and the first gate; the second gate oxide layer ( Figure 3h (Not shown in the image) The insulating layer 308 located between the second active pillar sidewall and the second gate.

[0123] It should be noted that the gate oxide layer in a transistor can be used to sense different electric fields and apply them to the surface of the channel region, so that minority carriers in the first semiconductor layer are adsorbed onto the surface of the channel region and accumulate and invert, making the gate oxide layer the same as the doping type of the source and drain, thereby realizing the conduction between the source and drain.

[0124] In other embodiments, when an insulating layer 308 is formed on the sidewall of the first trench 304, the first gate structure includes a first gate; the second gate structure includes a second gate. Simultaneously, the insulating layer 308 located between the first gate structure and the first active pillar can be used as a first gate oxide layer corresponding to the first gate; the insulating layer 308 located between the second gate structure and the second active pillar can be used as a second gate oxide layer corresponding to the second gate.

[0125] Here, the materials of the first gate and the second gate may include metal (such as tungsten) or polysilicon; the materials of the first gate oxide layer and the second gate oxide layer may include silicon oxide.

[0126] In some embodiments, the method further includes: forming a channel region, a source at a first end of the channel region, and a drain at a second end of the channel region in the first active pillar to form a first transistor; forming a channel region, a source at the first end of the channel region, and a drain at the second end of the channel region in the second active pillar to form a second transistor; the first transistor and the second transistor form a transistor group; wherein the first end and the second end are opposite ends in the extension direction of the channel region; the extension direction is parallel to the direction of the semiconductor layer thickness.

[0127] Here, a fourth trench 314 is formed between the first gate structure 3131 and the second gate structure 3132.

[0128] Next, refer to Figure 3h , Figure 3i , Figure 3j Step S206 is performed to form a capping layer 315 on the fourth groove 314 to form a second air gap isolation structure 316 in the fourth groove 314.

[0129] Here, the capping layer 315 is located above the second air gap isolation structure 316 and the first gate structure 3131 and the second gate structure 3132, and the capping layer 315 is in contact with the insulating layer 308 located on the sidewall of the first trench 304, so that the capping layer 315, the first gate structure 3131, the support layer 312, and the second gate structure 3132 form a closed second air gap isolation structure 316; in some specific embodiments, the top of the capping layer 315 is substantially flush with the top of the protective layer 309.

[0130] Here, the second air gap isolation structure 316 can be used to reduce the coupling capacitance between adjacent first transistors and second transistors, thereby improving the performance of the memory.

[0131] In some specific embodiments, the constituent materials of the capping layer include, but are not limited to, silicon oxide; the methods for forming the capping layer include, but are not limited to, PVD, CVD, or ALD processes.

[0132] It should be noted that, Figures 3a to 3jThe dimensions of each structure are for illustrative purposes only and do not represent actual dimensions. In actual applications, the diameter of the second and fourth grooves along the first direction is very narrow. The protective layer 309 can be formed above the second groove, so that a first air gap isolation structure 310 can be formed in the second groove. The cap layer 315 can be formed above the opening of the fourth groove, so that a second air gap isolation structure 316 can be formed in the fourth groove.

[0133] In various embodiments of this application, a first air gap isolation structure is provided between the active pillar groups, and a second air gap isolation structure is provided between the first active pillar and the second active pillar in each active pillar group. In this way, multiple active pillar groups in the semiconductor structure, as well as the first active pillar and the second active pillar in each active pillar group, can be separated by the air gap isolation structure. This reduces the coupling capacitance between transistors formed using the active pillars and between transistor groups formed using the active pillar groups, thereby improving the performance of the semiconductor structure.

[0134] This application further provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method described in the above embodiments, and the semiconductor structure includes:

[0135] An active pillar group is located in a semiconductor layer; the active pillar group includes: a first active pillar and a second active pillar;

[0136] The first air gap isolation structure is located between adjacent active column groups;

[0137] The second air gap isolation structure is located between the adjacent first active column and the second active column.

[0138] In some embodiments, the active pillar groups are arranged in an array along a first direction and a second direction, respectively; both the first direction and the second direction are perpendicular to the direction of the semiconductor layer thickness.

[0139] The first active post and the second active post are arranged side by side along the first direction;

[0140] The semiconductor structure also includes:

[0141] The first gate structure is located between the second air gap isolation structure and the first active pillar;

[0142] The second gate structure is located between the second air gap isolation structure and the second active pillar.

[0143] In some embodiments, the dimension of the second air gap isolation structure along the first direction is larger than the dimension of the first air gap isolation structure along the first direction.

[0144] In some embodiments, the semiconductor structure further includes: an insulating layer located between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the active pillar group;

[0145] A protective layer is located above the active column and the first air gap isolation structure;

[0146] A capping layer is located above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the capping layer is flush with the top of the protective layer.

[0147] In some embodiments, the semiconductor structure further includes:

[0148] A support layer is located between the first active pillar and the second active pillar, and below the first gate structure and the second gate structure.

[0149] In some embodiments, both the first active post and the second active post include:

[0150] Channel area;

[0151] The source electrode is located at the first end of the channel region;

[0152] The drain is located at the second end of the channel region; the first end and the second end are opposite ends in the extension direction of the channel region; the extension direction is parallel to the direction of the semiconductor layer thickness.

[0153] In some embodiments, the angle between the first direction and the second direction ranges from 0 to 90 degrees.

[0154] This application also provides a memory, including:

[0155] The semiconductor structures described in the above embodiments;

[0156] A memory cell, wherein the memory cell is connected to one of the source and drain terminals of an active pillar in the semiconductor structure; and

[0157] Bit lines are connected to the remaining one of the source and drain of each active pillar in a row of active pillars in the semiconductor structure.

[0158] In some embodiments, the memory provided in this application includes various types of memory. For example, dynamic random access memory, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0159] In some embodiments, the storage cell includes a capacitor; the capacitor includes a second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode may be connected to the source of a transistor in the transistor array, and the first electrode may be connected to a reference voltage, which may be ground or other voltages. The capacitor is used to store written data.

[0160] In some embodiments, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected between the bit line and the source of a transistor in the semiconductor structure; or, the adjustable resistor is connected between the bit line and the drain of a transistor in the semiconductor structure, and the adjustable resistor is used to adjust the state of the stored data by the bit line voltage provided by the bit line.

[0161] It should be noted that only some common memories are listed here as examples, and the scope of protection of this application is not limited to these. Any memory containing transistors provided in the embodiments of this application is within the scope of protection of this application.

[0162] This application provides a storage system, including: a memory as described in the above embodiments; and,

[0163] A memory controller, connected to the memory and used to control the memory.

[0164] This application provides a method for manufacturing a memory, the method comprising:

[0165] A semiconductor structure is formed; the semiconductor structure is manufactured by the semiconductor structure manufacturing method provided in the above embodiments.

[0166] A memory cell is formed, wherein the memory cell is connected to one of the source and drain of an active pillar in the semiconductor structure;

[0167] A bit line is formed, which is connected to the remaining one of the source and drain electrodes in a row of active pillars in the semiconductor structure.

[0168] In practical applications, the word lines are connected to the gate of each of the semiconductor structures. The word lines provide a word line voltage and control the conduction or cutoff of the channel region in each transistor. The bit lines, extending along the first direction, are connected to the drain of each of the semiconductor structures. The bit lines are used to perform read or write operations on the memory cell when each transistor is turned on.

[0169] The memory manufactured by the method of manufacturing the memory provided in this application is similar to the memory in the above embodiments. For technical features not disclosed in detail in the embodiments of this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0170] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0171] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0172] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Active pillars are located within the semiconductor layer; The active pillar group includes: a first active pillar and a second active pillar; the active pillar group extends only along the direction of the semiconductor layer thickness; The first air gap isolation structure is located between adjacent active column groups; The second air gap isolation structure is located between the adjacent first active column and the second active column.

2. The semiconductor structure according to claim 1, characterized in that, The active pillar groups are arranged in an array along a first direction and a second direction, respectively; both the first direction and the second direction are perpendicular to the direction of the semiconductor layer thickness. The first active post and the second active post are arranged side by side along the first direction; The semiconductor structure also includes: The first gate structure is located between the second air gap isolation structure and the first active pillar; The second gate structure is located between the second air gap isolation structure and the second active pillar.

3. The semiconductor structure according to claim 2, characterized in that, The dimension of the second air gap isolation structure along the first direction is larger than the dimension of the first air gap isolation structure along the first direction.

4. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes: an insulating layer located between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the active pillar group; A protective layer is located above the active column group and the first air gap isolation structure; A capping layer is located above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the capping layer is flush with the top of the protective layer.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A support layer is located between the first active pillar and the second active pillar, and below the first gate structure and the second gate structure.

6. The semiconductor structure according to claim 1, characterized in that, Both the first active post and the second active post include: Channel area; The source electrode is located at the first end of the channel region; The drain is located at the second end of the channel region; the first end and the second end are opposite ends in the extension direction of the channel region; the extension direction is parallel to the direction of the semiconductor layer thickness.

7. The semiconductor structure according to claim 2, characterized in that, The angle between the first direction and the second direction ranges from 0 to 90 degrees.

8. A memory, characterized in that, include: The semiconductor structure according to any one of claims 1 to 7; A memory cell, wherein the memory cell is connected to one of the source and drain of an active pillar in the semiconductor structure; as well as Bit lines are connected to the remaining one of the source and drain of each active pillar in a row of active pillars in the semiconductor structure.

9. A storage system, characterized in that, include: The memory as described in claim 8; as well as, A memory controller, connected to the memory and used to control the memory.

10. A method for manufacturing a semiconductor structure, characterized in that, include: Provides a semiconductor layer; Forming the first and second trenches; A third trench is formed; The second trench and the third trench divide the semiconductor layer into active pillar groups; the active pillar groups include a first active pillar and a second active pillar separated by the first trench; A protective layer is formed on the second trench to form a first air gap isolation structure in the second trench; A first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar are formed on the sidewall of the first trench, and a fourth trench is formed between the first gate structure and the second gate structure. A capping layer is formed on the fourth groove to form a second air gap isolation structure in the fourth groove.

11. The manufacturing method according to claim 10, characterized in that, The first trench and the second trench penetrate the semiconductor layer and are alternately arranged along a first direction; the third trench penetrates the semiconductor layer and is arranged along a second direction; The active pillar groups are arranged in an array along a first direction and a second direction, respectively; both the first direction and the second direction are perpendicular to the direction of the semiconductor layer thickness. The first active post and the second active post are arranged side by side along the first direction.

12. The manufacturing method according to claim 11, characterized in that, After the first trench and the second trench are formed, an insulating layer is formed on the sidewall of each of the first trench and the second trench. The step of forming a protective layer on the second trench includes: A protective layer in contact with the insulating layer is formed on top of the second trench where the insulating layer is formed; The method further includes: When a protective layer is formed on the second trench, a protective layer covering the insulating layer is formed in the first trench where the insulating layer is formed.

13. The manufacturing method according to claim 12, characterized in that, The method further includes: Before forming the first gate structure covering one side of the first active pillar and the second gate structure covering one side of the second active pillar, an insulating material is filled in the first trench where the protective layer is formed, and a portion of the protective layer, a portion of the insulating layer and a portion of the insulating material located in the first trench are removed to form a support layer at the bottom of the first trench.

14. The manufacturing method according to claim 10, characterized in that, The provision of the semiconductor layer includes: A substrate is provided; the substrate includes silicon on insulator, the silicon on insulator including a bottom silicon layer, an intermediate silicon oxide layer on the bottom silicon layer, and a top silicon layer on the intermediate silicon oxide layer; the top silicon layer is the semiconductor layer; The first trench and the second trench penetrate the top silicon layer.

15. The manufacturing method according to claim 10, characterized in that, The first gate structure includes a first gate oxide layer and a first gate; the second gate structure includes a second gate oxide layer and a second gate. The step of forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on the sidewall of the first trench includes: A first gate oxide layer is formed on one side of the first active pillar; a first gate is formed covering the first gate oxide layer; and A second gate oxide layer is formed on one side of the second active pillar; a second gate is formed covering the second gate oxide layer.

16. A method for manufacturing a memory, characterized in that, The method includes: A semiconductor structure is formed; the semiconductor structure is manufactured by the semiconductor structure manufacturing method provided in any one of claims 10 to 15; A memory cell is formed, wherein the memory cell is connected to one of the source and drain of an active pillar in the semiconductor structure; A bit line is formed, which is connected to the remaining one of the source and drain electrodes in a row of active pillars in the semiconductor structure.

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