A series-connected double-gate LIGBT device and a manufacturing method thereof

Abstract

This invention provides a series-connected dual-gate LIGBT device and its manufacturing method. A first dielectric oxide layer and a polysilicon electrode constitute a vertical field plate, which is distributed throughout the drift region of the second conductivity type, forming a uniform field IGBT device with a vertical field plate array. Simultaneously, a low-voltage control voltage circuit, such as a MOS, is formed at the IGBT cathode using a compatible process. Vertical field plate structures are fabricated on both sides of the low-voltage control voltage circuit using a compatible process, with the vertical field plate serving as a dielectric isolation trench for high and low voltage isolation. Taking a MOS as an example, the drain of the low-voltage MOS is shorted to the cathode of the IGBT, forming two devices connected in series, with their gates shorted, controlling both devices simultaneously with the same gate voltage. Since they are connected in series, the current of the MOS is the same as the current of the IGBT. Therefore, the current of the entire device can be limited by changing the gate voltage of the low-voltage MOS, suppressing parasitic p-n-p-n latch-up.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors and mainly proposes a series dual-gate LIGBT device and its manufacturing method. Background Technology

[0002] Lateral insulated-gate bipolar transistors (IGBTs) are composite power semiconductor devices combining the high input impedance of MOSFETs and the conductance modulation characteristics of BJTs. Due to their advantages such as low turn-on voltage, low drive power consumption, strong current capability, high withstand voltage, good thermal stability, and good integration, they are widely used in intelligent ICs such as automotive electronics, smart grids, and motor drives. However, for traditional IGBTs, when the collector current increases to a certain level, the forward voltage becomes large enough to turn on the NPN transistor, causing the parasitic NPN and PNP transistors to saturate. At this point, the parasitic thyristors conduct, and the gate loses its original control function, resulting in a latch-up phenomenon—the latch-up effect of IGBTs. The latch-up resistance of IGBTs is also an important parameter for evaluating their operating characteristics, as it limits their operating range. After latch-up occurs, the anode current increases rapidly, generating excessive power consumption and leading to device failure. Therefore, to control the anode current, it is necessary to suppress the parasitic effect to ensure the gate's control function. SOI materials are favored by researchers due to their advantages of low parasitic capacitance, low power consumption, low leakage current, suppression of latch-up effect, and good process compatibility. They are now widely used in power IC and LIGBT research.

[0003] To suppress the latch-up effect of uniformly field-controlled IGBTs and improve the gate control capability of the device, a low-voltage control circuit, such as a MOS, is fabricated in the cathode region of the IGBT using a compatible process. A vertical field plate structure is used as a dielectric isolation trench for high-low voltage isolation. Taking the MOS as an example, the drain of the MOS is shorted to the cathode of the IGBT, and the gate is connected, ultimately forming a series-connected low-voltage MOS and high-voltage IGBT. Through this series structure, after the MOS is turned on with a gate voltage applied, the drain current of the MOS is the same as the anode current of the IGBT. Therefore, the current of the entire device can be limited by changing the gate voltage of the low-voltage MOS, thereby controlling the parasitic pnpn latch-up from being turned on. This invention proposes a series-connected dual-gate IGBT device and its manufacturing method, which solves the gate runaway problem caused by the latch-up effect of IGBTs, has stronger gate control capability, and its manufacturing method is relatively simple. Summary of the Invention

[0004] This invention utilizes a compatible process to form a low-voltage control circuit in the cathode region of the uniform IGBT and connects it in series with the IGBT, proposing a series dual-gate IGBT device. This solves the gate runaway problem caused by the latch-up effect of the IGBT and improves the operating characteristics of the IGBT.

[0005] To achieve the above-mentioned objectives, the technical solution of the present invention—a series dual-gate LIGBT device—is as follows:

[0006] A series dual-gate LIGBT device, consisting of a low-voltage section and a high-voltage section:

[0007] The high-voltage section includes: a fourth dielectric buried oxide layer 34 located above a first conductivity type semiconductor substrate 11; a second conductivity type drift region 21 located above the fourth dielectric buried oxide layer 34; a first conductivity type well region 12 located to the left of the second conductivity type drift region 21; a second conductivity type well region 22 located to the right of the second conductivity type drift region 21; a first conductivity type heavily doped cathode region 15 and a second conductivity type heavily doped cathode region 25 located within the first conductivity type well region 12; cathode region metal 54 located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25; and anode region metal 55 located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25. The upper surface of a heavily doped anode region 16 of a first conductivity type; the heavily doped anode region 16 of a first conductivity type is located in a well region 22 of a second conductivity type; the second dielectric oxide layer 32 is located above the well region 12 of the first conductivity type, and its left end is in contact with the heavily doped cathode region 25 of the second conductivity type, and its right end is in contact with the drift region 21 of the second conductivity type; the third dielectric oxide layer 33 is located on the upper surface of the drift region 21 of the second conductivity type between the second dielectric oxide layer 32 and the heavily doped anode region 16 of the first conductivity type; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;

[0008] The low-voltage section includes: a first conductivity type well region 12, a first conductivity type heavily doped source region 13, a second conductivity type heavily doped source region 23, and a second conductivity type heavily doped drain region 24 located in the first conductivity type well region 12; a second dielectric oxide layer 32 located above the first conductivity type well region 12, with its left end in contact with the second conductivity type heavily doped source region 23 and its right end in contact with the second conductivity type heavily doped drain region 24; a control gate polysilicon electrode 42 covering the upper surface of the second dielectric oxide layer 32; a third dielectric oxide layer 33 located above the polysilicon electrode 41; a drain metal 53 located on the upper surface of the second conductivity type heavily doped drain region 24; and a source metal 52 located on the upper surfaces of the first conductivity type heavily doped source region 13 and the second conductivity type heavily doped drain region 24.

[0009] The first dielectric oxide layer 31 and the polycrystalline silicon electrode 41 constitute a longitudinal field plate, and the first dielectric oxide layer 31 surrounds the polycrystalline silicon electrode 41. The longitudinal field plate is distributed throughout the entire second conductivity type drift region 21, forming a longitudinal field plate array. The longitudinal field plate is also formed in the cathode region and the source end using the same process as the longitudinal field plate in the drift region. The longitudinal field plate penetrates through the first type conductive well region 12 and the second conductivity type drift region 21 to the fourth dielectric buried oxide layer 34. The longitudinal field plate also penetrates in the z direction and is distributed on both sides of the low voltage region as a dielectric isolation trench. The polycrystalline silicon electrodes 41 on both sides of the low voltage region are grounded. The longitudinal field plates distributed throughout the entire second conductivity type drift region 21 are evenly spaced in the x direction and connected to the metal strip 51 through through holes to form an internal equipotential ring. The horizontal direction from the cathode region to the anode region is the x direction, the downward direction of the depth of the longitudinal field plate is the y direction, and the inward direction perpendicular to the xy plane is the z direction.

[0010] As a preferred embodiment, the longitudinal field plate of the high-voltage section is formed simultaneously with the longitudinal field plates of the cathode region and the source end using the same process, and the depth of the longitudinal field plate of the high-voltage section is deeper than the depth of the drift region 21 of the second conductivity type. The longitudinal field plate of the high-voltage section is in contact with the fourth dielectric buried oxide layer 34; and / or the width of the etched dielectric isolation trench is reduced so that the oxide layer completely fills the trench during the subsequent trench wall oxidation process, and the longitudinal field plate of the cathode region becomes a full dielectric trench.

[0011] As a preferred embodiment, the longitudinal field plate near the first conductivity type heavily doped source region 13 and the longitudinal field plate between the second conductivity type heavily doped drain region 24 and the first conductivity type heavily doped cathode region 15 are both grounded via metal strip 51.

[0012] As a preferred embodiment, the longitudinal and transverse spacing of adjacent longitudinal field plates distributed throughout the second conductivity type drift region 21 are equal; and / or the cross-sectional shape of the longitudinal field plates is rectangular, circular, elliptical, or hexagonal.

[0013] As a preferred embodiment, the longitudinal field plate near the first conductivity type heavily doped source region 13 and the longitudinal field plate between the second conductivity type heavily doped drain region 24 and the first conductivity type heavily doped cathode region 15 are both grounded via metal strip 51.

[0014] As a preferred embodiment, the longitudinal field plates with isolation function are distributed on both sides of the low-voltage control circuit and connected to the fourth dielectric buried oxide layer 34. The longitudinal field plates simultaneously deplete the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21. The longitudinal field plates connected to the fourth dielectric buried oxide layer 34 play the role of high and low voltage isolation.

[0015] As a preferred embodiment, the device is an SOI structure or a bulk silicon device, wherein the dielectric oxide layer is silicon dioxide or a high-k or low-k material; and in addition to bulk silicon devices, this device structure is also applied in SiC and GaN semiconductor materials.

[0016] And / or the low-voltage control circuit is a MOS or a CMOS circuit; the high-voltage part is an N-type lateral insulated gate bipolar transistor (LIGBT), or a P-type lateral insulated gate bipolar transistor (P-LIGBT) formed by compatible processes, or constitutes a CMOS circuit; the device is an enhancement-mode structure or an accumulation-mode structure.

[0017] As a preferred embodiment, a first conductivity type doped layer is implanted in the drift region. The doped layer is located on the upper surface of the second conductivity type drift region (21), or below the third dielectric oxide layer 33, or in a discontinuous structure in the z-direction.

[0018] Alternatively, an N-type injection can be added to the channel region below the second dielectric oxide layer 32 of the high-voltage LIGBT, so that the IGBT is normally open, meaning the entire device is controlled by the gate voltage of the low-voltage region.

[0019] Alternatively, the channel region below the second dielectric oxide layer 32 can be formed without diffusion, meaning the device has no channel and is an accumulation-type device.

[0020] Or the heavy doping concentration is greater than 1e18cm. -3 .

[0021] The present invention also provides a method for manufacturing a series dual-gate LIGBT device, comprising the following steps:

[0022] Step 1: Select SOI material, which includes a Si first conductivity type semiconductor substrate 11, a fourth dielectric buried oxide layer 34, and a second conductivity type drift region 21;

[0023] Step 2: Form the grooves using photolithography and etching;

[0024] Step 3: Form the first dielectric oxide layer 31 in the tank;

[0025] Step 4: Deposit polycrystalline silicon and etch it onto the silicon plane to form a polycrystalline silicon electrode 41;

[0026] Step 5: Ion implantation of impurities of the first conductivity type and push-junction to form a well region 12 of the first conductivity type; ion implantation of impurities of the second conductivity type and push-junction to form a well region 22 of the second conductivity type.

[0027] Step 6: Grow and form the third dielectric oxide layer 33, and then form the second dielectric oxide layer 32 by etching;

[0028] Step 7: Deposit and etch polysilicon to form the control gate polysilicon electrode 42;

[0029] Step 8: Implant to form a first conductivity type heavily doped source region 13, a first conductivity type heavily doped cathode region 15, a first conductivity type heavily doped anode region 16, a second conductivity type heavily doped source region 23, a second conductivity type heavily doped drain region 24, and a second conductivity type heavily doped cathode region 25;

[0030] Step 9: Etch the third dielectric oxide layer 33 to form contact holes, then deposit and etch the metal strip 51 to form surface metal strips and metal electrodes.

[0031] As a preferred embodiment, the second conductivity type drift region 21 in step 1 is formed by implanting N-type dopant and pushing the junction; and / or the first conductivity type well region 12 and the second conductivity type well region 22 obtained by implantation and pushing the junction in step 5 are formed by multiple implantations and activations with different energies.

[0032] As a preferred embodiment, when forming the first conductivity type heavily doped anode region 16, the second conductivity type heavily doped anode region 26 is formed simultaneously, thus forming a reverse-conducting IGBT structure, and / or the longitudinal field plate closest to the IGBT cathode in the second conductivity type drift region 21 of the device is penetrated in the z-direction to block the holes injected from the collector to the emitter.

[0033] The beneficial effects of this invention are as follows: the vertical field plate introduces a global MIS depletion mechanism in the device off-state, depleting the drift region 21 of the second conductivity type. The field plates in the drift region 21 of the second conductivity type are connected by metal strips 51 to form a bulk equipotential ring to modulate the electric field, making the electric field distribution inside the device uniform. The main innovation is the formation of a low-voltage control circuit MOS in the IGBT cathode region using a compatible process, while simultaneously fabricating a vertical field plate structure on both sides of the low-voltage control circuit using a compatible process, with the gates connected. The same gate voltage controls the two devices, and the vertical field plate acts as a dielectric isolation trench for high and low voltage isolation. The MOS drain is shorted to the IGBT cathode, forming two devices connected in series: a low-voltage NMOS and a high-voltage IGBT. Since they are connected in series, the total current of the devices is the same; the current of the MOS is the same as the current of the IGBT. Therefore, the current of the entire device can be limited by changing the gate voltage of the low-voltage MOS, thereby controlling the parasitic pnpn latch-up and effectively avoiding the latch-up effect of the IGBT device, thus improving the IGBT's operating characteristics. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 1;

[0035] Figure 2 This is a top view of the cell structure of a series dual-gate SOI LIGBT device according to Example 1;

[0036] Figure 3 This is a schematic diagram of the cell structure of a series dual-gate silicon LIGBT device according to Example 2;

[0037] Figure 4 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 3;

[0038] Figure 5 This is a schematic diagram of the cell structure of a series dual-gate silicon LIGBT device according to Example 4;

[0039] Figure 6 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 5;

[0040] Figure 7 This is a top view of the cell structure of a series dual-gate SOI LIGBT device according to Example 5;

[0041] Figure 8 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 6;

[0042] Figure 9 This is a top view of the cell structure of a series dual-gate SOI LIGBT device according to Example 6;

[0043] Figure 10 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 7;

[0044] Figure 11 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 8;

[0045] Figure 12 This is a schematic diagram of the cell structure of a series dual-gate SOI LIGBT device according to Example 9;

[0046] Figures 13(a)-13(j) This is a schematic diagram of the process flow of the device described in Example 1;

[0047] 11 is a semiconductor substrate of the first conductivity type; 12 is a well region of the first conductivity type; 13 is a heavily doped source region of the first conductivity type; 14 is a heavily doped drain region of the first conductivity type; 15 is a heavily doped cathode region of the first conductivity type; 16 is a heavily doped anode region of the first conductivity type; 21 is a drift region of the second conductivity type; 22 is a well region of the second conductivity type; 23 is a heavily doped source region of the second conductivity type; 24 is a heavily doped drain region of the second conductivity type; 25 is a heavily doped cathode region of the second conductivity type; 26 is a heavily doped anode region of the second conductivity type; 31 is a first dielectric oxide layer; 32 is a second dielectric oxide layer; 33 is a third dielectric oxide layer; 34 is a fourth dielectric buried oxide layer; 41 is a polycrystalline silicon electrode; 42 is a control gate polycrystalline silicon electrode; 51 is a metal strip; 52 is a source metal; 53 is a drain metal; 54 is a cathode metal; 55 is an anode metal. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Example 1

[0050] Example 1 describes a series dual-gate SOI LIGBT device, such as Figures 1-2 As shown, it is divided into a low-pressure section and a high-pressure section:

[0051] The high-voltage section includes: a fourth dielectric buried oxide layer 34 located above a first conductivity type semiconductor substrate 11; a second conductivity type drift region 21 located above the fourth dielectric buried oxide layer 34; a first conductivity type well region 12 located to the left of the second conductivity type drift region 21; a second conductivity type well region 22 located to the right of the second conductivity type drift region 21; a first conductivity type heavily doped cathode region 15 and a second conductivity type heavily doped cathode region 25 located within the first conductivity type well region 12; cathode region metal 54 located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25; and anode region metal 55 located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25. The upper surface of a heavily doped anode region 16 of a first conductivity type; the heavily doped anode region 16 of a first conductivity type is located in a well region 22 of a second conductivity type; the second dielectric oxide layer 32 is located above the well region 12 of the first conductivity type, and its left end is in contact with the heavily doped cathode region 25 of the second conductivity type, and its right end is in contact with the drift region 21 of the second conductivity type; the third dielectric oxide layer 33 is located on the upper surface of the drift region 21 of the second conductivity type between the second dielectric oxide layer 32 and the heavily doped anode region 16 of the first conductivity type; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;

[0052] The low-voltage section includes: a first conductivity type well region 12, a first conductivity type heavily doped source region 13, a second conductivity type heavily doped source region 23, and a second conductivity type heavily doped drain region 24 located in the first conductivity type well region 12; a second dielectric oxide layer 32 located above the first conductivity type well region 12, with its left end in contact with the second conductivity type heavily doped source region 23 and its right end in contact with the second conductivity type heavily doped drain region 24; a control gate polysilicon electrode 42 covering the upper surface of the second dielectric oxide layer 32; a third dielectric oxide layer 33 located above the polysilicon electrode 41; a drain metal 53 located on the upper surface of the second conductivity type heavily doped drain region 24; and a source metal 52 located on the upper surfaces of the first conductivity type heavily doped source region 13 and the second conductivity type heavily doped drain region 24.

[0053] The first dielectric oxide layer 31 and the polycrystalline silicon electrode 41 constitute a longitudinal field plate, and the first dielectric oxide layer 31 surrounds the polycrystalline silicon electrode 41. The longitudinal field plate is distributed throughout the entire second conductivity type drift region 21, forming a longitudinal field plate array. The longitudinal field plate is also formed in the cathode region and the source end using the same process as the longitudinal field plate in the drift region. The longitudinal field plate penetrates through the first type conductive well region 12 and the second conductivity type drift region 21 to the fourth dielectric buried oxide layer 34. The longitudinal field plate also penetrates in the z direction and is distributed on both sides of the low voltage region as a dielectric isolation trench. The polycrystalline silicon electrodes 41 on both sides of the low voltage region are grounded. The longitudinal field plates distributed throughout the entire second conductivity type drift region 21 are evenly spaced in the x direction and connected to the metal strip 51 through through holes to form an internal equipotential ring. The horizontal direction from the cathode region to the anode region is the x direction, the downward direction of the depth of the longitudinal field plate is the y direction, and the inward direction perpendicular to the xy plane is the z direction.

[0054] Heavily doped doping concentration greater than 1e18cm -3 .

[0055] The longitudinal field plate is formed simultaneously with the cathode region and the source end longitudinal field plate using the same process, and the depth of the field plate is deeper than the depth of the second conductivity type drift region 21. The longitudinal field plate is in contact with the fourth dielectric buried oxide layer 34.

[0056] The longitudinal and transverse spacing of adjacent longitudinal field plates distributed throughout the second conductivity type drift region 21 are equal; and / or the cross-sectional shape of the longitudinal field plates is rectangular, circular, elliptical, or hexagonal.

[0057] The dielectric isolation trench is located on both sides of the low-voltage MOSFET and extends in the z-direction to provide isolation.

[0058] The longitudinal field plate near the first conductivity type heavily doped source region 13 and the longitudinal field plate between the second conductivity type heavily doped drain region 24 and the first conductivity type heavily doped cathode region 15 are both grounded through metal strip 51.

[0059] In this embodiment, the longitudinal field plate has a square cross-sectional shape, and adjacent columns of longitudinal field plates are arranged alternately. The cathode region and the source end field plate have rectangular cross-sectional shapes, and two columns of longitudinal field plates are arranged parallel to each other in the z-direction.

[0060] Its basic working principle is as follows:

[0061] Taking the first conductivity type semiconductor material as P-type as an example, under the gate bias voltage V gWhen the voltage is 0, the vertical field plate introduces a global MIS depletion mechanism, forming an equipotential ring within the device through metal strips 51 to modulate the electric field, resulting in a uniform electric field distribution inside the device. A low-voltage control circuit MOS is fabricated in the IGBT cathode region using a compatible process, isolated by a dielectric isolation trench. The MOS drain is shorted to the IGBT cathode, and the gates are connected, forming a series-connected low-voltage MOS and high-voltage IGBT. After applying the gate voltage, both the MOS and IGBT turn on. The drain current of the MOS is the same as the anode current of the IGBT. Therefore, the current can be limited by changing the gate voltage, thereby limiting the current of the IGBT device and suppressing the parasitic pnpn latch-up of the IGBT. In summary, the series-connected dual-gate IGBT device proposed in this invention solves the gate runaway problem caused by latch-up due to excessive anode current in the IGBT, improving the device's gate control capability.

[0062] Figure 13 shows a schematic diagram of the process flow of Embodiment 1 of the present invention, which specifically includes the following steps:

[0063] Step 1: Select SOI material, which includes a Si first conductivity type semiconductor substrate 11, a fourth dielectric buried oxide layer 34, and a second conductivity type drift region 21; as shown in Figure 13(a);

[0064] Step 2: Form the groove by photolithography and etching, as shown in Figure 13(b);

[0065] Step 3: Form the first dielectric oxide layer 31 in the tank, as shown in Figure 13(c);

[0066] Step 4: Deposit polycrystalline silicon and etch it onto the silicon plane to form a polycrystalline silicon electrode 41, as shown in Figure 13(d) and Figure 13(e);

[0067] Step 5: Ion implantation of impurities of the first conductivity type and push-junction to form a well region 12 of the first conductivity type; ion implantation of impurities of the second conductivity type and push-junction to form a well region 22 of the second conductivity type, as shown in Figure 13(f);

[0068] Step 6: Grow and form the third dielectric oxide layer 33, and then form the second dielectric oxide layer 32 by etching, as follows. Figure 12 (g);

[0069] Step 7: Deposit and etch polysilicon to form the control gate polysilicon electrode 42, as shown in Figure 13(h);

[0070] Step 8: Implant to form a first conductivity type heavily doped source region 13, a first conductivity type heavily doped cathode region 15, a first conductivity type heavily doped anode region 16, a second conductivity type heavily doped source region 23, a second conductivity type heavily doped drain region 24, and a second conductivity type heavily doped cathode region 25, as shown in Figure 13(i).

[0071] Step 9: Etch the third dielectric oxide layer 33 to form contact holes, then deposit and etch the metal strip 51 to form surface metal strips and metal electrodes, as shown in Figure 13(j).

[0072] It is important to note that:

[0073] In the manufacturing method described above, in step 1, silicon on the N-type insulator can be pushed together by high-energy implantation of an undoped silicon wafer to form a drift region 21 of the second conductivity type.

[0074] In the manufacturing method described above, the first conductive type well 12 and the second conductive type well region 22 obtained by high-energy injection and push-bonding in step 5 can also be formed by multiple high-energy injections and activations of different energies.

[0075] In the manufacturing method described above, all the dielectric oxide layers can be formed by thermal growth or by deposition and etching.

[0076] In the manufacturing method described above, the depth of the longitudinal field plate array of the medium isolation tank and the drift zone can be above the buried oxide layer, on the surface of the buried oxide layer, or inside the buried oxide layer.

[0077] Example 2

[0078] like Figure 3 The diagram shown is a schematic diagram of a series dual-gate SOI LIGBT device structure in Example 2. The difference between this example and Example 1 is that the device is a bulk silicon device instead of an SOI device, and the drift region is formed by high-energy injection push-well. The field plate is uniformly distributed in the second conductivity type drift region 21. The dielectric isolation trench is on both sides of the MOS and inserted into the substrate. Its working principle is basically the same as that of Example 1.

[0079] Example 3

[0080] like Figure 4 The diagram shown is a schematic of a series dual-gate SOI LIGBT device structure according to Embodiment 3. The difference between this example and Embodiment 1 is that a first conductivity type doped layer is implanted in the drift region. This doped layer can be located on the upper surface of the second conductivity type drift region 21, below the third dielectric oxide layer 33, or in a discontinuous structure in the z-direction, etc. The x, y, and z directions are shown in the attached diagram. This structure can assist in the depletion of the drift region while providing holes, enhancing the conductivity modulation effect of the device. Its working principle is basically the same as that of Embodiment 1.

[0081] Example 4

[0082] like Figure 5The diagram shown is a schematic diagram of a series dual-gate bulk silicon LIGBT device structure in Example 4. The difference between this example and Example 1 is that, in addition to using bulk silicon material, the drift region field plate and the dielectric isolation trench of the cathode are both inserted into the substrate. The longitudinal field plate can simultaneously deplete the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21. Its working principle is basically the same as that of Example 1.

[0083] Example 5

[0084] like Figure 6 Figure 7 shows a schematic diagram of a series dual-gate SOI LIGBT device structure in Example 5. The difference between this example and Example 1 is that the longitudinal field plate closest to the IGBT cathode in the drift region of the device extends through the z-direction, blocking holes injected from the collector to the emitter. A large number of holes accumulate on the side of the longitudinal field plate closest to the IGBT cathode in the drift region, further enhancing the conductivity modulation effect of the device and reducing the on-resistance and on-voltage drop. Its working principle is basically the same as that of Example 1. At the same time, the longitudinal field plate closest to the IGBT cathode in the drift region is compatible with the isolation trench process, that is, the depth is the same.

[0085] Example 6

[0086] like Figure 8 , 9 The diagram shows a schematic diagram and top view of the cell region structure of a series dual-gate SOI LIGBT device in Example 6. The difference between this example and Example 1 is that the drain terminal is also formed into a longitudinal field plate through a compatible process. At the same time, when forming the first conductivity type heavily doped anode region 16, the second conductivity type heavily doped anode region 26 is also formed, thus forming a reverse conduction IGBT structure RC-IGBT (Reverse Conducting IGBT) structure. It has bidirectional conduction capability, which can enhance the conductivity modulation effect of the device and shorten the IGBT turn-off time. At the same time, the spacing in the z direction can be controlled to control its snapback effect. Its working principle is basically the same as that of Example 1.

[0087] Example 7

[0088] like Figure 10 The diagram shown is a schematic of a series dual-gate SOI LIGBT device structure according to Example 7. The difference between this example and Example 1 is that by reducing the width of the etched dielectric isolation trench, the oxide layer completely fills the trench during the subsequent oxidation process of the trench wall, and the longitudinal field plate of the cathode region becomes a fully dielectric trench. Its working principle is basically the same as that of Example 1.

[0089] Example 8

[0090] like Figure 11The diagram shown is a schematic of a series dual-gate SOI LIGBT device structure according to Example 8. The difference between this example and Example 1 is that an N-type injection is added to the channel region below the second dielectric oxide layer 32 of the high-voltage LIGBT, making the IGBT normally open, meaning the entire device is controlled by the gate voltage in the low-voltage region. Its working principle is basically the same as in Example 1.

[0091] Example 9

[0092] like Figure 12 The diagram shown is a schematic of a series dual-gate SOI LIGBT device structure in Example 9. The difference between this example and Example 1 is that the LIGBT does not form a channel region through diffusion; that is, the device is an accumulation-type device without an inverting channel, and the entire device is controlled by the low-voltage gate voltage. Its working principle is basically the same as in Example 1.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A series dual-gate LIGBT device, characterized in that... It is divided into a low-voltage section and a high-voltage section: The high-voltage section includes: a fourth dielectric buried oxide layer (34) located above a first conductivity type semiconductor substrate (11); a second conductivity type drift region (21) located above the fourth dielectric buried oxide layer (34); a first conductivity type well region (12) located to the left of the second conductivity type drift region (21); a second conductivity type well region (22) located to the right of the second conductivity type drift region (21); a first conductivity type heavily doped cathode region (15) and a second conductivity type heavily doped cathode region (25) located in the first conductivity type well region (12); a cathode region metal (54) located on the upper surface of the first conductivity type heavily doped cathode region (15) and the second conductivity type heavily doped cathode region (25); and an anode region metal (55) located on the upper surface of the cathode region. The upper surface of the first conductivity type heavily doped anode region (16); the first conductivity type heavily doped anode region (16) is located in the second conductivity type well region (22); the second dielectric oxide layer (32) is located above the first conductivity type well region (12), and its left end is in contact with the second conductivity type heavily doped cathode region (25), and its right end is in contact with the second conductivity type drift region (21); the third dielectric oxide layer (33) is located on the upper surface of the second conductivity type drift region (21) between the second dielectric oxide layer (32) and the first conductivity type heavily doped anode region (16); the control gate polysilicon electrode (42) covers the upper surface of the second dielectric oxide layer (32) and partially extends to the upper surface of the third dielectric oxide layer (33); The low-voltage section includes: a first conductivity type well region (12), a first conductivity type heavily doped source region (13), a second conductivity type heavily doped source region (23), and a second conductivity type heavily doped drain region (24) located in the first conductivity type well region (12); a second dielectric oxide layer (32) located above the first conductivity type well region (12), with its left end in contact with the second conductivity type heavily doped source region (23) and its right end in contact with the second conductivity type heavily doped drain region (24); a control gate polysilicon electrode (42) covering the upper surface of the second dielectric oxide layer (32), and a third dielectric oxide layer (33) located above the polysilicon electrode (41); a drain metal (53) located on the upper surface of the second conductivity type heavily doped drain region (24), and a source metal (52) located on the upper surfaces of the first conductivity type heavily doped source region (13) and the second conductivity type heavily doped drain region (24); The first dielectric oxide layer (31) and the polycrystalline silicon electrode (41) constitute a longitudinal field plate, and the first dielectric oxide layer (31) surrounds the polycrystalline silicon electrode (41). The longitudinal field plate is distributed throughout the second conductivity type drift region (21) to form a longitudinal field plate array. The longitudinal field plate is formed simultaneously in the cathode region and the source end using the same process as the longitudinal field plate in the drift region. The longitudinal field plate penetrates through the first conductivity type trap region (12) and the second conductivity type drift region (21) to the fourth dielectric buried oxide layer (34). The longitudinal field plate also penetrates in the z direction and is distributed on both sides of the low voltage region as a dielectric isolation trench. The polycrystalline silicon electrodes (41) on both sides of the low voltage region are grounded. The longitudinal field plates distributed throughout the second conductivity type drift region (21) are evenly spaced in the x direction and connected to the metal strip (51) through through holes to form an internal equipotential ring. The horizontal direction from the cathode region to the anode region is the x direction, the downward direction of the longitudinal field plate depth is the y direction, and the direction perpendicular to the xy plane and inward is the z direction.

2. The series dual-gate LIGBT device according to claim 1, characterized in that: The longitudinal field plate of the high voltage section is formed simultaneously with the longitudinal field plates of the cathode region and the source end using the same process, and the depth of the longitudinal field plate of the high voltage section is deeper than the depth of the drift region (21) of the second conductivity type. The longitudinal field plate of the high voltage section is in contact with the fourth dielectric buried oxide layer (34); and / or the width of the etched dielectric isolation trench is reduced so that the oxide layer completely fills the trench during the subsequent trench wall oxidation process, and the longitudinal field plate of the cathode region becomes a full dielectric trench.

3. The series dual-gate LIGBT device according to claim 1, characterized in that: The longitudinal and transverse spacing of adjacent longitudinal field plates distributed throughout the second conductivity type drift region (21) are equal; and / or the cross-sectional shape of the longitudinal field plates is rectangular, circular, elliptical, or hexagonal.

4. A series dual-gate LIGBT device according to claim 1, characterized in that: The longitudinal field plate near the first conductivity type heavily doped source region (13) and the longitudinal field plate between the second conductivity type heavily doped drain region (24) and the first conductivity type heavily doped cathode region (15) are both grounded by metal strips (51).

5. A series dual-gate LIGBT device according to claim 1, characterized in that: The longitudinal field plate with isolation function is distributed on both sides of the low voltage control circuit and is connected to the fourth dielectric buried oxide layer (34). The longitudinal field plate simultaneously depletes the first conductivity type semiconductor substrate (11) and the second conductivity type drift region (21). The longitudinal field plate connected to the fourth dielectric buried oxide layer (34) plays the role of high and low voltage isolation.

6. A series dual-gate LIGBT device according to claim 1, characterized in that: The device is an SOI structure or a bulk silicon device, and its dielectric oxide layer is silicon dioxide or a high-k or low-k material; in addition to bulk silicon devices, this device structure is also applied in SiC and GaN semiconductor materials; And / or the low-voltage control circuit is a MOS or a CMOS circuit; the high-voltage part is an N-type lateral insulated gate bipolar transistor (LIGBT), or a P-type lateral insulated gate bipolar transistor (P-LIGBT) formed by compatible processes, or constitutes a CMOS circuit; the device is an enhancement-mode structure or an accumulation-mode structure.

7. A series dual-gate LIGBT device according to claim 1, characterized in that: A first conductivity type doped layer is implanted in the drift region. The doped layer is located on the upper surface of the second conductivity type drift region (21), or below the third dielectric oxide layer (33), or in a discontinuous structure in the z direction. Alternatively, an N-type injection can be added to the channel region below the second dielectric oxide layer (32) of the high-voltage LIGBT, so that the IGBT is normally open, that is, the entire device is controlled by the gate voltage of the low-voltage region. Alternatively, the channel region below the second dielectric oxide layer (32) can be formed without diffusion, i.e., the device has no channel and is an accumulation type device; Or the heavy doping concentration is greater than 1e18cm. -3 .

8. A method for manufacturing a series dual-gate LIGBT device according to any one of claims 1 to 5, characterized in that... Includes the following steps: Step 1: Select SOI material, which includes a first conductivity type semiconductor substrate (11), a fourth dielectric buried oxide layer (34), and a second conductivity type drift region (21). Step 2: Form the grooves using photolithography and etching; Step 3: Form the first dielectric oxide layer (31) in the tank; Step 4: Deposit polycrystalline silicon and etch it onto the silicon plane to form a polycrystalline silicon electrode (41). Step 5: Ion implantation of impurities of the first conductivity type and push-junction to form a well region of the first conductivity type (12); ion implantation of impurities of the second conductivity type and push-junction to form a well region of the second conductivity type (22). Step 6: Grow and form a third dielectric oxide layer (33), and then form a second dielectric oxide layer (32) by etching. Step 7: Deposit and etch polysilicon to form a control gate polysilicon electrode (42); Step 8: Implant to form a first conductivity type heavily doped source region (13), a first conductivity type heavily doped cathode region (15), a first conductivity type heavily doped anode region (16), a second conductivity type heavily doped source region (23), a second conductivity type heavily doped drain region (24), and a second conductivity type heavily doped cathode region (25); Step 9: Etch the third dielectric oxide layer (33) to form contact holes, then deposit and etch the metal strip (51) to form surface metal strips and metal electrodes.

9. A method for manufacturing a series dual-gate LIGBT device according to claim 8, characterized in that: The second conductivity type drift region (21) in step 1 is formed by implanting N-type dopant and pushing the junction; and / or the first conductivity type well region (12) and the second conductivity type well region (22) obtained by implantation and pushing the junction in step 5 are formed by multiple implantations and activations with different energies.

10. A method for manufacturing a series dual-gate LIGBT device according to claim 8, characterized in that: When the first conductivity type heavily doped anode region (16) is formed, the second conductivity type heavily doped anode region (26) is formed at the same time, that is, the reverse conduction type IGBT structure is formed; And / or the longitudinal field plate closest to the IGBT cathode in the second conductivity type drift region (21) of the device is penetrated in the z direction to block the holes injected from the collector into the emitter.

Images