Semiconductor devices and methods for forming semiconductor devices

Abstract

Various embodiments of the present invention pertain to a two-dimensional carrier gas (2DCG) semiconductor device, which includes an ohmic source / drain electrode having a plurality of protrusions separated by gaps and projecting from the bottom surface of the ohmic source / drain electrode. The ohmic source / drain electrode is located on a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Furthermore, the ohmic source / drain electrode is separated from another ohmic source / drain electrode, also located on the semiconductor film. The semiconductor film includes a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction. The channel layer houses the 2DCG, which extends along the heterojunction and is ohmically coupled to the ohmic source / drain electrode and the other ohmic source / drain electrode. A gate electrode is located on the semiconductor film between the ohmic source / drain electrode and the other source / drain electrode. According to other embodiments of this application, a method for forming a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] Over the past few decades, silicon-based semiconductor devices have become the standard. However, semiconductor devices based on alternative materials are attracting increasing attention due to their superior performance compared to silicon-based devices. For example, semiconductor devices based on gallium nitride and other group III-V semiconductor materials are gaining popularity due to their increased channel mobility and enhanced thermal performance compared to silicon-based devices. Summary of the Invention

[0003] According to one embodiment of this application, a semiconductor device is provided, comprising: a semiconductor film including a channel layer and a barrier layer, wherein the channel layer and the barrier layer are vertically stacked and contact at a heterojunction; a two-dimensional carrier gas (2DCG) located in the channel layer and extending laterally along the heterojunction; a first source / drain electrode and a second source / drain electrode located on the two-dimensional carrier gas and ohmically coupled to the two-dimensional carrier gas; and a gate electrode located on the semiconductor film and laterally located between the first source / drain electrode and the second source / drain electrode; wherein the first source / drain electrode has a plurality of first protrusions protruding from the bottom surface of the first source / drain electrode into the semiconductor film.

[0004] According to another embodiment of this application, a semiconductor device is provided, comprising: a channel layer; a barrier layer stacked perpendicularly to the channel layer and in direct contact with the channel layer; a two-dimensional carrier gas (2DCG) located in the channel layer and extending laterally along the interface where the barrier layer and the channel layer are in direct contact; a first source electrode / drain electrode and a second source electrode / drain electrode located on the two-dimensional carrier gas and ohmically coupled to the two-dimensional carrier gas; and a gate electrode located on the two-dimensional carrier gas and laterally located between the first source electrode / drain electrode and the second source electrode / drain electrode; wherein the first source electrode / drain electrode has a first vertical spacing and a second vertical spacing from the two-dimensional carrier gas, wherein the second vertical spacing is greater than the first vertical spacing, and wherein the first source electrode / drain electrode has a second vertical spacing continuously extending from a first side of the first source electrode / drain electrode facing the second source electrode / drain electrode to a second side of the first source electrode / drain electrode opposite to the first side.

[0005] According to another embodiment of this application, a method for forming a semiconductor device is provided, the method comprising: forming a semiconductor film including a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction, wherein a two-dimensional carrier gas (2DCG) is located in the channel layer and extends laterally along the heterojunction; selectively performing a first etching on the semiconductor film to form a plurality of first-level trenches, wherein the first-level trenches have a periodic pattern; forming a first source / drain electrode and a second source / drain electrode, wherein the first source / drain electrode and the second source / drain electrode are laterally spaced and ohmically coupled to the two-dimensional carrier gas, and wherein the first source / drain electrode fills the plurality of first-level trenches; and forming a gate electrode on the semiconductor film, the gate electrode being laterally located between the first source / drain electrode and the second source / drain electrode.

[0006] Embodiments of this application provide ohmic electrodes for two-dimensional carrier gas (2DCG) semiconductor devices. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 Cross-sectional views of some embodiments of a two-dimensional carrier gas (2DCG) semiconductor device are shown. The 2DCG semiconductor device includes an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode.

[0009] Figure 2 It shows Figure 1 Some embodiments of the 2DCG semiconductor device along Figure 1 A top view of line A.

[0010] Figures 3A to 3F It shows Figure 2 A top view of some alternative embodiments of the 2DCG semiconductor device.

[0011] Figure 4 It shows Figure 1 Enlarged cross-sectional views of some embodiments of the 2DCG semiconductor device.

[0012] Figures 5A to 5D It shows Figure 1 Cross-sectional views of some alternative embodiments of the 2DCG semiconductor device.

[0013] Figure 6Cross-sectional views of some embodiments of a vertical 2DCG semiconductor device are shown. The vertical 2DCG semiconductor device includes an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of the ohmic source / drain electrode.

[0014] Figures 7A to 7C It shows Figure 6 Cross-sectional views of some alternative embodiments of the vertical 2DCG semiconductor device.

[0015] Figure 8A and Figure 8B Various cross-sectional views of some embodiments of a multi-channel 2DCG semiconductor device are shown. The multi-channel 2DCG semiconductor device includes an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode.

[0016] Figure 9A and Figure 9B It shows Figure 8A and Figure 8B Various cross-sectional views of some alternative embodiments of multi-channel 2DCG semiconductor devices.

[0017] Figures 10 to 13 A series of cross-sectional views are shown of some embodiments of a method for forming a 2DCG semiconductor device, the 2DCG semiconductor device including an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode.

[0018] Figures 14 to 16 It shows Figures 10 to 13 A series of cross-sectional views of some alternative embodiments of the method.

[0019] Figure 17 It shows Figures 10 to 13 Block diagrams of some embodiments of the method.

[0020] Figures 18 to 23 A series of cross-sectional views are shown of some embodiments of a method for forming a vertical 2DCG semiconductor device, which includes an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode.

[0021] Figures 24 to 27 A series of cross-sectional views are shown of some embodiments of a multi-channel 2DCG semiconductor device, which includes an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0024] A two-dimensional carrier gas (2DCG) semiconductor device may include a semiconductor film, a 2DCG, a pair of ohmic source / drain electrodes, and a gate electrode. The semiconductor film includes a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction. The 2DCG is located in the channel layer and extends along the heterojunction. The ohmic source / drain electrodes are ohmically coupled to the 2DCG and recessed into the top of the semiconductor film. Furthermore, the ohmic source / drain electrodes are spaced apart along the length of the 2DCG. The gate electrode is located on top of the semiconductor film and between the source / drain electrodes.

[0025] The formation of the ohmic source / drain electrode may involve etching a semiconductor film to form a single cuboid groove extending across the width of the 2DCG and subsequently filling the groove with an ohmic metal. However, by removing material from the semiconductor film, etching reduces the density of the 2DCG directly beneath the groove, and thus increases the resistance of the 2DCG directly beneath the groove. Because the groove is cuboid in shape and extends across the width of the 2DCG, the increased resistance directly beneath the groove may impede current flow through the ohmic source / drain electrode and may limit current flow to a single edge of the ohmic source / drain electrode facing another ohmic source / drain electrode. Therefore, the effective ohmic contact area can be small. A small effective ohmic contact area can lead to current congestion, thereby limiting heat generation to a smaller area and potentially increasing the likelihood of device failure. Furthermore, a small effective ohmic contact area can result in high contact resistance from the ohmic source / drain electrode to the 2DCG.

[0026] To reduce contact resistance, the depth of the groove can be increased. However, if the depth is too large, it may damage the 2DCG directly beneath the groove, increasing contact resistance. Furthermore, etching uniformity decreases with increasing depth and may exacerbate inherent non-uniformities in etching from wafer center to wafer edge, from batch to batch, and from wafer to wafer. This, in turn, can lead to increased non-uniformity in contact resistance and potentially reduce the batch manufacturing yield of 2DEG semiconductor devices. Moreover, semiconductor films can have large band gaps and therefore high resistance, making contact resistance highly sensitive to non-uniformity in etching.

[0027] Various embodiments of the present invention relate to a 2DCG semiconductor device, which includes an ohmic source / drain electrode having a plurality of protrusions separated by gaps and projecting from the bottom surface of the ohmic source / drain electrode. The ohmic source / drain electrode is located on a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Furthermore, the ohmic source / drain electrode is separated from another ohmic source / drain electrode, also located on the semiconductor film. The semiconductor film includes a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction. The channel layer accommodates the 2DCG extending along the heterojunction and is ohmically coupled to the ohmic source / drain electrode and the other ohmic source / drain electrode. A gate electrode is located on the semiconductor film between the ohmic source / drain electrode and the other source / drain electrode.

[0028] Because the vertical spacing between the 2DCG and the ohmic source / drain electrodes is larger at the gap than directly below the protrusion, the density of the 2DCG is greater directly below the gap than directly below the protrusion. Therefore, the resistance of the 2DCG is smaller directly below the gap than directly below the protrusion. Since the gap can span the ohmic source / drain electrodes and extend around the protrusion, the smaller resistance directly below the gap facilitates current flow from the edges of the protrusion on multiple sides of the ohmic source / drain electrodes, and thus the effective ohmic contact area can be larger.

[0029] A larger effective ohmic contact area reduces current congestion and distributes current across the ohmic source / drain electrodes. Reduced current congestion and distributed current increase the area over which heat generated during the operation of the 2DCG semiconductor device can be dissipated, improving its thermal performance and thus reliability. Furthermore, a larger effective ohmic contact area results in lower contact resistance from the ohmic source / drain electrodes to the 2DCG.

[0030] Due to the larger effective ohmic contact area, the depth to which the protrusion extends into the semiconductor film can be reduced while still maintaining low contact resistance. This reduced depth, in turn, increases etching uniformity while forming grooves within which the protrusion forms. Furthermore, due to the larger vertical spacing at the gaps, and because etching is not performed at the gaps, the current directly below the gaps is minimally or unaffected by etching non-uniformity. Because the current is minimally or unaffected by non-uniformity, the contact resistance is also minimally affected by non-uniformity. This increases yield.

[0031] refer to Figure 1 A cross-sectional view 100 of some embodiments of a 2DCG semiconductor device is provided, which includes multiple ohmic source / drain electrodes 102 having individual multiple protrusions 102p. The 2DCG semiconductor device can be, for example, a group III nitride device and / or a depletion-type high electron mobility transistor (D-HEMT). However, other suitable device types are also possible.

[0032] Ohmic source / drain electrodes 102 are located on the semiconductor film 104 and are laterally spaced. Furthermore, the ohmic source / drain electrodes 102 are ohmically coupled to 2DCG 106 in the semiconductor film 104. Protrusions 102p are separated by gaps 108 and protrude from the bottom surface 102bs of the ohmic source / drain electrodes 102 into the semiconductor film 104, the bottom surface 102bs being flush with or approximately flush with the top surface of the semiconductor film 104. In an alternative embodiment, the bottom surface 102bs is raised or recessed relative to the top surface.

[0033] Semiconductor film 104 includes a channel layer 110 and a barrier layer 112. The channel layer 110 is located below the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction, thus having a different band gap than the barrier layer 112. Furthermore, the channel layer 110 is spaced apart from the ohmic source / drain electrode 102 by the barrier layer 112. The barrier layer 112 is polarized, so that positive charges are offset towards the bottom surface of the barrier layer 112, while negative charges are offset towards the top surface of the barrier layer 112. Polarization can be caused, for example, by spontaneous and / or piezoelectric polarization effects.

[0034] Because the barrier layer 112 is polarized, 2DCG 106 is formed in the channel layer 110. 2DCG 106 extends along the heterojunction and has a high concentration of mobile electrons. Due to the high concentration of mobile electrons, 2DCG 106 is conductive and can also be referred to as two-dimensional electron gas (2DEG) 106e.

[0035] Because the vertical spacing between 2DCG 106 and the ohmic source / drain electrode 102 is larger at gap 108 than directly below protrusion 102p, the density of 2DCG 106 is greater directly below gap 108 than directly below protrusion 102p. Therefore, the resistance of 2DCG 106 is smaller directly below gap 108 than directly below protrusion 102p. This is better seen below (see example...). Figure 2 The gap 108 can extend laterally across the ohmic source / drain electrode 102 and is laterally located around the protrusion 102p. Therefore, the small resistance directly below the gap 108 can facilitate current flow from the edges of the protrusion 102p on multiple sides of the ohmic source / drain electrode 102, and thus the effective ohmic contact area 114 of the ohmic source / drain electrode 102 can be large.

[0036] A larger effective ohmic contact area 114 reduces current congestion and distributes current across the ohmic source / drain electrode 102. Reduced current congestion and distributed current increase the area over which heat generated during operation of the 2DCG semiconductor device can be dissipated, improving thermal performance and thus reliability. Furthermore, a larger effective ohmic contact area 114 results in lower contact resistance from the ohmic source / drain electrode 102 to the 2DCG 106.

[0037] Due to the larger effective ohmic contact area 114, the depth Dp into which the protrusion 102p extends in the semiconductor film 104 can be reduced while still maintaining low contact resistance. Etching uniformity typically decreases with increasing depth and typically increases with decreasing depth. The reduced depth can further increase etching uniformity while forming grooves within which the protrusion 102p is formed. For example, etching uniformity can increase from wafer center to wafer edge, from batch to batch, and from wafer to wafer. Furthermore, due to the larger vertical spacing at gap 108, and because etching is not performed at gap 108, the current directly below gap 108 is minimally affected by non-uniformity in etching. Because the current is minimally affected by non-uniformity, the contact resistance is also minimally affected by non-uniformity, and yield can be increased.

[0038] Continue to refer to Figure 1The semiconductor film 104 also includes a buffer layer 116. The buffer layer 116 separates the channel layer 110 and the barrier layer 112 from the substrate 118 beneath the semiconductor film 104. Furthermore, the buffer layer 116 buffers and / or transitions between differences in lattice constant, crystal structure, coefficient of thermal expansion, other suitable parameters, or any combination thereof from the substrate 118 to the channel layer 110. By buffering and / or transitioning between these differences, the crystal quality of the channel layer 110 and the barrier layer 112 can be higher, and / or the stress on the channel layer 110 and the barrier layer 112 can be lower. For example, this can enhance the performance of the 2DCG semiconductor device and / or reduce its failure rate.

[0039] Gate electrode 120 is located on semiconductor film 104, laterally positioned between ohmic source / drain electrodes 102. During use of the 2DCG semiconductor device, gate electrode 120 is selectively biased to generate an electric field that controls the continuity of the 2DCG 106 from the first ohmic source / drain electrode 102a to the second ohmic source / drain electrode 102b. For example, when gate electrode 120 is biased with a voltage greater than a threshold voltage, gate electrode 120 can generate an electric field that depletes a portion of the underlying mobile carriers in the 2DCG 106 and disrupts continuity.

[0040] In some embodiments, the semiconductor film 104 is or comprises a group III-V semiconductor material or a group II-VI semiconductor material. In other embodiments, the semiconductor film 104 is or comprises some other suitable semiconductor material for 2DCG semiconductor devices.

[0041] In some embodiments, the channel layer 110 is or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable group III-V materials, or any combination thereof. In some embodiments, the channel layer 110 is or includes a binary group III-V material and / or includes the same elements as the buffer layer 116. For example, the channel layer 110 and the buffer layer 116 may be or include gallium nitride. In some embodiments, the channel layer 110 is undoped.

[0042] In some embodiments, the barrier layer 112 is or comprises aluminum gallium nitride (e.g., AlGaN), indium aluminum nitride (e.g., InAlN), aluminum nitride (e.g., AlN), aluminum gallium arsenide (e.g., AlGaAs), indium aluminum arsenide (e.g., InAlAs), indium gallium arsenide (e.g., InGaAs), some other suitable III-V materials, or any combination thereof. In some embodiments, the barrier layer 112 is or comprises a ternary III-V material and / or is undoped. In some embodiments, the barrier layer 112 is aluminum gallium nitride, and the channel layer 110 is gallium nitride.

[0043] In some embodiments, the buffer layer 116 is or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable III-V materials, or any combination thereof.

[0044] In some embodiments, substrate 118 is or includes silicon, sapphire, some other suitable crystalline material, or any combination thereof. In at least some embodiments where semiconductor film 104 is or includes a III-V material, substrate 118 does not contain a III-V semiconductor material. In some embodiments, substrate 118 is a bulk semiconductor substrate and / or a semiconductor wafer.

[0045] In some embodiments, the ohmic source / drain electrode 102 is or includes titanium, aluminum, nickel, gold, some other suitable metal, or any combination thereof. In some embodiments, each ohmic source / drain electrode 102 is or includes a four-layer stack, comprising a titanium layer, an aluminum layer above the titanium layer, a nickel layer above the aluminum layer, and a gold layer above the nickel layer. In other embodiments, each ohmic source / drain electrode 102 includes a two-layer stack, comprising a titanium layer and an aluminum layer above the titanium layer.

[0046] Each ohmic source / drain electrode 102 has a first vertical spacing and a second vertical spacing with respect to the 2DCG 106 and / or the heterojunction. The first vertical spacing is located directly below the protrusion 102p, and the second vertical spacing is located at the gap 108 and is larger than the first vertical spacing. In some embodiments, as will be better seen below (see, for example...) Figure 2 The gap 108 may extend laterally across the ohmic source / drain electrode 102. Therefore, in some embodiments, each source / drain electrode 102 may have a second vertical spacing that is continuous from a first side (or sidewall) of the source / drain electrode facing another source / drain electrode to a second side (or sidewall) of the source / drain electrode opposite to the first side (or sidewall). Similarly, each ohmic source / drain electrode 102 has a first height and a second height at the protrusion 102p and the gap 108, respectively. The first height is at the protrusion 102p, and the second height is at the gap 108 and is less than the first height. In some embodiments, each source / drain electrode 102 may have a second height that is continuous from a first side (or sidewall) of the source / drain electrode facing another source / drain electrode to a second side (or sidewall) of the source / drain electrode opposite to the first side (or sidewall).

[0047] In some embodiments, the protrusions 102p of the ohmic source / drain electrodes (e.g., the first ohmic source / drain electrode 102a or the second ohmic source / drain electrode 102b) collectively have a larger surface area than a single cuboid protrusion occupying the same area. "Same area" means that the two-dimensional (2D) projections of the single cuboid protrusions onto the top surface of the substrate 118 have the same or substantially the same dimensions (e.g., width and length) and occupy the same or substantially the same area as the 2D projections of the protrusions 102p onto the top surface of the substrate 118.

[0048] In some embodiments, the gate electrode 120 is or includes nickel, gold, platinum, iridium, titanium nitride, aluminum copper, palladium, some other suitable metals and / or metallic materials, or any combination thereof. For example, the gate electrode 120 may be a multilayer nickel / gold stack, a multilayer platinum / gold stack, a multilayer palladium / gold stack, a multilayer iridium / gold stack, a multilayer titanium nitride / aluminum copper / titanium nitride stack, or some other suitable multilayer stack.

[0049] refer to Figure 2 along Figure 1 Line A provides Figure 1 Top view 200 of some embodiments of the 2DCG semiconductor device. Note that... Figure 1 The cross-sectional view 100 can, for example, be along... Figure 2 Line B is cut off. However, other suitable locations are also possible. Additionally, note that the ohmic source / drain electrode 102 is located at... Figure 1 The portion above the protrusion 102p is shown in dashed lines.

[0050] The protrusions 102p of each ohmic source / drain electrode 102 span the ohmic source / drain electrode distribution and are arranged in multiple rows and columns. Note that Figure 2 The rows in the middle extend from left to right, and Figure 2 The columns extend from top to bottom. The protrusions 102p of each ohmic source / drain electrode 102 are arranged in six rows and three columns. However, in an alternative embodiment, the protrusions 102p of each ohmic source / drain electrode 102 may be arranged in some other suitable number of rows and / or some other suitable number of columns. Furthermore, the protrusions 102p are arranged in a periodic pattern and have a square layout. In an alternative embodiment, the protrusions 102p have some other suitable layouts.

[0051] Because of the vertical spacing between 2DCG 106 and the ohmic source / drain electrode 102 (see, for example, Figure 1The density of 2DCG 106 is greater at gap 108 than directly below protrusion 102p, so the density of 2DCG 106 is greater directly below gap 108 than directly below protrusion 102p. Furthermore, the density of 2DCG 106 is unaffected or minimally affected by etching non-uniformity to form the grooves that form protrusion 102p within it. Therefore, current 202 can flow laterally across the ohmic source / drain electrode 102 and laterally around protrusion 102p, and can be unaffected or minimally affected by etching non-uniformity to form the grooves. As described above, this reduces current congestion, reduces contact resistance, and increases yield.

[0052] refer to Figures 3A to 3F Provided Figure 2 Top views 300A-300F of some alternative embodiments of the 2DCG semiconductor device.

[0053] exist Figure 3A In the column, the protrusions 102p are staggered along the rows, and the even-numbered columns are offset relative to the odd-numbered columns in the direction of column extension. Furthermore, each even-numbered column has a different number of protrusions 102p than the odd-numbered columns. In an alternative embodiment, each even-numbered column has the same number of protrusions 102p as the odd-numbered columns. Note that in... Figure 3A In the middle, the column number for the ohmic source / drain electrode 102 is separate and increases from left to right, starting from the beginning.

[0054] exist Figure 3B In the middle, the protrusion 102p and Figure 3A Similar to the one in [the text], except that the protrusions 102p have a hexagonal layout. Furthermore, the number of protrusions 102p is [the same as in the text]. Figure 3A Unlike the odd-numbered columns, each column in the even-numbered columns has the same number of spikes, 102p.

[0055] exist Figure 3C In the middle, the protrusion 102p and Figure 3A It is the same as the one in the picture, except that the protrusion 102p has a circular layout.

[0056] exist Figure 3D In the middle, the protrusion 102p and Figure 3A Similar to the one in [the text], except that the protrusions 102p have a triangular layout. Furthermore, the number of protrusions 102p is [the same as in the text]. Figure 3A The differences.

[0057] exist Figure 3E In the middle, the protrusion 102p and Figure 3A Similar to the one in [the text], except that the protrusions 102p have a rhomboid layout. Furthermore, the number of protrusions 102p is [the same as in the text]. Figure 3A The differences.

[0058] exist Figure 3FIn the first ohmic source / drain electrode 102a, the protrusion 102p has a different arrangement than the protrusion 102p of the second ohmic source / drain electrode 102b. The protrusion 102p of the first ohmic source / drain electrode 102a has the following arrangement: Figure 2 The layout in the middle, and the protrusion 102p of the second ohmic source / drain electrode 102b has as Figure 3C The layout in the image. In an alternative embodiment, the protrusion 102p of the first ohmic source / drain electrode 102a has the following characteristics: Figure 3A , Figure 3B , Figure 3D and Figure 3E In any of the layouts or some other suitable layouts, and / or the protrusion 102p of the second ohmic source / drain electrode 102b has as follows Figure 3A , Figure 3B , Figure 3D and Figure 3E Any of the layouts or some other suitable layouts.

[0059] Although Figure 2 and Figures 3A to 3F A specific number of protrusions 102p is shown, but more or fewer protrusions 102p are possible. Although Figure 2 and Figures 3A to 3F It is shown as having a specific number of rows and columns, but more or fewer rows and / or more or fewer columns are possible. Although Figure 3A and Figures 3C to 3E as well as Figure 3F The second ohmic source / drain electrode 102b is shown as having a different number of protrusions 102p per column in even-numbered columns compared to odd-numbered columns, but each column in even-numbered columns may optionally have the same number of protrusions 102p as the odd-numbered columns. Although Figure 2 and Figure 3B as well as Figure 3F The first ohmic source / drain electrode 102a is shown as having the same number of protrusions 102p per column as the odd columns, but the even columns may optionally have a different number of protrusions 102p per column than the odd columns.

[0060] refer to Figure 4 Provided Figure 1 The box within BX Figure 1 An enlarged cross-sectional view 400 shows a portion of an embodiment of a 2DCG semiconductor device. As shown, the protrusion 102p extends therein to a barrier layer 112, which is a multilayer film. In an alternative embodiment, the barrier layer 112 is a single-layer film. Furthermore, in an alternative embodiment, the barrier layer 112 is a multilayer film having more or fewer layers.

[0061] In some embodiments of the 2DCG semiconductor device based on gallium nitride, the barrier layer 112 includes: 1) an aluminum nitride (e.g., AlN) layer 112a; 2) a first undoped aluminum gallium nitride (e.g., u-Al) layer located on the aluminum nitride layer 112a. 0.25 3) An n-doped aluminum gallium nitride (e.g., n-Al) layer 112b on top of the first undoped aluminum gallium nitride layer 112b. 0.25 GaN layer 112c; 4) and a second undoped aluminum gallium nitride (e.g., u-Al) layer located above the n-doped aluminum gallium nitride layer 112c. 0.25 GaN layer 112d. In at least some of these embodiments, the channel layer 110 is or includes undoped gallium nitride (e.g., u-GaN). Although specific materials have been identified above for the channel layer 110 and the barrier layer 112, other suitable materials are possible.

[0062] In some embodiments, the aluminum nitride layer 112a, the first undoped aluminum gallium nitride layer 112b, and the second undoped aluminum gallium nitride layer 112d have a thickness of about 1 nanometer, while the n-doped aluminum gallium nitride layer 112c has a thickness of about 8 nanometers, and the channel layer 110 has a thickness of about 10 nanometers. In alternative embodiments, any layer or combination of layers in the barrier layer 112 (e.g., 112a-112d) may have some other suitable thickness, and / or the channel layer 110 may have some other suitable thickness. In some embodiments, the doping concentration of the n-doped aluminum gallium nitride layer 112c is [value missing] per cubic centimeter (e.g., cm³). -3 Approximately 5x10 18 One atom. In an alternative embodiment, the doping concentration is some other suitable value.

[0063] refer to Figures 5A to 5D Provided Figure 1 Cross-sectional views 500A-500D of some alternative embodiments of the 2DCG semiconductor device.

[0064] exist Figure 5A In the semiconductor film 104, the bottom surface 102bs of the ohmic source / drain electrode 102 is recessed to a depth Dp2 relative to the top surface of the semiconductor film 104. This recess increases the effective ohmic contact area 114 and thus reduces the contact resistance from the ohmic source / drain electrode 102 to the 2DCG 106.

[0065] exist Figure 5BIn this embodiment, the semiconductor film 104 further includes a capping layer 502 located above the channel layer 110 and the barrier layer 112. The capping layer 502 can, for example, be used to facilitate the formation of an ohmic contact from the ohmic source / drain electrode 102 to the 2DCG 106. Furthermore, for example, the capping layer 502 can be used to adjust or otherwise enhance the density and / or carrier mobility at the 2DCG 106. In at least some embodiments, this is achieved by doping the capping layer 502 with impurities to provide mobile carriers to the 2DCG 106.

[0066] In some embodiments, capping layer 502 is or includes gallium nitride (e.g., GaN), indium gallium nitride (e.g., InGaN), some other suitable III-V materials, or any combination thereof. In some embodiments, capping layer 502 is the same material as channel layer 110. In some embodiments, capping layer 502 is undoped. In other embodiments, capping layer 502 is doped. In some embodiments, capping layer 502 is the same material as channel layer 110, but channel layer 110 is undoped, and capping layer 502 is doped. In embodiments where capping layer 502 is doped, capping layer 502 is doped with an n-type donor impurity to provide mobile electrons to 2DCG 106, since 2DCG 106 is 2DEG 106e. For example, in at least some embodiments where semiconductor film 104 is based on gallium nitride, capping layer 502 may be doped with silicon, carbon, or some other suitable type of n-type donor impurity to provide mobile electrons.

[0067] exist Figure 5C In this configuration, the channel layer 110 is located above the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction. Furthermore, the barrier layer 112 is spaced apart from the ohmic source / drain electrode 102 by the channel layer 110. The barrier layer 112 is polarized, so that positive charges are offset towards the bottom surface of the barrier layer 112, and negative charges are offset towards the top surface of the barrier layer 112. Polarization can be caused, for example, by spontaneous and / or piezoelectric polarization effects.

[0068] Because the barrier layer 112 is polarized, 2DCG 106 is formed in the channel layer 110. 2DCG 106 extends along the heterojunction and has a high concentration of mobile holes. Due to the high concentration of mobile holes, 2DCG 106 is conductive and can also be referred to as two-dimensional hole gas (2DHG) 106h.

[0069] exist Figure 5D In China, 2DCG semiconductor devices and Figure 5C Like the one in it, besides it also includes Figure 5BThe capping layer 502. In embodiments where the capping layer 502 is doped, it is doped with a p-type acceptor impurity to provide mobile holes to the 2DCG 106, since the 2DCG 106 is a 2DHG 106h. For example, in at least some embodiments where the semiconductor film 104 is based on gallium nitride, the capping layer 502 may be doped with magnesium or some other suitable type of p-type acceptor impurity to provide mobile holes.

[0070] refer to Figure 6 A cross-sectional view 600 of some embodiments of a vertical 2DCG semiconductor device is provided, the vertical 2DCG semiconductor device including a plurality of ohmic source / drain electrodes 102 having a plurality of protrusions 102p projecting from the bottom of an ohmic source / drain electrode 102. The vertical 2DCG semiconductor device, as... Figure 1 The 2DCG semiconductor device, except for the third ohmic source / drain electrode 102c, is located below the gate electrode 120, on the underside of the semiconductor film 104. Furthermore, the buffer layer 116 is omitted (see, for example...). Figure 1 ) and substrate 118 (see example) Figure 1 The semiconductor film 104 includes a drift layer 602 and a current blocking layer (CBL) 604 that separate the third ohmic source / drain electrode 102c from the channel layer 110 and the barrier layer 112. The CBL 604 is located above the drift layer 602 and inserted into the top of the drift layer 602. The drift layer 602 is doped and extends through a hole 606 in the CBL 604 to the channel layer 110. The hole 606 is located above the third ohmic source / drain electrode 102c and below the gate electrode 120.

[0071] During the use of the 2DCG semiconductor device, the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b operate as source electrodes, while the third ohmic source / drain electrode 102c operates as drain electrodes, and vice versa. Furthermore, depending on whether the gate electrode 120 is biased by a voltage exceeding a threshold voltage, current selectively flows from the drain electrode through the via 606 to the source electrode. When the gate electrode 120 is biased by a voltage exceeding the threshold voltage, the gate electrode 120 can generate an electric field that depletes a portion of the 2DCG 106 carrying mobile carriers below, preventing current from flowing from the drain electrode to the source electrode. Additionally, the 2DCG 106 can be continuous from the first ohmic source / drain electrode 102a to the second ohmic source / drain electrode 102b, and current can flow through it. The 2DCG semiconductor device can be, for example, a vertical HEMT or some other suitable vertical device.

[0072] The breakdown voltage is increased by increasing the channel length through the vertical dimension. Increasing the thickness of the drift layer 602 increases the breakdown voltage, while decreasing the thickness decreases it. Current flowing laterally through the via 606 has multiple parallel paths to the source electrode. Therefore, the on-resistance is reduced, and the current carrying capacity is increased. The capacity of the current flowing vertically through the via 606 is proportional to the coverage size of the via 606, which is proportional in two lateral dimensions rather than just one. Because the chip area is defined in two lateral dimensions, and the coverage size of the via 606 is proportional in both lateral dimensions, the capacity (e.g., current density) of the current flowing vertically per unit chip area can be high.

[0073] In some embodiments, the third ohmic source / drain electrode 102c is or includes titanium, aluminum, nickel, gold, some other suitable metal, or any combination thereof. In some embodiments, the third ohmic source / drain electrode 102c is or includes a four-layer stack comprising a titanium layer, an aluminum layer beneath the titanium layer, a nickel layer beneath the aluminum layer, and a gold layer beneath the nickel layer. In some embodiments, the third ohmic source / drain electrode 102c is associated with, except that it has no protrusions, the third ohmic source / drain electrode 102c. Figure 1 The first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b are described as being the same.

[0074] In some embodiments, the drift layer 602 is or comprises gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable III-V materials, or any combination thereof. In some embodiments, the drift layer 602 is or comprises the same material as the channel layer 110. In at least some embodiments, the drift layer 602 is doped with an n-type donor impurity. For example, in at least some embodiments of the semiconductor film 104 based on gallium nitride, the drift layer 602 may be doped with silicon, carbon, or some other suitable type of n-type donor impurity.

[0075] In some embodiments, CBL 604 is or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable III-V materials, or any combination thereof. In some embodiments, CBL 604 is or includes the same material as drift layer 602. In some embodiments, CBL 604 is doped. In at least some embodiments where CBL 604 is doped, CBL 604 is doped with p-type acceptor impurities, and therefore with impurities of the opposite type to those in drift layer 602. For example, in at least some embodiments where semiconductor film 104 is based on gallium nitride, CBL 604 may be doped with magnesium or some other suitable type of p-type acceptor impurity.

[0076] refer to Figures 7A to 7C Provided Figure 6 Cross-sectional views 700A-700C of some alternative embodiments of the vertical 2DCG semiconductor.

[0077] exist Figure 7A In the semiconductor film 104, the bottom surface 102bs of the ohmic source / drain electrode 102 is recessed to a depth Dp2 relative to the top surface of the semiconductor film 104. This recess increases the effective ohmic contact area 114 and thus reduces the contact resistance from the ohmic source / drain electrode 102 to the 2DCG 106.

[0078] exist Figure 7B In this embodiment, the third ohmic source / drain electrode 102c includes a plurality of protrusions 102p. The protrusions 102p of the third ohmic source / drain electrode 102c are described in the same way as the protrusions 102p of the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b. Therefore, the protrusions 102p of the third ohmic source / drain electrode 102c increase the effective ohmic contact area 114 of the third ohmic source / drain electrode 102c and reduce the contact resistance of the third ohmic source / drain electrode 102c. Furthermore, the protrusions 102p of the third ohmic source / drain electrode 102c protrude from the top surface 102ts of the third ohmic source / drain electrode 102c into the semiconductor film 104, the top surface 102ts being flush with or approximately flush with the bottom surface of the semiconductor film 104. In an alternative embodiment, the top surface 102ts is raised or recessed relative to the bottom surface.

[0079] exist Figure 7C In this structure, the channel layer 110 is located above the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction. Furthermore, the barrier layer 112 is spaced apart from the ohmic source / drain electrode 102 by the channel layer 110. The barrier layer 112 is polarized, so positive charges are offset towards the bottom surface of the barrier layer 112, and negative charges are offset towards the top surface of the barrier layer 112. Polarization can be caused, for example, by spontaneous and / or piezoelectric polarization effects. Because the barrier layer 112 is polarized, a 2DCG 106 is formed in the channel layer 110. The 2DCG 106 extends along the heterojunction and has a high concentration of mobile holes. Due to the high concentration of mobile holes, the 2DCG 106 is conductive and can also be referred to as a 2DHG 106h.

[0080] refer to Figure 8A and Figure 8B Various cross-sectional views 800A, 800B are provided for some embodiments of a multi-channel 2DCG semiconductor device, which includes a pair of ohmic source / drain electrodes 102 having individual plurality of protrusions 102p. Figure 8B Corresponding to along Figure 8AThe cross-sectional view of line C in the diagram is 800B, and... Figure 8A Corresponding to along Figure 8B The cross-sectional view of line C in Figure 800A is shown. For example, a multi-channel 2DCG semiconductor device can be a group III nitride device and / or a depletion-type high electron mobility transistor (D-HEMT). However, other suitable device types are also possible.

[0081] The ohmic source / drain electrode 102 is located on the semiconductor film 104 and is ohmically coupled to a plurality of 2DCGs 106 in the semiconductor film 104 at individual effective ohmic contact regions 114. Protrusions 102p are separated by gaps 108 and protrude from the bottom surface 102bs of the ohmic source / drain electrode 102 into the semiconductor film 104, the bottom surface 102bs being flush with or approximately flush with the top surface of the semiconductor film 104. In an alternative embodiment, the bottom surface 102bs is raised or recessed relative to the top surface.

[0082] Semiconductor film 104 is located on substrate 118 and forms fin structure 104f (see example). Figure 8B Furthermore, the semiconductor film 104 includes a buffer layer 116 and a plurality of heterojunction structures 802 vertically stacked above the buffer layer 116. The buffer layer 116 buffers and / or transitions from the substrate 118 to the heterojunction structures 802 between differences in lattice constant, crystal structure, coefficient of thermal expansion, other suitable parameters, or any combination thereof.

[0083] The heterojunction structure 802 includes a separate channel layer 110 and a separate barrier layer 112. The channel layer 110 is located below the respective barrier layer 112 and is in direct contact with the respective barrier layer 112 at the heterojunction. The barrier layer 112 is polarized, so that positive charges are offset toward the bottom surface of the barrier layer 112. Due to the polarization, 2DCG 106 is formed in the channel layer 110. The 2DCG 106 extends along the heterojunction and has a high concentration of mobile electrons. Due to the high concentration, the 2DCG 106 can also be referred to as 2DEG 106e.

[0084] Gate electrode 120 and gate dielectric layer 804 are located on fin structure 104f and extend laterally across fin structure 104f between ohmic source / drain electrodes 102. Furthermore, gate dielectric layer 804 separates gate electrode 120 from fin structure 104f. During use of the 2DCG semiconductor device, gate electrode 120 is selectively biased to generate an electric field that manipulates the continuity of 2DCG 106 from first ohmic source / drain electrode 102a to second ohmic source / drain electrode 102b.

[0085] The ohmic source / drain electrode 102 is as described above. Therefore, the effective ohmic contact area 114 of the ohmic source / drain electrode 102 is large. This larger effective ohmic contact area 114 can further reduce the contact resistance from the ohmic source / drain electrode 102 to the 2DCG 106. Furthermore, the larger effective ohmic contact area 114 can reduce current congestion, thereby improving thermal performance and reliability.

[0086] Because multi-channel 2DCG semiconductor devices include multiple 2DCGs 106 (e.g., channels), current can be distributed across the 2DCGs 106, increasing current carrying capacity. Furthermore, because the protrusions 102p are separated by gaps 108, the protrusions 102p can extend through the 2DCGs 106 without disrupting the continuity of the 2DCGs 106 laterally across the ohmic source / drain electrodes 102. This is, for example... Figure 2 It is easier to see in the middle, Figure 2 You can follow Figure 8A Cut off line A in the middle.

[0087] In some embodiments, each channel layer 110 as described above Figure 1 The counterparts of these are described, and / or each barrier layer 112 as per [the description of the counterparts of these counterparts]. Figure 1 The counterparts described herein. In some embodiments, buffer layer 116, substrate 118, gate electrode 120, or any combination thereof, as described above... Figure 1 As described. In some embodiments, the gate dielectric layer 804 is or includes silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof.

[0088] refer to Figure 9A and Figure 9B Provided Figure 8A and Figure 8B Various cross-sectional views 900A, 900B of some alternative embodiments of a multi-channel 2DCG semiconductor device, wherein the multi-channel 2DCG semiconductor device has multiple fin structures 104f and additional heterojunction structures 802. Figure 9B Corresponding to along Figure 9A The cross-sectional view of line D in the middle is 900B, and Figure 9A Corresponding to along Figure 9B The cross-sectional view of line D in the diagram is 900A. Furthermore... Figure 2 The top view 200 can, for example, be along... Figure 9A Cut off line A in the middle.

[0089] Although Figure 2 and Figures 3A to 3F Described about Figure 1 The layout and arrangement of the 102p protrusions, but the layout and arrangement are applicable to Figure 4 , Figures 5A to 5D , Figure 6 , Figures 7A to 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B Any one of them. For example, Figure 8A The protrusion 102p can have such Figure 3C The circular layout in the middle. Although Figure 4 Described about Figure 1 The multilayer embodiment of the barrier layer 112, but Figures 5A to 5D , Figure 6 , Figures 7A to 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B Any of the blocking layers 112 in the middle can also be as follows: Figure 4 Multiple layers within. Although Figure 5A Described Figure 1 A variation of the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b, wherein the bottom surface 102bs is recessed, but this variation is suitable for Figure 4 , Figures 5B to 5D , Figure 6 , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B The first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b in either one. Although Figure 5B Described Figure 1 A variation of the semiconductor film 104, wherein the semiconductor film 104 includes a capping layer 502, but Figure 4 , Figure 5A , Figure 5C , Figure 6 , Figures 7A to 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B The semiconductor film 104 in any one of them may have a capping layer 502. Although Figure 5C Described Figure 1 A variation of the semiconductor film 104, wherein the channel layer 110 is located above the barrier layer 112 and the 2DCG 106 is 2DHG 106h, but this variation is applicable to Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A and Figure 9B Any one of them. Regarding... Figure 8A , Figure 8B , Figure 9A and Figure 9B The variation applies to every heterojunction structure 802. Although Figure 5D Described Figure 1 A first variant of the semiconductor film 104, wherein the channel layer 110 is located above the barrier layer 112 and the 2DCG 106 is the 2DHG 106h, and is further described. Figure 1 A second variation of the semiconductor film 104, wherein the semiconductor film 104 includes a capping layer 502, but the first and second variations are applicable to Figure 4 , Figure 5A , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A and Figure 9B Any one of them. Regarding... Figure 8A , Figure 8B , Figure 9A and Figure 9B The first variation applies to each of the heterojunction structures 802, while the second variation applies to combinations of heterojunction structures 802. Although Figure 7B Described Figure 6 A variation of the third ohmic source / drain electrode 102c, wherein the third ohmic source / drain electrode 102c has a protrusion 102p, this variation is suitable for Figure 7A and Figure 7C Any one of them. Although Figure 7C Described Figure 6 A variation of the semiconductor film 104, wherein 2DCG 106 is 2DHG 106h, but this variation is applicable to Figure 7A and Figure 7B Semiconductor film 104 in any one of them. Although Figure 8A , Figure 8B , Figure 9A and Figure 9B 2DCG 106 is described as 2DEG 106e, but 2DEG 106e may optionally be 2DHG 106h. In at least some of these alternative embodiments, the channel layer 110 and the barrier layer 112 of each heterojunction structure 802 are stacked, so that the barrier layer 112 is located below the channel layer 110.

[0090] refer to Figures 10 to 13 A series of cross-sectional views 1000-1300 of some embodiments of a method for forming a 2DCG semiconductor device, the 2DCG semiconductor device including an ohmic source / drain electrode having a plurality of protrusions projecting from the bottom of an ohmic source / drain electrode. For example, the method can be used to form Figure 1 2DCG semiconductor devices or some other suitable 2DCG semiconductor devices.

[0091] like Figure 10 As shown in cross-sectional view 1000, a semiconductor film 104 is formed over a substrate 118. The semiconductor film 104 includes a vertically stacked channel layer 110, a barrier layer 112, and a buffer layer 116. The process for forming the semiconductor film 104 may include, for example, sequentially depositing the various layers of the semiconductor film 104 from the bottom to the top of the semiconductor film 104 by metal-organic chemical vapor deposition (MOCVD) and / or some other suitable deposition process. However, other suitable processes for forming the semiconductor film 104 are possible.

[0092] The channel layer 110 is located below the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction, thus having a different band gap than the barrier layer 112. The barrier layer 112 is polarized, so that positive charges are offset towards the bottom surface of the barrier layer 112 and negative charges are offset towards the top surface of the barrier layer 112. Polarization can be caused, for example, by spontaneous and / or piezoelectric polarization effects. Due to polarization, 2DCG 106 is formed in the channel layer 110 and extends along the heterojunction with a high concentration of mobile electrons. Due to the high concentration, 2DCG 106 is conductive and can also be referred to as 2DEG 106e.

[0093] In alternative embodiments, such as Figure 5C As shown, the channel layer 110 is located above the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction. In such an alternative embodiment, polarization results in the 2DCG 106 having a high concentration of mobile holes rather than mobile electrons. Therefore, in these alternative embodiments, the 2DCG 106 can also be referred to as a 2DHG. In alternative embodiments, as Figure 5B and / or Figure 5D As shown, the semiconductor film 104 also includes a capping layer 502 located above the channel layer 110 and the barrier layer 112. The capping layer 502 can be, for example, as described above... Figure 5B and / or Figure 5D As stated above.

[0094] Buffer layer 116 separates channel layer 110 and barrier layer 112 from substrate 118. Furthermore, buffer layer 116 buffers and / or transitions between the substrate 118 and channel layer 110 in terms of lattice constant, crystal structure, coefficient of thermal expansion, other suitable parameters, or any combination thereof. By buffering and / or transitioning between these differences, the crystal quality of channel layer 110 and barrier layer 112 can be higher, and / or the stress on channel layer 110 and barrier layer 112 can be lower. This can, for example, enhance the performance of the forming 2DCG semiconductor device and / or reduce 2DCG semiconductor device failures.

[0095] The channel layer 110, barrier layer 112, buffer layer 116, substrate 118, or any combination thereof can be, for example, as described above regarding Figure 1 In some embodiments, the channel layer 110 is undoped and / or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable III-V materials, or any combination thereof. In some embodiments, the barrier layer 112 is undoped and / or includes aluminum gallium nitride (e.g., AlGaN), indium aluminum nitride (e.g., InAlN), aluminum nitride (e.g., AlN), aluminum gallium arsenide (e.g., AlGaAs), indium aluminum arsenide (e.g., InAlAs), indium gallium arsenide (e.g., InGaAs), some other suitable III-V materials, or any combination thereof. In some embodiments, the buffer layer 116 is or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable III-V materials, or any combination thereof. In some embodiments, the substrate 118 is or includes silicon, sapphire, some other suitable crystalline material, or any combination thereof. Although the channel layer 110, barrier layer 112, and buffer layer 116 are described as III-V group materials, II-VI group and other suitable semiconductor materials are also acceptable.

[0096] like Figure 11 As shown in cross-sectional view 1100, trench etching is selectively performed on semiconductor film 104 to form first-level trenches 1104 of a first group 1102a and a second group 1102b. The first group 1102a and the second group 1102b are laterally spaced and correspond to the source / drain electrodes being formed, as seen below. The first-level trenches 1104 are separated by gaps 108 and extend into semiconductor film 104 to a depth Dp. Furthermore, the first-level trenches 1104 extend from the top surface of semiconductor film 104 into semiconductor film 104 and are spaced apart from the heterojunctions that are in direct contact with channel layer 110 and barrier layer 112. In some embodiments, the process for performing trench etching includes: 1) forming a mask on semiconductor film 104; 2) performing trench etching on semiconductor film 104 with the mask in place; and 3) removing the mask. However, other suitable processes are also possible.

[0097] In some embodiments, the first-level groove 1104 has a similarity to... Figure 2 The same top layout as the 102p protrusions in the middle, and / or Figure 11 Corresponding to the direction Figure 2 The intermediate manufacturing state of the formation of 2DCG semiconductor devices, thereby Figure 2 You can follow Figure 11 Line A is cut off. In other embodiments, the first-level groove 1104 has the same... Figures 3A to 3F The protrusions 102p in any one of the groups have the same top layout or some other suitable top layout. Furthermore, in some embodiments, the first hierarchical grooves 1104 of the first group 1102a have the same top layout as the first hierarchical grooves 1104 of the second group 1102b. In some embodiments, the first hierarchical grooves 1104 are in a periodic pattern.

[0098] like Figure 12 As shown in cross-sectional view 1200, a plurality of ohmic source / drain electrodes 102 ohmically coupled to the 2DCG 106 are formed on the 2DCG 106. The ohmic source / drain electrodes 102 include a first ohmic source / drain electrode 102a and a second ohmic source / drain electrode 102b. The ohmic source / drain electrodes 102 correspond to and fill the first-level recesses 1104 of the first group 1102a and the first-level recesses 1104 of the second group 1102b, respectively. Therefore, the ohmic source / drain electrodes 102 include a plurality of individual protrusions 102p extending into the semiconductor film 104. The protrusions 102p are separated from each other by gaps 108 and are independent of and fill the first-level recesses 1104 (see example...). Figure 11 ).

[0099] In some embodiments, the process for forming the ohmic source / drain electrode 102 includes: 1) depositing an ohmic metal layer covering the semiconductor film 104; 2) patterning the ohmic metal layer into the ohmic source / drain electrode 102; and 3) annealing the ohmic source / drain electrode 102. However, other suitable processes are also possible. For example, patterning can be performed by photolithography / etching processes or some other suitable patterning processes. For example, a mask can be formed on the ohmic metal layer, metal etching can be performed on the ohmic metal layer while the mask is in place, and the mask can be removed. Annealing can, for example, reduce contact resistance and / or otherwise enhance the performance of the ohmic source / drain electrode 102.

[0100] In some embodiments, the ohmic source / drain electrode 102 is or includes titanium, aluminum, nickel, gold, some other suitable metal, or any combination thereof. In some embodiments, each ohmic source / drain electrode 102 is or includes a four-layer stack, comprising a titanium layer, an aluminum layer above the titanium layer, a nickel layer above the aluminum layer, and a gold layer above the nickel layer. In other embodiments, each ohmic source / drain electrode 102 includes a two-layer stack, comprising a titanium layer and an aluminum layer above the titanium layer.

[0101] Because the vertical spacing between 2DCG 106 and the ohmic source / drain electrode 102 is larger at gap 108 than directly below protrusion 102p, the density of 2DCG 106 is greater directly below gap 108 than directly below protrusion 102p. Therefore, the resistance of 2DCG 106 is smaller directly below gap 108 than directly below protrusion 102p. For example, as... Figure 2 As can be seen, the gap 108 can extend laterally across the ohmic source / drain electrode 102 and is laterally located around the protrusion 102p. Therefore, the small resistance directly below the gap 108 can facilitate current flow from the edges of the protrusion 102p on multiple sides of the ohmic source / drain electrode 102, thus the effective ohmic contact area 114 of the ohmic source / drain electrode 102 can be large.

[0102] A larger effective ohmic contact area 114 reduces current congestion and distributes current across the ohmic source / drain electrode 102. Reduced current congestion and distributed current increase the heat dissipation area generated during operation of the 2DCG semiconductor device, improving thermal performance and thus reliability. Furthermore, a larger effective ohmic contact area 114 results in lower contact resistance from the ohmic source / drain electrode 102 to the 2DCG 106.

[0103] Due to the larger effective ohmic contact area 114, the depth Dp into which the protrusion 102p extends in the semiconductor film 104 can be reduced while still maintaining low contact resistance. Etching uniformity typically decreases with increasing depth and typically increases with decreasing depth. In performing [the process related to...] Figure 11 During the described groove etching, the reduced depth can increase etching uniformity. Furthermore, due to the larger vertical spacing at gap 108, and because etching is not performed at gap 108, the current directly below the gap can be largely unaffected by etching non-uniformity. Because the current is largely unaffected by non-uniformity, the contact resistance is also largely unaffected by non-uniformity, resulting in higher yield.

[0104] like Figure 13 As shown in cross-sectional view 1300, a gate electrode 120 is formed on the semiconductor film 104, and the gate electrode 120 is laterally located between the ohmic source electrode / drain electrode 102. In some embodiments, the process 120 for forming the gate electrode includes: 1) depositing a gate electrode layer; and 2) patterning the gate electrode layer into the gate electrode 120. However, other suitable processes are also possible. In some embodiments, the gate electrode 120 is or includes nickel, gold, platinum, iridium, titanium nitride, aluminum copper, palladium, some other suitable metals and / or metallic materials, or any combination thereof.

[0105] Although the reference method describes Figures 10 to 13However, we will understand. Figures 10 to 13 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 10 to 13 Described as a series of actions, but it will be understood that the order of the actions may be changed in other embodiments. Although Figures 10 to 13 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0106] refer to Figures 14 to 16 Provided Figures 10 to 13 A series of cross-sectional views 1400-1600 of some alternative embodiments of the method, wherein a protrusion extends from the bottom surface of an ohmic source / drain electrode recessed relative to the top surface of the semiconductor film into the semiconductor film. For example, the method can be used to form Figure 5A 2DCG semiconductor devices or some other suitable 2DCG semiconductor devices.

[0107] like Figure 14 As shown in the cross-sectional view 1400, the execution regarding Figure 10 and Figure 11 The described action. For example, regarding... Figure 10 As described above, a semiconductor film 104 is formed over the substrate 118. Furthermore, as per [the relevant information]... Figure 11 The semiconductor film 104 is selectively etched with grooves to form first-level grooves 1104 of the first group 1102a and first-level grooves 1102b of the second group 1102b.

[0108] like Figure 15 As shown in cross-sectional view 1500, a second trench etching is selectively performed on the semiconductor film 104 to form a plurality of second-level trenches 1502. In an alternative embodiment, the second trench etching is performed prior to the trench etching. The second-level trenches 1502 are independent of the first-level trenches 1104 of the first group 1102a and the first-level trenches 1104 of the second group 1102b, and overlap with the first-level trenches 1104 of the first group 1102a and the first-level trenches 1104 of the second group 1102b, respectively. Furthermore, the second-level trenches 1502 extend into the semiconductor film 104 to a depth Dp2, which is less than the depth Dp into the semiconductor film 104 of the first-level trenches 1104. In some embodiments, the second-level trenches 1502 completely cover the first-level trenches 1104. In some embodiments, the process for performing the second trench etching includes: 1) forming a mask on the semiconductor film 104; 2) performing the second trench etching on the semiconductor film 104 with the mask in place; and 3) removing the mask. However, other suitable processes are also possible.

[0109] like Figure 16 As shown in the cross-sectional view 1600, the execution regarding Figure 12 and Figure 13 The described action involves forming a plurality of ohmic source / drain electrodes 102 on a semiconductor film 104, and further filling the first-level grooves 1104 of the first group 1102a and the first-level grooves 1104 and the second-level grooves 1502 of the second group 1102b, as described above. Figure 12 As described above. Furthermore, the gate electrode 120 is formed on the semiconductor film 104 and laterally positioned between the ohmic source electrode / drain electrode 102, as per [the relevant information]. Figure 13 As described above, due to the second-level groove 1502, the bottom surface 102bs (the protrusion 102p extends from the bottom surface 102bs) is recessed relative to the top surface of the semiconductor film 104. Furthermore, this increases the effective ohmic contact area 114 of the ohmic source / drain electrode 102, and thus reduces the contact resistance of the ohmic source / drain electrode 102.

[0110] Although the reference method description Figures 14 to 16 However, we will understand. Figures 14 to 16 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 14 to 16 Described as a series of actions, but it will be understood that the order of the actions may be changed in other embodiments. Although... Figures 14 to 16 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0111] refer to Figure 17 Provided Figures 10 to 13 A block diagram 1700 shows some embodiments of the method.

[0112] At 1702, a semiconductor film is formed on the substrate, wherein the semiconductor film includes a channel layer and a barrier layer that are vertically stacked and in direct contact at the heterojunction, and wherein 2DCG extends along the heterojunction in the channel layer. See, for example. Figure 10 .

[0113] At 1704, selective trench etching is performed on the semiconductor film to form a first-level trench of a first group and a second group of first-level trenches. See, for example. Figure 11 In some embodiments, a second trench etching is selectively performed on the semiconductor film to form a plurality of second-level trenches, the second-level trenches being independent of the first-level trenches of the first group and the first-level trenches of the second group, and respectively located above the first-level trenches of the first group and the first-level trenches of the second group. See, for example, [link to documentation]. Figure 15 .

[0114] At position 1706, a pair of ohmic source / drain electrodes are formed, wherein the ohmic source / drain electrodes are independent of the first-level grooves of the first group and the first-level grooves of the second group, and respectively fill the first-level grooves of the first group and the first-level grooves of the second group. For example, see Figure 12 .

[0115] At position 1708, a gate electrode is formed on the semiconductor film, laterally positioned between the ohmic source / drain electrodes. See, for example... Figure 13 .

[0116] Although Figure 17 The block diagram 1700 shown and described herein is a series of actions or events; however, it will be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown may be required to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0117] refer to Figures 18 to 23 A series of cross-sectional views 1800-2300 illustrate some embodiments of a method for forming a vertical 2DCG semiconductor device, the vertical 2DCG semiconductor device including an ohmic source / drain electrode having a plurality of protrusions extending from the bottom of an ohmic source / drain electrode. For example, this method can be used to form... Figure 6 2DCG semiconductor devices or some other suitable 2DCG semiconductor devices.

[0118] like Figure 18 As shown in cross-sectional view 1800, a drift layer 602 is formed. The drift layer 602 is a doped semiconductor layer and includes a first doped layer 602a, a second doped layer 602b above the first doped layer 602a, and a third doped layer 602c above the second doped layer 602b. The first doped layer 602a, the second doped layer 602b, and the third doped layer 602c share a common material but have different doping concentrations. For example, the first doped layer 602a may have a higher doping concentration than the third doped layer 602c, and the third doped layer 602c may have a higher doping concentration than the second doped layer 602b.

[0119] In some embodiments, the drift layer 602 is or includes gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (e.g., InP), some other suitable group III-V materials, or any combination thereof. In at least some embodiments where the subsequently formed 2DCG is a 2DEG, the drift layer 602 is doped with an n-type donor impurity. For example, in at least some embodiments where the semiconductor film 104 is based on gallium nitride, the drift layer 602 may be doped with silicon, carbon, or some other suitable type of n-type donor impurity. In at least some embodiments where the subsequently formed 2DCG is a 2DHG, the drift layer 602 is doped with a p-type acceptor impurity.

[0120] like Figure 19 As shown in cross-sectional view 1900, CBL 604 is formed on top of drift layer 602 and inserted into the top of drift layer 602. Furthermore, CBL 604 has a hole 606 through which drift layer 602 can extend. CBL 604 is configured to block current flow for the vertical 2DCG semiconductor being formed.

[0121] In some embodiments, the process for forming CBL 604 includes selectively doping portions of drift layer 602 with: 1) a dopant having a doping type opposite to that of drift layer 602 (e.g., n-type versus p-type); and / or 2) a dopant that increases the band gap of drift layer 602. For example, when drift layer 602 is n-type and drift layer 602 is or includes gallium nitride, drift layer 602 may be selectively doped with magnesium or other suitable p-type dopant. As another example, when drift layer 602 is n-type and drift layer 602 is or includes gallium nitride, drift layer 602 may be doped with aluminum or some other suitable material configured to increase the band gap of n-type gallium nitride. For example, doping can be selectively performed by the following steps: 1) forming a mask over drift layer 602; 2) doping drift layer 602 with the mask in place; and 3) removing the mask. Although the above methods are used to form CBL 604, other suitable processes are also possible.

[0122] like Figure 20 As shown in cross-sectional view 2000, the channel layer 110 and the barrier layer 112 are formed as vertically stacked above the drift layer 602 and CBL 604. Together, the channel layer 110, barrier layer 112, drift layer 602, and CBL 604 form a semiconductor film 104. The process for forming the channel layer 110 and the barrier layer 112 may, for example, include sequentially depositing the channel layer 110 and the barrier layer 112 by MOCVD and / or some other suitable deposition process. However, other suitable processes for forming the channel layer 110 and the barrier layer 112 are possible.

[0123] The channel layer 110 is located below the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction, and therefore has a different band gap than the barrier layer 112. The barrier layer 112 is polarized, so positive charges are offset towards the bottom surface of the barrier layer 112 and negative charges are offset towards the top surface of the barrier layer 112. Due to the polarization, 2DCG 106 is formed in the channel layer 110 and extends along the heterojunction with a high concentration of mobile electrons. Due to the high concentration, 2DCG 106 is conductive and can also be referred to as 2DEG 106e.

[0124] In alternative embodiments, such as Figure 7C As shown, the channel layer 110 is located above the barrier layer 112 and is in direct contact with the barrier layer 112 at the heterojunction. In such an alternative embodiment, polarization results in the 2DCG 106 having a high concentration of mobile holes rather than mobile electrons. Therefore, in these alternative embodiments, the 2DCG 106 can also be referred to as a 2DHG. In alternative embodiments, as Figure 5B and / or Figure 5D As shown, the semiconductor film 104 also includes a capping layer 502 located above the channel layer 110 and the barrier layer 112. The capping layer 502 can be, for example, as described above... Figure 5B and / or Figure 5D As stated above.

[0125] like Figure 21 As shown in the cross-sectional diagram 2100, the execution regarding... Figure 11 and Figure 12 The described action involves selectively performing trench etching on the semiconductor film 104 to form first-level trenches 1104 of the first group 1102a and first-level trenches 1104 of the second group 1102b, as described regarding... Figure 11 As described above. Multiple ohmic source / drain electrodes 102 are formed on the semiconductor film 104, and further fill the first-level grooves 1104 of the first group 1102a and the first-level grooves 1104 of the second group 1102b, as per [the relevant information]. Figure 12 As described above. In an alternative embodiment, a second trench etching is selectively performed on the semiconductor film 104 to form a plurality of second-level trenches 1502, as per [the previous description]. Figure 15 The second groove etching can be performed before the groove etching or between the groove etching and the formation of the ohmic source / drain electrode 102.

[0126] like Figure 22As shown in cross-sectional view 2200, a third ohmic source / drain electrode 102c is formed on the lower side of the semiconductor film 104, below the hole 606, of the ohmic source / drain electrode 102. The third ohmic source / drain electrode 102c is described similarly to the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b, except that the third ohmic source / drain electrode 102c has no protrusion. In an alternative embodiment, the third ohmic source / drain electrode 102c has the following characteristics: Figure 7B The protrusion in the middle. Furthermore, the third ohmic source / drain electrode 102c can, for example, be as described regarding... Figure 12 It is formed as described for the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b.

[0127] like Figure 23 As shown in the cross-sectional diagram 2300, the execution regarding... Figure 13 The described action is to form a gate electrode 120 on the semiconductor film 104, the gate electrode 120 being laterally located between the first ohmic source / drain electrode 102a and the second ohmic source / drain electrode 102b.

[0128] Although the reference method describes Figures 18 to 23 However, we will understand. Figures 18 to 23 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 18 to 23 Described as a series of actions, but it will be understood that the order of the actions may be changed in other embodiments. Although... Figures 18 to 23 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0129] refer to Figures 24 to 27 A series of cross-sectional views 2400-2700 are provided for some embodiments of a multi-channel 2DCG semiconductor device including an ohmic source / drain electrode, the ohmic source / drain electrode having multiple protrusions projecting from the bottom of the ohmic source / drain electrode. For example, this method can be used to form Figure 8A and Figure 8B Multichannel 2DCG semiconductor devices.

[0130] like Figure 24 As shown in cross-sectional view 2400, a semiconductor film 104 is formed over the substrate 118. A fin structure is formed on the exterior of the semiconductor film 104 in cross-sectional view 2400. However, the fin structure can be, for example, as shown in... Figure 8B The fin structure 104f, and / or Figure 24 It can correspond to the direction Figure 8B The intermediate manufacturing state of the formation of multi-channel 2DCG semiconductor devices, thereby Figure 8BIt can be along Figure 24 Line C is cut off in the diagram. Furthermore, the semiconductor film 104 includes a buffer layer 116 and a plurality of heterojunction structures 802 vertically stacked above the buffer layer 116. The buffer layer 116 buffers and / or transitions from the substrate 118 to the heterojunction structures 802 between differences in lattice constant, crystal structure, coefficient of thermal expansion, other suitable parameters, or any combination thereof.

[0131] The heterojunction structure 802 includes a separate channel layer 110 and a separate barrier layer 112. The channel layer 110 is located below the respective barrier layer 112 and is in direct contact with the respective barrier layer 112 at the heterojunction. The barrier layer 112 is polarized, so that positive charges are offset toward the bottom surface of the barrier layer 112. Due to the polarization, 2DCG 106 is formed in the channel layer 110. The 2DCG 106 extends along the heterojunction and has a high concentration of mobile electrons. Due to the high concentration, the 2DCG 106 can also be referred to as 2DEG 106e.

[0132] In an alternative embodiment, the channel layer 110 is located above the corresponding barrier layer 112 and is in direct contact with the corresponding barrier layer 112 at the heterojunction. In such an alternative embodiment, polarization results in the 2DCG 106 having a high concentration of mobile holes rather than mobile electrons. Therefore, in these alternative embodiments, the 2DCG 106 can also be referred to as a 2DHG. In alternative embodiments, such as Figure 5B and / or Figure 5D As shown, the semiconductor film 104 also includes a capping layer 502 located above the channel layer 110 and the barrier layer 112. The capping layer 502 can be, for example, as described above... Figure 5B and / or Figure 5D As stated above.

[0133] The process for forming the semiconductor film 104 may include, for example, 1) sequentially depositing the various layers of the semiconductor film 104 from the bottom to the top of the semiconductor film 104; and 2) subsequently patterning the semiconductor film 104 into a fin structure. However, other suitable processes for forming the semiconductor film 104 are possible. For example, deposition can be performed by MOCVD and / or some other suitable deposition processes. For example, patterning can be performed by photolithography / etching processes and / or some other suitable patterning processes.

[0134] like Figure 25 and Figure 26 The cross-sectional views 2500 and 2600 are shown respectively, and the relevant parameters are executed accordingly. Figure 25 and Figure 26 The described action. In Figure 25At the location, selectively perform trench etching on the semiconductor film 104 to form first-level trenches 1104 of the first group 1102a and first-level trenches 1104 of the second group 1102b, as per [reference to...]. Figure 11 As stated above. Figure 26 At this location, multiple ohmic source / drain electrodes 102 are formed on the semiconductor film 104 and fill the first-level grooves 1104 of the first group 1102a and the first-level grooves 1104 of the second group 1102b, as per [reference to...]. Figure 12 As described above. In an alternative embodiment, a second trench etching is selectively performed on the semiconductor film 104 to form a plurality of second-level trenches 1502, as per [the previous description]. Figure 15 The second groove etching can be performed before the groove etching or between the groove etching and the formation of the ohmic source / drain electrode 102.

[0135] Because the protrusion 102p is separated by the gap 108, the first-level groove 1104 and therefore the protrusion 102p can extend through the 2DCG 106 without disrupting the continuity of the 2DCG 106 laterally across the ohmic source / drain electrode 102. This is, for example, in... Figure 2 It is easier to see in the middle. Figure 2 You can follow Figure 26 Cut off line A in the middle.

[0136] like Figure 27 As shown in cross-sectional view 2700, a gate dielectric layer 804 and a gate electrode 120 are formed on a semiconductor film 104, the gate dielectric layer 804 and the gate electrode 120 spanning a fin structure 104f formed by the semiconductor film 104 (see example...). Figure 8B In some embodiments, the process for forming the gate dielectric layer 804 and the gate electrode 120 includes: 1) depositing a dielectric layer; 2) depositing a gate electrode layer over the dielectric layer; and 3) patterning the dielectric layer and the gate electrode layer as the gate dielectric layer 804 and the gate electrode 120, respectively. However, other suitable processes are possible.

[0137] Although the reference method describes Figures 24 to 27 However, we will understand. Figures 24 to 27 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 24 to 27 Described as a series of actions, but it will be understood that the order of the actions may be changed in other embodiments. Although... Figures 24 to 27 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0138] In some embodiments, the present invention provides a semiconductor device comprising: a semiconductor film including a channel layer and a barrier layer, wherein the channel layer and the barrier layer are vertically stacked and contact at a heterojunction; a 2DCG located in the channel layer and extending laterally along the heterojunction; a first source / drain electrode and a second source / drain electrode located on the 2DCG and ohmically coupled to the 2DCG; and a gate electrode located on the semiconductor film and laterally positioned between the first source / drain electrode and the second source / drain electrode; wherein the first source / drain electrode has a plurality of first protrusions projecting from the bottom surface of the first source / drain electrode into the semiconductor film. In some embodiments, the first protrusions are periodically patterned from a first side of the first source / drain electrode to a second side of the first source / drain electrode opposite to the first side. In some embodiments, the first protrusions are located in multiple rows and columns. In some embodiments, the first protrusions are spaced apart from the heterojunction. In some embodiments, the bottom surface is flush with the top surface of the semiconductor film. In some embodiments, the bottom surface is recessed relative to the top surface of the semiconductor film. In some embodiments, the barrier layer and the channel layer comprise a III-V group material. In some embodiments, the semiconductor film includes a capping layer located above the channel layer and the barrier layer, wherein a first protrusion protrudes into the capping layer and is spaced apart from the channel layer and the barrier layer. In some embodiments, the first protrusion protrudes into the barrier layer and is spaced apart from the channel layer.

[0139] In some embodiments, the present invention provides another semiconductor device, comprising: a channel layer; a barrier layer stacked perpendicularly to and in direct contact with the channel layer; a 2DCG located in the channel layer and extending laterally along the interface where the barrier layer and the channel layer are in direct contact; a first source / drain electrode and a second source / drain electrode located on the 2DCG and ohmically coupled to the 2DCG; and a gate electrode located on the 2DCG and laterally positioned between the first source / drain electrode and the second source / drain electrode; wherein the first source / drain electrode has a first vertical spacing and a second vertical spacing with respect to the 2DCG, wherein the second vertical spacing is greater than the first vertical spacing, and wherein the first source / drain electrode has a second vertical spacing that extends continuously from a first side of the first source / drain electrode facing the second source / drain electrode to a second side of the first source / drain electrode opposite to the first side. In some embodiments, the bottom of the first source / drain electrode has a gap having a periodic pattern. In some embodiments, the first vertical spacing is located directly below a pair of bottom protrusions of the first source / drain electrode, wherein the second vertical spacing is located at the gap separating the bottom protrusions. In some embodiments, the barrier layer and the channel layer at least partially form a fin structure, wherein the gate electrode spans the fin structure and extends along the opposing sidewalls of the fin structure. In some embodiments, the channel layer and the barrier layer form a heterojunction structure repeated multiple times in a vertical stack, wherein the vertical stack at least partially forms a fin structure, and wherein the gate electrode extends along the sidewall of each heterojunction structure in the vertical stack. In some embodiments, the semiconductor device further includes: a semiconductor drift layer located below the channel layer and the barrier layer; a current blocking layer inserted in the top of the semiconductor drift layer, vertically located between the semiconductor drift layer and the channel layer and the barrier layer, wherein the current blocking layer has a hole located below the gate electrode; and a third source / drain electrode located below the hole, on the underside of the semiconductor drift layer.

[0140] In some embodiments, the present invention provides a method for forming a semiconductor device, the method comprising: forming a semiconductor film including a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction, wherein a 2DCG is located in the channel layer and extends laterally along the heterojunction; selectively performing a first etching on the semiconductor film to form a plurality of first-level trenches, wherein the first-level trenches have a periodic pattern; forming a first source / drain electrode and a second source / drain electrode, wherein the first source / drain electrode and the second source / drain electrode are laterally spaced and ohmically coupled to the 2DCG, and wherein the first source / drain electrode fills the plurality of first-level trenches; and forming a gate electrode on the semiconductor film, the gate electrode being laterally located between the first source / drain electrode and the second source / drain electrode. In some embodiments, the method further comprises performing a second etching on the semiconductor film to form a second-level trench; wherein the plurality of first-level trenches overlap with the second-level trenches, and wherein the first etching extends into the semiconductor film to a greater depth than the second etching extends into the semiconductor film. In some embodiments, the formation of the first source / drain electrode includes depositing an ohmic metal, wherein the semiconductor film has individual sidewalls in the first-level trench, the individual sidewalls extending from the top surface of the semiconductor film to the bottom of the first-level trench during deposition. In some embodiments, the method further includes: forming a semiconductor drift layer; selectively doping the top of the semiconductor drift layer to form a current blocking layer over the semiconductor drift layer, wherein the current blocking layer has a hole at which the top is not selectively doped; and forming a third source / drain electrode directly below the hole; wherein a channel layer and a blocking layer are formed over the semiconductor drift layer and the current blocking layer, wherein a gate electrode is formed directly above the hole, and wherein the first source / drain electrode and the second source / drain electrode are formed directly above the current blocking layer. In some embodiments, the formation of the semiconductor film includes repeatedly and alternately depositing the channel layer and the blocking layer.

[0141] According to one embodiment of this application, a semiconductor device is provided, comprising: a semiconductor film including a channel layer and a barrier layer, wherein the channel layer and the barrier layer are vertically stacked and contact at a heterojunction; a two-dimensional carrier gas (2DCG) located in the channel layer and extending laterally along the heterojunction; a first source / drain electrode and a second source / drain electrode located on the 2DCG and ohmically coupled to the 2DCG; and a gate electrode located on the semiconductor film and laterally positioned between the first source / drain electrode and the second source / drain electrode; wherein the first source / drain electrode has a plurality of first protrusions protruding from the bottom surface of the first source / drain electrode into the semiconductor film. In some embodiments, the first protrusions are periodically patterned from a first side of the first source / drain electrode to a second side of the first source / drain electrode opposite to the first side. In some embodiments, the first protrusions are located in multiple rows and columns. In some embodiments, the first protrusions are spaced apart from the heterojunction. In some embodiments, the bottom surface is flush with the top surface of the semiconductor film. In some embodiments, the bottom surface is recessed relative to the top surface of the semiconductor film. In some embodiments, the barrier layer and the channel layer comprise a III-V group material. In some embodiments, the semiconductor film comprises a capping layer located above the channel layer and the barrier layer, and a first protrusion protrudes into the capping layer and is spaced apart from the channel layer and the barrier layer. In some embodiments, the first protrusion protrudes into the barrier layer and is spaced apart from the channel layer.

[0142] According to another embodiment of this application, a semiconductor device is provided, comprising: a channel layer; a barrier layer stacked perpendicularly to and in direct contact with the channel layer; a two-dimensional carrier gas (2DCG) located in the channel layer and extending laterally along the interface between the barrier layer and the channel layer in direct contact; a first source / drain electrode and a second source / drain electrode located on the 2DCG and ohmically coupled to the 2DCG; and a gate electrode located on the 2DCG and laterally positioned between the first source / drain electrode and the second source / drain electrode; wherein the first source / drain electrode has a first vertical spacing and a second vertical spacing from the 2DCG, wherein the second vertical spacing is greater than the first vertical spacing, and wherein the first source / drain electrode has a second vertical spacing continuously extending from a first side of the first source / drain electrode facing the second source / drain electrode to a second side of the first source / drain electrode opposite to the first side. In some embodiments, the bottom of the first source / drain electrode has a gap having a periodic pattern. In some embodiments, a first vertical spacing is located directly below a pair of bottom protrusions of a first source / drain electrode, and a second vertical spacing is located at a gap separating the bottom protrusions. In some embodiments, a barrier layer and a channel layer at least partially form a fin structure, and a gate electrode spans the fin structure and extends along opposite sidewalls of the fin structure. In some embodiments, a channel layer and a barrier layer form a heterojunction structure repeated multiple times in a vertical stack, wherein the vertical stack at least partially forms a fin structure, and a gate electrode extends along the sidewall of each heterojunction structure in the vertical stack. In some embodiments, the semiconductor device further includes: a semiconductor drift layer located below the channel layer and the barrier layer; a current blocking layer inserted in the top of the semiconductor drift layer, vertically located between the semiconductor drift layer and the channel layer and the barrier layer, wherein the current blocking layer has a hole located below the gate electrode; and a third source / drain electrode located below the hole, on the underside of the semiconductor drift layer.

[0143] According to another embodiment of this application, a method for forming a semiconductor device is provided, the method comprising: forming a semiconductor film including a channel layer and a barrier layer that are vertically stacked and directly contacted at a heterojunction, wherein a two-dimensional carrier gas (2DCG) is located in the channel layer and extends laterally along the heterojunction; selectively performing a first etching on the semiconductor film to form a plurality of first-level trenches, wherein the first-level trenches have a periodic pattern; forming a first source / drain electrode and a second source / drain electrode, wherein the first source / drain electrode and the second source / drain electrode are laterally spaced and ohmically coupled to the two-dimensional carrier gas, and wherein the first source / drain electrode fills the plurality of first-level trenches; and forming a gate electrode on the semiconductor film, the gate electrode being laterally located between the first source / drain electrode and the second source / drain electrode. In some embodiments, the method for forming a semiconductor device further comprises: performing a second etching on the semiconductor film to form a second-level trench; wherein the plurality of first-level trenches overlap with the second-level trenches, and wherein the depth of the first etching extending into the semiconductor film is greater than the depth of the second etching extending into the semiconductor film. In some embodiments, the formation of the first source / drain electrode includes depositing ohmic metal, and wherein the semiconductor film has individual sidewalls in the first-level trench, the individual sidewalls extending from the top surface of the semiconductor film to the bottom of the first-level trench during deposition. In some embodiments, the method for forming a semiconductor device further includes: forming a semiconductor drift layer; selectively doping the top of the semiconductor drift layer to form a current blocking layer over the semiconductor drift layer, wherein the current blocking layer has a hole at which the top is not selectively doped; and forming a third source / drain electrode directly below the hole; wherein a channel layer and a blocking layer are formed over the semiconductor drift layer and the current blocking layer, wherein a gate electrode is formed directly above the hole, and wherein the first source / drain electrode and a second source / drain electrode are formed directly above the current blocking layer. In some embodiments, the formation of the semiconductor film includes repeatedly and alternately depositing the channel layer and the blocking layer.

[0144] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: A semiconductor film includes a channel layer and a barrier layer, wherein the channel layer and the barrier layer are stacked vertically and contact each other at a heterojunction; A two-dimensional carrier gas is located in the channel layer and extends laterally along the heterojunction; The first source / drain electrode and the second source / drain electrode, in the cross-sectional view, are located above the two-dimensional carrier gas and ohmically coupled to the two-dimensional carrier gas; and The gate electrode is located on the semiconductor film and laterally positioned between the first source / drain electrode and the second source / drain electrode; A semiconductor drift layer is located beneath the semiconductor film; A current blocking layer is located below the semiconductor film, above the semiconductor drift layer, and recessed into the semiconductor drift layer; and The third source / drain electrode is located below the gate electrode on the lower side of the semiconductor drift layer. The first source electrode / drain electrode has a plurality of first protrusions protruding downward from the bottom surface of the first source electrode / drain electrode into the semiconductor film. In a cross-sectional view, the third source electrode / drain electrode has a plurality of second protrusions protruding upward toward the gate electrode into the semiconductor drift layer, and has a larger total number of protrusions than the first source electrode / drain electrode. The semiconductor drift layer has a third protrusion protruding upward through the current blocking layer. The third protrusion covers the plurality of second protrusions in the cross-sectional view and has a top surface flush with the top surface of the current blocking layer in the cross-sectional view.

2. The semiconductor device of claim 1, wherein, The first protrusion forms a periodic pattern from the first side of the first source electrode / drain electrode to the second side of the first source electrode / drain electrode opposite to the first side.

3. The semiconductor device of claim 1, wherein, The first protrusion is located in multiple rows and columns.

4. The semiconductor device of claim 1, wherein, The first protrusion is spaced apart from the heterojunction.

5. The semiconductor device of claim 1, wherein, The bottom surface is flush with the top surface of the semiconductor film.

6. The semiconductor device of claim 1, wherein, The bottom surface is recessed relative to the top surface of the semiconductor film.

7. The semiconductor device of claim 1, wherein, The barrier layer and the channel layer comprise III-V group materials.

8. The semiconductor device according to claim 1, wherein, The semiconductor film is a III-V group semiconductor material or a II-VI group semiconductor material, or includes III-V group semiconductor materials or II-VI group semiconductor materials.

9. The semiconductor device according to claim 1, wherein, The first protrusion protrudes into the barrier layer and is spaced apart from the channel layer.

10. A semiconductor device, comprising: The first channel layer and the first barrier layer are stacked perpendicularly to each other and are in direct contact at the first interface; The first two-dimensional carrier gas is located in the first channel layer and extends laterally along the first interface; The second channel layer and the second barrier layer are stacked perpendicularly to each other and are in direct contact at the second interface, wherein the second channel layer and the second barrier layer are located on top of the first channel layer and the first barrier layer; The second two-dimensional carrier gas is located in the second channel layer and extends laterally along the second interface; The first source / drain electrode and the second source / drain electrode are laterally spaced apart from each other in a first direction and are located on the first two-dimensional carrier gas and the second two-dimensional carrier gas, and are ohmically coupled to the first two-dimensional carrier gas and the second two-dimensional carrier gas; and The gate electrode is located above the first two-dimensional carrier gas and the second two-dimensional carrier gas and is laterally located between the first source electrode / drain electrode and the second source electrode / drain electrode in the first direction; The first source electrode / drain electrode has a first vertical spacing and a second vertical spacing from the first two-dimensional carrier gas, wherein the second vertical spacing is greater than the first vertical spacing, and wherein the first source electrode / drain electrode has a second vertical spacing continuously extending from a first side of the first source electrode / drain electrode facing the second source electrode / drain electrode to a second side of the first source electrode / drain electrode opposite to the first side, wherein the first barrier layer and the first channel layer, as well as the second barrier layer and the second channel layer, at least partially form a fin structure, wherein the gate electrode spans the fin structure between the first source electrode / drain electrode and the second source electrode / drain electrode in the first direction, and has a pair of leg portions that are laterally spaced apart from each other in a second direction perpendicular to the first direction and extend vertically downward along the opposite sidewalls of the fin structure in a third direction perpendicular to the first and second directions, and wherein the pair of leg portions have a separate bottom surface that is raised relative to the first two-dimensional carrier gas and recessed relative to the bottom surface portion of the first source electrode / drain electrode, the separate bottom surface being embedded in the first barrier layer.

11. The semiconductor device according to claim 10, wherein, The bottom of the first source / drain electrode has a gap, and the gap has a periodic pattern.

12. The semiconductor device according to claim 10, wherein, The first vertical spacing is located directly below a pair of bottom protrusions of the first source / drain electrode, and the second vertical spacing is located at the gap that separates the bottom protrusions.

13. The semiconductor device according to claim 10, wherein, The first channel layer is or includes gallium nitride, gallium arsenide, or indium phosphide.

14. The semiconductor device according to claim 10, wherein, The first barrier layer is or includes aluminum gallium nitride.

15. The semiconductor device according to claim 10, wherein, in, The gate electrode is or includes nickel, gold, platinum, iridium, titanium nitride, aluminum copper, and palladium.

16. A method for forming a semiconductor device, the method comprising: A semiconductor film is formed, the semiconductor film including a first channel layer, a first barrier layer located on the first channel layer, a second channel layer located on the first barrier layer, and a second barrier layer located on the second channel layer, wherein the first channel layer and the first barrier layer are in contact at a first heterojunction and the second channel layer and the second barrier layer are in contact at a second heterojunction, wherein a first two-dimensional carrier gas and a second two-dimensional carrier gas are respectively located in the first channel layer and the second channel layer; A first etching is performed on the semiconductor film to form a fin structure; After the first etching, a second etching is selectively performed on the fin structure to form a plurality of first-level grooves, wherein the plurality of first-level grooves have a periodic pattern, wherein the plurality of first-level grooves have a periodic pattern, spaced apart from the first channel layer, and individually expose the second two-dimensional carrier gas and the individual sidewalls of the first barrier layer, the second channel layer and the second barrier layer. A third etching is performed on the fin structure to form a second-level groove, wherein the plurality of first-level grooves and the second-level grooves overlap, and wherein the second etching extends to a depth in the fin structure greater than the depth of the third etching; A first source / drain electrode and a second source / drain electrode are formed, wherein the first source / drain electrode and the second source / drain electrode are laterally spaced and ohmically coupled to the first two-dimensional carrier gas and the second two-dimensional carrier gas, and wherein the first source / drain electrode fills the plurality of first-level grooves; and A gate electrode is formed on the fin structure, the gate electrode being laterally located between the first source / drain electrode and the second source / drain electrode, wherein the gate electrode has a pair of leg portions, the fin structure is laterally arranged between the pair of leg portions, and wherein the pair of leg portions extend vertically downward along the opposite sidewalls of the fin structure and have a separate bottom surface that is recessed relative to the second two-dimensional carrier gas and raised relative to the first two-dimensional carrier gas and the second two-dimensional carrier gas.

17. The method according to claim 16, wherein, The semiconductor film is or includes III-V group semiconductor materials or II-VI group semiconductor materials.

18. The method according to claim 16, wherein, The first barrier layer is or includes aluminum gallium nitride.

19. The method of claim 16, wherein, The first channel layer is or includes gallium nitride, gallium arsenide, or indium phosphide.

20. The method of claim 16, wherein, The gate electrode is or includes nickel, gold, platinum, iridium, titanium nitride, aluminum copper, and palladium.

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