Echo cancellation system and echo cancellation method

Abstract

The present invention relates to an echo cancellation system. A digital-to-analog conversion circuit is used to generate an analog transmission signal according to a digital transmission signal. A first echo cancellation circuit is used to generate a first echo cancellation signal according to the digital transmission signal. A processing circuit is used to generate an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a received signal. An analog-to-digital conversion circuit is used to generate a digital value according to the analog processing signal and two limiting levels. A storage circuit is used to store a lookup table. The lookup table records an offset value corresponding to the digital value. The storage circuit is also used to generate a first output signal according to the digital value and the offset value. The offset value is updated according to an error value related to the first output signal.

Description

Technical Field

[0001] The present invention relates to an echo cancellation technology, and more particularly to an echo cancellation system and an echo cancellation method. Background Art

[0002] With the development of communication technology, various communication systems have been developed and adopted in many different applications. In a communication system using full-duplex technology, there will be a transmission signal and a reception signal on a pair of transmission lines. When the impedance of the two transmission lines is not matched or there is a mismatch in the hybrid integrated architecture of the receiving device, the transmission signal may be introduced into the received signal and cause an echo. In some related technologies, the echo can be eliminated by using echo cancellation technology. However, when the limiting level of the analog-to-digital conversion circuit in the communication system is offset, the quantization noise may be increased and affect the signal-to-noise ratio (SNR) of the communication system. Summary of the invention

[0003] Some embodiments of the present invention relate to an echo cancellation system. The echo cancellation system includes a digital-to-analog conversion circuit, a first echo cancellation circuit, a processing circuit, an analog-to-digital conversion circuit, and a storage circuit. The digital-to-analog conversion circuit is used to generate an analog transmission signal according to a digital transmission signal. The first echo cancellation circuit is used to generate a first echo cancellation signal according to the digital transmission signal. The processing circuit is used to generate an analog processing signal according to the analog transmission signal, the first echo cancellation signal, and a received signal. The analog-to-digital conversion circuit is used to generate a digital value according to the analog processing signal and two of a plurality of limiting levels. The storage circuit is used to store a lookup table. The lookup table records an offset value corresponding to the digital value. The storage circuit is also used to output a first output signal according to the digital value and the offset value. The offset value is updated according to an error value related to the first output signal.

[0004] Some embodiments of the present invention relate to an echo cancellation method. The echo cancellation method includes: generating an analog transmission signal according to a digital transmission signal through a digital-to-analog conversion circuit; generating a first echo cancellation signal according to the digital transmission signal through a first echo cancellation circuit; generating an analog processing signal according to the analog transmission signal, the first echo cancellation signal and a received signal through a processing circuit; generating a digital value according to the analog processing signal and two clipping levels among a plurality of clipping levels through an analog-to-digital conversion circuit; storing a lookup table through a storage circuit and outputting a first output signal according to the digital value and an offset value corresponding to the digital value, wherein the lookup table records the offset value; and updating the offset value in the lookup table according to an error value related to the first output signal.

[0005] In summary, in the echo cancellation system and the echo cancellation method of the present invention, the offset value can be updated according to the corresponding error value. Accordingly, even if the clipping level deviates, the updated offset value can be used to keep the output signal roughly at the middle value of the two deviated clipping levels. In this way, the quantization noise can be minimized and the signal-to-noise ratio of the system can be maintained (or improved). BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0007] Figure 1 is a schematic diagram of an echo cancellation system according to some embodiments of the present invention;

[0008] Figure 2A is a schematic diagram of the operation of the analog-to-digital conversion circuit according to some embodiments of the present invention when the limiting level does not deviate;

[0009] Figure 2B is a schematic diagram of the operation of the analog-to-digital conversion circuit when the limiting level deviates according to some embodiments of the present invention;

[0010] Figure 3 is a schematic diagram of a lookup table according to some embodiments of the present invention;

[0011] Figure 4 is a schematic diagram of a signal-to-noise ratio according to some embodiments of the present invention; and

[0012] Figure 5 is a flow chart of an echo cancellation method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0013] In this specification, the term “coupled” may also refer to “electrically coupled”, and the term “connected” may also refer to “electrically connected.” “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.

[0014] refer to Figure 1 . Figure 1 FIG. 1 is a schematic diagram of an echo cancellation system S1 according to some embodiments of the present invention. In some embodiments, the echo cancellation system S1 is applied to an Ethernet system.

[0015] In some embodiments, the echo cancellation system S1 adopts full-duplex technology. That is, there is a pair of transmission lines in the system, and the two transmission lines carry transmission signals and reception signals respectively. Figure 1For example, the transmission signal of the echo cancellation system S1 is a digital transmission signal TX, and the reception signal of the echo cancellation system S1 is a reception signal RXC.

[0016] by Figure 1 For example, the echo cancellation system S1 includes a data transmission circuit 100 , an echo cancellation circuit 200 , and an echo cancellation circuit 300 . The data transmission circuit 100 is coupled to the echo cancellation circuit 200 and the echo cancellation circuit 300 .

[0017] The data transmission circuit 100 includes a digital-to-analog conversion circuit (DAC) 110, a processing circuit 120, an analog-to-digital conversion circuit (ADC) 130, a storage circuit 140, a mixing circuit 150, and an update circuit 160. The DAC circuit 110 and the echo cancellation circuit 200 are coupled to the processing circuit 120. For example, the DAC circuit 110 and the echo cancellation circuit 200 may be coupled to the processing circuit 120 via a hybrid integrated circuit (hybrid) HY. The processing circuit 120 is coupled to the analog-to-digital conversion circuit 130. The analog-to-digital conversion circuit 130 is coupled to the storage circuit 140. The storage circuit 140 is coupled to the mixing circuit 150 and the update circuit 160. The mixing circuit 150 is coupled to the update circuit 160. The echo cancellation circuit 300 is coupled to the mixing circuit 150.

[0018] In operation, the digital-to-analog conversion circuit 110 can receive a digital transmission signal TX. The digital-to-analog conversion circuit 110 can generate an analog transmission signal TXC according to the digital transmission signal TX. For example, the digital-to-analog conversion circuit 110 can perform a digital-to-analog conversion process to convert the digital transmission signal TX into an analog transmission signal TXC. The analog transmission signal TXC can be output to the outside (outside the data transmission circuit 100) through the hybrid integrated circuit HY.

[0019] The processing circuit 120 can receive a reception signal RXC from an external source, and generate an analog processing signal AFE_O according to the reception signal RXC. In some embodiments, the processing circuit 120 is implemented by an analog front-end processing circuit.

[0020] However, in some cases (e.g., impedance mismatch between two transmission lines or mismatch in the hybrid integrated architecture of the receiving device), the analog transmission signal TXC may be introduced (e.g., introduced through the hybrid integrated circuit HY) into the transmission line carrying the reception signal RXC, thereby causing an echo.

[0021] The echo cancellation circuit 200 can also receive the digital transmission signal TX. The echo cancellation circuit 200 can generate an echo cancellation signal EC1 according to the digital transmission signal TX to cancel most of the echoes in the system at the analog end. For example, the hybrid integrated circuit HY can subtract the echo cancellation signal EC1 from the analog transmission signal TXC, and input the calculation result to the processing circuit 120. In some embodiments, the hybrid integrated circuit HY includes two current sources, one of which corresponds to the analog transmission signal TXC, and the other corresponds to the echo cancellation signal EC1. In some embodiments, the echo cancellation circuit 200 includes at least a digital-to-analog conversion circuit and a filter circuit (not shown in the figure).

[0022] The echo cancellation circuit 300 can also receive the digital transmission signal TX. The echo cancellation circuit 300 can generate an echo cancellation signal EC2 according to the digital transmission signal TX to eliminate the remaining echo at the digital end. In some embodiments, the echo cancellation circuit 300 includes at least one filter circuit (not shown).

[0023] The echo cancellation signal EC1 and the echo cancellation signal EC2 can eliminate the influence of the echo on the signal in the system, thereby improving the signal-to-noise ratio (SNR) of the system.

[0024] As mentioned above, if the analog transmission signal TXC is introduced into the transmission line carrying the receiving signal RXC, an echo will be caused. That is, the processing circuit 120 will receive part or all of the analog transmission signal TXC to generate the analog processing signal AFE_O according to the analog transmission signal TXC, the echo cancellation signal EC1 and the receiving signal RXC.

[0025] The analog-to-digital conversion circuit 130 may receive the analog processing signal AFE_O and perform an analog-to-digital conversion process on the analog processing signal AFE_O to convert the analog processing signal AFE_O into a digital value (codeword) CW.

[0026] refer to Figure 2A . Figure 2A is a schematic diagram showing the operation of the analog-to-digital conversion circuit 130 when the slice level SL does not deviate according to some embodiments of the present invention.

[0027] In practice, the analog-to-digital conversion circuit 130 may have a function of corresponding a plurality of slicer levels SL to a plurality of digital values ​​(codewords) CW (ie, an analog-to-digital conversion function). Figure 2AFor example, the clipping level SL includes the clipping level SL[-n]-SL[+n], and the digital value CW includes the digital value CW[-(n+1)]-CW[+n]. Further, any two adjacent clipping levels SL may correspond to a digital value CW. This digital value CW may be substantially equal to the middle value between the two adjacent clipping levels SL, but is not limited thereto. In operation, the analog-to-digital conversion circuit 130 may determine between which two adjacent clipping levels SL (i.e., the clipping level SL closest to and greater than the level of the analog processing signal AFE_O and the clipping level SL closest to and less than the level of the analog processing signal AFE_O) the level of the received analog processing signal AFE_O falls, and select and output the digital value CW corresponding to the two adjacent clipping levels SL. For example, the clipping level SL[+1] and the clipping level SL[0] correspond to the digital value CW[0]. Accordingly, if the analog-to-digital conversion circuit 130 determines that the level of the received analog processing signal AFE_O falls between the limiting level SL[+1] and the limiting level SL[0], then the analog-to-digital conversion circuit 130 will select the digital value CW[0] and output the digital value CW[0].

[0028] Based on the above operating principle, the analog-to-digital conversion circuit 130 will correspond all levels falling between the limit level SL[0] and the limit level SL[+1] to a single digital value CW[0]. It can be understood that the analog-to-digital conversion circuit 130 has multiple gears defined by level intervals. When the analog processing signal AFE_O falls within a specific level interval, the analog-to-digital conversion circuit 130 outputs the digital value CW corresponding to the gear. However, most of the values ​​of these levels are not exactly the same as the digital value CW[0], so there will be a difference (i.e., noise) between the level of the digital value CW output by the analog-to-digital conversion circuit 130 and the actual level of the analog processing signal AFE_O. These noises are also called quantization noise.

[0029] refer to Figure 2A as well as Figure 2B . Figure 2B is a schematic diagram showing the operation of the analog-to-digital conversion circuit 130 when the slice level SL deviates according to some embodiments of the present invention.

[0030] In some embodiments, these clipping levels SL may deviate from the originally designed level values ​​due to changes in the manufacturing process or ambient temperature. That is, the deviated clipping levels SL'[+n]-SL'[-n] respectively include deviation values ​​SH[-n]-SH[+n]. For example, Figure 2B If the difference between the deviation clipping level SL'[+1] and the deviation clipping level SL'[0] is greater than Figure 2AThe difference between the clipping level SL[+1] and the clipping level SL[0] in represents the Figure 2B There will be more levels corresponding to the single digital value CW[0] (i.e., the width of the clipping level interval corresponding to the same digital value increases). The level values ​​in these level intervals widened due to deviation have a larger difference with the digital value CW[0], thus increasing the quantization noise of the analog-to-digital conversion circuit 130.

[0031] In order to avoid the above problems, in the present invention, the storage circuit 140 may store a lookup table (such as Figure 3 In some embodiments, the storage circuit 140 is implemented by a register.

[0032] refer to Figure 3 . Figure 3 is a schematic diagram of a lookup table LUT according to some embodiments of the present invention. Figure 3 For example, the lookup table LUT records the digital values ​​CW[-n]-CW[+n] and the corresponding multiple offset values ​​OFF[-(n+1)]-OFF[+n].

[0033] Taking the digital value CW[0] as an example, in the lookup table LUT, the digital value CW[0] is mapped to the sum of the digital value CW[0] and the offset value OFF[0]. Figure 2B When determining that the level of the received analog processing signal AFE_O falls within the level interval between the deviation from the clipping level SL'[0] and the deviation from the clipping level SL'[+1], the analog-to-digital conversion circuit 130 may first select the corresponding digital value CW[0]. Figure 3 The lookup table LUT in the storage circuit 140 (or other control circuits operate using the lookup table LUT in the storage circuit 140) outputs the sum of the digital value CW[0] and the offset value OFF[0] as Figure 1 In some embodiments, the initial value of these offset values ​​OFF[-(n+1)]-OFF[+n] is 0, and can be updated by the update circuit 160 to converge to an appropriate value. This part will be described in detail in the following paragraphs.

[0034] Reference again Figure 1. After the digital value CW output by the analog-to-digital conversion circuit 130 is converted into the output signal OUT1 by the storage circuit 140, the mixing circuit 150 can receive the output signal OUT1. The mixing circuit 150 can generate the output signal OUT2 according to the output signal OUT1 and the echo cancellation signal EC2. For example, the mixing circuit 150 adds the output signal OUT1 to the echo cancellation signal EC2 to generate the output signal OUT2. The output signal OUT2 can reflect the received signal RXC and the error value ER. For example, the error value ER includes the echo and quantization noise that are not completely eliminated in the output signal OUT2 (for example: the quantization noise corresponding to the non-deviated clipping level, the quantization noise corresponding to the deviated clipping level).

[0035] In some embodiments, in the initial several working cycles (for example but not limited to 10 working cycles), the filter coefficients of the echo cancellation circuit 300 may be updated according to the output signal OUT2 and the least mean square (LMS) operation procedure. After the filter coefficients of the echo cancellation circuit 300 are stabilized, the offset values ​​OFF[-(n+1)]-OFF[+n] are updated (as shown in the following formula (1)). In each working cycle after the system is stabilized, the offset values ​​OFF[-(n+1)]-OFF[+n] may be updated more than once.

[0036] Reference again Figure 1 as well as Figure 3 As described above, the update circuit 160 may update the offset values ​​OFF[-(n+1)]-OFF[+n] in the lookup table LUT. For example, Figure 1 , if the analog-to-digital conversion circuit 130 selects and outputs the digital value CW[0], the update circuit 160 may update the offset value OFF[0] corresponding to the digital value CW[0] according to the digital value CW[0] and the output signal OUT2 (which may reflect the error value ER corresponding to the digital value CW[0]). In some embodiments, the update circuit 160 may update each offset value according to the following formula (1):

[0037] OFF[i]=OFF[i]-M×ER…Formula (1)

[0038] Wherein i ranges from -(n+1) to +n, n is a positive integer, OFF[i] on the right side of the equal sign is the current offset value, M is the strength value and can be designed according to system requirements, ER is the error value, and OFF[i] on the left side of the equal sign is the updated offset value.

[0039] The above strength values ​​are related to the eigenvalue of the least mean square procedure of the system and can range from 2 -10 ~2 -5, but the present invention is not limited to this scope.

[0040] For example, when the offset value OFF[0] is updated by the above formula (1), the updated offset value OFF[0] will approach or be substantially equal to the middle value between the deviation value SH[0] and the deviation value SH[+1].

[0041] The more times the analog-to-digital conversion circuit 130 selects and outputs the digital value CW[0], the closer the updated offset value OFF[0] will be to the intermediate value between the deviation value SH[0] and the deviation value SH[+1]. Accordingly, the quantization noise can be minimized. On the contrary, if the analog-to-digital conversion circuit 130 has never selected and output the digital value CW[0] (i.e., no cumulative times), the offset value OFF[0] will not be updated. However, if the digital value CW[0] has never been selected by the analog-to-digital conversion circuit 130, this relatively represents that there is no (or very few) corresponding level in the analog processing signal AFE_O. Therefore, even if the offset value OFF[0] is not updated, it will not affect the quantization noise.

[0042] It should be noted here that although Figure 1 In the embodiment, the offset value OFF[0] is updated according to the error value ER reflected by the node N1 where the output signal OUT2 is located. However, the present invention is not limited to the above. In some other embodiments, the offset value OFF[0] can be updated according to the error value reflected by other internal nodes of the back-end circuit.

[0043] Based on the above operation, the present invention can make the updated offset value OFF[0] close to or substantially equal to the middle value between the offset value SH[0] and the offset value SH[+1] without correcting the offset limit level SL'[0]-SL'[+1] of the analog-to-digital conversion circuit 130, so that the output signal OUT1 (the sum of the digital value CW[0] and the updated offset value OFF[0]) is roughly maintained at the middle value of the corresponding two offset limit levels, thereby minimizing the quantization noise and maintaining (or improving) the signal-to-noise ratio of the system.

[0044] In addition, for ease of understanding, the above content is described using the digital value CW[0] as an example. Other digital values ​​CW also have similar operations and will not be described in detail here.

[0045] refer to Figure 4 . Figure 4 is a schematic diagram of a signal-to-noise ratio according to some embodiments of the present invention. Figure 4 For example, after 10 operating cycles, the system's signal-to-noise ratio will improve by 1 to 3 dB.

[0046] Please also refer to Figures 1 to 5. Figure 5is a flow chart of an echo cancellation method 500 according to some embodiments of the present invention. The echo cancellation method 500 includes operations S510, S520, S530, S540, S550 and S560.

[0047] In operation S510, the analog transmission signal TXC is generated according to the digital transmission signal TX by the digital-to-analog conversion circuit 110. In some embodiments, the digital-to-analog conversion circuit 110 may perform a digital-to-analog conversion process to convert the digital transmission signal TX into the analog transmission signal TXC.

[0048] In operation S520, the echo cancellation circuit 200 generates an echo cancellation signal EC1 according to the digital transmission signal TX. In some embodiments, the echo cancellation circuit 200 includes at least a digital-to-analog conversion circuit and a filter circuit to generate the echo cancellation signal EC1, thereby canceling most of the echoes in the system at the analog end.

[0049] In operation S530, the processing circuit 120 generates an analog processing signal AFE_O according to the analog transmission signal TXC, the echo cancellation signal EC1 and the receiving signal RXC. In some embodiments, the processing circuit 120 is implemented by an analog front-end processing circuit.

[0050] In operation S540, the analog-to-digital conversion circuit 130 generates a digital value CW according to the analog processing signal AFE_O and the two clipping levels SL. In some embodiments, the digital value CW may be substantially equal to the middle value between the two clipping levels SL. If the analog-to-digital conversion circuit 130 determines that the level of the analog processing signal AFE_O falls between the two clipping levels SL, the analog-to-digital conversion circuit 130 outputs the digital value CW.

[0051] In operation S550, the lookup table LUT is stored by the storage circuit 140, and the output signal OUT1 is output according to the digital value CW and the offset value OFF corresponding to the digital value CW. In some embodiments, the two limit levels SL may deviate from the originally designed level values ​​due to changes in the manufacturing process or the ambient temperature. Accordingly, the offset value OFF can be updated according to the above formula (1), and the storage circuit 140 can output the sum of the digital value CW and the updated offset value OFF as the output signal OUT1 according to the digital value CW output by the analog-to-digital conversion circuit 130.

[0052] In operation S560 , the offset value OFF is updated according to the error value ER. In some embodiments, the offset value OFF is updated according to the above formula (1), and the error value ER is related to the output signal OUT1 of the storage circuit 140 .

[0053] In summary, in the echo cancellation system and the echo cancellation method of the present invention, the offset value can be updated according to the corresponding error value. Therefore, even if the clipping level deviates, the updated offset value can be used to keep the output signal roughly at the middle value of the two deviated clipping levels. In this way, the quantization noise can be minimized and the signal-to-noise ratio of the system can be maintained (or improved).

[0054] Although the present invention has been disclosed as above by way of embodiments, this is not intended to limit the present invention. Any technician with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the definition of the claims.

[0055] Description of reference numerals:

[0056] 100: Data transmission circuit

[0057] 110: Digital-to-analog conversion circuit

[0058] 120: Processing circuit

[0059] 130: Analog-to-digital conversion circuit

[0060] 140: Storage circuit

[0061] 150: Hybrid Circuit

[0062] 160: Update circuit

[0063] 200, 300: echo cancellation circuit

[0064] 500: echo cancellation method

[0065] S1: Echo Cancellation System

[0066] TX: digital transmission signal

[0067] TXC: Analog transmission signal

[0068] RXC: Receive signal

[0069] EC1, EC2: echo cancellation signal

[0070] HY: Hybrid Integrated Circuit

[0071] AFE_O: analog processing signal

[0072] SL, SL[+n]-SL[-n]: Limiting level

[0073] CW, CW[+n]-CW[-(n+1)]: digital value

[0074] SL'[+n]-SL'[-n]: Deviation from the limit level

[0075] SH[-n]-SH[+n]: deviation value

[0076] LUT: Look Up Table

[0077] OFF, OFF[-(n+1)]-OFF[+n]: offset value

[0078] OUT1, OUT2: output signal

[0079] ER: Error value

[0080] N1: Node

[0081] S510, S520, S530, S540, S550, S560: Operation

Claims

1. An echo cancellation system, comprising: A digital-to-analog conversion circuit, used to generate an analog transmission signal according to a digital transmission signal; a first echo cancellation circuit, configured to generate a first echo cancellation signal according to the digital transmission signal; a processing circuit for generating an analog processed signal according to the analog transmission signal, the first echo cancellation signal and a received signal; an analog-to-digital conversion circuit for generating a digital value according to the analog processed signal and two of the plurality of slice levels; as well as A storage circuit is used to store a lookup table, wherein the lookup table records an offset value corresponding to the digital value, wherein the storage circuit is also used to output a first output signal according to the digital value and the offset value, wherein the offset value is updated according to an error value related to the first output signal.

2. The echo cancellation system according to claim 1, characterized in that: Also includes: a second echo cancellation circuit, configured to generate a second echo cancellation signal according to the digital transmission signal; as well as A mixing circuit is used to generate a second output signal according to the first output signal and the second echo cancellation signal.

3. The echo cancellation system according to claim 2, characterized in that: The second output signal reflects the received signal and the error value.

4. The echo cancellation system according to claim 2, characterized in that: An initial value of the offset value corresponding to the digital value is 0.

5. The echo cancellation system according to claim 4, characterized in that: The offset value corresponding to the digital value is updated according to a current offset value, a strength value, and the error value.

6. The echo cancellation system according to claim 5, characterized in that: The two clipping levels correspond to two offset values, and the offset value corresponding to the digital value is updated according to the two offset values ​​corresponding to the two clipping levels to generate an updated offset value, and a sum of the digital value and the updated offset value is the first output signal.

7. The echo cancellation system according to claim 6, characterized in that: The updated offset value is substantially equal to a middle value between the two deviation values ​​corresponding to the two slice levels.

8. The echo cancellation system according to claim 2, characterized in that: Also includes: An update circuit is coupled to the storage circuit and the mixing circuit to receive the digital value and the second output signal respectively, and then update the offset value corresponding to the digital value.

9. The echo cancellation system according to claim 2, characterized in that: A plurality of filter coefficients of the second echo cancellation circuit are updated according to the second output signal and a least mean square operation procedure.

10. An echo cancellation method, comprising: Generate an analog transmission signal according to a digital transmission signal through a digital-to-analog conversion circuit; Generate a first echo cancellation signal according to the digital transmission signal through a first echo cancellation circuit; Generate an analog processed signal by a processing circuit according to the analog transmission signal, the first echo cancellation signal and a receiving signal; Generate a digital value according to the analog processed signal and two of the plurality of slice levels by an analog-to-digital conversion circuit; A storage circuit stores a lookup table and outputs a first output signal according to the digital value and an offset value corresponding to the digital value, wherein the lookup table records the offset value; as well as The offset value in the lookup table is updated according to an error value related to the first output signal.

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