A RISC-V-based SOC startup method

Abstract

The present invention relates to the field of microelectronics, and more particularly to a RISC-V-based SOC startup method, comprising the following steps: setting a startup mode by setting chip pin levels; storing a ZSBL program in a BootROM and executing the ZSBL program after a chip power-on reset; executing the ZSBL program to connect to an SPI controller and, depending on the startup mode, transfer a FSBL program from an SPI SD card or SPI FLASH to an ITIM; jumping to the ITIM to execute the FSBL program; the FSBL program to configure a PLL frequency increase, cancel a DDR controller reset, perform DDR memory control training, and then transfer a BBL and an OS to the DDR; and jumping to the BBL program and OS program in the DDR to complete system startup. The present invention has the following beneficial effects: using the ITIM to perform the startup process improves the efficiency of SOC startup.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and in particular to a RISC-V-based SOC startup method. Background Art

[0002] The currently widely used SoC power-up process allows program execution from two different addresses: external Flash memory and internal ROM. The power-up address can be selected using the chip pin value. When executing from external Flash memory, the software sets up a bootloader at power-up, transfers the code and data from the Flash memory to the ITCM and DTCM, and then jumps to the ITCM to begin execution. When executing from ROM, fixed code is stored in the ROM and then jumps directly to the ITCM for continued execution. This method of executing from the internal ROM and then the ITCM is only useful during debugging, when the debugger initializes the ITCM. Otherwise, due to the lack of an initialization program in the ITCM, normal execution will not occur. As shown above, the ITCM and DTCM are used as instruction and data memory, but lack cache and DDR, thus failing to fully utilize the time-sharing multiplexing advantages of TCM and cache switching. Furthermore, only two startup modes, Flash and ROM, are supported. Another SoC boot process includes: after power-on reset, the PC points to the Reset Vector ROM to determine the boot mode; the ZSBL moves the FSBL from the L2 LIM based on the pin selection; the FSBL configures the PLL for frequency upscaling; configures the DDR PLL, PHY, and controller; downloads the BBL to the DDR memory; enables the L2 LIM to be configured in L2 cache mode; and jumps to the DDR memory to execute the BBL. As can be seen above, while this approach improves boot efficiency by reusing the L2 cache as the LIM boot memory, most single-core SoCs currently do not utilize L2 cache, making this solution unsuitable for a wider range of SoCs. Therefore, research on SoC boot technology is necessary to improve boot efficiency and provide a wider range of boot modes.

[0003] After searching, the applicant discovered that Chinese Patent CN102467472A is the prior art closest to the present application. Its publication date is May 23, 2012, and it discloses a BOOT startup device for a SOC chip, comprising: a memory interface module, provided with a memory bus interface for connecting to an external memory; a DMA bus interface module, provided with a DMA bus interface for transferring data from the external memory to a storage space corresponding to a target address; a BOOT processing module, connected to the memory interface module and the DMA bus interface module, for sending data read and write commands to the external memory via the memory interface module and converting data transmitted from the external memory into data compatible with the DMA bus interface module; and a parameter configuration module for configuring the parameters of the DMA bus interface module, the memory interface module, and the BOOT processing module. This improves the startup efficiency of the SOC by adding hardware, which introduces new hardware and increases the cost of the SOC, but still fails to solve the current problem of low SOC startup efficiency. Summary of the Invention

[0004] The present invention aims to solve the technical problem of the current lack of a high-efficiency startup solution suitable for commonly used SOCs. This paper proposes a RISC-V-based SOC startup method that can improve the startup efficiency of SOCs supporting the RISC-V architecture.

[0005] To solve the above technical problems, the present invention adopts the following technical solution: a RISC-V-based SOC startup method, comprising the following steps:

[0006] The boot mode is set by setting the chip pin level, and the boot mode includes a maintenance boot mode and a self-boot boot mode. In the maintenance boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI SDCard, and in the self-boot boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI FLASH.

[0007] Store the ZSBL program in BootRom, and execute the ZSBL program from BootRom after the chip is powered on and reset;

[0008] The ZSBL program executes to open the SPI controller and, depending on the boot mode, moves the FSBL program from the SPI SD Card or SPI FLASH to the ITIM;

[0009] After the ZSBL program is executed, it jumps to ITIM to execute the FSBL program;

[0010] The FSBL program configures the PLL frequency increase, cancels the DDR controller reset and performs DDR memory control training, and then moves the BBL and OS from the SPI SD Card or SPI FLASH to the DDR;

[0011] After the FSBL program is executed, it jumps to the BBL program and OS program in the DDR, thus completing the system startup.

[0012] Preferably, the method for executing the ZSBL program from BootRom includes:

[0013] After the chip is powered on and reset, the core PC points to the MSEL register of the Modelsel ROM and takes the value. The jump is performed according to the value of the MSEL register. The value of the MSEL register of the Modelsel ROM is determined by the chip pin;

[0014] When the value of the MSEL register is 00B, it is started in Debug mode and the PC jumps to the interrupt service routine of the debugger module. When the value of the MSEL register is not 00B, it is started in BootRom mode and the PC jumps to the ZSBL program in BootRom.

[0015] Preferably, the ZSBL program specifically performs the following steps:

[0016] Select to move the FSBL program from SPI FLASH or SPI SD card according to the value of the MSEL register. If the value of the MSEL register is 01B or 11B, the FSBL program is moved from SPI FLASH to ITIM. If the value of the MSEL register is 10B, the FSBL program is moved from the SPI SD card to ITIM.

[0017] Jump the PC to the starting address of the FSBL program in ITIM to complete the execution of the ZSBL program.

[0018] Preferably, the method for configuring ITIM includes:

[0019] Configure ICache in ITIM mode, including:

[0020] Create an ITIM entry in ICache. The last row of ITIM entries is used to exit ITIM mode.

[0021] After the chip is powered on and reset, when writing to the ITIM entries, the empty entries of the ITIM are directly requested for use. When the last row of ITIM entries is written, the ITIM mode is exited.

[0022] Preferably, the method for transferring the FSBL program to the ITIM comprises:

[0023] Writing to the row address of ITIM simultaneously obtains the allocation of ITIM space;

[0024] Read the FSBL program segments in sequence and write them starting from the address of row 0 of ITIM;

[0025] After all FSBL programs are written into ITIM, writing 0 to the next row of ITIM addresses means releasing ITIM space and exiting ITIM mode.

[0026] After the core executes the FSBL program, it will read the 0 at the last row of ITIM address, then release the ITIM space and exit ITIM mode.

[0027] Preferably, the FSBL program specifically performs the following steps:

[0028] Configuring PLL parameters, which are stored in the SCU component, and enabling frequency upscaling;

[0029] After checking if the PLL is locked, switch the core to the target frequency;

[0030] Undo device reset, undo DDR reset;

[0031] Conduct DDR memory control training;

[0032] Load the BBL program and OS program from SPI FLASH or SPI SD card into DDR, and use 0x8000_0000 address of DDR as the starting address;

[0033] The PC jumps to 0x8000_0000 to execute the BBL program and OS program, completing the system startup.

[0034] Preferably, the PLL includes a Core PLL and a DDR PLL, and after checking that both the Core PLL and the DDR PLL are locked, the core is switched to the target frequency.

[0035] The beneficial effects of the present invention include: using ITIM to carry out the startup process, thereby improving the efficiency of SOC startup; having low requirements for SOC hardware and being applicable to the startup of a wider range of SOCs; providing multiple startup modes, facilitating the startup of SOCs for different purposes.

[0036] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described below with reference to the accompanying drawings:

[0038] Figure 1 The figure is a flow chart of a RISC-V-based SOC startup method according to an embodiment of the present invention.

[0039] Figure 2 The figure is a flow chart of a method for executing a ZSBL program from BootRom according to an embodiment of the present invention.

[0040] Figure 3 Schematic diagram of the ZSBL program execution method according to an embodiment of the present invention.

[0041] Figure 4 The figure is a flowchart of a method for configuring ITIM according to an embodiment of the present invention.

[0042] Figure 5 FIG. 4 is a flow chart of a method for transferring an FSBL program to an ITIM according to an embodiment of the present invention.

[0043] Figure 6 FIG. 1 is a flow chart of a FSBL program execution method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following is an explanation and description of the technical solutions of the embodiments of the present invention in conjunction with the drawings of the embodiments of the present invention. However, the following embodiments are only preferred embodiments of the present invention and are not exhaustive. Based on the embodiments in the implementation manner, other embodiments obtained by those skilled in the art without creative work are all within the scope of protection of the present invention.

[0045] In the following description, terms such as "inside", "outside", "up", "down", "left", "right", etc. that indicate directions or positional relationships are only used to facilitate the description of the embodiments and simplify the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0046] Glossary: ZSBL (Zero Stage Bootloader), initial stage loader. FSBL (first stage boot loader), first stage loader. SOC (system on chip), system-on-chip. RISC-V is an open instruction set architecture (ISA) based on the principles of reduced instruction set computing (RISC). V stands for fifth-generation RISC. RISC (Reduced Instruction Set Computer RISC), reduced instruction set computer. ITIM (Instruction Tightly Integrated Memory), iCache (Instruction Cache). PLL (Phase-Locked Loops), phase-locked loop or frequency multiplier. OS (Operating System), operating system. BBL (BIOS boot loader), second-stage boot program.

[0047] A RISC-V based SOC startup method, please refer to the attached Figure 1 , including the following steps:

[0048] Step A01) setting a boot mode by setting chip pin levels. The boot modes include a maintenance boot mode and a self-boot boot mode. In the maintenance boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI SDCard. In the self-boot boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI FLASH.

[0049] Step A02) storing the ZSBL program in the BootROM, and executing the ZSBL program from the BootROM after the chip is powered on and reset;

[0050] Step A03) The ZSBL program executes to open the SPI controller and, depending on the boot mode, moves the FSBL program from the SPI SD Card or SPI FLASH to the ITIM;

[0051] Step A04) After the ZSBL program is executed, jump to the ITIM to execute the FSBL program;

[0052] Step A05) The FSBL program configures the PLL to increase the frequency, cancels the DDR controller reset, and performs DDR memory control training, and then moves the BBL and OS from the SPI SD card or SPI FLASH to the DDR;

[0053] Step A06) After the FSBL program is executed, it jumps to the BBL program and OS program in the DDR, completing the system startup. Using the storage space in the ITIM mode can improve the efficiency of the startup.

[0054] Please see the attached Figure 2 , the methods for executing the ZSBL program from BootRom include:

[0055] Step B01) After the chip is powered on and reset, the core PC points to the MSEL register of the Modelsel ROM and takes a value, and jumps according to the value of the MSEL register. The value of the MSEL register of the Modelsel ROM is determined by the chip pin;

[0056] Step B02) If the MSEL register value is 00B, the system boots in debug mode, and the PC jumps to the debugger module's interrupt service routine. If the MSEL register value is not 00B, the system boots in boot ROM mode, and the PC jumps to the ZSBL routine in the boot ROM. After power-on reset, the core, S_Bus, and ModelsEL ROM operate at an external crystal oscillator at 50 MHz. The core PC points to 0x1004, and the PC jumps based on MSEL[1:0]. The contents of the ModelsEL ROM are shown in Table 1. 0x1004 is the MSEL register address.

[0057] Table 1 Modelsel ROM contents

[0058] Address Contents 0x1000 The MSEL pin state 0x1004 auipc t0,0 0x1008 lw t1,-4(t0) 0x100c slli t1,t1,0x3 0x1010 add t0, t0, t1 0x1014 lw t0,252(t0) 0x1018 jr,t0

[0059] Select Debug mode or Boot ROM mode based on MSEL[1:0]. Table 2 shows the mapping between the MSEL register contents and the boot mode. The corresponding boot mode is implemented based on the MSEL register contents. The MSEL register stores two bits of data.

[0060] Table 2 Mapping table between MSEL register contents and startup modes

[0061]

[0062] Please see the attached Figure 3 , the ZSBL program specifically performs the following steps:

[0063] Step C01) Selecting to transfer the FSBL program from the SPI FLASH or the SPI SD card based on the value of the MSEL register, as shown in Table 3, if the value of the MSEL register is 01B or 11B, the FSBL program is transferred from the SPI FLASH to the ITIM; if the value of the MSEL register is 10B, the FSBL program is transferred from the SPI SD card to the ITIM;

[0064] Step C02) Jump the PC to the starting address of the FSBL program in ITIM to complete the execution of the ZSBL program.

[0065] Table 3 Mapping table between MSEL register contents and FSBL program storage locations

[0066] MSEL FSBL location 01 SPI FLASH 10 SPI SD card 11 SPI FLASH

[0067] Please see the attached Figure 4 , the methods for configuring ITIM include:

[0068] Configure ICache in ITIM mode, including:

[0069] Step D01) creating an ITIM entry in the ICache, where the last row of ITIM entries is used to exit ITIM mode;

[0070] Step D02) After the chip is powered on and reset, when writing to the ITIM entries, directly apply for the use of empty entries in the ITIM. When writing to the last row of ITIM entries, exit the ITIM mode.

[0071] Please see the attached Figure 5 , the methods for porting FSBL programs to ITIM include:

[0072] Step E01) writing to the row address of the ITIM simultaneously obtains the allocation of ITIM space;

[0073] Step E02) reading the FSBL program segments in sequence and performing write operations starting from the row 0 address of the ITIM;

[0074] Step E03) After all FSBL programs are written into the ITIM, writing 0 to the next row of ITIM addresses indicates releasing the ITIM space and exiting the ITIM mode.

[0075] After the core executes the FSBL program, it will read the 0 at the last row of ITIM address, then release the ITIM space and exit ITIM mode.

[0076] Please see the attached Figure 6 , the FSBL program specifically performs the following steps:

[0077] Step F01) configuring PLL parameters, storing the PLL parameters in the SCU component, and enabling frequency upscaling;

[0078] Step F02) After checking if the PLL is locked, switch the core to the target frequency;

[0079] Step F03) canceling the device reset and canceling the DDR reset;

[0080] Step F04) performing DDR memory control training;

[0081] Step F05) Load the BBL program and OS program from the SPI FLASH or SPI SD card into the DDR, with the 0x8000_0000 address of the DDR as the starting address;

[0082] Step F06) The PC jumps to 0x8000_0000 to execute the BBL program and the OS program, completing the system startup.

[0083] The PLL includes the Core PLL and DDR PLL. After checking that both the Core PLL and DDR PLL are locked, switch the core frequency to the target frequency.

[0084] The beneficial effects of this embodiment include: using ITIM to carry out the startup process to improve the efficiency of SOC startup; having low requirements for SOC hardware and being applicable to the startup of a wider range of SOCs; providing multiple startup modes to facilitate the startup of SOCs for different purposes.

[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Those skilled in the art will understand that the present invention includes, but is not limited to, the contents described in the drawings and the above specific embodiments. Any modifications that do not deviate from the functional and structural principles of the present invention are intended to be included within the scope of the claims.

Claims

1. A RISC-V based SOC startup method, characterized in that: The following steps are involved: The boot mode is set by setting the chip pin level, and the boot mode includes a maintenance boot mode and a self-boot boot mode. In the maintenance boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI SDCard, and in the self-boot boot mode, the FSBL program, the BBL program, and the OS program are stored in the SPI FLASH. Store the ZSBL program in BootRom, and execute the ZSBL program from BootRom after the chip is powered on and reset; The ZSBL program executes to open the SPI controller and, depending on the boot mode, moves the FSBL program from the SPI SD Card or SPI FLASH to the ITIM; After the ZSBL program is executed, it jumps to ITIM to execute the FSBL program; The FSBL program configures the PLL frequency increase, cancels the DDR controller reset and performs DDR memory control training, and then moves the BBL and OS from the SPI SD Card or SPI FLASH to the DDR; After the FSBL program is executed, it jumps to the BBL program and OS program in the DDR, thus completing the system startup.

2. A RISC-V based SOC startup method according to claim 1, characterized in that: Methods for executing the ZSBL program from BootRom include: After the chip is powered on and reset, the core PC points to the MSEL register of the Modelsel ROM and takes the value. The jump is performed according to the value of the MSEL register. The value of the MSEL register of the Modelsel ROM is determined by the chip pin; When the value of the MSEL register is 00B, it is started in Debug mode and the PC jumps to the interrupt service routine of the debugger module. When the value of the MSEL register is not 00B, it is started in BootRom mode and the PC jumps to the ZSBL program in BootRom.

3. A RISC-V based SOC startup method according to claim 2, characterized in that: The ZSBL program specifically performs the following steps: Select to move the FSBL program from SPI FLASH or SPI SD card according to the value of the MSEL register. If the value of the MSEL register is 01B or 11B, the FSBL program is moved from SPI FLASH to ITIM. If the value of the MSEL register is 10B, the FSBL program is moved from the SPI SD card to ITIM. Jump the PC to the starting address of the FSBL program in ITIM to complete the execution of the ZSBL program.

4. A RISC-V based SOC startup method according to any one of claims 1 to 3, characterized in that: Methods for configuring ITIM include: Configure ICache in ITIM mode, including: Create an ITIM entry in ICache. The last row of ITIM entries is used to exit ITIM mode. After the chip is powered on and reset, when writing to the ITIM entries, it directly applies for the empty entries of the ITIM. When the last row of ITIM entries is written, the ITIM mode is exited.

5. A RISC-V based SOC startup method according to claim 4, characterized in that: Methods for migrating FSBL programs to ITIM include: Writing to the row address of ITIM simultaneously obtains the allocation of ITIM space; Read the FSBL program segments in sequence and write them starting from the row 0 address of ITIM; After all FSBL programs are written into ITIM, writing 0 to the next row of ITIM addresses means releasing ITIM space and exiting ITIM mode.

6. A RISC-V based SOC startup method according to any one of claims 1 to 3, characterized in that: The FSBL program specifically performs the following steps: Configuring PLL parameters, which are stored in the SCU component, and enabling frequency upscaling; After checking if the PLL is locked, switch the core to the target frequency; Undo device reset, undo DDR reset; Conduct DDR memory control training; Load the BBL program and OS program from SPI FLASH or SPI SD card into DDR, and use 0x8000_0000 address of DDR as the starting address; The PC jumps to 0x8000_0000 to execute the BBL program and OS program, completing the system startup.

7. A RISC-V based SOC startup method according to any one of claims 1 to 3, characterized in that: The PLL includes a Core PLL and a DDR PLL. After checking that both the Core PLL and the DDR PLL are locked, the core is switched to the target frequency.

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