Method and system for storing high read data at a low impact read disturb page of a memory device

Abstract

This application relates to storing high read data at low impact read disturb pages of a memory device. A high read data manager of a memory device receives a request to perform a data relocation operation on a first word line of a plurality of word lines of the memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines that the first word line comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion related to additional data stored on additional word lines of the plurality of word lines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target word line for relocating the data; and responsive to identifying the one or more low read disturb pages of the target word line, stores at least a portion of the data at the one or more low read disturb pages of the target word line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to storing high read data at low impact read disturb pages of a memory device. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] According to an aspect of the present application, a method is provided. The method includes receiving, by a processing device, a request to perform a data relocation operation on a first word line of a plurality of word lines of a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determining that the first word line comprises data stored at one or more high read disturb pages of the plurality of pages; determining whether the data comprises a characteristic that satisfies a threshold criterion related to additional data stored on additional word lines of the plurality of word lines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifying one or more low read disturb pages of the plurality of pages of a target word line for relocating the data; and responsive to identifying the one or more low read disturb pages of the target word line, storing at least a portion of the data at the one or more low read disturb pages of the target word line.

[0004] According to another aspect of the present application, a method is provided. The method includes receiving, by a processing device, a request to write data to a memory device, wherein the request comprises an indication that the data has a characteristic, and wherein the memory device comprises a plurality of multi-level memory cells, and wherein each multi-level memory cell comprises a plurality of pages; identifying, by the processing device, a target word line of a plurality of word lines of the memory device in view of the characteristic; selecting one or more low read disturb pages of the plurality of pages of the target word line; and storing at least a portion of the data at the one or more low read disturb pages of the target word line.

[0005] According to yet another aspect of the present application, a system is provided. The system comprises: a memory device; and a processing device operably coupled with the memory device to perform operations comprising: receiving, by the processing device, a request to perform a data relocation operation on a first word line of a plurality of word lines of a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determining that the first word line comprises data stored at one or more high read disturbance pages of the plurality of pages; determining whether the data comprises a characteristic that satisfies a threshold criterion related to additional data stored on additional word lines of the plurality of word lines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifying one or more low read disturbance pages of the plurality of pages of a target word line for relocating the data; and responsive to identifying the one or more low read disturbance pages of the target word line, storing at least a portion of the data at the one or more low read disturbance pages of the target word line. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will become more fully understood from the detailed description given herein and from the accompanying drawings, wherein various embodiments of the disclosure are shown. The drawings are intended to be illustrative and not limiting.

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the present disclosure is illustrated.

[0008] Figure 2 is a flow diagram of an example method to facilitate relocating high read data to low impact read disturbance pages of a memory device according to some embodiments of the present disclosure.

[0009] Figures 3A-3B An example of relocating high read data to low impact read disturbance pages of a memory device according to some embodiments of the present disclosure is illustrated.

[0010] Figure 4 is a flow diagram of an example method to store high read data at low impact read disturbance pages of a memory device based on a write request according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to expediting configuration updates of a memory device. The memory sub-system can be a storage device, a memory module, or a combination of a storage device and a memory module. The following description is made in connection with a storage device. Figure 1Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0013] A memory sub-system can include high-density non-volatile memory devices in which data is expected to be retained when power is not supplied to the memory devices. One example of a non-volatile memory device is a "not-and" (NAND) memory device. Below, reference is made to a NAND memory device as an example of a non-volatile memory device. However, the examples described below can be applicable to other types of non-volatile memory devices. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a group of physical blocks. Each block is composed of a group of pages. Each page is composed of a group of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store binary information of one or more bits and has various logic states related to the number of bits being stored. The logic states can be represented by binary values, such as "0" and "1" or a combination of such values.

[0014] A memory device can include multi-level memory cells. Each multi-level memory cell can be configured with different page levels, where each page level can be used to store a particular significant bit level of the memory cell. For example, a memory device configured with multi-level cells (MLC) can store two bits per cell. In such an example, the MLC can include a lower page for programming the least significant bit of the MLC and a higher page (or upper page) for programming its most significant bit. Similarly, a memory device configured with triple-level cells (TLC) can store three bits per cell. In such an example, the TLC can include a lower page for programming the least significant bit of the TLC and multiple higher pages - an upper page and an additional page - for programming its second and most significant bits, respectively.

[0015] In a conventional memory sub-system, data can be read as a series of word lines within a block. Typically, when data is read from the memory cells of a word line, a particular pass voltage is applied to that word line to perform the read operation. At the same time, a higher voltage level is applied to the word lines adjacent to the word line being read. This higher voltage causes the memory cells of the adjacent word lines to appear transparent to the storage sub-system such that they do not interfere with the read operation. In some examples, a particular word line can include data that is more frequently read than data stored in other word lines in a particular data block. This frequently accessed data can be generally referred to as "high read" or "hot read" data.

[0016] A word line containing high read data can have a parasitic effect on neighboring word lines because repeated reads of a particular word line can cause repeated application of higher pass voltages to those neighboring word lines. This can result in a condition known as read disturb. Read disturb is an error condition that can occur when one or more bits are changed during a read operation, causing an increase in the original bit error rate (RBER) of those bits. As noted above, due to the repeated application of higher voltages applied to these word lines during read operations, unselected word lines can experience high read disturb level stress. The severity of read disturb on neighboring word lines can significantly increase when data being repeatedly read is stored in a page of memory cells that are subject to greater read stress than other pages (i.e., "high read disturb pages"). In conventional systems, this is due to a large difference between the voltage necessary to perform a data read from certain pages (e.g., lower pages (least significant bits)) and the high pass voltage applied to unselected neighboring word lines. The significant increase in read disturb experienced by unselected pages can result in a significant increase in bit error rate over a shorter period of time. This, in turn, can result in a decrease in data reliability and performance, as well as a significantly shortened memory device useful life.

[0017] Conventional memory sub-systems do not make significant attempts to mitigate these problems, but instead opt to perform garbage collection and / or folding operations more frequently. Additionally, when performing these operations, conventional systems typically move all valid data sequentially to another location. These solutions typically do not take into account the cause of read disturb degradation.

[0018] Aspects of the present disclosure address the above and other deficiencies by storing high read data at low impact read disturb pages of a memory device. In one embodiment, a high read data manager of a memory sub-system controller can receive a request to perform a data relocation operation (e.g., a garbage collection operation, a data folding operation, etc.). The high read data manager can determine whether the data selected for relocation is high read data, and if so, intelligently select a target word line for relocating the high read data to reduce the impact of read disturb on neighboring word lines. Additionally, the high read data manager can store the high read data on a page that is subject to a minimal amount of read disturb or a lower amount of read disturb compared to other pages of memory cells of the target word line (i.e., a "low read disturb page") to significantly reduce the impact of applying higher voltages on unselected neighboring word lines. In another embodiment, the high read data manager can receive a request to write new data to a memory device, where the write request specifies that the high read data. The high read data manager can utilize a similar process to identify a low read disturb page of a target word line for writing the high read data to in order to reduce the impact of read disturb on unselected neighboring word lines.

[0019] Advantages of the present disclosure include, but are not limited to, significantly reducing the read disturb impact of high read data on neighboring unselected word lines. By actively identifying high read data and positioning that data to a low read disturb page of a target memory cell, the difference between the pass voltages applied to neighboring word lines can be significantly reduced. This can significantly reduce the read disturb impact on unselected neighboring word lines caused by high read data. Additionally, by reducing the overall read disturb impact, the reliability and performance of the memory device can be significantly improved as the memory device can tolerate higher read disturb before performing a garbage collection operation or a folding operation. This in turn can result in a significantly reduced write amplification rate, which can further improve the performance and reliability of the memory device.

[0020] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination thereof.

[0021] The memory sub-system 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0023] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to multiple memory sub-systems 110 of different types. Figure 1An example of a host system 120 coupled to a memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0024] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0025] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 A memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0027] Some examples of non-volatile memory devices (e.g., memory devices 130) include “NAND” type flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without a prior erasure of the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device used to store data. For some types of memory, such as NAND, pages can be grouped to form blocks.

[0029] Although non-volatile memory components are described, such as 3D cross-point arrays of non-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “NOR” flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0030] The memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry having specialized (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory sub-system controller 115 can include a processing device configured to execute instructions stored in local memory 119, including one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that handle the control of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0032] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the local memory 119 is illustrated as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1 The example memory sub-system 110 in FIG. 1 is illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., by an external host, or provided by a processor or controller separate from the memory sub-system).

[0033] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130 and convert responses associated with memory devices 130 into information for host system 120.

[0034] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from memory sub-system controller 115 and decode the addresses to access memory devices 130.

[0035] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory device, which is a raw memory device 130 with control logic on-die (e.g., local controller 132) and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] Memory sub-system 110 can include a high read data manager 113 that can be used to relocate and / or store high read data at low impact read disturb pages of memory devices 130. In some embodiments, memory sub-system controller 115 includes at least a portion of high read data manager 113. In some embodiments, high read data manager 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of high read data manager 113 and is configured to perform the functionality described herein.

[0037] In various implementations, the high read data manager 113 can receive a request to perform a data relocation operation on data stored on a source word line of a data block of the memory device 130, 140. The relocation operation can be a garbage collection operation, a data folding operation, etc. The memory device 130, 140 can include multi-level memory cells. Each multi-level memory cell can be configured with different page levels, where each page level can be used to store a particular valid bit level of the memory cell. For example, a memory device configured with multi-level cells (MLC) can store two bits per cell. In such an example, the MLC can include a lower page for programming the least significant bit of the MLC and a higher page (or upper page) for programming its most significant bit. Similarly, a memory device configured with triple-level cells (TLC) can store three bits per cell. In such an example, the TLC can include a lower page for programming the least significant bit of the TLC and multiple higher pages - an upper page and an additional page - for programming its second and most significant bits, respectively. In other embodiments, the memory device can be configured as any other memory type, such as quad-level cells (QLC) memory, penta-level cells (PLC) memory, etc., or memory that stores a non-integer number of bits per cell (e.g., 3.5 bits per cell, 4.5 bits per cell).

[0038] In response to receiving the request, the high read data manager 113 can determine that the source word line to be relocated includes data stored at a high read disturb page of that word line. The high read data manager 113 can then determine whether the data of that source word line is high read (or "hot read") data. As described in further detail below, the high read data manager 113 can make this determination by analyzing memory cells of word lines adjacent to the source word line. If the high read data manager 113 determines that the data stored in the source word line is high read data, one or more target word lines of a target data block can be identified to store the relocated data. Subsequently, the high read data manager 113 can store the data in a low read disturb page of the target word line or target word lines.

[0039] In some implementations, the high read data manager 113 can be invoked in response to receiving a write request from a host system to write new data to the memory device 130, 140. In such an example, the received request can include an indication that the data to be written to the memory device 130, 140 is data that is to be high read. The high read data manager 113 can utilize the techniques described above (and below with respect to FIG. 2) to determine whether the data to be written is high read data. If the data is determined to be high read data, the high read data manager 113 can identify one or more target word lines of a target data block to store the data. Subsequently, the high read data manager 113 can store the data in a low read disturb page of the target word line or target word lines. Figure 4The process can be similar to the process described above with respect to identifying one or more target word lines in a target data block to store the data. Subsequently, the high read data manager 113 can store the data in a low read disturbance page of the identified target word line.

[0040] The following description relates to Figures 2-4 Further details describing the operation of the high read data manager 113 are described below.

[0041] Figure 2 is an example method 200 to facilitate relocating high read data to a low impact read disturbance page of a memory device, in accordance with some embodiments of the present disclosure. The method 200 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by the high read data manager 113 of the memory device 130. Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 210, the processing logic receives a request to perform a data relocation operation on a word line of a memory device (e.g., the memory device 130 in the memory system 100). Figure 1 In some implementations, the relocation operation can be part of a memory management operation, such as a garbage collection operation to relocate data from one data block stripe of a memory device to a new destination block stripe of that memory device. The request to perform a garbage collection operation or other memory management operation can be initiated in response to determining that a data consolidation is to be performed on a candidate data block to free up memory resources for a subsequent program / erase cycle. In other implementations, the data relocation operation can be a folding operation to migrate data from one memory device location to another memory device location. The request to perform a folding operation can be initiated to pack valid data together, which can free up more memory device storage space for additional program operations, error avoidance operations, wear leveling operations, etc. In some implementations, the folding operation can be performed as part of a garbage collection operation. In various implementations, the request can be initiated in response to detecting a high error rate for a particular data block of a memory device, detecting a high read disturbance level for a word line of a particular data block of a memory device, etc.

[0043] As described above, the memory device can include multi-level memory cells. Each multi-level memory cell can be configured with different page levels, where each page level can be used to store a particular valid bit level of the memory cell. For example, a memory device configured with multi-level cells (MLC) can store two bits per cell. In such an example, the MLC can include a lower page for programming the least significant bit of the MLC and a higher page (or upper page) for programming its most significant bit. Similarly, a memory device configured with triple-level cells (TLC) can store three bits per cell. In such an example, the TLC can include a lower page for programming the least significant bit of the TLC and multiple higher pages - an upper page and an additional page - for programming its second and most significant bits, respectively.

[0044] At operation 220, the processing logic determines that the first word line includes data stored at one or more high read disturb pages. In various embodiments, the processing logic can analyze the word lines of the data block to be relocated and determine, prior to relocating the data, whether the data of a particular word line is programmed at a high read disturb page or a low read disturb page of the memory cell. As described above, since data stored at a high read disturb page can cause a significantly higher level of read disturb in neighboring word lines, the processing logic can identify those word lines having data stored at a high read disturb page to facilitate efficient relocation of high read data.

[0045] At operation 230, the processing logic determines whether the data stored at the high read disturb pages of the source word line includes a data characteristic that satisfies a threshold criterion related to the data stored on other word lines in the source data block of the memory device. In various embodiments, the threshold criterion can be associated with data that is actively read, high read, hot read, etc. In other words, determining that the data characteristic satisfies the threshold can indicate that the data is high read. As described above, since data stored at a high read disturb page of one word line can cause a higher level of read disturb in neighboring word lines, high read data can significantly increase the read disturb impact on neighboring word lines. In some embodiments, the processing logic can make this determination based on the number of read operations performed on the data of the word line. In such an example, the processing logic can determine a read count associated with the source word line, where the read count includes an indication of the number of host read operations performed on the memory cells of that word line.

[0046] The memory sub-system controller can maintain one or more counters associated with read operations performed to the memory device. In various implementations, the counter(s) can be maintained based on different levels of granularity. For example, a counter can track read operations performed on a particular data block, logical block address (LBA), word line address, etc. Processing logic can use the counter(s) maintained by the sub-system controller to determine a read count. Once the read count has been determined, the processing logic can determine whether the read count satisfies a read threshold criterion associated with a high read data condition. In various implementations, the read threshold criterion can specify a particular number of read operations performed, a percentage of read operations performed on a source word line relative to total read operations performed on a data block, a percentage of read operations performed on a source word line relative to neighboring word lines, etc. Responsive to determining that the number of read operations performed on the source word line satisfies the threshold, the processing logic can determine that the source word line contains high read data. Otherwise, the processing logic can determine that the source word line does not contain high read data.

[0047] In some implementations, the processing logic can determine whether a source word line contains data that includes characteristics that satisfy a threshold criterion (e.g., the word line contains high read data) based on a level of read disturbance detected in neighboring word lines (which can be determined using measured bit error rates of the neighboring word lines). In such examples, the processing logic can first identify neighboring word lines of a source word line, where the source word line is located between two neighboring word lines. For example, if the source word line is the third word line in a data block, the processing logic can identify the second and fourth word lines in the block (the two word lines that are most neighboring to the third word line). Subsequently, the processing logic can determine whether the source word line has a low bit error rate and whether the two neighboring word lines have a high bit error rate, which can indicate a high level of read disturbance of the neighboring word lines.

[0048] To make this determination, the processing logic can determine a bit error rate associated with at least a portion of memory cells of the source word line, a second bit error rate associated with at least a portion of memory cells of one neighboring word line, and a third bit error rate associated with at least a portion of memory cells of another neighboring word line. The processing logic can then determine whether the bit error rates of the two neighboring word lines satisfy a threshold criterion associated with a high read disturbance condition. In various implementations, the threshold criterion can indicate a number of encountered errors, a percentage value, etc. If the bit error rates of the neighboring word lines (the second and third bit error rates) satisfy the threshold, the processing logic can determine whether the bit error rate of the source word line also satisfies the threshold. If the bit error rate of the source word line is low and the bit error rates of the neighboring word lines are high, this can indicate that there is a high level of read disturbance at the neighboring word lines. In such examples, the processing logic can determine that the source word line contains high read data that should be relocated to a low read disturbance page in a destination word line.

[0049] At operation 240, the processing logic identifies one or more low read disturb pages of a target word line for relocating the data in response to determining that the data contains characteristics that satisfy the threshold criteria (e.g., the data is high read data). As described above, the low read disturb pages can be used to program the most significant bits of the memory cells. In MLC implementations, the processing logic can identify one or more upper pages of the MLC memory cells because that page is used to program the most significant bits. In TLC implementations, the processing logic can identify one or more additional pages of the TLC memory cells because that page is used to program the most significant bits.

[0050] In some implementations, the processing logic can store the high read data from the original source word line across multiple target word lines. In such examples, the processing logic can identify one group of additional low read disturb pages on one target word line in the target data block and an additional group of low read disturb pages on another target word line. Subsequently, the processing logic can store different portions of the high read data across the multiple groups of low read disturb pages of the target word lines. In one example, the processing logic can divide the high read data across two word lines. In another example, the processing logic can divide the high read data across more than two word lines.

[0051] In some implementations, the processing logic can select a target word line for storing the high read data that is not adjacent to other word lines that can be negatively affected by the high read data (e.g., "weak" word lines). In such examples, after selecting a potential target word line, the processing logic can identify word lines that are adjacent to the potential target word line. Subsequently, the processing logic can determine a bit error rate associated with at least a portion of the memory cells of the adjacent word lines. The processing logic can determine whether this bit error rate satisfies a threshold criteria and, if so, designate that word line as a "weak" word line. In various implementations, the threshold criteria can be associated with a high error rate condition, a high voltage level, etc. If the processing logic determines that an adjacent word line is a "weak" word line, the processing logic can identify another potential target word line that is not adjacent to the "weak" word line. In various implementations, the processing logic can first identify any "weak" word lines in the target data block and then select a target word line for the high read data that is not adjacent to any of the "weak" word lines in the target data block.

[0052] At operation 250, the processing logic stores at least a portion of the data at the one or more low read disturb pages of the target word line in response to identifying the one or more low read disturb pages of the target word line. As described above, in some implementations, the processing logic can store the high read data at the low read disturb pages of a single target word line. Alternatively, the processing logic can store the high read data at the low read disturb pages of multiple target word lines.

[0053] Figures 3A-3BThis describes how high read data is relocated to a memory device according to some embodiments of the present disclosure (e.g., Figure 1 Examples of low-impact read interference pages in memory device 130. In various embodiments, data relocation operations can be performed by... Figure 1 The high-read data manager 113 executes, as mentioned above. Figure 2 And the following text about Figure 4 As described.

[0054] like Figure 3A As shown, the high-read data manager can receive a request to perform a data relocation operation on a word line of the source data block 310 of the memory device. As described above, this request can be initiated in response to a discarded item collection operation, a data folding operation, etc. In various embodiments, the high-read data manager can analyze the word lines of the source block 310 (e.g., word lines 311-316) to determine whether the data stored on any of these word lines is high-read (e.g., “hot-read”) data and, if so, whether the high-read data can be relocated to a low-read interference page of the destination word line to reduce the impact of read interference on adjacent word lines.

[0055] In response to a request to perform a data relocation operation, the high read data manager can determine whether to high read data in the source word line in order to efficiently guide its relocation. As shown, the high read data manager can detect that data (data 313-A) stored at word line 313 is stored at the high read interference (RD) page of the memory cell of that word line. As described above, in some embodiments, the high read data manager can determine whether to high read (e.g., “hot read”) data 313-A based on the properties of adjacent word lines (e.g., word lines 312 and 314). Figure 3A As shown, the bit error rate associated with the memory cells of word lines 312 and 314 indicates a high bit error rate. The presence of a high bit error rate indicates that these word lines are experiencing a high level of read interference. As mentioned above, this can be a result of the higher voltage level applied to these word lines when reading data from word line 313. The high bit error rate present on these word lines indicates that the data stored at word line 313 is being read frequently.

[0056] The high-read data manager can then identify the target word line in the target data block 320. For example... Figure 3AAs shown in the middle, the high read data manager can identify word lines in the data block 320 with low bit error rates as potential target candidates. Subsequently, any candidate word lines that are adjacent to weak word lines (e.g., word lines with high bit error rates) can be excluded from consideration for relocating high read data. As shown, word line 322 has a high bit error rate associated with its memory cells and is designated as a weak word line, causing the high read data manager to exclude word lines 321 and 323 from consideration. As shown, word line 324 is selected as a target word line and data 313-A is relocated to a low read disturb (RD) page of word line 324 (e.g., data 324-A).

[0057] Figure 3B As shown, the high read data manager can receive a request to perform a data relocation operation on the word lines of a source data block 330 of a memory device. As described above, the request can be initiated in response to a garbage collection operation, a data folding operation, etc. In various embodiments, the high read data manager can analyze the word lines of the source block 330 (e.g., word lines 331-336) to determine whether the data stored on any of the word lines is high read (e.g., “hot read”) data and, if so, whether the high read data can be relocated to a low read disturb page of a destination word line to reduce the impact of read disturb on adjacent word lines. The high read data manager can utilize the processes described in Figure 2 and Figure 3A to detect high read data for relocation to a low read disturb page of a target word line of a target data block.

[0058] As shown in the middle, the high read data manager can identify word lines in the data block 320 with low bit error rates as potential target candidates. Subsequently, any candidate word lines that are adjacent to weak word lines (e.g., word lines with high bit error rates) can be excluded from consideration for relocating high read data. As shown, word line 322 has a high bit error rate associated with its memory cells and is designated as a weak word line, causing the high read data manager to exclude word lines 321 and 323 from consideration. As shown, word line 324 is selected as a target word line and data 313-A is relocated to a low read disturb (RD) page of word line 324 (e.g., data 324-A). Figure 3B As shown in the middle, the high read data manager can identify word lines in the data block 320 with low bit error rates as potential target candidates. Subsequently, any candidate word lines that are adjacent to weak word lines (e.g., word lines with high bit error rates) can be excluded from consideration for relocating high read data. As shown, word line 322 has a high bit error rate associated with its memory cells and is designated as a weak word line, causing the high read data manager to exclude word lines 321 and 323 from consideration. As shown, word line 324 is selected as a target word line and data 313-A is relocated to a low read disturb (RD) page of word line 324 (e.g., data 324-A).

[0059] It should be noted that while Figures 3A-3B source and destination blocks are depicted with a particular number of word lines, aspects of the disclosure can be applied to memory devices configured with data blocks containing more or fewer word lines. Additionally, while Figures 3A-3BRedirection of data programmed to a memory device is depicted, although aspects of the disclosure can apply to programming new data on a first example based on a write request received from a host system. This latter embodiment is described below with respect to Figure 4 A more detailed description.

[0060] Figure 4 is an example method 400 for storing high read data at a low impact read disturb page of a memory device based on a write request according to some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by a high read data manager 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 410, processing logic receives a request to write data to a memory device, where the request includes an indication that the data includes a particular characteristic. In various implementations, the characteristic can be associated with the data to be written being high read data. In such examples, a system providing the data (e.g., a host system) can pre-determine that the data can be accessed more frequently than other data and configure the write request to indicate that characteristic in the request. For example, the data can include frequently accessed values, such as lookup table values, configuration values, conversion constants, etc. In some implementations, the request can provide this indication by setting a flag or indicator in the request to a value indicating that the accompanying data will be high read data. As described above, the memory device can include multi-level memory cells. Each multi-level memory cell can be configured with different page levels, where each page level can be used to store a particular level of significance of the memory cell. For example, a memory device configured with multi-level cells (MLC) can store two bits per cell. In such examples, the MLC can include a lower page for programming the least significant bits of the MLC and a higher page (or upper page) for programming the most significant bits thereof. Similarly, a memory device configured with triple-level cells (TLC) can store three bits per cell. In such examples, the TLC can include a lower page for programming the least significant bits of the TLC and multiple higher pages - upper pages - for programming the second significant bits thereof and an additional page for programming the most significant bits thereof.

[0062] At operation 420, the processing logic identifies a target word line for storing the data in a data block of the memory device in view of the characteristic. As described above, a characteristic associated with data that can be frequently accessed (e.g., high read) relative to other data can direct the processing logic to select a target word line accordingly. In various embodiments, the processing logic can select a potential target word line based on whether the potential target is a weak word line. As described above with respect to Figure 2 weak word line. In such an example, the processing logic can identify a potential target word line and determine a bit error rate of at least a portion of the memory cells of that word line. Subsequently, the processing logic can determine whether the determined bit error rate satisfies a threshold criterion. In various embodiments, the threshold criterion can be associated with a high error rate condition, a high voltage level, and the like. In response to determining that the bit error rate does not satisfy the threshold criterion, the processing logic can select that word line as the target for storing the data. Otherwise, the processing logic can identify another word line as the target.

[0063] In some embodiments, the processing logic can also consider word lines adjacent to the potential target word line. As described above, the processing logic can bypass a potential target word line that is adjacent to a weak word line because high read data can negatively affect the adjacent weak word line. In such an example, the processing logic performs a similar process as described above with respect to Figure 2 After selecting a potential target word line, the processing logic can identify an adjacent word line to the potential target, determine a bit error rate of at least a portion of the memory cells of the adjacent word line, and determine whether that bit error rate satisfies a threshold criterion. If so, the processing logic can determine that the adjacent word line is a weak word line and subsequently identify another potential target for storing high read data.

[0064] In some embodiments, the processing logic can store high read data across multiple word lines. In such an example, the processing logic can identify multiple word lines in a data block (or multiple data blocks) for storing high read data in the above process.

[0065] At operation 430, the processing logic selects one or more low read disturb pages of the target word line for storing the data. As described above, the low read disturb pages can be used to program the most significant bits of the memory cells. In MLC embodiments, the processing logic can identify one or more upper pages of the MLC memory cells because that page is used to program the most significant bits. In TLC embodiments, the processing logic can identify one or more additional pages of the TLC memory cells because that page is used to program the most significant bits. In examples where multiple target word lines are selected for storing data, a group of low read disturb pages of each of the target word lines can be selected.

[0066] At operation 440, the processing logic stores at least a portion of the data at one or more low read disturbance pages of the target word line. In examples where a single word line is selected, the data is stored at the low read disturbance pages of that word line. In examples where multiple word lines are selected, the data is stored at the low read disturbance pages of each of the word lines.

[0067] Figure 5 An example machine of a computer system 500 is illustrated in FIG. 5, which can execute a set of instructions that can cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to a high read data manager 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1 Figure 1 The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. Figure 1

[0068] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0069] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0070] ​​Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via network 520.

[0071] Data storage system 518 may include a machine-readable storage medium 524 (also referred to as computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0072] In one embodiment, instruction 526 includes instructions for implementing a high-read data manager (e.g., Figure 1 The machine-readable storage medium 524 is a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be understood as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0073] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, is considered to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0074] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0075] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the methods. The structure for a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0077] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0078] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: receiving, by a processing device, a request to perform a data relocation operation on a first word line of a plurality of word lines of a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determining that the first word line comprises data stored at one or more high read disturb pages in the plurality of pages; determining whether the data comprises a characteristic that satisfies a threshold criterion related to additional data stored on additional word lines of the plurality of word lines; in response to determining that the data comprises the characteristic that satisfies the threshold criterion, identifying a target word line in a non-empty target data block for relocating the data; determining whether any word line adjacent to the target word line has a bit error rate that exceeds a corresponding threshold; and in response to determining that there is no word line adjacent to the target word line that has a bit error rate that exceeds the corresponding threshold, storing at least a portion of the data at one or more low read disturb pages of the target word line.

2. The method of claim 1, wherein the data relocation operation comprises at least one of a garbage collection operation or a folding operation.

3. The method of claim 1, wherein the one or more high read disturb pages suffer more read disturb than the one or more low read disturb pages.

4. The method of claim 1, wherein determining whether the data comprises the characteristic that satisfies the threshold criterion comprises: identifying a second word line of the plurality of word lines, wherein the second word line is adjacent to the first word line; and identifying a third word line of the plurality of word lines, wherein the third word line is adjacent to the first word line, and wherein the first word line is between the second word line and the third word line.

5. The method of claim 4, further comprising: determining a first bit error rate associated with at least a portion of the memory cells of the first word line; determining a second bit error rate associated with at least a portion of the memory cells of the second word line; determining a third bit error rate associated with at least a portion of the memory cells of the third word line; determining whether the second bit error rate and the third bit error rate satisfy a threshold criterion associated with a high read disturb condition; in response to determining that the second bit error rate and the third bit error rate satisfy the threshold criterion, determining whether the first bit error rate satisfies the threshold criterion; and in response to determining that the first bit error rate does not satisfy the threshold criterion, determining that the first word line comprises data having the characteristic.

6. The method of claim 1, wherein determining whether the data comprises the characteristic that satisfies the threshold criterion comprises: determining a read count associated with the first word line, wherein the read count comprises an indication of a number of host read operations performed on the memory cells of the first word line; determining whether the read count satisfies a read threshold criterion associated with a high read data condition; and in response to determining that the read count satisfies the read threshold criterion, determining that the first word line comprises data having the characteristic.

7. The method of claim 1, further comprising: identifying one or more additional low read disturbance pages of an additional target word line; and storing an additional portion of the data at the one or more additional low read disturbance pages of the additional target word line.

8. The method of claim 1, further comprising: identifying a second target word line, wherein the second target word line is adjacent to the target word line; determining a bit error rate associated with at least a portion of the memory cells of the second target word line; determining whether the bit error rate satisfies a threshold criterion associated with a high error rate condition; and in response to determining that the bit error rate satisfies the threshold criterion, identifying one or more additional low read disturbance pages of an additional target word line for relocating the data, wherein the additional target word line is not adjacent to the second target word line.

9. A method comprising: receiving, by a processing device, a request to write data to a memory device, wherein the request comprises an indication that the data has a characteristic, wherein the memory device comprises a plurality of multi-level memory cells, and wherein each multi-level memory cell comprises a plurality of pages; identifying, by the processing device, a target word line of a plurality of word lines in a non-empty target data block of the memory device in view of the characteristic; determining whether any word line adjacent to the target word line has a bit error rate that exceeds a corresponding threshold; in response to determining that there is no word line adjacent to the target word line that has a bit error rate that exceeds the corresponding threshold, selecting one or more low read disturbance pages of the plurality of pages of the target word line; and storing at least a portion of the data at the one or more low read disturbance pages of the target word line.

10. The method of claim 9, wherein the one or more low read disturbance pages suffer less read disturbance than one or more high read disturbance pages of the plurality of pages.

11. The method of claim 9, wherein identifying the target word line comprises: identifying a first word line of the plurality of word lines; determining a first bit error rate associated with at least a portion of the memory cells of the first word line; determining whether the first bit error rate satisfies a threshold criterion associated with a high error rate condition; and in response to determining that the bit error rate does not satisfy the threshold criterion, selecting the first word line as the target word line for storing the data.

12. The method of claim 11, further comprising: identifying a second word line of the plurality of word lines, wherein the second word line is adjacent to the first word line; determining a second bit error rate associated with at least a portion of the memory cells of the second word line; determining whether the second bit error rate satisfies the threshold criterion; and in response to determining that the second bit error rate satisfies the threshold criterion, identifying an additional target word line for storing the data, wherein the additional target word line is not adjacent to the second word line.

13. The method of claim 9, further comprising: identifying one or more additional low read disturbance pages of an additional target word line; and storing at least a portion of the data at one or more low read disturbance pages of the target word line.

14. A system comprising: a memory device; and a processing device operably coupled with the memory device to perform operations comprising: receiving, by a processing device, a request to perform a data relocation operation on a first word line of a plurality of word lines of a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determining that the first word line comprises data stored at one or more high read disturbance pages of the plurality of pages; determining whether the data comprises a characteristic that satisfies a threshold criterion related to additional data stored on an additional word line of the plurality of word lines; in response to determining that the data comprises the characteristic that satisfies the threshold criterion, identifying a target word line of a non-empty target data block for relocating the data; determining whether any word line adjacent to the target word line has a bit error rate that exceeds a corresponding threshold; and in response to determining that there is no word line adjacent to the target word line that has a bit error rate that exceeds the corresponding threshold, storing at least a portion of the data at one or more low read disturbance pages of the target word line.

15. The system of claim 14, wherein the one or more high read disturbance pages suffer more read disturbance than the one or more low read disturbance pages.

16. The system of claim 14, wherein to determine whether the data comprises the characteristic that satisfies the threshold criterion, the processing device is to perform further operations comprising: identifying a second word line of the plurality of word lines, wherein the second word line is adjacent to the first word line; and identifying a third word line of the plurality of word lines, wherein the third word line is adjacent to the first word line, and wherein the first word line is between the second word line and the third word line.

17. The system of claim 16, wherein the processing device is to perform further operations comprising: determining a first bit error rate associated with at least a portion of the memory cells of the first word line; determining a second bit error rate associated with at least a portion of the memory cells of the second word line; determining a third bit error rate associated with at least a portion of the memory cells of the third word line; determining whether the second bit error rate and the third bit error rate satisfy a threshold criterion associated with a high read disturbance condition; in response to determining that the second bit error rate and the third bit error rate satisfy the threshold criterion, determining whether the first bit error rate satisfies the threshold criterion; and in response to determining that the first bit error rate does not satisfy the threshold criterion, determining that the first word line comprises data having the characteristic.

18. The system of claim 14, wherein to determine whether the data comprises the characteristic that satisfies the threshold criterion, the processing device is to perform further operations comprising: determining a read count associated with the first word line, wherein the read count comprises an indication of a number of host read operations performed on the memory cells of the first word line; determining whether the read count satisfies a read threshold criterion associated with a high read data condition; and in response to determining that the read count satisfies the read threshold criterion, determining that the first word line comprises data having the characteristic.

19. The system of claim 14, wherein the processing device is to perform further operations comprising: identifying one or more additional low read disturbance pages of an additional target word line; and storing an additional portion of the data at the one or more additional low read disturbance pages of the additional target word line.

20. The system of claim 14, wherein the processing device is to perform further operations comprising: identifying a second target word line, wherein the second target word line is adjacent to the target word line; determining a bit error rate associated with at least a portion of the memory cells of the second target word line; determining whether the bit error rate satisfies a threshold criterion associated with a high error rate condition; and in response to determining that the bit error rate satisfies the threshold criterion, identifying one or more additional low read disturbance pages of an additional target word line for relocating the data, wherein the additional target word line is not adjacent to the second target word line.

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