Semiconductor device with recessed pads for die stack interconnection

Abstract

Semiconductor devices with recessed pads for die stack interconnection are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include a surface having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to one another via the insulating material. The semiconductor assembly can also include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via that extends continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically to semiconductor dies having recessed pads for electrical interconnection with other semiconductor dies. Background Technology

[0002] A packaged semiconductor die containing memory chips, microprocessor chips, and imager chips typically comprises a semiconductor die mounted on a substrate and encased in a protective cover. The semiconductor die may contain functional features, such as memory cells, processor circuitry, and imager devices, as well as bonding pads electrically connected to these functional features. The bonding pads may be electrically connected to terminals outside the protective cover to allow the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures are constantly driving semiconductor manufacturers to reduce the size of die packages to fit within the space constraints of electronic devices, while simultaneously increasing the functional capacity of each package to meet operating parameters. One method for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's "coverage area") is to vertically stack multiple semiconductor dies on top of each other within a single package. Dies in such vertically stacked packages can be electrically coupled to each other and / or electrically coupled to the substrate via wires, interconnects, or other conductive structures. However, conventional solder interconnects used for electrically coupling dies in vertically stacked packages significantly increase the overall package height. Hybrid bonding techniques can reduce package height, but typically have stringent requirements for alignment, surface cleanliness, and planarization, which can be difficult and costly to achieve. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor assembly comprising: a die stack including a plurality of semiconductor dies, wherein each semiconductor die includes: a first surface including a first insulating material; a second surface opposite to the first surface including a second insulating material; a recess in the first surface; and a conductive pad within the recess, wherein adjacent semiconductor dies in the die stack are directly coupled to each other via respective first and second insulating materials of the adjacent semiconductor dies; and a conductive structure electrically coupled to each of the semiconductor dies, wherein the conductive structure includes: a monolithic via extending through each of the semiconductor dies in the die stack; and a plurality of protrusions extending laterally from the monolithic via, wherein the plurality of protrusions and the monolithic via are made of a continuous material, and wherein each protrusion is positioned within the recess of a corresponding one of the semiconductor dies and electrically coupled to the conductive pad within the recess.

[0005] Another aspect of this disclosure provides a semiconductor assembly comprising: a die stack including a plurality of semiconductor dies, wherein each semiconductor die includes: an upper surface including an upper dielectric layer, a lower surface including a lower dielectric layer, a recess in the upper surface or the lower surface, and a conductive pad within the recess, wherein adjacent semiconductor dies in the die stack are coupled to each other via a direct bonding between the respective upper and lower dielectric layers of the adjacent semiconductor dies; and a conductive structure electrically coupled to the semiconductor. Each of the dies, wherein the conductive structure comprises: a monolithic via extending continuously through each of the semiconductor dies in the die stack and positioned adjacent to the recess; and a plurality of protrusions extending laterally from the monolithic via, wherein the plurality of protrusions and the monolithic via are made of a continuous material, and wherein each protrusion is positioned within the recess of a corresponding one of the semiconductor dies and electrically coupled to the conductive pad within the recess; and an insulating material between the monolithic via and at least a portion of each semiconductor die remote from the conductive pad.

[0006] Another aspect of this disclosure provides a method for manufacturing a semiconductor assembly, wherein the method includes: forming a recess having a conductive pad in the surface of each of a plurality of semiconductor dies; assembling the semiconductor dies into a die stack such that the recesses are vertically aligned; forming a channel through each of the semiconductor dies in the die stack, wherein the channel is connected to each of the recesses; applying at least one material layer to at least a portion of the channel; and depositing a conductive material into each of the channel and the recess to electrically couple the conductive pads of the semiconductor dies to each other. Attached Figure Description

[0007] Many aspects of the invention can be better understood by referring to the accompanying drawings. The components in the drawings are not necessarily to scale. The focus is on clearly illustrating the principles of the invention.

[0008] Figure 1 This is a partial schematic side cross-sectional view of a semiconductor die configured according to an embodiment of the present invention.

[0009] Figure 2A This is a partial schematic side cross-sectional view of a semiconductor assembly during the initial stage of the manufacturing process, according to an embodiment of the present invention.

[0010] Figure 2B This is an embodiment of the technology of the present invention during another stage of the manufacturing process. Figure 2A A partial schematic side cross-sectional view of the semiconductor assembly.

[0011] Figures 2C to 2H Description of embodiments of the present invention for use in Figure 2B Various configurations of recesses and channels in semiconductor assemblies.

[0012] Figure 2I This is an embodiment of the technology according to the invention during another stage of the manufacturing process. Figure 2A A partial schematic side cross-sectional view of the semiconductor assembly.

[0013] Figure 2J to 2L This is an embodiment of the technology according to the present invention. Figure 2I A close-up view of a portion of a semiconductor assembly.

[0014] Figure 2M This is an embodiment of the technology according to the invention during another stage of the manufacturing process. Figure 2A A partial schematic side cross-sectional view of the semiconductor assembly.

[0015] Figure 2N This is an embodiment of the technology according to the present invention. Figure 2M A close-up view of a portion of a semiconductor assembly.

[0016] Figure 2O This is an embodiment of the technology of the present invention during another stage of the manufacturing process. Figure 2A A partial schematic side cross-sectional view of the semiconductor assembly.

[0017] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor assembly according to an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of a system comprising a semiconductor device or package configured according to an embodiment of the technology according to the present invention. Detailed Implementation

[0019] The following describes several embodiments of a semiconductor device and specific details of associated systems and methods. In some embodiments, for example, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die may include a first (e.g., upper) surface having a first insulating material and a second (e.g., lower) surface having a second insulating material. Additionally, each semiconductor die may include a recess formed in at least one of the first or second surfaces, and a conductive pad within the recess. The insulating material on the surface of the semiconductor die may include a dielectric material (e.g., an oxide or nitride material) such that the semiconductor dies can be directly coupled to each other via dielectric bonding. The semiconductor assembly may also include a conductive structure electrically coupled to each of the semiconductor dies. The conductive structure may include a monolithic via extending continuously through each of the semiconductor dies in the die stack, and a plurality of protrusions extending from the via. The protrusions and vias may be made of a continuous monolithic material. Each protrusion may be positioned within a recess of a corresponding semiconductor die and may be electrically coupled to a conductive pad within the recess. Conductive structures can be formed, for example, by using electroless plating or electroplating processes, after semiconductor dies have been assembled into a die stack.

[0020] Compared to conventional devices and manufacturing processes, the present invention offers several advantages. For example, because adjacent semiconductor dies can be directly coupled via insulating material on the die surfaces rather than through additional insertion structures such as solder bumps or pillars, vertical separation between semiconductor dies can be reduced or minimized, thus allowing for smaller package heights. Furthermore, because the conductive structure of the electrically coupled semiconductor dies can be formed in situ after the die stack is formed, the method described herein provides reliable inter-die interconnects while avoiding the stringent alignment, surface cleaning, and planarization requirements associated with hybrid bonding methods.

[0021] Those skilled in the art will recognize that the appropriate stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context, the term "substrate" can refer to a wafer-level substrate or a single die-level substrate. Furthermore, unless the context otherwise indicates, semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques can be used to deposit materials. Similarly, for example, plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques can be used to remove materials.

[0022] Numerous specific details are disclosed herein to provide a detailed and useful description of embodiments of the invention. However, those skilled in the art will understand that the invention may have additional embodiments, and may be described without further reference. Figures 1 to 4The details of the described embodiments are practiced in several cases. For example, some details of semiconductor devices and / or packages well known in the art have been omitted so as not to obscure the technical aspects of the invention. Generally, it should be understood that various other devices and systems besides the specific embodiments disclosed herein are within the scope of the invention.

[0023] As used herein, the terms “vertical,” “horizontal,” “upper,” “lower,” “above,” and “below” may refer to the relative orientation or position of a feature in a semiconductor device, taking into account the orientation shown in the figures. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be broadly understood to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0024] Figure 1 This is a partially schematic side cross-sectional view of a semiconductor die 100 (“Die 100”) configured according to an embodiment of the present invention. The die 100 includes a semiconductor substrate 102 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) having a first (e.g., upper) side 104 and a second (e.g., lower) side 106. One or both of the first side 104 and the second side 106 may be a front and / or active side, containing various types of semiconductor components, such as memory circuitry (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (e.g., NAND, NOR) or other types of memory circuitry), controller circuitry (e.g., DRAM controller circuitry), logic circuitry, processing circuitry, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components, and / or other semiconductor features. Optionally, the first side 104 or the second side 106 may be a rear and / or passive side that does not contain any active semiconductor components. The semiconductor substrate 102 may have any suitable thickness, such as less than or equal to 100 μm, 75 μm, 50 μm, 25 μm or 10 μm.

[0025] In some embodiments, the die 100 has a first (e.g., upper) surface 108 comprising a first (e.g., upper) insulating material 112, and a second (e.g., lower) surface 110 comprising a second (e.g., lower) insulating material 114. The first insulating material 112 may partially or completely cover a first side 104 of the semiconductor substrate 102, and the second insulating material 114 may partially or completely cover a second side 106 of the semiconductor substrate 102. The first insulating material 112 and the second insulating material 114 may each have any suitable thickness, for example, less than or equal to 5 μm, 2 μm, 1 μm, 500 nm, 200 nm, 150 nm, or 100 nm.

[0026] The first insulating material 112 and / or the second insulating material 114 may each be or comprise one or more layers of dielectric material, such as passivation materials, polyimide materials, and / or other suitable materials for covering the surface of a semiconductor device. In some embodiments, the first insulating material 112 and / or the second insulating material 114 each comprise a dielectric material (e.g., oxide material, nitride material, etc.) suitable for direct dielectric bonding (e.g., oxide-oxide bonding, nitride-nitride bonding, etc.). For example, the first insulating material 112 and / or the second insulating material 114 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, polycrystalline silicon nitride, polycrystalline silicon oxide, tetraethyl orthosilicate (TEOS), and the like. In some embodiments, the first insulating material 112 and / or the second insulating material 114 may comprise a dielectric material having a small dielectric constant relative to silicon oxide (“low-κ dielectric material”). Such low-κ dielectric materials may include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymer dielectrics, silicon-based polymer dielectrics, etc.

[0027] The die 100 also includes components for communicating with other devices (e.g., another semiconductor die), such as at least one conductive pad 120. The conductive pad 120 may be a conductive component (e.g., a bonding pad, contact, trace, metal layer) suitable for forming an electrical interconnect with another device. In the illustrated embodiment, the conductive pad 120 is located on a first surface 108 of the die 100 and may be electrically coupled to a semiconductor component in a first side 104 of the semiconductor substrate 102 via signal routing components (e.g., routing layers, vias, traces, etc. – omitted for simplicity) extending through a first insulating material 112. However, in other embodiments, the conductive pad 120 may be located on a second surface 108 of the die 100 and may be electrically coupled to a semiconductor component in a second side 106 of the semiconductor substrate 102.

[0028] The conductive pad 120 can be positioned within a recess 122 in the bare die 100. For example, in Figure 1In this embodiment, the recess 122 is located in the first surface 108 of the die 100. However, in other embodiments, the recess 122 may be located in the second surface 110 of the die 100. The conductive pad 120 may be positioned at the bottom surface 124 of the recess 122 and may partially or completely cover the bottom surface 124. In some embodiments, the recess 122 extends partially into the semiconductor substrate 102 such that the bottom surface 124 of the recess 122 is vertically offset from the first side 104 (e.g., below) of the semiconductor substrate 102. Alternatively, the recess 122 may be entirely located in the first insulating material 112 such that the bottom surface 124 of the recess 122 is aligned with or above the first side 104 of the semiconductor substrate 102. Optionally, the first insulating material 112 may also include a recessed region 126 that partially or completely surrounds the recess 122. The recessed region 126 may extend into the semiconductor substrate 102 and may separate the conductive pad 120 from the semiconductor substrate 102.

[0029] The geometry (e.g., size, shape) of the recess 122 can vary as needed. For example, the recess 122 may have a depth D ranging from 1 μm to 10 μm or from 1 μm to 5 μm. In some embodiments, the depth D does not exceed 10 μm, 5 μm, 4 μm, 3 μm, 2 μm, or 1 μm. The recess 122 may have a width W ranging from 5 μm to 50 μm or from 10 μm to 20 μm. In some embodiments, the width W is greater than or equal to 5 μm, 10 μm, 15 μm, or 20 μm. Optionally, the ratio between the width W and the depth D may be at least 1.5:1, 2:1, 2.5:1, or 5:1. Additionally, although the recess 122 is in Figure 1 While depicted as having a rectangular vertical cross-sectional shape, in other embodiments, the recess 122 may have different vertical cross-sectional shapes (e.g., square, trapezoidal, triangular, U-shaped, etc.). Similarly, the horizontal cross-sectional shape of the recess 122 (e.g., the shape of the recess 122 when viewed from directly above) may be rectangular, square, circular, elliptical, or any other suitable shape. In some embodiments, the geometry and position of the recess 122 are configured to provide a “shadowing” effect to protect the conductive pad 120 during the material deposition process, as further described below.

[0030] Although Figure 1A single conductive pad 120 and recess 122 are shown, but in other embodiments, the die 100 may include multiple conductive pads 120 and recesses 122. For example, the die 100 may include at least two, three, four, five, ten, fifteen, twenty, 50, 100, hundreds, thousands, or more conductive pads 120 and / or recesses 122. The conductive pads 120 and recesses 122 may be located on the upper surface 108 of the die 100, the lower surface 110 of the die 100, or a suitable combination thereof. In embodiments where the die 100 includes multiple conductive pads 120 and recesses 122, the recesses 122 may be spaced apart from each other and distributed along the upper surface 108 and / or lower surface 110 of the die 100, and each conductive pad 120 may be located within a corresponding recess 122.

[0031] Figures 2A to 2O This section describes the semiconductor assembly 200 (“assembly 200”) during various stages of the manufacturing process according to embodiments of the present invention. First, refer to… Figure 2A Assembly 200 includes a die stack 202 having a plurality of dies 100 (reference numerals are shown for clarity only for subgroups of dies 100). Each of the dies 100 may contain the references above. Figure 1 Any of the described features, such that the same number (e.g., insulation material 114 versus insulation material 114a) is used for identification. Figures 1 to 20 Same or similar components. Although Figure 2A The die stack 202 is described as containing twelve dies 100, but in other embodiments, the die stack 202 may contain a different number of dies 100, such as two, three, four, five, six, seven, eight, nine, or ten dies 100.

[0032] In the initial stages of the manufacturing process, bare dies 100 are assembled to form a die stack 202. Each bare die 100 can be directly coupled to at least one adjacent bare die, such that no additional components or structures (e.g., conductive bumps or pillars) are inserted between the surfaces of adjacent bare dies. In the illustrated embodiment, for example, an upper bare die 100a is coupled to a lower bare die 100b via a direct engagement between a lower surface 110a of the upper bare die 100a and an upper surface 108b of the lower bare die 100b. As previously described, the lower surface 110a and the upper surface 108b may each comprise a corresponding insulating material 114a, 112b, which may be or comprise a dielectric material (e.g., an oxide or nitride material). Thus, according to techniques known to those skilled in the art, the upper and lower bare dies 100a-b can be coupled to each other via a direct dielectric engagement (e.g., an oxide-oxide engagement or a nitride-nitride engagement) between the insulating materials 114a, 112b. In some embodiments, all the die 100s are assembled into a vertical stack and then bonded to each other in a single process step. In other embodiments, the die 100s may be sequentially stacked and bonded to each other in multiple process steps.

[0033] In the illustrated embodiment, the upper surface 108 of each die 100 includes a recess 122 with a conductive pad 120, as previously described. Figure 1 As described in the text. When the die 100 is assembled into a die stack 202, the recesses 122 and conductive pads 120 of each die 100 are vertically aligned with each other. For example, as Figure 2A As shown, each recess 122 and conductive pad 120 may be positioned and / or intersect with the vertical axis A of the die stack 202. However, in other embodiments, the recesses 122 and conductive pads 120 may be arranged differently. For example, some or all of the recesses 122 and conductive pads 120 may be located on the lower surface 110 of the corresponding die 100, rather than on the upper surface 108. As another example, some of the recesses 122 and conductive pads 120 may not be vertically aligned with each other and / or may be positioned along different vertical axes. Additionally, although the vertical axis A is depicted as the central vertical axis of the die stack 202, in other embodiments, the vertical axis A may be laterally offset from the central vertical axis of the die stack 202. Optionally, some of the dies 100 may not include any recesses 122 and / or conductive pads 120.

[0034] Next reference Figure 2BThe manufacturing process may include forming a channel 204 within the die stack 202. In the illustrated embodiment, the channel 204 extends through the entire height of the die stack 202 and through each of the dies 100, for example, from the upper surface 108 of the uppermost die 100c to the lower surface 110d of the lowermost die 100d. In other embodiments, the channel 204 may extend only partially through the die stack 202 and only through a subgroup of dies 100. The channel 204 may connect to some or all of the recesses 122 of the dies 100 to form a continuous open space or region within the die stack 202. For example, the channel 204 may be aligned with and / or at least partially overlap with a vertical axis A, such that the channel 204 intersects at least a portion of each recess 122.

[0035] Figures 2C to 2H Description of embodiments of the present invention for use in Figure 2B Various examples of the configuration 220a-f of the recess 122 and channel 204 of the assembly 200. Specifically, Figures 2C to 2H This is a top view of the boundaries (shown in dashed lines) of the individual recesses 122 and channels 204; other components of the assembly 200 are omitted for clarity.

[0036] First, refer to Figure 2C In configuration 220a, channel 204 is laterally offset from recess 122 such that the center C1 of channel 204 is spaced apart from the center C2 of recess 122. In the illustrated embodiment, channel 204 intersects and overlaps with a single side 222 of recess 122. However, in other embodiments, channel 204 may intersect and / or overlap with two, three, or all four sides of recess 122.

[0037] Next reference Figure 2D Configuration 220b is generally similar to configuration 220a, except that channel 204 overlaps with a single corner 224 of recess 122. Channel 204 also intersects and overlaps with the two sides 226, 228 of recess 122 that connect to corner 224. Alternatively, channel 204 may overlap with two or three corners of recess 122.

[0038] Next reference Figure 2E In configuration 220c, channel 204 and recess 122 are centered together, such that the center C1 of channel 204 and the center C2 of recess 122 are aligned and overlapped. Figure 2EIn one embodiment, channel 204 intersects and overlaps with two opposing sides 230, 232 of recess 122. Alternatively, channel 204 may intersect and overlap with a different number of sides of recess 122 (e.g., a single side, three sides, all four sides). Furthermore, in other embodiments, channel 204 may be offset from recess 122 such that the center C1 of channel 204 may be offset from and spaced apart from the center C2 of recess 122 (e.g., as previously stated in...). Figure 2C and 2D (Depicted in Chinese).

[0039] Next reference Figure 2F Configuration 220d can be generally similar to configuration 220c, except that channel 204 is completely contained within the boundary of recess 122 and tangent to two opposite sides 234, 236 of recess 122. However, in other embodiments, channel 204 may be tangent to a different number of sides of recess 122 (e.g., a single side, three sides, all four sides) while remaining contained within recess 122. Optionally, channel 204 may be tangent to some sides of recess 122 while intersecting and overlapping with other sides of recess 122, such that channel 204 is only partially within recess 122.

[0040] Next reference Figure 2G In configuration 220e, channel 204 is completely contained within recess 122 and is tangent to a single side 238 of recess 122 without contacting the other three sides 240-244 of recess 122. In other embodiments, channel 204 may be tangent to two, three, or all four sides of recess 122 while remaining contained within recess 122. Additionally, although Figure 2G The center C1 of channel 204 is depicted as offset from the center C2 of recess 122, but in other embodiments the center C1 of channel 204 may be aligned with and overlap with the center C2 of recess 122.

[0041] Next reference Figure 2H Configuration 220f is largely similar to configuration 220e, except that channel 204 does not contact any of the sides 246 to 252 of recess 122. Although Figure 2H Channel 204 is shown centered within recess 122, but in other embodiments, the center C1 of channel 204 may be offset from the center C2 of recess 122.

[0042] Figures 2C to 2H Any of the features of configuration 220a-f can be combined with each other and / or incorporated into Figure 2B Of the 200 assemblies. Additionally... Figures 2C to 2HThe configurations 220a-f can vary in many different ways. For example, while the recess 122 is depicted as a square or rectangle and the channel 204 as a circle, in other embodiments, the recess 122 and / or the channel 204 may each have different shapes (e.g., elliptical, triangular, trapezoidal, etc.). Additionally, the relative sizes of the recess 122 and the channel 204 can be varied as needed; for example, the recess 122 may have a larger surface area than the channel 204, the recess 122 may have a smaller surface area than the channel 204, or the recess 122 may have the same surface area as the channel 204. The amount of overlap between the recess 122 and the channel 204 can also be modified. In some embodiments, for example, the channel 204 overlaps with no more than 90%, 80%, 70%, 60%, 50%, 40%, 30%, 20%, or 10% of the horizontal surface area of ​​the recess 122.

[0043] Refer again Figure 2B The geometry (e.g., size, shape) of channel 204 can vary as needed. For example, channel 204 can have any suitable length, such as at least 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 100 μm, 150 μm, 400 μm, 450 μm, or 500 μm. The width of channel 204 (e.g., maximum, minimum, or average width) can not exceed 20 μm, 15 μm, 10 μm, 5 μm, 4 μm, 1 μm, 2 μm, or 1 μm. The ratio of channel length to channel width (e.g., maximum, minimum, or average width) can be at least 20:1, 10:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, or 100:1. While the illustrated embodiment depicts channel 204 as having a variable width (e.g., wider near the top and bottom ends of die stack 202 and narrower near the center of die stack 202), in other embodiments, channel 204 may have a uniform or substantially uniform width. The horizontal cross-sectional shape of channel 204 (e.g., the shape of channel 204 when viewed from directly above) may be circular, elliptical, square, rectangular, or any other suitable shape.

[0044] Channel 204 can be formed using any suitable material removal process, such as an etching process (e.g., a Bosch process or other processes for forming through-silicon vias (TSVs), a drilling process, or a combination thereof. For example, etching may be performed starting from the uppermost die 100c and proceeding downwards into the die stack 202, starting from the lowermost die 100d and proceeding upwards into the die stack 202, or performed simultaneously or sequentially in both directions. In some embodiments, channel 204 may comprise two segments: an upper segment formed by etching downwards from the uppermost die 100c, and a lower segment formed by etching upwards from the lowermost die 100d. In other embodiments, channel 204 may comprise a single segment formed by etching from a single direction (e.g., upwards only or downwards only).

[0045] Let's refer to the following. Figure 2I and 2J ( Figure 2J yes Figure 2I (A close-up view of a portion), at least one material layer 206 is deposited within the channel 204. The material layer 206 may coat at least a portion of the channel 204 while leaving the conductive pad 120 of the bare die 100 at least partially or completely exposed. For example, as optimally located in Figure 2J As can be seen, material layer 206 covers the sidewall surfaces of the semiconductor substrates 102a-b of the upper and lower bare dies 100a-b along channel 204. Material layer 206 may also cover the sidewall surfaces of insulating materials 114a, 112b along channel 204. In the illustrated embodiment, material layer 206 does not extend into recess 122b and / or is sufficiently spaced from at least a portion of conductive pad 120b, such that conductive pad 120b is partially or completely uncovered by material layer 206.

[0046] However, in other embodiments, the material layer 206 may extend partially into the recess 122b and / or onto the conductive pad 120b. Figure 2K For example, material layer 206 includes region 207a, which covers a portion of conductive pad 120b (e.g., the portion closest to channel 204) while leaving the remaining portion of conductive pad 120b exposed (e.g., the portion furthest from channel 204 and / or within recess 122b). For example, region 207a may cover no more than 90%, 80%, 70%, 60%, 50%, 40%, 30%, 20%, 10%, or 5% of the surface area of ​​conductive pad 120b. As another example, in Figure 2L In this configuration, material layer 206 includes a region 207b that covers the upper surface of recess 122b, away from the conductive pad 120b, such that the surface of conductive pad 120b remains fully exposed. Optionally, material layer 206 may be located over a portion of conductive pad 120b (e.g., as shown in the image). Figure 2K(as shown) and above the portion of the recess 122b that is away from the conductive pad 120b (e.g., as shown) Figure 2L (As shown) extension.

[0047] The composition of material layer 206 can be varied as needed. In some embodiments, for example, material layer 206 comprises at least one layer of insulating material, such as a dielectric and / or passivation material (e.g., an oxide or nitride material, such as silicon oxide, silicon nitride, etc.). The insulating material electrically isolates the semiconductor substrate 102 of the bare die 100 from the conductive material (e.g., copper) to be deposited within the channel 204, as referenced below. Figure 2M and 2N Alternatively or in combination, material layer 206 may include at least one barrier material configured to reduce or prevent the diffusion and / or electromigration of conductive materials. For example, the barrier material may be or include materials that reduce or prevent copper diffusion, such as tantalum, tantalum nitride, titanium, titanium nitride, tungsten, nickel, etc. The barrier material may also promote the adhesion of conductive materials (e.g., adhesion to insulating materials and / or to the semiconductor substrate 102 of the bare die 100).

[0048] Although Figure 2I to 2L This description focuses on a single material layer 206 within channel 204. However, in other embodiments, assembly 200 may comprise multiple discrete material layers 206 within channel 204, such as two, three, four, five, or more material layers 206. In some embodiments, for example, assembly 200 comprises a first material layer (e.g., an insulating material layer) and a second material layer (e.g., a barrier material layer). The first material layer may be deposited prior to the second material layer, such that the first material layer is interposed between the second material layer and the bare die 100. Each material layer 206 may independently have any suitable thickness, such as less than or equal to 5 μm, 2 μm, 1 μm, 500 nm, 200 nm, 150 nm, or 100 nm.

[0049] Material layer 206 can be deposited using any suitable material deposition process known to those skilled in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, material layer 206 is created using a deposition process in which the orientation of a reactant source (e.g., a reactant gas stream) relative to assembly 200 influences the location of material formation (also referred to herein as a "directional deposition process"), such as CVD or PVD. When using a directional deposition process, recess 122 can provide a shading effect that reduces the amount of reactant reaching the surface of conductive pad 120, or completely prevents reactant from reaching the surface of conductive pad 120. For example, in Figure 2I In one embodiment, if reactant gas is introduced into channel 204 from the top of die stack 202, some material can be deposited onto conductive pad 120 (e.g., as shown in the image). Figure 2K (as shown), but the overhang provided by the recess 122 prevents the conductive pad 120 from being completely covered by the deposited material. Conversely, if the reactant gas is introduced into the channel 204 from the bottom of the die stack 202, then the material can be deposited primarily on the upper surface of the recess 122 (e.g., as shown). Figure 2L (as shown) and / or away from the conductive pad 120. Therefore, the conductive pad 120 may remain partially or completely uncovered by the material layer 206 during the deposition process.

[0050] Let's refer to the following. Figure 2M and 2N ( Figure 2N yes Figure 2M (A close-up view of a portion), the manufacturing process includes depositing conductive material into channel 204 to form conductive structure 208. Conductive structure 208 electrically interconnects die 100, thus enabling die 100 to communicate with each other and / or with external components (e.g., another semiconductor die, packaging substrate, external device, etc.). In the illustrated embodiment, conductive structure 208 is a continuous volume of conductive material comprising an elongated monolithic via 210 and a plurality of protrusions 212 monolithically formed with the via 210. The via 210 may extend partially or completely through die stack 202 and may be positioned adjacent to each of the recesses 122 of die 100. The protrusions 212 may extend laterally from the via 210 and into the recesses 122. As best as in Figure 2M As can be seen, each protrusion 212 can partially or completely fill the corresponding recess 122b and can be electrically coupled to the conductive pad 120b within the recess 122b. Therefore, signals can be transmitted to and / or from the corresponding die 100b through the conductive pad 120b, the protrusion 212, and the via 210.

[0051] The conductive structure 208 may be made of any suitable conductive material, such as copper, tungsten, nickel, gold, or combinations thereof. The conductive material may be deposited using any suitable technique known to those skilled in the art. In some embodiments, for example, the conductive structure 208 is deposited using an electroplating process, such as an electroless electroplating process or an electroplating process. In such embodiments, the electroplating process may include an initial step of applying a seed material layer to the surface of the channel 204 (e.g., to the material layer 206 within the channel 204) and / or to the conductive pad 120 of the die 100. The seed layer may comprise any suitable conductive material (e.g., titanium, copper) and may be applied using sputtering, CVD, PVD, ALD, or other techniques known to those skilled in the art. Optionally, the die 100 may have already contained a seed layer on the conductive pad 120 before being assembled into the die stack 202, or the conductive pad 120 itself may serve as a seed layer.

[0052] Subsequently, an electroplating process can be performed to form a conductive structure 208 from the seed layer. The conductive structure 208 may partially or completely fill the channels 204 and recesses 122, so that the geometry (e.g., size, shape) of the conductive structure 208 is the same as or substantially similar to the geometry of the channels 204 and recesses 122. In some embodiments, because the conductive structure 208 is made of a continuous monolithic material and formed in situ after the die stack 202 is assembled, the method described herein avoids the alignment, surface cleaning, planarization, and / or other low-tolerance process parameter issues involved when performing direct metal-to-metal bonding between discrete vias in individual dies.

[0053] Next reference Figure 2O The die stack 202 can be incorporated into a larger semiconductor device or package containing components known to those skilled in the art. For example, the die stack 200 can be mounted on a substrate 260, which may be or include a package substrate, interposer, printed circuit board, redistribution layer (RDL), dielectric spacers, or another semiconductor die (e.g., a logic die). In such embodiments, the bottom surface 262 of the via 210 of the conductive structure 208 can be electrically coupled to contacts (e.g., bonding pads, vias, etc.) exposed on the substrate 260, thus allowing the die stack 202 to communicate with the substrate 260. Although Figure 2O While via 210 is described as being directly coupled to substrate 260, in other embodiments, assembly 200 may include electrical interconnects (e.g., conductive bumps or pillars) inserted between and coupled to via 210 and substrate 260. Substrate 260 itself may be coupled to conductive elements 264 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) for connection to external devices.

[0054] In some embodiments, the upper surface 266 of the via 210 of the conductive structure 208 is electrically coupled to another semiconductor die 268 (shown in dashed lines). The via 210 may be directly connected to contacts on the semiconductor die 268 (e.g., bonding pads, exposed vias, etc.), or indirectly connected via electrical interconnects (e.g., conductive bumps or pillars not shown) inserted between the via 210 and the semiconductor die 268. However, in other embodiments, the semiconductor die 268 is optional and may be omitted.

[0055] The die stack 202 may be encapsulated in a molding material 270, such as a resin, epoxy resin, silicone-based material, polyimide, or any other material suitable for protecting the various components of the die stack 202 from contamination and / or physical damage. The molding material 270 may cover the upper and / or lateral surfaces of the die stack 202 and at least a portion of the substrate 260. In embodiments where the semiconductor die 268 is omitted, the molding material 270 may cover the exposed upper surface 266 of the via 210. The assembly 200 may also include other packaging components such as an external heat sink, a housing (e.g., a thermally conductive housing), electromagnetic interference (EMI) shielding components, etc.

[0056] Although assembly 200 is depicted as comprising a single conductive structure 208, references Figures 2A to 2O The described process can be modified to produce a semiconductor assembly having multiple conductive structures 208 (e.g., two, three, four, five, six, seven, eight, nine, ten, twenty, 50, 100, hundreds, thousands or more conductive structures 208). In such embodiments, some or all of the dies 100 of the die stack 202 may include multiple recesses 122 and conductive pads 120 aligned along multiple vertical axes. For example, a first set of recesses 122 and pads 120 may be positioned along a first vertical axis, a second set of recesses 122 and pads 120 may be positioned along a second vertical axis, and so on. Subsequently, multiple channels 204 may be formed in the die stack 202, wherein each channel 204 is connected to a corresponding set of recesses 122 (e.g., as previously referenced). Figures 2B to 2H (Description). One or more material layers 206 may subsequently be deposited into some or all of the channels 204 (e.g., as described above). Figure 2I to 2L Each channel 204 may subsequently be partially or completely filled with a conductive material to form a plurality of conductive structures 208 (e.g., as previously referenced). Figure 2M and 2N (Description). Each conductive structure 208 may be a continuous monolithic structure electrically coupled to a corresponding set of conductive pads 120 and interconnected with the corresponding die 100.

[0057] Figure 3 This is a flowchart illustrating a method 300 for manufacturing a semiconductor assembly according to an embodiment of the present invention. Method 300 can be used to manufacture any of the devices and packages described herein, for example... Figure 1 Semiconductor bare dies 100 and / or Figures 2A to 2O Semiconductor assembly 200.

[0058] Method 300 begins at step 310, wherein at least one recess is formed in each of a plurality of semiconductor dies (e.g., Figure 1The recess 122). The recesses may be formed using semiconductor manufacturing techniques known to those skilled in the art (e.g., selectively removing portions of the semiconductor substrate and / or insulating material by etching and / or other suitable processes). Step 310 may also include forming a conductive pad in each recess, for example by selectively depositing a conductive material in each recess (e.g., Figure 1 Conductive pad 120).

[0059] In step 320, method 300 continues assembling the semiconductor dies into a die stack. Step 320 may include previously referenced... Figure 2A Any of the steps in the discussion. For example, step 320 may include arranging semiconductor dies in a vertical stack such that the surfaces of adjacent semiconductor dies are in direct contact with each other, and then connecting the adjacent semiconductor dies to each other via direct dielectric bonding between insulating materials on the surfaces of the dies.

[0060] In step 330, method 300 includes forming a channel through each of the semiconductor dies after the semiconductor dies have been assembled into a die stack. Step 330 may include previously referenced... Figures 2B to 2H Any of the processes described. For example, step 330 may include removing material from the die stack using etching, drilling, or the like to create channels. The channels may connect to some or all of the recesses to form continuous space within the die stack.

[0061] In step 340, method 300 optionally includes applying at least one material layer to at least a portion of the channel. Step 340 may include the above reference. Figure 2I to 2L Any of the processes described. For example, step 340 may include applying a first material layer (e.g., an insulating material layer) to the wall of the channel, followed by applying a second material layer (e.g., a diffusion barrier material layer) onto the first material layer. As described above, the material layers can be applied using directional deposition processes (e.g., CVD, PVD), and the recess can protect the conductive pad from being covered by the material layer during the directional deposition process, thus keeping the conductive pad at least partially exposed.

[0062] In step 350, method 300 continues to deposit conductive material into the channels and recesses. Step 350 may include the above reference. Figure 2M and 2NAny of the processes described. For example, step 350 may include applying a seed layer to at least a portion of the channel (e.g., to the material layer applied in step 340) and / or to the conductive pads of the semiconductor die, and then forming a conductive material on the seed layer using electroplating (e.g., electroless plating or electroplating) or other suitable material deposition process. The deposition of the conductive material can create a continuous conductive structure within the channel and recess. The conductive structure can be electrically coupled to each of the exposed conductive pads in a semiconductor die stack that is electrically interconnected.

[0063] In some embodiments, the deposition process of step 350 may use a "bottom-up fill" or "overfill" technique to reduce or prevent voiding at the middle portions of channels within the die stack. In such embodiments, step 350 may include introducing at least one additive into the channels and / or recesses according to techniques known to those skilled in the art, such that conductive material is preferentially deposited onto selected areas of the channels and / or recesses. For example, step 350 may include introducing at least one accelerating additive (e.g., bis-(3-sulfopropyl disulfide)) configured to increase the deposition rate on the middle portions of the channels and / or recesses. Alternatively or in combination, step 350 may include introducing at least one inhibiting additive (e.g., polyethylene glycol) configured to reduce the deposition rate on the outer portions of the channels and / or away from the recesses. Thus, conductive material may first fill the middle portions of the channels and / or recesses and then fill the outer portions of the channels, thereby forming a continuous monolithic via with virtually no voiding, seams, gaps, etc.

[0064] In some embodiments, some or all of the steps of method 300 may be repeated to form a die stack having multiple discrete conductive structures of interconnected semiconductor dies. For example, some or all of steps 330, 340, and / or 350 may be performed multiple times, such as two, three, four, five, ten, twenty, or more times. Optionally, after step 350, method 300 may further include incorporating a semiconductor assembly into a semiconductor package, as previously referenced. Figure 2O Description. In such embodiments, method 300 may include mounting a die stack onto a substrate and electrically coupling a conductive structure to the substrate (e.g., directly or via intervening solder bumps, pillars, etc.). Method 300 may subsequently include encapsulating at least a portion of the die stack and / or the substrate with a molding material.

[0065] References above Figures 1 to 3 Any of the semiconductor devices and / or packages with the described features can be incorporated into any of a large number of larger and / or more complex systems, a representative example of which is... Figure 4System 400 is schematically shown in the diagram. System 400 may include a processor 402, a memory 404 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 406, and / or other subsystems or components 408. (See above reference) Figures 1 to 3 The described semiconductor dies and / or assemblies may be included in Figure 4 The resulting system 400 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 400 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, networked appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and microcomputers. Additional representative examples of system 400 include lamps, cameras, vehicles, etc. Regarding these and other examples, system 400 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. Accordingly, components of system 400 can include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0066] In summary, it should be understood that specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Therefore, the invention is not limited except by the appended claims. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be combined or removed in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit such advantages to fall within the scope of the invention. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor assembly comprising: A die stack comprising multiple semiconductor dies, wherein each semiconductor die comprises: The first surface comprises a first insulating material. A second surface, opposite to the first surface, comprises a second insulating material. The recess in the first surface, and Conductive pad, which is located within the recess, Adjacent semiconductor dies in the die stack are directly coupled to each other via the respective first and second insulating materials of the adjacent semiconductor dies; as well as A conductive structure electrically coupled to each of the semiconductor dies, wherein the conductive structure comprises: A monolithic through-hole extending through each of the semiconductor dies in the die stack, and Multiple protrusions extend laterally from the monolithic via, wherein the multiple protrusions and the monolithic via are made of a continuous material, and wherein each protrusion is positioned within a recess of a corresponding one in the semiconductor die and electrically coupled to the conductive pad within the recess.

2. The semiconductor assembly of claim 1, further comprising at least one material layer between the monolithic via and at least one sidewall surface of each semiconductor die.

3. The semiconductor assembly of claim 2, wherein the at least one material layer comprises an insulating layer.

4. The semiconductor assembly of claim 2, wherein the at least one material layer comprises a diffusion barrier layer.

5. The semiconductor assembly of claim 2, wherein the at least one material layer covers no more than a portion of the conductive pad within the recess.

6. The semiconductor assembly of claim 1, wherein the first and second insulating materials each comprise a nitride or an oxide material.

7. The semiconductor assembly of claim 1, wherein each semiconductor die comprises a semiconductor substrate, and the recess extends through the semiconductor substrate.

8. The semiconductor assembly of claim 1, wherein the recess has a width ranging from 5 μm to 50 μm and a depth ranging from 1 μm to 10 μm.

9. A semiconductor assembly comprising: A die stack comprising multiple semiconductor dies, wherein each semiconductor die comprises: The upper surface, which includes an upper dielectric layer, The lower surface, which includes the lower dielectric layer, The recess in the upper surface or the lower surface, and Conductive pad, which is located within the recess, Adjacent semiconductor dies in the die stack are coupled to each other via a direct bonding between the respective upper and lower dielectric layers of the adjacent semiconductor dies; A conductive structure electrically coupled to each of the semiconductor dies, wherein the conductive structure comprises: A single via, which extends continuously through each of the semiconductor dies in the die stack and is positioned adjacent to the recess, and Multiple protrusions extend laterally from the monolithic via, wherein the multiple protrusions and the monolithic via are made of a continuous material, and wherein each protrusion is positioned within a recess of a corresponding one in the semiconductor die and electrically coupled to the conductive pad within the recess; as well as An insulating material is disposed between the monolithic through-hole and at least a portion of each semiconductor die remote from the conductive pad.

10. The semiconductor assembly of claim 9, wherein the monolithic via extends continuously from the upper surface of the uppermost semiconductor die in the die stack to the lower surface of the lowermost semiconductor die in the die stack.

11. The semiconductor assembly of claim 9, wherein the recesses of the semiconductor die are vertically aligned.

12. The semiconductor assembly of claim 9, further comprising a diffusion barrier material between the insulating material and the monolithic via.

13. A method for manufacturing a semiconductor assembly, the method comprising: A recess with a conductive pad is formed on the surface of each of the multiple semiconductor dies; The semiconductor dies are assembled into a die stack such that the recesses are vertically aligned. Forming a channel through each of the semiconductor dies in the die stack, wherein the channel is connected to each of the recesses; At least one material layer is applied to at least a portion of the channel; as well as Conductive material is deposited into each of the channels and recesses to electrically couple the conductive pads of the semiconductor die to each other.

14. The method of claim 13, wherein the conductive material is deposited using an electroless plating process or an electroplating process.

15. The method of claim 14, wherein depositing the conductive material comprises introducing at least one additive into the channel such that the conductive material is preferentially deposited on one or more selected regions of the channel.

16. The method of claim 13, wherein the at least one material layer is applied to at least one sidewall of each semiconductor die and less than all of the conductive pad of each semiconductor die.

17. The method of claim 13, wherein the at least one material layer is applied using a directional deposition process.

18. The method of claim 17, wherein the recess reduces or prevents the at least one material layer from being applied to the conductive pad during the directional deposition process.

19. The method of claim 13, wherein each of the semiconductor dies comprises an upper dielectric layer and a lower dielectric layer, and assembling the semiconductor dies comprises directly bonding the upper and lower dielectric layers of adjacent semiconductor dies to each other.

20. The method of claim 13, wherein the conductive material deposited into the channel forms a monolithic via, and wherein the method further comprises electrically coupling the bottom surface of the monolithic via to a substrate.

21. The method of claim 13, wherein the conductive material deposited into the channel forms a monolithic via, and wherein the method further comprises electrically coupling the upper surface of the monolithic via to another semiconductor die.

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