Display substrate and display device

Abstract

A display substrate and a display device, in which a display area has a lower edge extending in the horizontal direction and a left edge extending in the vertical direction, the display area includes a left display area and a right display area, the left display area includes a first edge display area and a first middle display area extending along the left edge, the horizontal direction and the vertical direction intersect; a frame area surrounds at least part of the display area; a first power supply voltage lead provides a first power supply voltage and is located in the frame area; the first power supply voltage lead includes a lower lead extending along the portion of the lower edge corresponding to the first edge display area, but does not extend along the portion of the lower edge corresponding to the first middle display area; the first power supply voltage line includes an edge voltage line located at the edge of the first edge display area and a middle voltage line located at the first middle display area; the edge voltage line is directly connected to the lower lead to provide the first power supply voltage to the sub-pixel located in the first edge display area, and the middle voltage line is spaced apart from the lower lead.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] Compared with traditional liquid crystal displays (LCDs), organic light-emitting diode (OLED) display products have the advantages of self-luminescence, wide color gamut, high contrast, and light weight, making them widely used in mobile phones, tablet computers and other fields.

[0003] Usually, it is necessary to lead various signal lines such as data lines in the display area to the fan-out region, and then connect to the integrated circuit (IC) through the fan-out region. The fan-out region is located in the border area that does not perform the display function. With people's continuous pursuit of the visual effects of display products, narrow borders and full-screen displays have gradually become the general trend of the development of current OLED display products. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes: a display area, a non-display area, a first power supply voltage lead and a first power supply voltage line. The display area is provided with sub-pixels and has a lower edge extending in a horizontal direction and a left edge extending in a vertical direction, wherein the horizontal direction intersects with the vertical direction, and a dividing line extending in the vertical direction divides the display area into a left display area and a right display area, wherein the left display area includes a first edge display area extending along the left edge and a first middle display area located near the right display area in the first edge display area; the non-display area includes a border area surrounding at least part of the display area; a first power supply voltage lead is configured to provide a first power supply voltage and is located in the border area; the first power supply voltage lead includes a lower lead extending along a portion of the lower edge corresponding to the first edge display area, but does not extend along a portion of the lower edge corresponding to the first middle display area; the first power supply voltage line includes an edge voltage line located along the first edge display area and a middle voltage line located in the first middle display area; the edge voltage line is directly connected to the lower lead to provide the first power supply voltage to the sub-pixel located in the first edge display area, and the middle voltage line is spaced apart from the lower lead.

[0005] For example, in at least one embodiment of the present disclosure, in a display substrate provided, the first power supply voltage line includes a longitudinal voltage line extending along the longitudinal direction and a transverse voltage line extending along the transverse direction, and the longitudinal voltage line and the transverse voltage line are arranged in different layers; the longitudinal voltage line includes an edge longitudinal voltage line located in the first edge display area, and the transverse voltage line includes an edge transverse voltage line located in the first edge display area and intersecting with the edge longitudinal voltage line, and the edge longitudinal voltage line and the edge transverse voltage line constitute the edge voltage line; the first power supply voltage lead also includes a left lead extending along the left edge of the display area, the edge longitudinal voltage line is directly connected to the lower lead, and the edge transverse voltage line is directly connected to the left lead.

[0006] For example, in at least one embodiment of the present disclosure, in a display substrate provided, the sub-pixel includes: a driving transistor, a light-emitting device and a data transistor, the driving transistor is configured to control the size of a driving current flowing through the light-emitting device, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, the data transistor is configured to write a data signal into a gate of the driving transistor in response to a first control signal, and the data line is configured to transmit the data signal to the sub-pixel; the display area includes a lower display area and an upper display area, the lower display area is close to the lower edge, and the upper display area is located on a side of the lower display area away from the lower edge in the longitudinal direction; the lower display area includes a first area and a second area, the first area includes a first sub-area and a second sub-area close to the left edge in the transverse direction A second sub-region away from the left edge, the data line passing through the first sub-region and the second region includes a first connecting line extending along the longitudinal direction in the first sub-region and a second connecting line extending along the transverse direction in the second region; the first connecting line is arranged in the same layer as the longitudinal voltage line, the second connecting line is arranged in the same layer as the transverse voltage line, and the first connecting line and the second connecting line of the same data line are electrically connected through a first connecting hole; the first sub-region is located in the first middle display area, and the second region is at least partially located in the middle display area; the first sub-region has a left endpoint closest to the left edge of the display area in the transverse direction, and a straight line extending along the longitudinal direction and passing through the left endpoint is a boundary line between the first edge display area and the first middle display area.

[0007] For example, in at least one embodiment of the present disclosure, in a display substrate provided, the dividing line passes through the second area and divides the second area into a third sub-area close to the left edge of the display area and a fourth sub-area away from the left edge of the display area, the first sub-area is located in the first edge display area, and the second sub-area is located in the first middle display area; the lower display area also includes a third area, the third area is located in the first edge display area, and is located on the side of the second area away from the first area in the horizontal direction; the edge horizontal voltage line includes a lower edge horizontal voltage line located in the third area, the edge longitudinal voltage line passes through the third area, and is The lower edge transverse voltage line intersects at a first intersection, the left end of the lower edge transverse voltage line is electrically connected to the left lead, and the right end of the lower edge transverse voltage line opposite to the left end is disconnected from the second connection line in the second area by a first break; the edge voltage line includes a plurality of edge longitudinal voltage lines and a plurality of edge transverse voltage lines, and the plurality of edge longitudinal voltage lines and the plurality of edge transverse voltage lines are interwoven into a grid, and the grid includes a plurality of the first intersections; at the position of each of a portion of the plurality of first intersections, one edge longitudinal voltage line is electrically connected to one of the lower edge transverse voltage lines through a first via.

[0008] For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of edge longitudinal voltage lines are electrically connected to the plurality of edge transverse voltage lines through the plurality of first vias, the planar pattern formed by the positions of the plurality of first vias is a connecting line segment located in the third area, and the extension direction of the connecting line segment intersects both the longitudinal direction and the transverse direction.

[0009] For example, in at least one embodiment of the present disclosure, in a display substrate, the third region is a corner region defined by a second side of the second region close to the left edge in the lateral direction, the left edge, and the lower edge.

[0010] For example, in at least one embodiment of the present disclosure, in a display substrate, the frame area includes a frame corner area surrounding the corner area, and a grid-shaped auxiliary first power supply voltage line is arranged in the frame corner area, and the grid-shaped auxiliary first power supply voltage line includes a plurality of longitudinal auxiliary voltage lines and a plurality of transverse auxiliary voltage lines. The plurality of longitudinal auxiliary voltage lines extend along the longitudinal direction and are arranged in the same layer as the longitudinal voltage lines, and each of the plurality of longitudinal auxiliary voltage lines has a first end in the longitudinal direction directly connected to the first power supply voltage lead, and each of the plurality of longitudinal auxiliary voltage lines has a second end in the longitudinal direction opposite to its first end and electrically connected to one of the edge longitudinal voltage lines passing through the corner area; the plurality of transverse auxiliary voltage lines extend along the transverse direction and are arranged in the same layer as the plurality of longitudinal auxiliary voltage lines, and each of the plurality of transverse auxiliary voltage lines has an end in the transverse direction directly connected to the first power supply voltage lead, and each of the plurality of transverse auxiliary voltage lines has a second end in the transverse direction opposite to its first end and electrically connected to one of the edge longitudinal voltage lines.

[0011] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction; the plurality of pixel rows include a plurality of edge pixel rows close to the lower edge; the plurality of horizontal auxiliary voltage lines correspond one-to-one to the plurality of edge pixel rows, each of the plurality of edge pixel rows includes an edge sub-pixel closest to the left edge, and the plurality of edge longitudinal voltage lines include an edgemost longitudinal voltage line passing through the edge sub-pixel of each of the edge pixel rows; the second end of each of the plurality of horizontal auxiliary voltage lines is electrically connected to the edgemost longitudinal voltage line passing through the corresponding edge pixel row, and is electrically connected to the edge horizontal voltage line passing through the corresponding edge pixel row through a first edge via.

[0012] For example, in at least one embodiment of the present disclosure, in a display substrate provided, the transverse voltage line further includes a plurality of first transverse voltage lines, which are arranged in the longitudinal direction and located in the upper display area; the left end of the first transverse voltage line is electrically connected to the left lead, the edge transverse voltage line further includes an upper edge transverse voltage line located in the upper display area, the upper edge transverse voltage line being a part of one of the first transverse voltage lines; the longitudinal voltage line further includes a plurality of middle longitudinal voltage lines, which are arranged in the transverse direction, pass through a portion of the first middle display area and the upper display area along the longitudinal direction, and the plurality of The middle longitudinal voltage line, the multiple edge longitudinal voltage lines and the multiple first transverse voltage lines are interwoven into a grid; the multiple edge longitudinal voltage lines and the multiple first transverse voltage lines intersect at multiple auxiliary intersections in the first edge display area, and at each position of a part of the multiple auxiliary intersections, one edge longitudinal voltage line is electrically connected to one of the first transverse voltage lines through an auxiliary via, and the multiple edge longitudinal voltage lines are electrically connected to the multiple first transverse voltage lines through multiple auxiliary vias; the plane pattern formed by the positions of the multiple auxiliary vias is an auxiliary line segment located in the first edge display area.

[0013] For example, in at least one embodiment of the present disclosure, in a display substrate, an extension direction of the auxiliary line segment is the same as an extension direction of the connecting line segment; the display substrate includes a plurality of the auxiliary line segments, and the connecting line segment and the plurality of auxiliary line segments are arranged at intervals from each other along the longitudinal direction.

[0014] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area also includes an upper edge opposite to the lower edge, the first power supply voltage lead also includes an upper lead extending along the upper edge, and the upper lead is electrically connected to the left lead; the upper end of the edge longitudinal voltage line is connected to the upper lead, and the lower end of the edge longitudinal voltage line opposite to the upper end is directly connected to the lower lead; the longitudinal voltage line includes a middle longitudinal voltage line located in the first middle display area, and the middle longitudinal voltage line includes: a first longitudinal voltage line and a second longitudinal voltage line. A first longitudinal voltage line sequentially passes through the upper display area and at least part of the second area along the longitudinal direction, an upper end of the first longitudinal voltage line is electrically connected to the upper lead, and a lower end of the first longitudinal voltage line opposite to the upper end is disconnected from the first connecting line in the first sub-area by a second break; a second longitudinal voltage line sequentially passes through the upper display area and the first area along the longitudinal direction; the transverse voltage line includes an intermediate transverse voltage line located in the first area, the intermediate transverse voltage line is disconnected from the second connecting line in the second area by a third break, the second longitudinal voltage line intersects with the intermediate transverse voltage line at a second intersection, and the second longitudinal voltage line is electrically connected to the intermediate transverse voltage line at the second intersection through a second via.

[0015] For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of first transverse voltage lines intersect with the plurality of second longitudinal voltage lines at a plurality of third intersections, and at each position of at least a portion of the plurality of third intersections, one of the first transverse voltage lines is electrically connected to one of the second longitudinal voltage lines through a third via.

[0016] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area also includes a right edge opposite to the left edge, the first power lead also includes a right lead extending along the right edge, and the right lead is electrically connected to the upper lead; each of the multiple first horizontal voltage lines passes through the upper display area along the horizontal direction, and the right end of each of the multiple first horizontal voltage lines opposite to its left end is electrically connected to the right lead.

[0017] For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of intermediate longitudinal voltage lines and the plurality of first transverse voltage lines intersect with each other at a plurality of fourth intersections in the upper display area, and at each position of a part of the plurality of fourth intersections, one of the intermediate longitudinal voltage lines is electrically connected to one of the first transverse voltage lines through a fourth via hole; and a planar pattern formed by the positions of the plurality of fourth via holes is a fold line.

[0018] For example, in a display substrate provided in at least one embodiment of the present disclosure, the fold line includes a plurality of sub-fold lines extending from the left edge to the right edge, each of the plurality of sub-fold lines includes a plurality of fold line segments connected end to end; the plurality of fold line segments include a first line segment extending along a first direction and a second line segment extending along a second direction, the first direction intersects with the second direction, and the first direction and the second direction both intersect with the horizontal direction and the longitudinal direction, the first end of the first line segment intersects with the first end of the second line segment at an upper vertex; the plurality of vertices of the plurality of sub-fold lines are located on the second longitudinal voltage line, and the fourth vias at the positions of the vertices are all the second vias.

[0019] For example, in at least one embodiment of the present disclosure, in a display substrate provided, each of the plurality of sub-fold lines is W-shaped.

[0020] For example, in a display substrate provided in at least one embodiment of the present disclosure, the W-shaped sub-fold line includes the first line segment and the second line segment, a third line segment and a fourth line segment, the first line segment and the second line segment are located between the third line segment and the fourth line segment, the third line segment is connected to the first line segment, and the fourth line segment is connected to the second line segment; the first line segment is substantially parallel to the fourth line segment, and the second line segment is substantially parallel to the third line segment.

[0021] For example, in a display substrate provided in at least one embodiment of the present disclosure, the longitudinal direction is perpendicular to the transverse direction, the angle between the first line segment and the transverse direction is 45°, and the angle between the second line segment and the transverse direction is 45°.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the longitudinal direction, the auxiliary line segment is located between the third line segments of two adjacent sub-folding lines.

[0023] For example, in a display substrate provided in at least one embodiment of the present disclosure, the connecting line segment, the auxiliary line segment and the third line segment are substantially parallel to each other.

[0024] For example, in a display substrate provided in at least one embodiment of the present disclosure, the second longitudinal voltage line divides the first region into the first sub-region and the second sub-region, and the structure of the first sub-region and the structure of the second sub-region are basically axially symmetrical with respect to the second longitudinal voltage line; the lower display area includes a fourth region, and the structure of the fourth region and the structure of the second region are basically axially symmetrical with respect to the second longitudinal voltage line; the data line passing through the first region and the fourth region includes a third connecting line extending along the longitudinal direction in the second sub-region and a fourth connecting line extending along the transverse direction in the fourth region; the third connecting line is arranged in the same layer as the longitudinal voltage line, and the fourth connecting line is arranged in the same layer as the transverse voltage line, and the third connecting line and the fourth connecting line of the same data line are electrically connected through a second connecting hole; the right end of the middle transverse voltage line located in the first region opposite to its left end is disconnected from the fourth connecting line in the fourth region by a fourth break.

[0025] For example, in at least one embodiment of the present disclosure, the display substrate includes a plurality of first connection lines, a plurality of second connection lines, a plurality of third connection lines and a plurality of fourth connection lines; the plurality of first connection lines are electrically connected to the plurality of second connection lines through a plurality of first connection holes, respectively, and the plurality of third connection lines are electrically connected to the plurality of fourth connection lines through a plurality of second connection holes, respectively; the planar pattern formed by the plurality of first connection holes is a fifth line segment, and the fifth line segment is the boundary between the first area and the second area; the planar pattern formed by the plurality of second connection holes is a sixth line segment, and the sixth line segment is the boundary between the first area and the fourth area; the lower display area also includes a fifth area, and the structure of the fifth area is basically axially symmetrical with the structure of the third area relative to the second longitudinal voltage line, and the planar pattern of the plurality of fifth vias symmetrical to the plurality of first vias in the fifth area is a seventh line segment; the planar pattern formed by sequentially connecting the connection line segment, the fifth line segment, the sixth line segment and the seventh line segment is the same as the planar pattern of each of the plurality of sub-fold lines.

[0026] For example, in at least one embodiment of the present disclosure, in a display substrate, the planar shape of the first area is a first triangle, and the planar shape of the second area is a second triangle, and the first side of the first triangle close to the left edge in the lateral direction and the first side of the second triangle far from the left edge of the display area in the lateral direction at least partially overlap; the two lower vertices of the first triangle are located on the lower edge of the display area, and the left vertex of the two lower vertices of the first triangle close to the left edge is the left endpoint of the first sub-area; the first triangle is an isosceles triangle, and the second longitudinal voltage line is basically the perpendicular bisector of the base of the isosceles triangle.

[0027] For example, in a display substrate provided in at least one embodiment of the present disclosure, the frame area includes a left frame area extending along the left edge, and a plurality of auxiliary connection lines extending along the horizontal direction are arranged in the left frame area, and the plurality of auxiliary connection lines are arranged in the same layer as the edge longitudinal voltage line; the display area includes a pixel array, and the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the longitudinal direction; the plurality of pixel columns include an edge pixel column closest to the left edge, and the plurality of edge longitudinal voltage lines include an outer edge longitudinal voltage line passing through the edge pixel column; each of the plurality of auxiliary connection lines is electrically connected to the left lead at its left end in the horizontal direction, and each of the plurality of auxiliary connection lines is electrically connected to the outer edge longitudinal voltage line at its right end opposite to its left end in the horizontal direction, and is electrically connected to the left end of a corresponding one of the first horizontal voltage lines through a second edge via.

[0028] For example, in a display substrate provided in at least one embodiment of the present disclosure, the right display area includes a second edge display area extending along the right edge and a second middle display area located on a side of the second edge display area close to the left display area; the second edge display area is symmetrical with the first edge display area with respect to an axis of symmetry extending along the longitudinal direction, and the second middle display area is axially symmetrical with the first middle display area with respect to the second longitudinal voltage line.

[0029] For example, in at least one embodiment of the present disclosure, the display substrate further includes: a second power supply voltage line, configured to provide the sub-pixel with a second power supply voltage different from the first power supply voltage; the longitudinal voltage line is arranged in the same layer as the data line in the upper display area, and the transverse voltage line is arranged in the same layer as the second power supply voltage line.

[0030] At least one embodiment of the present disclosure further provides a display device, comprising any one of the display substrates provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0032] Figure 1 The figure is a schematic overall plan view of a display substrate provided according to an embodiment of the present disclosure.

[0033] Figure 2 To include Figure 1 A partial enlarged schematic diagram of the lower display area and part of the upper display area.

[0034] Figure 3A for Figure 1 A locally enlarged schematic diagram of region R1 in FIG.

[0035] Figure 3B-3D for Figure 1 Schematic diagram of part of the film layer in area R1.

[0036] Figure 4 To include Figure 1 A locally enlarged schematic diagram of region R2 and region R3 in FIG.

[0037] Figure 5A for Figure 4 A locally enlarged schematic diagram of region R2 in FIG.

[0038] Figures 5B-5D for Figure 4 Schematic diagram of part of the film layer in area R2.

[0039] Fig. 6A for Figure 1 A locally enlarged schematic diagram of area R3 in FIG.

[0040] Figure 6B-6D for Figure 1 Schematic diagram of part of the film layer in area R3.

[0041] Fig. 7A for Figure 1 A locally enlarged schematic diagram of area R4 in FIG.

[0042] Figures 7B-7D for Figure 1 Schematic diagram of part of the film layer in area R4.

[0043] Fig. 8A for Figure 1 A locally enlarged schematic diagram of area R5 in FIG.

[0044] Figures 8B-8C for Figure 1 Schematic diagram of part of the film layer in area R5.

[0045] Fig. 9 for Figure 1 A locally enlarged schematic diagram of area R6 in FIG.

[0046] Fig.10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0047] Figures 11A-11H Includes a schematic diagram of the different film layers in the pixel circuit.

[0048] Fig.11I for Figures 11A-11F Schematic diagram of film layer stacking.

[0049] Fig.12 It is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] The drawings in this disclosure are not drawn strictly according to the actual scale, and the number of horizontal voltage lines, vertical voltage lines, and various vias in the display substrate is not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structure.

[0053] The features such as "parallel", "perpendicular", and "identical" used in this disclosure include the features such as "parallel", "perpendicular", and "identical" in the strict sense, as well as the cases where "substantially parallel", "substantially perpendicular", "substantially identical", etc. contain certain errors, taking into account the errors associated with the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0054] When the number of a component is not specifically indicated in the following of the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0055] The "same layer" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (such as a patterning process). The "same layer" here does not always mean that the thickness of the multiple film layers is the same or the height of the multiple film layers in the cross-sectional view is the same.

[0056] Words indicating directions such as “longitudinal”, “transverse”, “upper”, “lower”, “left”, and “right” used in the present disclosure are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly, and are not limited to the directions shown in the drawings of the specification. For example, the “upper edge”, “lower edge”, “left edge”, and “right edge” are not limited to the up, down, left, and right shown in the drawings, as long as the relative position relationship defined for them is satisfied. The “left display area” and “right display area” are also not limited to the left and right in the drawings of the specification of this application, as long as the relative position relationship defined for them is satisfied. The “upper display area” and “lower display area” are also not limited to the upper and lower in the drawings of the specification of this application, as long as the relative position relationship defined for them is satisfied.

[0057] At least one embodiment of the present disclosure provides a display substrate, which includes: a display area, a non-display area, a first power supply voltage lead and a first power supply voltage line. The display area is provided with sub-pixels and has a lower edge extending in a horizontal direction and a left edge extending in a vertical direction, wherein the horizontal direction intersects with the vertical direction, and a dividing line extending in the vertical direction divides the display area into a left display area and a right display area, wherein the left display area includes a first edge display area extending along the left edge and a first middle display area located near the right display area in the first edge display area; the non-display area includes a border area surrounding at least part of the display area; a first power supply voltage lead is configured to provide a first power supply voltage and is located in the border area; the first power supply voltage lead includes a lower lead extending along a portion of the lower edge corresponding to the first edge display area, but does not extend along a portion of the lower edge corresponding to the first middle display area; the first power supply voltage line includes an edge voltage line located along the first edge display area and a middle voltage line located in the first middle display area; the edge voltage line is directly connected to the lower lead to provide the first power supply voltage to the sub-pixel located in the first edge display area, and the middle voltage line is spaced apart from the lower lead.

[0058] At least one embodiment of the present disclosure further provides a display device, comprising any one of the display substrates provided in the embodiments of the present disclosure.

[0059] For example, Figure 1 is a schematic overall plan view of a display substrate provided according to an embodiment of the present disclosure, Figure 2 To include Figure 1 A partial enlarged schematic diagram of the lower display area and part of the upper display area in FIG. Figure 1As shown, the display substrate 10 provided by at least one embodiment of the present disclosure includes: a display area 1, a frame area 2, a first power supply voltage lead 4 and a first power supply voltage line vss. The display area 1 is provided with sub-pixels, and has a lower edge 1a extending along the horizontal direction X and a left edge 1b extending along the longitudinal direction Y. The horizontal direction intersects with the longitudinal direction, for example, the horizontal direction is perpendicular to the longitudinal direction; of course, in other embodiments, the horizontal direction and the longitudinal direction may not be perpendicular. The display area 1 includes a left display area 11 and a right display area 12 arranged in the horizontal direction X. For example, a dividing line ML extending along the longitudinal direction Y divides the display area 1 into a left display area 11 and a right display area 12. For example, the dividing line ML is the midline of the lower edge 1a, so that the left display area 11 and the right display area 12 are symmetrical, and the display effect of the entire display substrate 10 is uniform, but it is not limited to the case where the dividing line ML is the midline of the lower edge 1a. The left display area 11 includes a first edge display area 11P extending along the left edge 1b and a first middle display area 11M located in the first edge display area 11P and close to the right display area 12; the frame area 2 is a non-display area surrounding at least part of the display area 1. For example, the display substrate 10 may further include a pad 3, which is located on a side of the lower edge 1a away from the display area 1; a first power supply voltage lead 4 is connected to the pad 3 to be configured to provide a first power supply voltage VSS, and is located within the border area 2; the first power supply voltage lead 4 includes a lower lead 41 extending along a portion of the lower edge 1a corresponding to the first edge display area 11P, but does not extend along a portion of the lower edge 1a corresponding to the first intermediate display area 11M; the first power supply voltage line vss includes an edge voltage line LP located in the first edge display area 11P and an intermediate voltage line LM located in the first intermediate display area 11M, the edge voltage line LP is in contact with the lower lead 41 and is electrically connected to provide the first power supply voltage VSS to the sub-pixel located in the first edge display area 11P, and the intermediate voltage line LM is spaced apart from the lower lead 41, that is, the intermediate voltage line LM is not directly connected to the lower lead 4 from the pad 3. In this way, in the display substrate 10 provided in the embodiment of the present disclosure, the edge voltage line is in contact with the lower lead 41 and is electrically connected to provide a VSS signal to the sub-pixel of the first edge display area 11P, and the middle voltage line LM is separated from the lower lead 41, that is, not in contact, but is connected to the left lead 42 or the upper lead 43, or other first power supply voltage lines vss to provide a VSS signal to the first middle display area 11M, that is, the first power supply voltage lead 4 led out from the pad 3 set on the side of the lower edge 1a away from the display area is not directly connected to the first middle display area 11M, that is, the middle voltage line LM is not connected to the pad 3 through the frame area 2, is not directly connected to the lower lead 41 of the first power supply voltage lead 4, and does not obtain the first power supply voltage VSS through the pad 3, but obtains the first power supply voltage VSS through the edge voltage line, thereby reducing the wiring set in the fan-out area, further reducing the fan-out area, so as to reduce the width of the lower frame, and further achieve a narrower frame.

[0060] For example, the edge voltage line LP is directly connected to the lower lead 41, that is, the edge voltage line LP and the lower lead 41 are in contact with each other, and there is no other structure between the edge voltage line LP and the lower lead 41 as a medium for connecting the two; for example, the edge voltage line LP and the lower lead 41 are arranged on the same layer and constitute a continuous integrated structure. In this case, the material of the edge voltage line LP and the lower lead 41 is the same and can be formed by the same composition process. In this way, the structure and manufacturing process of the display substrate can be simplified.

[0061] Of course, in other embodiments, the edge voltage line LP and the lower lead 41 can be arranged in different layers, and the two are in contact with each other through vias. It should be noted that in the present disclosure, the term "direct connection" means that two structures connected to each other (for example, the edge voltage line LP is directly connected to the lower lead 41, etc.) are in contact with each other, and there is no other structure between the two structures connected to each other as a medium for the connection between the two. For example, the two structures directly connected to each other can be a continuous one-piece molding structure. In this case, the materials of the two structures directly connected to each other are the same, and the two structures can be formed by the same composition process to simplify the manufacturing process of the display substrate; or, the materials of the two structures directly connected to each other can also be different. For example, the two structures directly connected to each other are both conductive signal lines, and the two can respectively use materials that match their functions to meet the needs of different performances such as different conductivity.

[0062] For example, for example, Figure 1 As shown, the first power supply voltage line vss includes a longitudinal voltage line YL extending along the longitudinal direction Y and a transverse voltage line XL extending along the transverse direction X, and the longitudinal voltage line YL and the transverse voltage line XL are arranged in different layers; the longitudinal voltage line YL includes an edge longitudinal voltage line YLP located in the first edge display area 11P, and the transverse voltage line XL includes an edge transverse voltage line XLP located in the first edge display area 11P and intersecting with the edge longitudinal voltage line YLP, and the edge longitudinal voltage line YLP and the edge transverse voltage line XLP constitute an edge voltage line LP; the first power supply voltage lead 4 also includes a left lead 42 extending along the left edge 1b of the display area 1, for example, the edge longitudinal voltage line YLP is connected to the lower lead 41, for example, arranged in the same layer and directly connected, and the edge transverse voltage line XLP is connected to the left lead 42, for example, arranged in the same layer and directly connected. For example, the edge longitudinal voltage line YLP runs through the entire display area in the first edge display area 11P in the longitudinal direction to provide the first power supply voltage VSS to the sub-pixels of the entire first edge display area 11P. In this way, the edge longitudinal voltage line YLP is directly connected to the lower lead 41 close thereto, which can save space and is beneficial to reducing the frame area outside the lower edge 1a.

[0063] For example, a first power supply voltage pin No. 1 4a is provided on the pad 3, the lower lead 41 is electrically connected to the first power supply voltage pin 4a, and the first power supply voltage pin 4a is located at the first end of the pad 3 close to the first edge display area 11P in the horizontal direction X. Therefore, the first power supply voltage pin 4a, the lower lead 41 and the edge longitudinal voltage line YLP of the first edge display area 11P are directly connected in sequence, which can effectively reduce the routing of the lower frame and reduce the frame area outside the lower edge 1a.

[0064] For example, Figure 1 As shown, in some embodiments, a first power supply voltage pin No. 2 4b may also be provided on the pad 3, and the first power supply voltage pin No. 2 4b is close to the right edge 1d, that is, located at the second end of the pad 3 in the horizontal direction X close to the second edge display area 12P below, and the structure related to the first power supply voltage line vss of the second edge display area 12P and the first edge display area 11P is axially symmetrical with respect to the symmetry axis extending along the longitudinal direction Y. Similar to the first power supply voltage pin No. 1 4a and the first power supply voltage line vss in the first edge display area 11P, the first power supply voltage pin No. 2 4b is directly connected to the edge longitudinal voltage line in the second edge display area 12P to provide the first power supply voltage VSS to the sub-pixels of the second edge display area 12P.

[0065] Fig. 6A for Figure 1 A partial enlarged schematic diagram of region R3 in FIG. Figure 6B-6D for Figure 1 Schematic diagram of a portion of the film layer in region R3. Figure 1 and Fig. 6A As shown, the lower end of the edge longitudinal voltage line YLP close to the lower lead 41 is connected. For example, the lower end of the edge longitudinal voltage line YLP is directly connected to the lower lead 41; for example, the edge longitudinal voltage line YLP and the lower lead 41 are arranged in the same layer and made of the same material, and can be formed by performing the same patterning process on the same film layer; for example, the edge longitudinal voltage line YLP and the lower lead 41 form an integrally formed structure.

[0066] Fig. 9 for Figure 1 A partial enlarged schematic diagram of region R6 in FIG. Figure 1 and Fig. 9As shown, the display area 1 further includes an upper edge 1c opposite to the lower edge 1a, and the first power supply voltage lead 4 further includes an upper lead 43 extending along the upper edge 1c, and the upper lead 43 is electrically connected to the left lead 42; the upper end of the edge longitudinal voltage line YLP is connected to the upper lead 43. For example, the upper end of the edge longitudinal voltage line YLP is directly connected to the upper lead 43; for example, the edge longitudinal voltage line YLP and the upper lead 43 are arranged in the same layer and made of the same material, and can be formed by performing the same patterning process on the same film layer; for example, the edge longitudinal voltage line YLP and the upper lead 43 form an integrated structure, so as to more reliably provide the first power supply voltage VSS through the edge longitudinal voltage line YLP, and reduce the connection resistance using the cross-layer connection method.

[0067] Of course, in some embodiments, the edge longitudinal voltage line and the upper lead and the lower lead may also be set in different layers, and the edge longitudinal voltage line is connected to the upper lead and the lower lead respectively through vias that penetrate the insulating layer between the conductive layer where the edge longitudinal voltage line is located and the conductive layer where the upper lead and the lower lead are located.

[0068] For example, Figure 1 As shown, combined Fig.10 The equivalent circuit diagram of the pixel circuit shown in FIG. 1 is a display substrate 10 further including a data line data, a sub-pixel including: a driving transistor T3, a light-emitting element and a data transistor T4, the driving transistor T3 is configured to control the magnitude of a driving current flowing through the light-emitting element, the light-emitting element is configured to receive the driving current and be driven by the driving current to emit light, the data transistor T4 is configured to write a data signal DATA into the gate of the driving transistor T3 in response to a first control signal, and the data line data is configured to transmit the data signal DATA to the sub-pixel; the display area 1 domain includes a lower display area 14 and an upper display area 13, the lower display area 14 is close to the lower edge 1a, and the upper display area 13 is located on a side of the lower display area 14 away from the lower edge 1a in the longitudinal direction; the lower display area 14 includes a first area ① and a second area ②, the first area ① includes a first area ① and a second area ② in the transverse direction X The first sub-region A close to the left edge 1b and the second sub-region B far from the left edge 1b, the data line data passing through the first sub-region A and the second region ② includes a first connection line DL1 extending along the longitudinal direction Y in the first sub-region A, a second connection line DL2 extending along the transverse direction X in the second region ②, and a fifth connection line DL5 extending along the longitudinal direction Y in the upper display area 13, the fifth connection line DL5 is arranged in the same layer as the first connection line DL1; the first connection line DL1 is arranged in the same layer as the longitudinal voltage line YL, the second connection line DL2 is arranged in the same layer as the transverse voltage line XL, the first connection line DL1 of the same data line data is electrically connected to the second connection line DL2 through the first connection hole VC1, and the fifth connection line DL5 of the same data line data is electrically connected to the third connection hole VC3 of the second connection line DL2. Thus, for a data line data, a line is formed as follows: Figure 1The three arrows in FIG. 4 indicate the transmission channels of the data signal DATA. For example, the plurality of data lines data are respectively connected to the pad 3 through the plurality of data signal leads CL, for example, are electrically connected to the integrated circuit IC in the pad 3 to provide the data line data with the data signal DATA.

[0069] For example, the first sub-region A is located in the first middle display area 11M, and the second region ② is at least partially located in the first middle display area 11M; the first sub-region A has a left end point PO closest to the left edge 1b of the display area 1 in the horizontal direction X, and the straight line extending along the longitudinal direction Y and passing through the left end point PO is the boundary line IL between the first edge display area 11P and the first middle display area 11M. That is, the area between the straight line and the left edge 1b is the first edge display area 11P. The first sub-region A is located in the first middle display area 11M.

[0070] For example, Figure 1-2 As shown, the dividing line IL passes through the second area ② and divides the second area ② into a third sub-area A close to the left edge 1b of the display area 1 and a fourth sub-area B away from the left edge 1b of the display area 1, the first sub-area A is located in the first edge display area 11P, and the second sub-area B is located in the first middle display area 11M.

[0071] Figure 3A for Figure 1 A partial enlarged schematic diagram of region R1 in FIG. Figure 3B-3D for Figure 1 Schematic diagram of part of the membrane layer in region R1. Figure 1-2 and Figures 3A-3D , or combined Figure 1 and Figures 6A-6D , the lower display area 14 also includes a third area ③, the third area ③ is located in the first edge display area 11P, and is located on the side of the second area ② away from the first area ① in the horizontal direction X; the edge transverse voltage line XLP includes a lower edge transverse voltage line XLP1 located in the third area ③, the edge longitudinal voltage line YLP passes through the third area ③, and intersects with the lower edge transverse voltage line XLP1 at a first intersection point P1, the left end of the lower edge transverse voltage line XLP1 is electrically connected to the left lead 42, and the right end of the lower edge transverse voltage line XLP1 opposite to its left end is disconnected from the second connection line DL2 in the second area ② through the first break OP1. The first break OP1 can be referred to Figure 1-2 , Figure 3A-3BIt is a partial schematic diagram, which only shows a limited number of pixels, and therefore, the first break OP1 is not illustrated. The edge voltage line includes a plurality of edge longitudinal voltage lines YLP and a plurality of edge transverse voltage lines XLP, and the plurality of edge longitudinal voltage lines YLP and the plurality of edge transverse voltage lines XLP are interwoven into a grid, and the grid includes a plurality of first intersections P1; at each position of a portion of the plurality of first intersections P1, an edge longitudinal voltage line YLP is electrically connected to a lower edge transverse voltage line XLP1 through a first via V1, so that there are a plurality of first vias V1 at the plurality of first intersections P1. In this way, the plurality of edge longitudinal voltage lines YLP and the plurality of lower edge transverse voltage lines XLP1 are electrically connected in the third region ③ to form a mesh structure, which can reduce the resistance of the first power supply voltage line vss transmitting the first power supply voltage VSS in the third region ③, and the voltage drop on the meshed first power supply voltage line vss formed by the edge longitudinal voltage lines YLP and the lower edge transverse voltage lines XLP1 in the third region ③ is low.

[0072] For example, Figure 3B The film layers shown are Figure 3C There is a first insulating layer between the film layers shown, a first via hole V1 penetrates the first insulating layer, and the edge longitudinal voltage line YLP is electrically connected to the lower edge transverse voltage line XLP1 through a first connection structure C1 passing through the first via hole V1.

[0073] For example, all first power supply voltage lines vss (vertical voltage lines YL) extending in the longitudinal direction Y in the display area 1 are arranged in the same layer as the data lines data in the upper display area 13, and the second power supply voltage lines XL in the display area 1 are arranged in the same layer; all first power supply voltage lines vss (horizontal voltage lines XL) extending in the X direction are located on the side of the longitudinal voltage line YL close to the substrate. For example, the longitudinal voltage line YL is located in the sixth conductive layer 580 below, and the horizontal voltage line XL is located in the fifth conductive layer 570 below. Of course, in other embodiments, it is not limited to this, as long as the longitudinal voltage line YL and the horizontal voltage line XL are arranged in different metal layers, and a first insulating layer is arranged between the two metal layers.

[0074] Figure 3A-3B Three first via holes V1 are shown as an example, but the number of the first via holes V1 is not limited.

[0075] For example, refer to Figure 1-2 , the plurality of edge longitudinal voltage lines YLP are electrically connected to the plurality of edge transverse voltage lines XLP through the plurality of first via holes V1, and the plane pattern formed by the positions of the plurality of first via holes V1 is the connection line segment SC located in the third area ③ ( Figure 1The dotted line in the third area ③ in the figure represents a connecting line segment SC), and the extending direction of the connecting line segment SC intersects both the horizontal direction X and the vertical direction Y. Here, the "planar pattern formed by the positions of the plurality of first via holes V1" refers to the overall pattern formed by the arrangement of the positions of the plurality of first via holes V1.

[0076] For example, in Figure 1-2 In the embodiment shown, the connecting line segment SC is a straight line segment to keep consistent with the shape of the W-shaped broken line described below. Of course, in other embodiments, if necessary, the connecting line segment SC may also be a curved line segment.

[0077] For example, Figure 1 As shown, the third area ③ is a corner area defined by the first side SL1, the left edge 1b and the lower edge 1a of the second area ② in the horizontal direction X. The third area ③ is a corner area in which the first break OP1 originally set due to the design of the data line data passing through the second area ② and the first area ① (Fanout in pixel, FIP technology) can be connected to the first power supply voltage signal in the corner area, thereby preventing signal interference caused by the floating wire, such as static electricity easily accumulated in the floating wire and causing static electricity interference.

[0078] The planar pattern of the plurality of third connection holes VC3 for respectively connecting the fifth connection line DL5 of the plurality of data lines data and the second connection line DL2 is a line segment, such as a straight line segment, which serves as the first side SL1 of the second area ② and also as the boundary between the third area ③ and the second area ②.

[0079] For example, refer to Figure 1-2 The frame area 2 includes a frame corner area 20 surrounding the corner area ③, and a grid-shaped auxiliary first power supply voltage line vss is arranged in the frame corner area 20. In this way, the voltage drop of the first power supply low voltage line in the first edge display area 11P can be greatly reduced.

[0080] Figure 4 To include Figure 1 A partial enlarged schematic diagram of the region R2 and the region R3, wherein the region R2 includes the frame corner region 20; Figure 5A for Figure 4 A partial enlarged schematic diagram of region R2 in FIG. Figures 5B-5D for Figure 4 Schematic diagram of a portion of the membrane layer in region R2. Figure 4 and Figures 5A-5DThe grid-shaped auxiliary first power supply voltage line vss includes: a plurality of longitudinal auxiliary voltage lines YAL and a plurality of transverse auxiliary voltage lines XAL. A plurality of longitudinal auxiliary voltage lines YAL extend along the longitudinal direction Y and are arranged in the same layer as the longitudinal voltage lines YL, wherein each of the plurality of longitudinal auxiliary voltage lines YAL has a first end in the longitudinal direction Y directly connected to the first power supply voltage lead 4 (e.g., the lower lead 41 or a corner lead connecting the lower lead 41 and the left lead 42), and each of the plurality of longitudinal auxiliary voltage lines YAL has a second end in the longitudinal direction Y opposite to the first end electrically connected to an edge longitudinal voltage line YLP passing through the corner area ③, for example, directly connected; a plurality of transverse auxiliary voltage lines XAL extend along the transverse direction X and are arranged in the same layer as the plurality of longitudinal auxiliary voltage lines YAL, wherein each of the plurality of transverse auxiliary voltage lines XAL has an end in the transverse direction X directly connected to the first power supply voltage lead 4 (e.g., the left lead 42 or a corner lead connecting the lower lead 41 and the left lead 42), and each of the plurality of transverse auxiliary voltage lines XAL has a second end in the transverse direction X opposite to the first end electrically connected to an edge longitudinal voltage line YLP. Figure 5D The multiple longitudinal auxiliary voltage lines YAL and the multiple transverse auxiliary voltage lines are arranged in the same layer, for example, in the same layer as the longitudinal voltage lines YL. The longitudinal auxiliary voltage lines YAL, the transverse auxiliary voltage lines and the longitudinal voltage lines YL can be formed simultaneously through the same patterning process to simplify the structure and manufacturing process of the display substrate.

[0081] For example, refer to Figures 5A-5D , the display area 1 includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction X and a plurality of pixel columns extending along the vertical direction Y; the plurality of pixel rows include a plurality of edge pixel rows PXR close to the lower edge 1a; a plurality of horizontal auxiliary voltage lines XAL correspond one-to-one to the plurality of edge pixel rows PXR, each of the plurality of edge pixel rows PXR includes an edge sub-pixel P closest to the left edge 1b, a plurality of edge longitudinal voltage lines YLP include an edgemost longitudinal voltage line YLP0 passing through the edge sub-pixel P of each edge pixel row PXR; the second end of each of the plurality of horizontal auxiliary voltage lines XAL is electrically connected to the edgemost longitudinal voltage line YLP0 passing through the corresponding edge pixel row PXR, for example, directly connected; and the second end of each of the plurality of horizontal auxiliary voltage lines XAL is electrically connected to the edge horizontal voltage line XLP passing through the corresponding edge pixel row PXR through a first edge via VP1. Figure 5C As shown, the second end of the horizontal auxiliary voltage line XAL is electrically connected to the edge horizontal voltage line XLP of the corresponding edge pixel row PXR through the first edge connection structure CP1 passing through the first insulating layer. Figures 5A-5DThe connection relationship of a horizontal auxiliary voltage line XAL to a corresponding edge pixel row PXR closest to the lower edge 1a is shown, and the connection of other edge pixel rows PXR is the same, except that in this embodiment, in order to adapt to the shape of the corner area, the lengths of the horizontal auxiliary voltage lines XAL corresponding to the edge pixel rows PXR are different. In other embodiments, if necessary, the lengths of the horizontal auxiliary voltage lines XAL of the edge pixel rows PXR can also be designed to adapt to the pixel arrangement of the display substrate.

[0082] For example, Figure 1 and Figure 5A-5B As shown, the second power supply voltage lead 4b-1 is located in the lower border area surrounding the lower edge 1a, and is electrically connected to the second power supply voltage pin 4b. The second power supply voltage line passing through multiple pixel columns is electrically connected to the second power supply voltage lead 4b-1, thereby providing the second power supply voltage VDD to the pixels of the multiple pixel columns.

[0083] For example, Figure 1 As shown, the horizontal voltage line XL also includes a plurality of first horizontal voltage lines XLU, which are arranged in the longitudinal direction Y and located in the upper display area 13; the left end of the first horizontal voltage line XLU is electrically connected to the left lead 42, and the edge horizontal voltage line XLP also includes an upper edge horizontal voltage line XLP2 located in the upper display area 13, and the upper edge horizontal voltage line XLP2 is a part of a first horizontal voltage line XLU. The longitudinal voltage line YL also includes a plurality of middle longitudinal voltage lines YLM, which are arranged in the transverse direction X and pass through a portion of the first middle display area 11M and the upper display area 13 along the longitudinal direction Y; the plurality of middle longitudinal voltage lines YLM, the plurality of edge longitudinal voltage lines YLP and the plurality of first horizontal voltage lines XLU are interwoven into a grid to reduce the resistance of the first power supply voltage line vss and reduce the voltage drop on the first power supply voltage line vss.

[0084] Multiple edge longitudinal voltage lines YLP and multiple first transverse voltage lines XLU intersect at multiple auxiliary intersections AP in the first edge display area 11P. At each position of a part of the multiple auxiliary intersections AP, one edge longitudinal voltage line YLP is electrically connected to one first transverse voltage line XLU in the first edge display area 11P through an auxiliary via AV. Multiple edge longitudinal voltage lines YLP are electrically connected to multiple first transverse voltage lines XLU through multiple auxiliary vias AV. The plane pattern formed by the positions of multiple auxiliary vias AV is an auxiliary line segment SA located in the first edge display area 11P. One end of the auxiliary line segment SA away from the left edge 1b is suspended, that is, there is no via pattern connected to one end of the auxiliary line segment SA away from the left edge 1b. The auxiliary line segment SA is different from the third line segment S3 of the W-shaped fold line described below. In this way, the resistance of the first power supply voltage line vss in the first edge display area 11P can be further effectively reduced, and the voltage drop of the first power supply voltage line vss in the first edge display area 11P can be reduced.

[0085] At the position of the auxiliary line segment SA, an edge longitudinal voltage line YLP is electrically connected to a first transverse voltage line XLU in the first edge display area 11P through an auxiliary via AV. Figures 3A-3D The structure of the region R1 shown is the same as that of Figures 3A-3D , which will not be repeated here.

[0086] For example, continue to refer to Figure 1 The extension direction of the auxiliary line segment SA is the same as the extension direction of the connecting line segment SC. For example, the length of the auxiliary line segment SA is the same as the length of the connecting line segment SC, so as to maintain the uniformity of the arrangement trend of the connection points connected by the via holes and prevent the display substrate from generating mura defects. For example, the display substrate 10 includes a plurality of auxiliary line segments SA, and the connecting line segment SC and the plurality of auxiliary line segments SA are arranged in a spaced relationship from each other along the longitudinal direction Y.

[0087] Fig. 7A for Figure 1 A partial enlarged schematic diagram of region R4 in FIG. Figures 7B-7D for Figure 1 Schematic diagram of a portion of the film layer in region R4. Figure 1 As shown, the longitudinal voltage line YL includes a middle longitudinal voltage line YLM located in the first middle display area 11M, and the middle longitudinal voltage line YLM includes: a first longitudinal voltage line YLM1 and a second longitudinal voltage line YLM2. The first longitudinal voltage line YLM1 sequentially passes through the upper display area 13 and at least part of the second area ② along the longitudinal direction Y. Figure 1 and Figures 7A-7DThe upper end of the first longitudinal voltage line YLM1 is electrically connected to the upper lead 43, and the lower end of the first longitudinal voltage line YLM1 opposite to the upper end is disconnected from the first connection line DL1 in the first sub-region A through the second break OP2. Fig. 7A and Fig.7D The partial diagram shown shows the second two second breaks OP2 in area ②. The second longitudinal voltage line YLM2 sequentially passes through the upper display area 13 and the first area ① along the longitudinal direction Y; the transverse voltage line XL includes a middle transverse voltage line XLM located in the first area ①, and the middle transverse voltage line XLM is disconnected from the second connection line DL2 in the second area ② through a third break OP3, as shown in FIG. Figure 1-2 As shown, the right end of the middle horizontal voltage line XLM in the first area ①, which is opposite to the left end, is disconnected from the fourth connection line DL4 in the fourth area ④ through the fourth break OP4. Therefore, both ends of each of the plurality of middle horizontal voltage lines XLM in the horizontal direction X are respectively disconnected from the corresponding second connection line D2 and the corresponding fourth connection line DL4.

[0088] As shown in the figure, the second longitudinal voltage line YLM2 intersects with the middle transverse voltage line XLM at the second intersection P2, and the second longitudinal voltage line YLM2 is electrically connected to the middle transverse voltage line XLM through the second via V2 at the second intersection P2.

[0089] For example, the second longitudinal voltage line YLM2 is electrically connected to the plurality of middle transverse voltage lines XLM arranged in the longitudinal direction through the plurality of second via holes V2 arranged in the longitudinal direction Y, respectively. Figures 7A-7D The partial area shown has three second via holes V2, but it does not mean that the display substrate has only three second via holes V2; for example, each of the plurality of middle horizontal voltage lines XLM passes through the second via hole V2 and the second vertical voltage line YLM2 to transmit the first power supply voltage VSS to each pixel in the first area ①. Figure 7B As shown, the second longitudinal voltage line YLM2 is connected to the middle transverse voltage line XLM through a second connection structure C2 passing through the second via hole V2.

[0090] For example, Figure 1As shown, a plurality of first horizontal voltage lines XLU located in the upper display area 13 intersect with the second vertical voltage line YLM2 at a plurality of third intersections P3, and, at each position of at least a portion of the plurality of third intersections P3, a first horizontal voltage line XLU is electrically connected to the second vertical voltage line YLM2 through a third via V3. Thus, by electrically connecting the middle horizontal voltage line XLM to the second longitudinal voltage line YLM2 through the second via V2, and the second longitudinal voltage line YLM2 to the first horizontal voltage line XLU through the third via V3, the first horizontal voltage line XLU is electrically connected to the first power supply voltage lead 4 (left lead 42), so that the first power supply voltage VSS is provided to the second longitudinal voltage line YLM2 through the first horizontal voltage line XLU, and the first power supply voltage VSS is provided to the middle horizontal voltage line XLM through the second longitudinal voltage line YLM2, thereby providing the first power supply voltage VSS to the pixels in the first area ①, instead of providing the first power supply voltage VSS to the sub-pixels in the first area ① by directly connecting the first power supply voltage line located in the first area ① to the first power supply voltage lead from the pad 3 in the border area surrounding the lower edge 1b. Combined with Figure 1 and Fig. 6A , Fig.6D It can be seen that the lower lead 41 is directly connected only to the edge longitudinal voltage line YLP located in the first edge display area 11P, but is not connected to the middle longitudinal voltage line YLM located in the first middle display area 11M and the second middle display area 12M.

[0091] For example, the second via hole V2 and the third via hole V3 both penetrate the first insulating layer.

[0092] For example, the first power supply voltage lead 4 and the longitudinal voltage line YLP are arranged in the same layer; for example, the first power supply voltage lead 4 and the longitudinal voltage line YLP are made of the same material and are a continuous integrally formed structure. They can be formed by the same patterning process, simplifying the structure and manufacturing process of the display substrate.

[0093] For example, Figure 1 As shown, the display area 1 also includes a right edge 1d opposite to the left edge 1b, and the first power lead also includes a right lead 44 extending along the right edge 1d, and the right lead 44 is electrically connected to the upper lead 43; each of the plurality of first transverse voltage lines XLU penetrates the upper display area 13 along the transverse direction X, and the right end of each of the plurality of first transverse voltage lines XLU opposite to its left end is electrically connected to the right lead 44, so as to simultaneously transmit the first power supply voltage VSS from the left and right ends of the first transverse voltage line XLU to the display area 1, thereby improving the speed of signal transmission, which is beneficial to improving the display quality of the display substrate.

[0094] For example, a plurality of intermediate longitudinal voltage lines YLM and a plurality of first transverse voltage lines XLU in the upper display area 13 intersect each other at a plurality of fourth intersections P4 in the upper display area 13 to be connected in a grid shape, which is beneficial to reducing the resistance of the first power supply voltage line vss. At each position of a portion of the fourth intersections P4 among the plurality of fourth intersections P4, an intermediate longitudinal voltage line YLM is electrically connected to a first transverse voltage line XLU through a fourth via V4, so that a plurality of first transverse voltage lines XLU extending in the transverse direction X in the upper display area 13 and an intermediate longitudinal voltage line YLM extending in the longitudinal direction Y are connected in a grid shape, so as to reduce the resistance of the first power supply voltage line vss in this portion located in the upper display area 13, and reduce the voltage drop on the first power supply voltage line vss.

[0095] The planar pattern formed by the positions of multiple fourth vias V4 is a broken line (dashed line), which is consistent with the shape of the W-shaped broken line formed by the boundary SL1 (dashed line) between the second area ② and the third area ③, the boundary between the second area ② and the fourth area ④ of the first area ①, namely the fifth line segment S5 (dashed line), the boundary between the first area ① and the fourth area ④, namely the sixth line segment S6 (dashed line), and the boundary SL3 (dashed line) between the fourth area ④ and the fifth area ⑤ (dashed line) (at least all are broken lines), which is beneficial to maintain the uniformity of the arrangement trend of the connection points connected by vias in the lower display area 14 and the connection points connected by vias in the upper display area 13, so as to prevent the display substrate from producing mura display defects.

[0096] The structure in which a middle longitudinal voltage line YLM is electrically connected to a first transverse voltage line XLU through a fourth via hole V4 is similar to Figures 3A-3D The structure of the region R1 shown is the same as that of Figures 3A-3D , which will not be repeated here.

[0097] For example, Figure 1 As shown, the fold line includes a plurality of sub-fold lines extending from the left edge 1b to the right edge 1d, and each of the plurality of sub-fold lines includes a plurality of fold line segments connected end to end; the plurality of fold line segments include a first line segment S1 (dashed line) extending along a first direction and a second line segment S2 (dashed line) extending along a second direction, the first direction intersects with the second direction, and the first direction and the second direction both intersect with the horizontal direction X and the longitudinal direction Y, the first end of the first line segment S1 coincides with the first end of the second line segment S2, for example, the first end of the first line segment S1 intersects with the first end of the second line segment S2 at the upper vertex TP; the plurality of vertices of the plurality of sub-fold lines are located on the second longitudinal voltage line YLM2, and the fourth vias V4 at the positions of the vertices are all second vias V2.

[0098] For example, Figure 1 As shown, each of the multiple sub-fold lines is W-shaped. Figure 1 The W-shaped dotted line in the figure is a sub-fold line.

[0099] For example, the W-shaped sub-broken line includes a first line segment S1 (dashed line) and a second line segment S2 (dashed line), a third line segment S3 (dashed line) and a fourth line segment S4 (dashed line), the first line segment S1 and the second line segment S2 are located between the third line segment S3 and the fourth line segment S4, the third line segment S3 is connected to the first line segment S1, and the fourth line segment S4 is connected to the second line segment S2; the first line segment S1 is substantially parallel to the fourth line segment S4, and the second line segment S2 is substantially parallel to the third line segment S3.

[0100] For example, the longitudinal direction is perpendicular to the transverse direction, the angle between the first line segment S1 and the transverse direction is 45°, and the angle between the second line segment S2 and the transverse direction is 45°, so as to ensure that the middle longitudinal voltage line YLM is connected to the first transverse voltage line XLU at more intersections through the fourth via V4 while maintaining the W-shaped routing as much as possible.

[0101] For example, in the longitudinal direction Y, the auxiliary line segment SA is located between the third line segments S3 of two adjacent sub-fold lines.

[0102] For example, the connecting line segment SC, the auxiliary line segment SA and the third line segment S3 are substantially parallel to each other to maintain the uniformity of the arrangement trend of the connecting points connected by vias at various positions in the first edge display area 11P to prevent the display substrate from generating mura display defects.

[0103] For example, Figure 2 As shown, the second longitudinal voltage line YLM2 divides the first area ① into a first sub-area A and a second sub-area B, and the structure of the first sub-area A and the structure of the second sub-area B are basically axisymmetric with respect to the second longitudinal voltage line YLM2; the lower display area 14 includes the fourth area ④, and the structure of the fourth area ④ and the structure of the second area ② are basically axisymmetric with respect to the second longitudinal voltage line YLM2; the data line data passing through the first area ① and the fourth area ④ includes a third connection line DL3 extending along the longitudinal direction Y in the second sub-area B, a fourth connection line DL4 extending along the transverse direction X in the fourth area ④, and a sixth connection line DL6 extending along the longitudinal direction Y in the upper display area 13, and the sixth connection line DL6 is arranged in the same layer with the first connection line DL1; the third connection line DL3 is arranged in the same layer with the longitudinal voltage line YL, and the fourth connection line DL4 is arranged in the same layer with the transverse voltage line XL, and the third connection line DL3 and the fourth connection line DL4 of the same data line data are electrically connected through the second connection hole VC2; the sixth connection line DL6 and the fourth connection line DL4 are electrically connected through the fourth connection hole VC4 to form a conduction channel for the data signal on the data line data.

[0104] For example, the display substrate 10 includes a plurality of first connection lines DL1, a plurality of second connection lines DL2, a plurality of third connection lines DL3 and a plurality of fourth connection lines DL4; the plurality of first connection lines DL1 are electrically connected to the plurality of second connection lines DL2 through a plurality of first connection holes VC1, respectively; the plurality of third connection lines DL3 are electrically connected to the plurality of fourth connection lines DL4 through a plurality of second connection holes VC2, respectively; the planar pattern formed by the plurality of first connection holes VC1 is the fifth line segment S5, and the fifth line segment S5 is the boundary between the first area ① and the second area ②; the planar pattern formed by the plurality of second connection holes VC2 is the sixth line segment S6, and the sixth line segment S6 is the boundary between the first area ① and the fourth area ④; the lower display area 14 also includes the fifth area ⑤, and the structure of the fifth area ⑤ is basically axially symmetrical with the structure of the third area ③ relative to the second longitudinal voltage line YLM2, and the planar pattern of the plurality of fifth vias V5 in the fifth area ⑤ that are symmetrical to the plurality of first vias V1 is the seventh line segment S7. Figure 1 As shown, the plane pattern formed by connecting the connecting line segment SC (dashed line), the fifth line segment S5 (dashed line), the sixth line segment S6 (dashed line) and the seventh line segment S7 (dashed line) in sequence is the same as the plane pattern of each sub-fold line in the multiple sub-fold lines (for example, W-shaped sub-fold lines) to maintain the uniformity of the arrangement trend of the connection points connected by vias in the lower display area 14 and the connection points connected by vias in the upper display area 13 to prevent the display substrate from producing mura display defects.

[0105] For example, Figure 1 As shown, the boundary line between the second area ② and the third area ③ is also the first side SL1 of the second area ②, and the angle between the first line segment S1 and the horizontal direction X is smaller than the angle between the first side SL1 and the horizontal direction X.

[0106] For example, Figure 1 and Figure 2 As shown, the plane shape of the first area ① is a first triangle, and the plane shape of the second area ② is a second triangle. The first side of the first triangle close to the left edge 1b in the horizontal direction X (i.e., the second connection line SL2) and the first side of the second triangle far from the left edge 1b of the display area 1 in the horizontal direction X (i.e., the second connection line SL2) at least partially overlap; the two lower vertices DP1 and DP2 of the first triangle are located on the lower edge 1a of the display area 1, and the left vertex of the two lower vertices of the first triangle close to the left edge 1b is the left end point PO of the first sub-area A; the first triangle is an isosceles triangle, and the second longitudinal voltage line YLM2 is basically the perpendicular bisector of the base of the isosceles triangle. Such an arrangement can make the arrangement of the data lines and the first power supply voltage lines of the entire display area 1 uniform and consistent, and prevent the display substrate from generating mura defects.

[0107] Fig. 8A for Figure 1 A partial enlarged schematic diagram of region R5 in FIG. Figures 8B-8C for Figure 1 Schematic diagram of a portion of the film layer in region R5. For example, refer to Figure 1 and Figures 8A-8C , the frame area 2 includes a left frame area 2a extending along the left edge 1b, and a plurality of auxiliary connection lines ACL extending along the horizontal direction X are arranged in the left frame area 2a, and the plurality of auxiliary connection lines ACL are arranged in the same layer as the edge longitudinal voltage line YLP. The display area 1 includes a pixel array, and the pixel array includes a plurality of pixel rows extending along the horizontal direction X and a plurality of pixel columns extending along the longitudinal direction Y. For example, the plurality of auxiliary connection lines ACL correspond one-to-one with the plurality of first transverse voltage lines XLU, and correspond one-to-one with the plurality of pixel rows of the upper display area 13. The plurality of pixel columns include an edge pixel column PXC0 closest to the left edge 1b, and the plurality of edge longitudinal voltage lines YLP include an outer edge longitudinal voltage line YLP-1 passing through the edge pixel column PXC0; each of the plurality of auxiliary connection lines ACL is electrically connected to the left lead 42 at its left end in the horizontal direction X, for example, directly connected, and each of the plurality of auxiliary connection lines ACL is electrically connected to the outer edge longitudinal voltage line YLP at its right end opposite to its left end in the horizontal direction X, and is connected to the left end ( Figure 8B The third connection structure C3) at the left end shown is electrically connected through the second edge via VP2.

[0108] For example, the auxiliary connection line ACL is arranged in the same layer as the left lead 42, and the materials of the two are the same, so that they are a continuous integrally formed structure. Of course, the materials of the two may also be different.

[0109] Here, taking the situation in the left border area 2a as an example, a plurality of auxiliary connection lines ACL are also provided in the right border area opposite to the left border area in the horizontal direction X. The connection method between the auxiliary connection line ACL in the right border area and the right end of the first horizontal voltage line XLU is the same as the connection method between the auxiliary connection line ACL in the left border area 2a and the left end of the first horizontal voltage line XLU, which will not be repeated here.

[0110] For example, refer to Figure 1 The right display area 12 includes a second edge display area 12P extending along the right edge 1d and a second middle display area 12M located on the side of the second edge display area 12P close to the left display area 11; the second edge display area 12P is symmetrical with the first edge display area 11P with respect to the symmetry axis extending along the longitudinal direction Y, and the second middle display area 12M is axially symmetrical with the first middle display area 11M with respect to the second longitudinal voltage line YLM2. The first middle display area 11M and the second middle display area 12M constitute a middle display area, the second sub-area B is located in the second middle display area 12M, and the first area ① is located in the middle display area.

[0111] For example, the first power supply voltage lead 4 also includes another lower lead 45 extending along the portion of the lower edge 1a corresponding to the second edge display area 12P. For example, the edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P contacts the other lower lead 45 to be electrically connected. For example, the two are directly connected, that is, the edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P contacts the other lower lead 451, and there is no other structure between the edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P and the other lower lead 45 as a medium for connecting the two; for example, the edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P is arranged on the same layer as the other lower lead 45, and constitutes a continuous one-piece molded structure.

[0112] Of course, in other embodiments, the edge voltage line for providing the first power supply voltage VSS in the second edge display area 12P and another lower lead 45 may be arranged in different layers, and the two may contact each other through vias.

[0113] For example, the display substrate 10 further includes a second power supply voltage line vdd ( Figure 1 (not shown), the second power supply voltage line vdd is configured to provide the sub-pixel with a second power supply voltage different from the first power supply voltage VSS; for example, the first power supply voltage VSS and the second power supply voltage VDD have opposite polarities. For example, the first power supply voltage VSS is at a low level, and the second power supply voltage VDD is at a high level. Of course, the first power supply voltage VSS can also be at a high level, and the second power supply voltage VDD can be at a low level.

[0114] For example, the longitudinal voltage line YL is arranged in the same layer as the data line data in the upper display area 13, and the transverse voltage line XL is arranged in the same layer as the second power supply voltage line.

[0115] Fig.10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure, FIG. 11A to FIG. 11H Includes a schematic diagram of the different film layers in the pixel circuit, Fig.11I for FIG. 11A to FIG. 11F Schematic diagram of film layer stacking. Fig.11A The dotted box in represents the area of ​​a sub-pixel.

[0116] In some examples, such as Fig.10 As shown, the display substrate further includes a plurality of sub-pixels, and at least some of the sub-pixels include a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120 .

[0117] For example, Figures 10 to 11IAs shown, the pixel circuit includes a plurality of transistors and at least one capacitor. For example, the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset control transistor T7, a third reset transistor T8 and a storage capacitor C.

[0118] For example, Figures 10 to 11I As shown, the display substrate further includes reset power signal lines 561 , 551 , and 554 , scan signal lines 552 , 531 , and 523 , a second power voltage line vdd, reset control signal lines 522 , 532 , and 553 , a light emitting control signal line 521 , and a data line 200 .

[0119] For example, Figures 10 to 11IAs shown, the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal lines 531 and 552 to receive the compensation control signal; the first electrode of the first reset control transistor T7 is electrically connected to the reset power supply signal line 561 to receive the reset signal Vinit2, the second electrode of the first reset control transistor T7 is electrically connected to the first electrode of the light emitting element (i.e., the N4 node), and the gate of the first reset control transistor T7 is electrically connected to the reset control signal line 522 to receive Reset control signal Reset(N+1); a first electrode of the third reset transistor T8 is electrically connected to the reset power supply signal line 551 to receive the reset signal Vref, a second electrode of the third reset transistor T8 is electrically connected to the second electrode of the driving transistor T3, and a gate of the third reset transistor T8 is electrically connected to the reset control signal line 522; a first electrode of the data writing transistor T4 is electrically connected to the second electrode of the driving transistor T3, a second electrode of the data writing transistor T4 is electrically connected to the data line 200 (data line data) to receive the data signal Data, and a gate of the data writing transistor T4 is electrically connected to the scanning signal line 523. The first electrode of the storage capacitor C is electrically connected to the second power supply voltage line vdd, and the second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the first electrode of the second reset transistor T1 is electrically connected to the reset power supply signal line 554 to receive the reset signal Vinit1, the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal lines 553 and 532 to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line 521 to receive the reset signal Vinit1; the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3; the gate of the second reset transistor T1 is electrically connected to the reset control signal lines 553 and 532 to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line 521 to receive the reset signal Vinit1; the second electrode of the second reset transistor T1 is electrically connected to the reset power supply signal line 554 ... The light emitting control signal EM is received and received, the first electrode of the first light emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T3, and the second electrode of the first light emitting control transistor T6 is electrically connected to the first electrode of the light emitting element 120; the first electrode of the second light emitting control transistor T5 is electrically connected to the second power supply voltage line vdd to receive the first power supply signal VDD, the second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, the gate of the second light emitting control transistor T5 is electrically connected to the light emitting control signal line 521 to receive the light emitting control signal EM, and the second electrode of the light emitting element 120 is electrically connected to the voltage terminal VSS.

[0120] It should be noted that, in the embodiment of the present disclosure, each pixel circuit can Fig.10 In addition to the 8T1C structure (i.e., eight transistors and one capacitor) shown, it can also be a structure including other numbers of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0121] Fig.11A An active semiconductor pattern 510 is shown. For example, Fig.11A As shown, the active semiconductor pattern 510 can be used to make the active layers of the above-mentioned driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, first reset control transistor T7 and third reset control transistor T8 to form the channel regions of the above-mentioned transistors. The active semiconductor pattern 510 includes the active layer pattern (channel region) and doping region pattern (source and drain region) of the above-mentioned transistors of each sub-pixel, and the active layer pattern and doping region pattern of the above-mentioned transistors in the same pixel circuit are integrally arranged.

[0122] For example, the active semiconductor pattern 510 may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductively doped to achieve electrical connection of the structures. For example, the source region and the drain region may be regions doped with p-type impurities.

[0123] Fig. 11B The first conductive layer pattern 520 is shown located on the side of the active semiconductor pattern 510 away from the substrate. Fig. 11B As shown, the first conductive layer pattern 520 includes a reset control signal line 522, a scan signal line 523, an electrode 524 of a capacitor, and a light emitting control signal line 521. For example, the first conductive layer pattern 520 may include gates of a driving transistor T3, a data writing transistor T4, a second light emitting control transistor T5, a first light emitting control transistor T6, a first reset control transistor T7, and a third reset control transistor T8.

[0124] It should be noted that Fig.11A The dashed rectangular boxes in the figure show the parts where the active semiconductor pattern 510 overlaps with the first conductive layer pattern 520, i.e., the channel regions. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductively connected by ion doping and other processes to serve as the first and second electrodes of each transistor. The source and drain of the transistor may be symmetrical in structure, so there may be no difference in the physical structure of the source and drain. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0125] For example, Fig. 11B and Fig.11IAs shown, the gate of the data writing transistor T4 may be the portion where the scanning signal line 523 overlaps with the active semiconductor pattern 510; the gate of the first light emission control transistor T6 may be the first portion where the light emission control signal line 521 overlaps with the active semiconductor pattern 510, and the gate of the second light emission control transistor T5 may be the second portion where the light emission control signal line 521 overlaps with the active semiconductor pattern 510. The gate of the third reset transistor T8 may be the first portion where the reset control signal line 522 overlaps with the active semiconductor pattern 510, and the gate of the first reset control transistor T7 may be the second portion where the reset control signal line 522 overlaps with the active semiconductor pattern 510.

[0126] Fig. 11C FIG. 5 shows a second conductive layer pattern 530 on a side of the first conductive layer pattern 520 away from the substrate. Fig. 11C As shown, the second conductive layer pattern 530 includes a scan signal line 531 , a second electrode 533 of a capacitor C, and a reset control signal line 532 .

[0127] Fig.11D The active layer pattern 540 on the side of the second conductive layer pattern 530 away from the substrate is shown. Fig.11D As shown, the active layer pattern 540 includes the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, when the active layers in the second reset transistor T1 and the threshold compensation transistor T2 are made of oxide semiconductor, since the transistor made of oxide semiconductor has good hysteresis characteristics and low leakage current, and has low mobility, the transistor made of oxide semiconductor can be used to replace the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, thereby achieving low leakage and improving the stability of the gate voltage of the transistor.

[0128] For example, Fig. 11C , 3D and Fig.11I As shown, the gate of the second reset transistor T1 may be the portion where the reset control signal line 532 overlaps with the active layer pattern 540 , and the gate of the threshold compensation transistor T2 may be the portion where the scan signal line 531 overlaps with the active layer pattern 540 .

[0129] Fig.11E FIG. 5 shows a third conductive layer 550 on a side of the active layer pattern 540 away from the substrate. Fig.11E As shown, the third conductive layer 550 includes a reset power signal line 554 , a reset control signal line 553 , a scan signal line 552 and a reset power signal line 551 .

[0130] For example, FIG. 11C to FIG. 11F as well as Fig.11IAs shown, the reset control signal line 553 overlaps with the channel region of the second reset transistor T1, the second reset transistor T1 includes a double gate located on both sides of the active layer, and the second reset transistor T1 is a double gate transistor; the scanning signal line 552 overlaps with the channel region of the threshold compensation transistor T2, the threshold compensation transistor T2 includes a double gate located on both sides of the active layer, and the threshold compensation transistor T2 is a double gate transistor.

[0131] For example, the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors, and the data writing transistor T4, the second emission control transistor T5, the first emission control transistor T6, the first reset control transistor T7 and the third reset control transistor T8 may be P-type transistors.

[0132] Fig.11F The fourth conductive layer 560 is shown located on the side of the third conductive layer 550 away from the substrate. Fig.11F As shown, the fourth conductive layer 560 includes a reset power signal line 561 , a connection portion 568 , a connection portion 569 , a connection portion 563 , a connection portion 567 , a connection portion 562 , a connection portion 564 , a connection portion 565 and a connection portion 566 .

[0133] For example, Figures 10 to 11I As shown, the two ends of the connection portion 568 are connected to the reset power signal line 551, and the middle is connected to the first electrode of the third reset transistor T8; the connection portion 569 connects the data line data and the second electrode of the data writing transistor T4; the connection portion 563 is used to electrically connect the first electrode of the data writing transistor T4 and the second electrode of the third reset transistor T8 to lead the reset signal Vref to the N2 node; the connection portion 567 is used to electrically connect the first electrode of the driving transistor T3 and the first electrode of the threshold compensation transistor T2; the middle of the connection portion 562 is connected to the second power voltage line vdd (as shown in FIG. Fig.11H , that is, the second power supply voltage line vdd), the two ends of the connecting part 562 are connected to one electrode 533 of the capacitor; one end of the connecting part 564 is connected to the second electrode 533 of the storage capacitor C, and the other end of the connecting part 564 is connected to the first electrode of the second light-emitting control transistor T5; the connecting part 565 is used to electrically connect the first electrode of the light-emitting element and the second electrode of the first light-emitting control transistor T6; the connecting part 566 is used to electrically connect the reset power supply signal line 554 and the first electrode of the second reset transistor T1.

[0134] Fig.11G The fifth conductive layer 570 is shown located on the side of the fourth conductive layer 560 away from the substrate. Fig.11GAs shown, the fifth conductive layer 570 includes a connecting portion 573, a connecting portion 575, a second power supply voltage line 572 (transmitting a second power supply voltage VDD), a connecting portion 574, and a horizontal voltage line XL (for example, a middle horizontal voltage line XLM, etc.). For example, the fifth conductive layer 570 also includes a fourth connecting line.

[0135] For example, Figures 10 to 11G As shown, the connection portion 573 is used to electrically connect with the data line data, for example, the data line data is electrically connected to some connection lines in the display area 1 extending in the horizontal direction X and arranged in a different layer from the data line data through the connection portion 573 to transmit the data signal DATA to the connection line; the connection portion 575 is a reserved pad, and the first connection line can be electrically connected to the second connection line through the reserved pad, or the longitudinal voltage line can be electrically connected to the transverse voltage line through the reserved pad. For example, the connection portion 574 is electrically connected to the connection portion 565 to realize the electrical connection between the second electrode of the first light-emitting control transistor T6 and the first electrode of the light-emitting element. For example, the second power supply voltage line 572 is electrically connected to the second power supply voltage line vdd.

[0136] Fig.11H The sixth conductive layer 580 is shown located on the side of the fifth conductive layer 570 away from the substrate. Fig.11H As shown, the sixth conductive layer 580 includes a data line data, a second power voltage line vdd, a fifth connection line 450 , a connection portion 584 and a connection portion 585 .

[0137] For example, the connection portion 584 and the connection portion 585 are electrically connected to first electrodes of different light emitting elements.

[0138] For example, Fig.11G and Fig.11H As shown, the data line data includes a transfer pad 290, and the data line data is connected to the connection part 573 through the transfer pad 290, so as to be electrically connected to some connection lines in the display area 1 that are arranged in a different layer from the data line data and extend in the horizontal direction X, so as to transmit the data signal DATA to the connection line. For example, the longitudinal voltage line YL includes a transfer pad 459, and the longitudinal voltage line YL can be electrically connected to the connection part 575 through the corresponding transfer pad 459, and the connection part 575 is electrically connected to the corresponding transverse voltage line XL that needs to be electrically connected to the longitudinal voltage line YL, so as to realize the electrical connection between the longitudinal voltage line YL and the transverse voltage line XL.

[0139] like Fig.12 As shown, at least one embodiment of the present disclosure further provides a display device 100, comprising any one of the display substrates 10 provided in at least one embodiment of the disclosure.

[0140] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A display substrate, comprising: A display area is provided with sub-pixels and has a lower edge extending in a horizontal direction and a left edge extending in a vertical direction, wherein the horizontal direction intersects the vertical direction, the display area includes a left display area and a right display area arranged in the horizontal direction, the left display area includes a first edge display area extending along the left edge and a first middle display area located in the first edge display area and close to the right display area; a non-display area, including a frame area surrounding at least a portion of the display area; a first power supply voltage lead, configured to provide a first power supply voltage and located in the border area, wherein the first power supply voltage lead includes a lower lead extending along a portion of the lower edge corresponding to the first edge display area, and the first power supply voltage lead does not extend along a portion of the lower edge corresponding to the first middle display area; first power supply voltage lines, including edge voltage lines located in the first edge display area and middle voltage lines located in the first middle display area, wherein the edge voltage lines are in contact with and electrically connected to the lower lead lines to provide the first power supply voltage to the sub-pixels located in the first edge display area, and the middle voltage lines are spaced apart from the lower lead lines; The first power supply voltage lead further includes a left lead extending along a left edge of the display area, the display area further includes an upper edge opposite to the lower edge, the first power supply voltage lead further includes an upper lead extending along the upper edge, the upper lead is electrically connected to the left lead; The middle voltage line provides the first power supply voltage to the first middle display area by being connected to the left lead or the upper lead, or other first power supply voltage lines that provide the first power supply voltage.

2. The display substrate according to claim 1, wherein: The first power supply voltage line comprises a longitudinal voltage line extending in the longitudinal direction and a transverse voltage line extending in the transverse direction, and the longitudinal voltage line and the transverse voltage line are arranged in different layers; The longitudinal voltage lines include edge longitudinal voltage lines located in the first edge display area, the transverse voltage lines include edge transverse voltage lines located in the first edge display area and intersecting with the edge longitudinal voltage lines, and the edge longitudinal voltage lines and the edge transverse voltage lines constitute the edge voltage lines; The edge longitudinal voltage line is directly connected to the lower lead, and the edge transverse voltage line is directly connected to the left lead.

3. The display substrate according to claim 2, further comprising a data line, wherein: The sub-pixel comprises: a driving transistor, a light-emitting device and a data transistor, wherein the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, the data transistor is configured to write a data signal into a gate of the driving transistor in response to a first control signal, and the data line is configured to transmit the data signal to the sub-pixel; The display area comprises a lower display area and an upper display area, the lower display area is close to the lower edge, and the upper display area is located on a side of the lower display area away from the lower edge in the longitudinal direction; The lower display area includes a first area and a second area, the first area includes a first sub-area close to the left edge in the horizontal direction and a second sub-area away from the left edge, the data line passing through the first sub-area and the second area includes a first connection line extending along the longitudinal direction in the first sub-area and a second connection line extending along the transverse direction in the second area; the first connection line is arranged in the same layer as the longitudinal voltage line, the second connection line is arranged in the same layer as the transverse voltage line, and the first connection line and the second connection line of the same data line are electrically connected through a first connection hole; the first sub-area is located in the first middle display area, and the second area is at least partially located in the first middle display area; The first sub-region has a left end point that is closest to the left edge of the display area in the horizontal direction, and a straight line extending along the vertical direction and passing through the left end point is a boundary line between the first edge display area and the first middle display area.

4. The display substrate according to claim 3, wherein: The dividing line passes through the second area and divides the second area into a third sub-area close to the left edge of the display area and a fourth sub-area far from the left edge of the display area, the first sub-area is located in the first edge display area, and the second sub-area is located in the first middle display area; The lower display area also includes: The third area is located in the first edge display area and is located on a side of the second area away from the first area in the horizontal direction, wherein: The edge transverse voltage line includes a lower edge transverse voltage line located in the third area, the edge longitudinal voltage line passes through the third area and intersects with the lower edge transverse voltage line at a first intersection, the left end of the lower edge transverse voltage line is electrically connected to the left lead, and the right end of the lower edge transverse voltage line opposite to the left end is disconnected from the second connection line in the second area through a first break; The edge voltage lines include a plurality of edge longitudinal voltage lines and a plurality of edge transverse voltage lines, the plurality of edge longitudinal voltage lines and the plurality of edge transverse voltage lines are interwoven with each other to form a grid, and the grid includes a plurality of the first intersections; At the position of each of a portion of the first intersections among the plurality of first intersections, one of the edge longitudinal voltage lines is electrically connected to one of the lower edge transverse voltage lines through a first via hole.

5. The display substrate according to claim 4, wherein: The plurality of edge longitudinal voltage lines are electrically connected to the plurality of edge transverse voltage lines through the plurality of first vias, and the planar pattern formed by the positions of the plurality of first vias is a connecting line segment located within the third region, and an extension direction of the connecting line segment intersects both the longitudinal direction and the transverse direction.

6. The display substrate according to claim 4, wherein: The third region is a corner region defined by the second side of the second region close to the left edge in the transverse direction, the left edge, and the lower edge.

7. The display substrate according to claim 6, wherein: The frame area includes a frame corner area surrounding the corner area, and the frame corner area is provided with a grid-shaped auxiliary first power supply voltage line, and the grid-shaped auxiliary first power supply voltage line includes: a plurality of longitudinal auxiliary voltage lines extending in the longitudinal direction and arranged in the same layer as the longitudinal voltage lines, wherein a first end of each of the plurality of longitudinal auxiliary voltage lines in the longitudinal direction is directly connected to the first power supply voltage lead, and a second end of each of the plurality of longitudinal auxiliary voltage lines in the longitudinal direction opposite to the first end thereof is electrically connected to one of the edge longitudinal voltage lines passing through the corner area; and A plurality of transverse auxiliary voltage lines extend along the transverse direction and are arranged in the same layer as the plurality of longitudinal auxiliary voltage lines, wherein each of the plurality of transverse auxiliary voltage lines is directly connected to the first power supply voltage lead at one end in the transverse direction, and each of the plurality of transverse auxiliary voltage lines is electrically connected to one of the edge longitudinal voltage lines at a second end in the transverse direction opposite to the first end.

8. The display substrate according to claim 7, wherein: The display area includes a pixel array, the pixel array includes a plurality of pixel rows extending in the horizontal direction and a plurality of pixel columns extending in the vertical direction; the plurality of pixel rows include a plurality of edge pixel rows close to the lower edge; the plurality of horizontal auxiliary voltage lines correspond to the plurality of edge pixel rows one by one, each edge pixel row in the plurality of edge pixel rows includes an edge sub-pixel closest to the left edge, and the plurality of edge longitudinal voltage lines include an edgemost longitudinal voltage line passing through the edge sub-pixels of each of the edge pixel rows; The second end of each of the plurality of transverse auxiliary voltage lines is electrically connected to the edgemost longitudinal voltage line passing through the corresponding edge pixel row, and is electrically connected to the edge transverse voltage line passing through the corresponding edge pixel row through a first edge via hole.

9. The display substrate according to claim 5, wherein: The horizontal voltage line also includes: A plurality of first transverse voltage lines are arranged in the longitudinal direction and are located in the upper display area, wherein the left end of each first transverse voltage line is electrically connected to the left lead, and the edge transverse voltage lines further include an upper edge transverse voltage line located in the upper display area, and the upper edge transverse voltage line is a part of one of the first transverse voltage lines; The longitudinal voltage line also includes: a plurality of middle longitudinal voltage lines arranged in the transverse direction, passing through a portion of the first middle display area and the upper display area along the longitudinal direction, wherein the plurality of middle longitudinal voltage lines, the plurality of edge longitudinal voltage lines and the plurality of first transverse voltage lines are interwoven into a grid; The plurality of edge longitudinal voltage lines intersect the plurality of first transverse voltage lines at a plurality of auxiliary intersections in the first edge display area, and at each position of a portion of the plurality of auxiliary intersections, one edge longitudinal voltage line is electrically connected to one first transverse voltage line through an auxiliary via hole, and the plurality of edge longitudinal voltage lines are electrically connected to the plurality of first transverse voltage lines through a plurality of the auxiliary via holes; The plane pattern formed by the positions of the plurality of auxiliary via holes is an auxiliary line segment located in the first edge display area, and one end of the auxiliary line segment away from the left edge is suspended.

10. The display substrate according to claim 9, wherein: The extension direction of the auxiliary line segment is the same as the extension direction of the connecting line segment; The display substrate includes a plurality of auxiliary line segments, and the connecting line segment and the plurality of auxiliary line segments are arranged in a spaced relationship from each other along the longitudinal direction.

11. The display substrate according to claim 9, wherein: The upper end of the edge longitudinal voltage line is connected to the upper lead, and the lower end of the edge longitudinal voltage line opposite to the upper end is directly connected to the lower lead; The longitudinal voltage line comprises a middle longitudinal voltage line located in the first middle display area, and the middle longitudinal voltage line comprises: A first longitudinal voltage line, sequentially passing through the upper display area and at least a portion of the second area along the longitudinal direction, wherein an upper end of the first longitudinal voltage line is electrically connected to the upper lead, and a lower end of the first longitudinal voltage line opposite to the upper end is disconnected from the first connection line in the first sub-area through a second break; and A second longitudinal voltage line passes through the upper display area and the first area in sequence along the longitudinal direction, wherein the transverse voltage line includes an intermediate transverse voltage line located in the first area, the intermediate transverse voltage line is disconnected from the second connection line in the second area by a third break, the second longitudinal voltage line intersects with the intermediate transverse voltage line at a second intersection, and the second longitudinal voltage line is electrically connected to the intermediate transverse voltage line through a second via at the second intersection.

12. The display substrate according to claim 11, wherein: The multiple first transverse voltage lines intersect the multiple second longitudinal voltage lines at multiple third intersections, and at the position of each of at least a part of the multiple third intersections, one of the first transverse voltage lines is electrically connected to one of the second longitudinal voltage lines through a third via.

13. The display substrate according to claim 11, wherein: The display area further includes a right edge opposite to the left edge, the first power lead further includes a right lead extending along the right edge, and the right lead is electrically connected to the upper lead; Each of the plurality of first transverse voltage lines penetrates the upper display area in the transverse direction, and a right end of each of the plurality of first transverse voltage lines opposite to a left end thereof is electrically connected to the right lead line.

14. The display substrate according to claim 13, wherein: The plurality of middle longitudinal voltage lines and the plurality of first transverse voltage lines intersect each other at a plurality of fourth intersections in the upper display area, and at each position of a portion of the fourth intersections among the plurality of fourth intersections, one of the middle longitudinal voltage lines is electrically connected to one of the first transverse voltage lines through a fourth via hole; The plane pattern formed by the positions of the plurality of fourth via holes is a fold line.

15. The display substrate according to claim 14, wherein: The fold line includes a plurality of sub-fold lines extending from the left edge to the right edge, and each of the plurality of sub-fold lines includes a plurality of fold line segments connected end to end; The plurality of broken line segments include a first line segment extending along a first direction and a second line segment extending along a second direction, the first direction intersects with the second direction, and both the first direction and the second direction intersect with the transverse direction and the longitudinal direction, and a first end of the first line segment intersects with a first end of the second line segment at an upper vertex; The plurality of vertices of the plurality of sub-fold lines are located on the second longitudinal voltage line, and the fourth via holes at the positions of the vertices are all the second via holes.

16. The display substrate according to claim 15, wherein: Each of the plurality of sub-folding lines is W-shaped.

17. The display substrate according to claim 16, wherein: The W-shaped sub-polyline includes the first line segment, the second line segment, the third line segment and the fourth line segment, the first line segment and the second line segment are located between the third line segment and the fourth line segment, the third line segment is connected to the first line segment, and the fourth line segment is connected to the second line segment; The first line segment is substantially parallel to the fourth line segment, The second line segment is substantially parallel to the third line segment.

18. The display substrate according to claim 17, wherein: The longitudinal direction is perpendicular to the transverse direction, the angle between the first line segment and the transverse direction is 45°, and the angle between the second line segment and the transverse direction is 45°.

19. The display substrate according to claim 17, wherein: In the longitudinal direction, the auxiliary line segment is located between the third line segments of two adjacent sub-fold lines.

20. The display substrate according to claim 19, wherein: The connecting line segment, the auxiliary line segment and the third line segment are substantially parallel to each other.

21. The display substrate according to any one of claims 15 to 20, wherein: The second longitudinal voltage line divides the first region into the first sub-region and the second sub-region, and the structure of the first sub-region and the structure of the second sub-region are substantially axisymmetric with respect to the second longitudinal voltage line; The lower display area includes a fourth area, and the structure of the fourth area is substantially axisymmetric with the structure of the second area relative to the second longitudinal voltage line; the data line passing through the first area and the fourth area includes a third connection line extending in the longitudinal direction in the second sub-area and a fourth connection line extending in the transverse direction in the fourth area; the third connection line is arranged in the same layer as the longitudinal voltage line, the fourth connection line is arranged in the same layer as the transverse voltage line, and the third connection line and the fourth connection line of the same data line are electrically connected through a second connection hole; A right end of the middle transverse voltage line in the first region opposite to its left end is disconnected from the fourth connection line in the fourth region through a fourth break.

22. The display substrate according to claim 21, wherein: The display substrate comprises a plurality of first connection lines, a plurality of second connection lines, a plurality of third connection lines and a plurality of fourth connection lines; the plurality of first connection lines are electrically connected to the plurality of second connection lines through a plurality of first connection holes, respectively, and the plurality of third connection lines are electrically connected to the plurality of fourth connection lines through a plurality of second connection holes, respectively; The plane pattern formed by the plurality of first connection holes is a fifth line segment, and the fifth line segment is a boundary between the first area and the second area; The plane pattern formed by the plurality of second connection holes is a sixth line segment, and the sixth line segment is a boundary between the first area and the fourth area; The lower display area further includes a fifth region, the structure of the fifth region is substantially axisymmetric with the structure of the third region relative to the second longitudinal voltage line, and the planar pattern of the plurality of fifth via holes in the fifth region that are symmetrical to the plurality of first via holes is a seventh line segment; A plane pattern formed by sequentially connecting the connecting line segment, the fifth line segment, the sixth line segment, and the seventh line segment is the same as a plane pattern of each of the plurality of sub-fold lines.

23. The display substrate according to claim 21, wherein: The planar shape of the first area is a first triangle, the planar shape of the second area is a second triangle, and a first side of the first triangle close to the left edge in the horizontal direction at least partially overlaps with a first side of the second triangle far from the left edge of the display area in the horizontal direction; Two lower vertices of the first triangle are located on the lower edge of the display area, and a left vertex of the two lower vertices of the first triangle close to the left edge is the left endpoint of the first sub-area; The first triangle is an isosceles triangle, and the second longitudinal voltage line is substantially a perpendicular bisector of a base of the isosceles triangle.

24. The display substrate according to any one of claims 9 to 20 and 22 to 23, wherein: The frame area includes a left frame area extending along the left edge, wherein a plurality of auxiliary connection lines extending along the horizontal direction are arranged in the left frame area, and the plurality of auxiliary connection lines are arranged in the same layer as the edge longitudinal voltage line; The display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction; the plurality of pixel columns include an edge pixel column closest to the left edge, and the plurality of edge longitudinal voltage lines include an outer edge longitudinal voltage line passing through the edge pixel column; Each of the multiple auxiliary connection lines is electrically connected to the left lead at its left end in the horizontal direction, and each of the multiple auxiliary connection lines is electrically connected to the outer edge longitudinal voltage line at its right end opposite to its left end in the horizontal direction, and is electrically connected to the left end of a corresponding one of the first horizontal voltage lines through a second edge via.

25. The display substrate according to any one of claims 13 to 20 and 22 to 23, wherein: The right display area includes a second edge display area extending along the right edge and a second middle display area located at a side of the second edge display area close to the left display area; The second edge display area is symmetrical to the first edge display area with respect to a symmetry axis extending along the longitudinal direction, and the second middle display area is axially symmetrical to the first middle display area with respect to the second longitudinal voltage line.

26. The display substrate according to any one of claims 3-20 and 22-23, wherein: The display substrate further comprises: a second power supply voltage line configured to provide a second power supply voltage different from the first power supply voltage to the sub-pixel; The longitudinal voltage line is arranged in the same layer as the data line in the upper display area, and the transverse voltage line is arranged in the same layer as the second power supply voltage line.

27. A display device comprising the display substrate according to any one of claims 1 to 26.

Images