Switching converter and control circuit therefor

Abstract

The embodiment of the present disclosure provides a switching converter and a control circuit thereof. The switching converter uses a power tube to control the transmission of electric energy from an input end to an output end to generate a direct current output voltage according to a direct current input voltage. The control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit and a latch circuit. The slope compensation circuit is configured to copy a triangular wave voltage signal generated by the oscillator circuit, generate a slope compensation current according to the copied triangular wave voltage signal, separate the slope compensation circuit from the oscillator circuit, and reset the triangular wave signals in the two circuits with different signals, so as to effectively avoid the false triggering of the modulation comparator and the occurrence of inductance current waveform disorder.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a switching converter and a control circuit thereof. BACKGROUND

[0002] In a fixed-frequency valley current mode boost converter, the internal clock resets the slope compensation current every cycle, especially when the inductor current is higher than the current limit value. If the clock reset occurs before the valley current limit value, it can cause the PWM modulator to be triggered incorrectly. In the next cycle, the inductor current waveform shows that the valley current is much lower than the current limit value before the lower tube is turned on, resulting in a disordered inductor current waveform. Therefore, how to maintain the regularity of the inductor current waveform in a fixed-frequency valley current mode boost converter is one of the technical problems to be solved. SUMMARY

[0003] Embodiments described herein provide a switching converter and a control circuit thereof to solve the problem of disordered inductor current waveform in a fixed-frequency valley current mode boost converter.

[0004] According to a first aspect of the present disclosure, a control circuit of a switching converter is provided, the switching converter controls the transmission of electrical energy from an input end to an output end by a power tube to generate a direct current output voltage according to a direct current input voltage, the control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit, and a latch circuit, wherein the oscillator circuit is configured to generate a triangular wave voltage signal according to a direct current source signal, and is further configured to generate a clock signal according to the triangular wave voltage signal; the slope compensation circuit is configured to copy the triangular wave voltage signal generated by the oscillator circuit, and then generate a slope compensation current according to the copied triangular wave voltage signal; the duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and a sampling current, and is further configured to generate a duty cycle modulation signal according to the sampling voltage and an error voltage; and the latch circuit is configured to generate a switching signal according to the clock signal and the duty cycle modulation signal, to control the conduction state of the power tube.

[0005] Optionally, the oscillator circuit comprises: a first current source, a first comparator, a first capacitor, a first transistor, a high-level pulse generating circuit, an input end of the first current source is connected to a voltage source, an output end of the first current source is connected to one end of the first capacitor and a positive input end of the first comparator, the output end of the first current source generates the triangular wave voltage signal; the other end of the first capacitor is grounded, and an inverting input end of the first comparator receives a reference voltage; an input end of the high-level pulse generating circuit is connected to an output end of the first comparator; the first transistor is connected in parallel across the first capacitor, a control end of the first transistor is connected to an output end of the high-level pulse generating circuit, and the output end of the high-level pulse generating circuit generates the clock signal.

[0006] Optionally, the slope compensation circuit comprises: a second current source, a second transistor, a third transistor, a fourth transistor, a second capacitor and a first resistor, the second transistor, the third transistor and the first resistor are connected in series between an input end and a ground end of the first current source; the second current source, the fourth transistor and the second capacitor are connected in series between the input end and the ground end of the first current source; the fourth transistor is connected in parallel across the second capacitor; a control end of the second transistor is connected to a first pole of the second transistor and a control end of a fifth transistor in the duty cycle modulation circuit, so as to mirror the generated slope compensation current to the duty cycle modulation circuit; a control end of the third transistor is connected to an output end of the second current source, so as to receive the copied triangular wave voltage signal; a control end of the fourth transistor is connected to a gate signal of a first power tube in the switching converter; the second current source has the same parameters as the first current source, the second capacitor has the same parameters as the first capacitor, and the fourth transistor has the same parameters as the first transistor.

[0007] Optionally, the duty cycle modulation circuit comprises: a second comparator, a fifth transistor, a third current source and a second resistor, the fifth transistor and the second resistor are connected in series between an input end and a ground end of the first current source; the third current source is connected in parallel with the fifth transistor; a positive input end of the second comparator is connected to a node between the fifth transistor and the second resistor and an output end of the third current source, so as to obtain the sampling voltage; an inverting input end of the second comparator receives an error amplification signal, and an output end of the second comparator outputs the duty cycle modulation signal.

[0008] Optionally, the latch circuit comprises a first latch and a second latch, a set end of the first latch is connected to an output end of the second comparator, a reset end of the first latch is connected to an output end of the high-level pulse generating circuit, and an output end of the first latch is connected to a control end of a first power tube in the switching converter; a set end of the second latch is connected to the output end of the second comparator, a reset end of the second latch is connected to the output end of the high-level pulse generating circuit, and an output end of the second latch is connected to a control end of a second power tube in the switching converter.

[0009] Optionally, the error amplification signal is a signal obtained by passing a direct-current output voltage and a preset reference voltage through an error amplifier.

[0010] Optionally, the control circuit is in a constant-frequency valley-current mode.

[0011] According to a second aspect of the present disclosure, a switching converter is provided, comprising a main power circuit configured to transmit electric energy from an input end to an output end by using a power tube control input end, so as to generate a direct-current output voltage according to a direct-current input voltage; and the control circuit of any one of the first aspect, used to generate a switching control signal to control a conduction state of the power tube.

[0012] Optionally, the main power circuit comprises an inductor, a first power tube, a second power tube, an output capacitor, and a load, the inductor and the first power tube are connected in series between the input end and a ground end, the second power tube is connected between a middle node of the inductor and the first power tube and the output end, the output capacitor is connected between the output end and the ground end, and the load is connected in parallel across the output capacitor.

[0013] Optionally, the switching converter is a boost converter.

[0014] The switching converter and the control circuit thereof according to the embodiments of the present disclosure adopt a power tube to control the transmission of electric energy from an input end to an output end, so as to generate a direct current output voltage according to a direct current input voltage. The control circuit comprises an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit and a latch circuit. The oscillator circuit is configured to generate a triangular wave voltage signal according to a direct current source signal, and is further configured to generate a clock signal according to the triangular wave voltage signal. The slope compensation circuit is configured to generate a slope compensation current according to the triangular wave voltage signal generated by the oscillator circuit after copying the triangular wave voltage signal. The duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and a sampling current, and is further configured to generate a duty cycle modulation signal according to the sampling voltage and an error voltage. The latch circuit is configured to generate a switching signal according to the clock signal and the duty cycle modulation signal, so as to control the conduction state of the power tube. Compared with the control circuit of a conventional constant-frequency valley-current mode boost converter, the slope compensation current is generated according to the copied triangular wave voltage signal, the slope compensation triangular wave circuit and the oscillator triangular wave circuit are separated, and the triangular wave signals in the two circuits are reset by different signals, so that the timing of resetting the slope compensation current is controlled, the false triggering of the PWM comparator is avoided, and the waveform of the inductor current is regular. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure. Wherein:

[0016] Figure 1 is an exemplary circuit diagram of a conventional switching converter;

[0017] Figure 2 is a waveform diagram corresponding to Figure 1

[0018] Figure 3 is a structural schematic diagram of a switching converter according to an embodiment of the present disclosure;

[0019] Figure 4 is an exemplary circuit diagram of a switching converter according to an embodiment of the present disclosure;

[0020] Figure 5 is a waveform diagram corresponding to a switching converter according to an embodiment of the present disclosure.

[0021] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0022] ​In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort also belong to the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0024] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is called the control electrode (control end), and the remaining two ends of the transistor are called the first electrode and the second electrode, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0025] In order to solve the problem of inductance current waveform disorder in the fixed-frequency valley-current mode boost converter, first, the control of the fixed-frequency valley-current mode boost converter is analyzed. Specifically, as shown in Figure 1 The existing conventional fixed-frequency valley-current mode boost converter 100 is an exemplary circuit diagram, combined with Figure 1The analysis of the inductance current waveform disorder problem is as follows: the current source Iosc charges the capacitor Css to generate a triangular wave VRAMP, the triangular wave signal VRAMP is used as an input signal of the comparator COMP, and at the same time, the triangular wave current is generated by falling to the resistor R1 through the transistor Mn0, the slope compensation current I_slope is generated by the mirror effect of the transistor Mp1 and the transistor Mp0, and finally the slope compensation current I_slope and the sampled inductance current (Idc-Isns) (where Idc is a constant current, and Isns is related to the sampled inductance current, and the inductance current can be 100,000 times of Isns) act on the resistor Rs to generate the sum point voltage (inductance sampling voltage), the sum voltage and the eaout voltage (output signal of the error amplifier) are compared through the comparator PWM_COMP to generate the MAIN_TRIP signal to turn on the lower transistor, so as to adjust the BOOST duty cycle. Specifically, the MAIN_TRIP signal and the clock signal CLK (the output of the comparator COMP is obtained through the high level pulse generator I1 to obtain CLK) are used to control the turn-on and turn-off of the power transistor ML and MH. After the control according to the above control principle, the corresponding waveform diagram is as shown in Figure 2 From top to bottom, the waveform diagrams are inductance current IL waveform diagram, clock signal CLK waveform diagram, slope compensation current I_slope waveform diagram, MAIN_TRIP signal waveform diagram, and waveform diagram of the gate signal LG of the transistor ML. As can be seen from the waveform diagram, before t1, the MAIN_TRIP signal has been high, but the inductance current IL is higher than the valley value current limit VY_LIM, so the upper transistor (MH) continues to be turned on, at t1, the CLK signal resets the I_slope current, which causes the sum voltage to be lower than the eaout voltage, the MAIN_TRIP signal is low, and the inductance current IL is lower than the current limit VY_LIM, but the I_slope current is small, so the MAIN_TRIP signal is still low and cannot open the lower transistor (ML), and the inductance current IL further decreases below the current limit VY_LIM, until t2, the sum voltage is higher than the eaout voltage, and the MAIN_TRIP signal opens the lower transistor ML, and the inductance current IL starts to rise, and then at t3, the next period clock arrives, the lower transistor ML is turned off, and the inductance current IL continues to decrease, thus forming the Figure 2 inductance current IL waveform shown in

[0026] Based on the above analysis, the embodiment of the present disclosure proposes a new switching converter and a control circuit to solve the problem of inductance current disorder. The embodiment of the present disclosure will be described in detail below.

[0027] As Figure 3As shown, a structure schematic diagram of a switching converter 200 is proposed in the embodiment of the present disclosure. It is first to be explained that the switching converter 200 in the embodiment of the present disclosure adopts power tube control input end to transmit electric energy to output end, so as to generate direct current output voltage Vout according to direct current input voltage Vin, as shown in Figure 3 As shown, the control circuit of the switching converter 200 comprises: an oscillator circuit 210, a slope compensation circuit 220, a duty cycle modulation circuit 230, and a latch circuit 240.

[0028] The oscillator circuit 210 is connected with the slope compensation circuit 220 and is configured to generate a triangular wave voltage signal according to a direct current source signal; in addition, the oscillator circuit 210 can also generate a clock signal CLK according to the triangular wave voltage signal; the slope compensation circuit 220 is connected with the oscillator circuit 210 and the duty cycle modulation circuit 230 and is configured to copy the triangular wave voltage signal generated by the oscillator circuit 210 and then generate a slope compensation current I_slope according to the copied triangular wave voltage signal, the slope compensation current I_slope being used to compensate the waveform of inductance current IL. The duty cycle modulation circuit 230 is connected with the slope compensation circuit 220 and is configured to generate a sampling voltage according to the slope compensation current I_slope obtained by the slope compensation circuit 220 and a sampling current, wherein the sampling current is obtained according to a constant current and the sampled inductance current. In addition, the duty cycle modulation circuit 230 can generate a duty cycle modulation signal MAIN_TRIP according to the sampling voltage and an error voltage after obtaining the sampling voltage, wherein the error voltage is the output signal of an error amplifier, and the specific error signal is obtained by the error amplifier according to the direct current output voltage of the switching converter and a preset reference voltage. The latch circuit 240 is connected with the oscillator circuit 210 and the duty cycle modulation circuit 230 and is configured to generate a switching signal according to the clock signal CLK generated by the oscillator circuit 210 and the duty cycle modulation signal MAIN_TRIP generated by the duty cycle modulation circuit 230, so as to control the conduction state of the power tube. In addition, the triangular wave signals in the slope compensation circuit and the oscillator circuit are reset by different signals respectively. Specifically, the triangular wave signal in the slope compensation circuit is reset by the gate signal LG of the first power tube in the switching converter, and the triangular wave signal in the oscillator circuit is reset by the clock signal.

[0029] With Figure 1Compared with the control circuit of the traditional switching converter in the prior art, the slope compensation circuit of the embodiment of the present disclosure is configured to copy the triangular wave voltage signal generated by the oscillator circuit, and then generate a slope compensation current according to the copied triangular wave voltage signal, so as to separate the slope compensation circuit from the oscillator circuit, and reset the triangular wave signals in the two circuits with different signals respectively, so as to control the timing of resetting the slope compensation current I_slope, specifically, the resetting is controlled through the gate signal LG of the first power tube, so that the situation of false triggering of the comparator (the comparator in the duty cycle modulation circuit) before the inductor current drops to the valley current value can be avoided, thereby ensuring the regularity of the waveform of the inductor current.

[0030] Specifically, as shown in Figure 4 The oscillator circuit 210 includes a first current source Iosc1, a first comparator COMP, a first capacitor Css1, a first transistor MN1, and a high-level pulse generation circuit 211. The input end of the first current source Iosc1 is connected to a voltage source VCC. The output end of the first current source Iosc1 is connected to one end of the first capacitor Css1 and the non-inverting input end of the first comparator COMP, and generates a triangular wave voltage signal VRAMP. The other end of the first capacitor Css1 is grounded. The inverting input end of the first comparator COMP receives a reference voltage VBG. The input end of the high-level pulse generation circuit 211 is connected to the output end of the first comparator COMP. The first transistor MN1 is connected in parallel across the first capacitor Css1. The control end of the first transistor MN1 is connected to the output end of the high-level pulse generation circuit 211, and the output end of the high-level pulse generation circuit 211 generates a clock signal CLK. In addition, the direct current source signal in the “generating a triangular wave voltage signal according to a direct current source signal” in the foregoing is the first current source Iosc1. Further, the high-level pulse generation circuit 211 can be a single-shot circuit generating a 20 ns to 30 ns pulse, for example, the high-level pulse generation circuit 211 can be a 20 ns one shot. The reference voltage VBG can be a voltage value of 0.6 V or 1.2 V.

[0031] As shown in Figure 4As shown, the slope compensation circuit 220 comprises a second current source Iosc2, a second transistor MP0, a third transistor MN0, a fourth transistor MN2, a second capacitor Css2, and a first resistor R1, the second transistor MP0, the third transistor MN0, and the first resistor R1 are connected in series between the input terminal of the first current source Iosc1 and the ground terminal; the second current source Iosc2, the fourth transistor MN2, and the second capacitor Css2 are connected in series between the input terminal of the first current source Iosc1 and the ground terminal; the fourth transistor MN2 is connected across the second capacitor Css2; the control terminal of the second transistor MP0 is connected to the first pole of the second transistor MP0 and the control terminal of the fifth transistor MP1 in the duty cycle modulation circuit 230, so as to mirror the generated slope compensation current I_slope to the duty cycle modulation circuit 230; the control terminal of the third transistor MN0 is connected to the output terminal of the second current source Iosc2, so as to receive the copied triangular wave voltage signal V_SLP; the control terminal of the fourth transistor MN2 is connected to the gate signal LG of the first power transistor ML in the switching converter; the second current source Iosc2 has the same parameters as the first current source Iosc1, the second capacitor Css2 has the same parameters as the first capacitor Css1, and the fourth transistor MN2 has the same parameters as the first transistor MN1, so as to ensure the copying of the triangular wave voltage signal generated by the oscillator circuit 210.

[0032] As shown in Figure 4 As shown, the duty cycle modulation circuit 230 comprises a second comparator PWM_COMP, a fifth transistor MP1, a third current source (Idc-Isns), and a second resistor RS, the fifth transistor MP1 and the second resistor RS are connected in series between the input terminal of the first current source Iosc1 and the ground terminal; the third current source (Idc-Isns) is connected in parallel with the fifth transistor MP1; the positive input terminal of the second comparator PWM_COMP is connected to the node between the fifth transistor MP1 and the second resistor RS, and the output terminal of the third current source (Idc-Isns), so as to obtain the sampling voltage Vsum; the inverting input terminal of the second comparator PWM_COMP receives the error amplification signal eaout, and the output terminal of the second comparator PWM_COMP outputs the duty cycle modulation signal MAIN_TRIP. It should be noted that the error amplification signal eaout is a signal obtained by passing the direct current output voltage and the preset reference voltage through an error amplifier.

[0033] As shown in Figure 4As shown, the latch circuit 240 comprises a first latch LH1 and a second latch LH2. The set end S of the first latch LH1 is connected to the output end of the second comparator PWM_COMP, the reset end R of the first latch LH1 is connected to the output end of the high-level pulse generating circuit 211, and the output end Q of the first latch LH1 is connected to the control end of the first power tube ML in the switching converter. The set end S of the second latch LH2 is connected to the output end of the second comparator PWM_COMP, the reset end R of the second latch LH2 is connected to the output end of the high-level pulse generating circuit 211, and the output end Q of the second latch LH2 is connected to the control end of the second power tube MH in the switching converter.

[0034] In combination Figure 4The circuit diagram of the switching converter of the embodiment of the present disclosure is used to illustrate the working principle of the control circuit of the switching converter: the first current source Iosc1 charges the first capacitor Css1 to generate a triangular wave voltage signal VRAMP, and the triangular wave voltage signal VRAMP is used as the positive input terminal signal of the first comparator COMP, and then compared with the negative input terminal signal VBG through the first comparator COMP, and then the high-level pulse generating circuit 211 outputs the clock signal CLK according to the comparison result; the second current source Iosc2 charges the second capacitor Css2 to generate a triangular wave voltage signal V_SLP (equivalent to copying the triangular wave voltage signal VRAMP), and the triangular wave voltage signal V_SLP drops to the first resistor R1 through the third transistor MN0 to generate a triangular wave current, and passes through the fifth transistor MP1 and the second The mirroring effect of transistor MP0 generates a slope compensation current I_slope. Ultimately, the slope compensation current I_slope and the sampling current (Idc-Isns) act on the second resistor RS to generate a sampling voltage Vsum. The sampling voltage Vsum is compared with the error voltage eaout (corresponding to the aforementioned error amplification signal) via the second comparator PWM_COMP to generate a duty cycle modulation signal MAIN_TRIP. The clock signal CLK and the duty cycle modulation signal MAIN_TRIP are respectively input to the set terminal S and reset terminal R of the first latch LH1 and the second latch LH2. The first output signal and the second output signal of the first latch LH1 and the second latch LH2 serve as the gate signals LG and HG of the first power transistor ML and the second power transistor MH, respectively, to control the turning on and off of the power transistors. Based on the above operating principle, when the triangular wave voltage signal VRAMP (the voltage of the clock charging capacitor (first capacitor Css1)) is higher than VBG, the first comparator COMP outputs a high level but cannot reset the slope compensation current I_slope. It can only reset the first capacitor Css1 and does not affect the slope compensation current I_slope. This is because the slope compensation current I_slope is generated by the copied triangular wave voltage signal V_SLP, and the control terminal of the fourth transistor is controlled by the gate signal LG of the first power transistor ML, that is, LG controls the reset of I_slope. Therefore, the slope compensation current I_slope can only be reset after the lower transistor start-up signal (the gate signal of the first power transistor ML) LG goes high. That is, when Figure 1 Based on the traditional circuit, a triangle wave generating circuit is copied to generate the V_SLP signal to control the slope compensation current I_slope, and the lower tube gate signal LG is introduced at the same time. Therefore, for Figure 2At time t1, although the first comparator COMP outputs a high level, LG does not go high. Therefore, the slope compensation current I_slope continues to increase and does not reset. In addition, the sampling voltage Vsum remains higher than the error voltage eaout. Therefore, while the current of the upper tube (the second power tube MH) is higher than the valley current limit, the duty cycle modulation signal MAIN_TRIP remains high, and the inductor current IL continues to decrease. Once the current of the upper tube (the second power tube MH) drops to the current limit point (the valley current limit value VY_LIM), the lower tube (the first power tube ML) is immediately turned on, and the inductor current IL increases.

[0035] Furthermore, the waveform obtained by the control circuit of the switching converter according to the embodiment of the present disclosure is as follows: Figure 5 As shown in the figure, from top to bottom are the waveform of the inductor current IL, the waveform of the clock signal CLK, the waveform of the slope compensation current I_slope, the waveform of the MAIN_TRIP signal, and the waveform of the gate signal LG of the first power tube ML. It can also be seen from the waveform that at time t1, the slope compensation current I_slope will continue to increase and will not reset until the current of the upper tube (the second power tube MH) is not less than the valley current limit value VY_LIM (that is, during the process of the inductor current IL dropping to the valley current limit value VY_LIM), the duty cycle modulation signal MAIN_TRIP is always high, and there is no Figure 2 In the case of low-to-medium voltage, once the current of the upper tube (the second power tube MH) drops to the current limit point (the valley current limit value VY_LIM), that is, when the inductor current IL drops to the valley current limit value VY_LIM, the lower tube (the first power tube ML) is immediately turned on, and the inductor current IL increases. Figure 5 It can be seen from the figure that the waveform of the inductor current IL is relatively regular.

[0036] In summary, compared to the control circuit of the existing switching converter, the control circuit of the switching converter in the embodiment of the present disclosure copies the triangular wave voltage signal generated by the oscillator circuit and then generates a slope compensation current based on the copied triangular wave voltage signal, thereby separating the slope compensation circuit from the oscillator circuit. Specifically, based on the traditional circuit, another triangular wave generating circuit is copied to generate the V_SLP signal to control the slope compensation current I_slope, and at the same time, the lower tube gate signal LG is introduced. The slope compensation current is only allowed to be reset when the lower tube is turned on, that is, when the signal LG is high. In this way, when the inductor current is higher than the current limit value, the clock is allowed to reset the slope compensation current only when the lower tube is in the on state, thereby ensuring the regular waveform of the inductor current.

[0037] Furthermore, the present disclosure provides a switching converter, such as Figure 3As shown, the switch converter 200 includes a main power circuit 250 configured to control the transmission of electric energy from the input end to the output end by using power tubes to generate a direct current output voltage Vout from a direct current input voltage Vin, and the control circuit (210-240) in the above embodiments for generating a switch driving signal to control the on-off state of the power tubes. The description of the control circuit (210-240) can be found in the corresponding description in the foregoing embodiments, which will not be repeated here. It should be noted that in the present disclosure, the power tube is a transistor that works in switch mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The power tube includes a high potential end and a low potential end on the current path, and a control end for receiving a driving signal to control the on-off of the power tube.

[0038] Preferably, as Figure 4 As shown, the main power circuit 250 includes an inductor L, a first power tube ML, a second power tube MH, an output capacitor Cout, and a load Rload: the inductor L and the first power tube ML are connected in series between the input end Vin and the ground end; the second power tube MH is connected between the intermediate node of the inductor L and the first power tube ML and the output end; the output capacitor Cout is connected between the output end Vout and the ground end; and the load Rload is connected in parallel across the output capacitor Cout. The control circuit (210-240) controls the on-off of the ML and MH by sending a switch driving signal to the control end of the ML and MH. It should be noted that Figure 4 The direct current input voltage Vin and the voltage source VCC of the control circuit are shared, but those skilled in the art should understand that Vin and VCC are not necessarily shared in actual applications, and the embodiments of the present disclosure are only to simplify the circuit diagram, and this is not the focus of the present disclosure.

[0039] In addition, in the above embodiments, the switch converter of the embodiments of the present disclosure is a boost converter, specifically a fixed-frequency valley-current mode boost converter.

[0040] In summary, compared with the existing switch converter, the switch converter of the embodiments of the present disclosure copies the triangular wave voltage signal generated by the oscillator circuit, and then generates a slope compensation current according to the copied triangular wave voltage signal, so as to separate the slope compensation circuit and the oscillator circuit, specifically, a triangular wave generation circuit is additionally copied on the basis of the traditional circuit to generate a V_SLP signal to control the slope compensation current I_slope, and a lower gate signal LG is introduced, only when the lower tube is turned on, i.e. the signal LG is high, the slope compensation current is allowed to be reset, so that when the inductor current is higher than the current limit value, the clock is allowed to reset the slope compensation current only when the lower tube is in the open state, thereby ensuring the regularity of the inductor current waveform.

[0041] The description of the same or corresponding module units in each embodiment in the present disclosure can be referred to each other.

[0042] In the above description, the well-known structural elements and steps are not described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the above-described methods in order to form the same structural elements. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0043] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details and are not limited to the specific embodiments. Obviously, many modifications and changes can be made according to the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The scope of protection of the present application should be limited by the scope defined by the claims of the present application.

[0044] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a" or "an" herein and in the following claims is intended to be interpreted to include the plural, the term "another" is used interchangeably with "another one" or "at least one." Similarly, the use of the term "includes" or "including" should be interpreted as incorporating by reference the disclosure of the above cited patent documents and should not be exclusive. Likewise, the use of the term "comprising" or "comprise" should be interpreted as incorporating by reference the disclosure of the above cited patent documents and should not be exclusive.

[0045] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0046] The above describes several embodiments of the present disclosure in detail, but it is obvious that those skilled in the art can make various modifications and changes to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a switching converter, wherein the switching converter uses a power transistor to control the transmission of power from an input terminal to an output terminal to generate a DC output voltage according to a DC input voltage, characterized in that: The control circuit includes: an oscillator circuit, a slope compensation circuit, a duty cycle modulation circuit, and a latch circuit. Wherein, the oscillator circuit is configured to generate a triangular wave voltage signal according to a DC source signal, and is further configured to generate a clock signal according to the triangular wave voltage signal; The slope compensation circuit is configured to copy the triangular wave voltage signal generated by the oscillator circuit and then generate a slope compensation current according to the copied triangular wave voltage signal; The duty cycle modulation circuit is configured to generate a sampling voltage according to the slope compensation current and the sampling current, and is further configured to generate a duty cycle modulation signal according to the sampling voltage and the error voltage; The latch circuit is configured to generate a switch signal according to the clock signal and the duty cycle modulation signal to control the conduction state of the power tube; The slope compensation circuit and the triangle wave signal in the oscillator circuit are reset using different signals respectively.

2. The control circuit according to claim 1, wherein: The oscillator circuit includes: a first current source, a first comparator, a first capacitor, a first transistor, and a high-level pulse generating circuit. The input end of the first current source is connected to a voltage source, the output end of the first current source is connected to one end of the first capacitor and the non-inverting input end of the first comparator, and the output end of the first current source generates the triangular wave voltage signal; The other end of the first capacitor is grounded, and the inverting input end of the first comparator receives a reference voltage; The input end of the high level pulse generating circuit is connected to the output end of the first comparator; The first transistor is connected in parallel to both ends of the first capacitor, the control end of the first transistor is connected to the output end of the high-level pulse generating circuit, and the output end of the high-level pulse generating circuit generates the clock signal.

3. The control circuit according to claim 2, characterized in that: The slope compensation circuit includes a second current source, a second transistor, a third transistor, a fourth transistor, a second capacitor and a first resistor. The second transistor, the third transistor, and the first resistor are sequentially connected in series between an input terminal of the first current source and a ground terminal; The second current source, the fourth transistor, and the second capacitor are sequentially connected in series between an input terminal of the first current source and a ground terminal; The fourth transistor is connected in parallel to both ends of the second capacitor; The control terminal of the second transistor is connected to the first electrode of the second transistor and the control terminal of the fifth transistor in the duty cycle modulation circuit, so as to mirror the generated slope compensation current into the duty cycle modulation circuit; The control end of the third transistor is connected to the output end of the second current source to receive the copied triangular wave voltage signal; The control terminal of the fourth transistor is connected to the gate signal of the first power transistor in the switching converter; The parameters of the second current source are the same as those of the first current source, the parameters of the second capacitor are the same as those of the first capacitor, and the parameters of the fourth transistor are the same as those of the first transistor.

4. The control circuit according to claim 3, characterized in that: The duty cycle modulation circuit includes: a second comparator, a fifth transistor, a third current source, and a second resistor. The fifth transistor and the second resistor are sequentially connected in series between the input terminal of the first current source and the ground terminal; The third current source is connected in parallel with the fifth transistor; The non-inverting input terminal of the second comparator is connected to the node between the fifth transistor and the second resistor, and the output terminal of the third current source to obtain the sampling voltage; the inverting input terminal of the second comparator receives the error amplified signal, and the output terminal of the second comparator outputs the duty cycle modulation signal.

5. The control circuit according to claim 4, characterized in that: The latch circuit includes a first latch and a second latch. The set terminal of the first latch is connected to the output terminal of the second comparator, the reset terminal of the first latch is connected to the output terminal of the high-level pulse generating circuit, and the output terminal of the first latch is connected to the control terminal of the first power transistor in the switching converter; The set end of the second latch is connected to the output end of the second comparator, the reset end of the second latch is connected to the output end of the high-level pulse generating circuit, and the output end of the second latch is connected to the control end of the second power tube in the switching converter.

6. The control circuit according to claim 4, characterized in that: The error amplified signal is a signal obtained by an error amplifier according to the DC output voltage and a preset reference voltage.

7. The control circuit according to claim 4, characterized in that: The control circuit is in a constant frequency valley current mode.

8. A switching converter, characterized in that: include: The main power circuit is configured to use a power tube to control the transmission of power from the input end to the output end, thereby generating a DC output voltage according to the DC input voltage; as well as The control circuit according to any one of claims 1 to 7, configured to generate a switch control signal to control the conduction state of the power tube.

9. The switching converter according to claim 8, wherein: The main power circuit includes: an inductor, a first power tube, a second power tube, an output capacitor, and a load: The inductor and the first power tube are connected in series between the input terminal and the ground terminal; The second power tube is connected between the inductor, the middle node of the first power tube and the output end; The output capacitor is connected between the output terminal and the ground terminal; The load is connected in parallel across the output capacitor.

10. The switching converter according to claim 8, wherein: The switching converter is a boost converter.

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