Digital shaping filter with order dynamically reconfigurable folding circuit structure and its design method

Abstract

The present disclosure provides a digital shaping filter with a dynamically reconfigurable folding circuit structure and a design method. The digital shaping filter includes: a data redefinition logic unit for performing bit width conversion; a data shift register unit for storing output data of the data redefinition logic unit; a first adder unit for performing addition operations according to the folding circuit structure; an impulse response coefficient register stack unit for writing impulse response coefficients; a reconstruction completion flag register unit for issuing a reconstruction completion signal; a multiplier unit for performing multiplication operations and receiving the output signal of the reconstruction completion flag register unit; a second adder unit for performing addition operations on the output data of the multiplier unit; an order reconstruction register unit for writing the order of the digital shaping filter; a timing control logic unit for selecting result data; and a selection output logic unit for outputting the result data.

Description

Technical Field

[0001] The present disclosure relates to the technical field of digital signal processing, and more particularly to a digital shaping filter with a dynamically reconfigurable folding circuit structure and a design method thereof. Background Art

[0002] Digital signal processing technology is widely used in fields such as radar signal processing, wireless transmission, and satellite communications, and digital filters are a key component of digital signal processing. In radar signal processing and wireless communication systems, the frequency bandwidth and power of the signal are subject to certain limitations. Wideband, high spectral efficiency, and low-loss shaping filtering of modulated signals are key technologies for implementing high-speed data transmission systems. Shaping filtering can improve bandwidth utilization while eliminating intersymbol interference and achieving optimal detection. With the advancement of digital signal processing and high-speed, large-scale digital integrated circuit technology, digital shaping filters offer higher precision, greater flexibility, and greater ease of large-scale integration compared to analog shaping filters. Consequently, digital shaping filters are the predominant form of shaping filters.

[0003] In the process of realizing the concept disclosed herein, the inventors discovered that there are at least the following problems in the related art: in the related art, after the design of the digital shaping filter is completed, the hardware structure is determined. If the characteristics of the digital shaping filter are to be changed, the parameters need to be reselected and the hardware structure of the digital shaping filter needs to be re-layouted, which wastes a lot of time and resources. Summary of the Invention

[0004] In view of this, the present disclosure provides a digital shaping filter with a dynamically reconfigurable order folding circuit structure and a design method thereof.

[0005] One aspect of the present disclosure provides a digital shaping filter with a dynamically reconfigurable folding circuit structure, comprising:

[0006] Data redefinition logic unit, used to perform bit width conversion on input data;

[0007] A data shift register unit, configured to store output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to a time sequence;

[0008] a first adder unit, configured to perform an addition operation on output data of the data shift register unit according to the folding circuit structure;

[0009] An impulse response coefficient register stack unit, used for writing impulse response coefficients of a digital shaping filter;

[0010] The reconstruction completion flag register unit is used to send a reconstruction completion signal when the order reconstruction register unit completes the reconstruction;

[0011] a multiplier unit, configured to perform a multiplication operation on the output data of the first adder unit according to the impulse response coefficient and receive an output signal of the reconstruction completion flag register unit;

[0012] a second adder unit, configured to perform an addition operation on output data of the multiplier unit when the multiplier unit receives a reconstruction completion signal;

[0013] An order reconstruction register unit, used for writing the order of the digital shaping filter;

[0014] A timing control logic unit, configured to control the selection output logic unit to select result data according to the order reconstruction register unit;

[0015] The output logic unit is selected to output result data according to the control of the timing control logic unit.

[0016] According to an embodiment of the present disclosure, the first adder unit is further configured to, when the order is 2i, perform an addition operation on data stored in an Mth data shift register and data stored in an Nth data shift register among the plurality of data shift registers according to a folding circuit structure, wherein i is an integer greater than 0, M∈[1,i], N∈[i+1,2i], M and N are both integers, and M+N=2i+1; and

[0017] When the order is 2j-1, the data stored in the Xth data shift register and the data stored in the Yth data shift register in the multiple data shift registers are added according to the folding circuit structure, where j is an integer greater than 0, X∈[1, j-1], Y∈[j+1, 2j-1], X and Y are both integers, and X+Y=2j.

[0018] According to an embodiment of the present disclosure, the multiplier unit is further configured to perform a multiplication operation on the data obtained by the addition operation performed by the first adder unit when the order is 2i and the data of the impulse response coefficient register file unit; and

[0019] The data obtained by the addition operation of the first adder unit when the order is 2j-1 and the data in the j-th data shift register are multiplied with the data of the impulse response coefficient register file unit respectively.

[0020] According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine the maximum order of reconstruction of the digital shaping filter according to the hardware structure of the digital shaping filter.

[0021] According to an embodiment of the present disclosure, the data transmission method of the folding circuit structure adopts a multi-stage data pipeline method, wherein the first adder unit, the multiplier unit, the second adder unit, and the selection output logic unit all include a register structure, so that the digital shaping filter can output the result data in each clock cycle.

[0022] According to an embodiment of the present disclosure, the digital shaping filter further includes:

[0023] The impulse response coefficient is quantized at a fixed point and expressed as follows:

[0024]

[0025] Wherein, D1 represents the impulse response coefficient after quantization, D2 represents the impulse response coefficient before quantization, C is the quantization base, and K is the bit width of the quantization base.

[0026] According to an embodiment of the present disclosure, the data bit width stored in the order reconstruction register unit is configured to be determined according to the digital shaping filter;

[0027] The data bit width stored in the impulse response coefficient register file unit is configured to be determined according to the digital shaping filter;

[0028] The data bit width stored in the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit;

[0029] The data bit width stored in the first adder unit is configured to be one bit wider than the data bit width stored in the data shift register unit;

[0030] The data bit width stored in the multiplier unit is configured to be the sum of the data bit width stored in the register in the first adder unit and the data bit width stored in the impulse response coefficient register file unit;

[0031] The bit width of the data stored in the second adder unit is configured to be determined by the bit width of the output data of the multiplier unit.

[0032] According to an embodiment of the present disclosure, the data bit width stored in the second adder unit is configured to be the bit width of the output data of the multiplier unit plus the bit width of the output data of the multiplier unit. Wherein, H is the maximum order that the hardware structure of the shaping filter can support.

[0033] Another aspect of the present disclosure provides a design method for a digital shaping filter with a dynamically reconfigurable folding circuit structure, comprising:

[0034] Determine the impulse response coefficient and the reconfigurable order according to the performance parameters of the digital shaping filter, and perform fixed-point quantization on the impulse response coefficient;

[0035] Inputting the impulse response coefficients and orders after fixed-point quantization into the digital shaping filter;

[0036] Reconstructing and configuring the impulse response coefficient register file unit and the order reconstruction register unit according to the bit width of the register in the digital shaping filter;

[0037] According to the order, the corresponding folding circuit structure is selected to calculate and obtain the result data;

[0038] Output result data.

[0039] According to an embodiment of the present disclosure, the calculation to obtain result data by selecting a corresponding folding circuit structure according to the order includes:

[0040] When the order is 2i, the first adder unit performs an addition operation on data stored in an Mth data shift register and data stored in an Nth data shift register among the multiple data shift registers according to the folding circuit structure, where i is an integer greater than 0, M∈[1,i], N∈[i+1,2i], M and N are both integers, and M+N=2i+1; and

[0041] When the order is 2j-1, the first adder unit performs an addition operation on the data stored in the Xth data shift register and the data stored in the Yth data shift register in the multiple data shift registers according to the folding circuit structure, where j is an integer greater than 0, X∈[1, j-1], Y∈[j+1, 2j-1], X and Y are both integers, and X+Y=2j.

[0042] According to an embodiment of the present disclosure, the digital shaping filter is reconstructed by writing the order and impulse response coefficient of the digital shaping filter into the order reconstruction register unit and the impulse response coefficient register stack unit respectively. When the reconstruction is completed, a signal is sent through the reconstruction completion flag register unit, causing the digital shaping filter to start calculation and control the selection output logic unit to select the result data for output through the timing control logic unit. Through this reconstruction method, the digital shaping filter can be quickly generated without changing the hardware circuit, and hardware duplication can be avoided within the optional order range of the digital shaping filter. Therefore, it at least partially overcomes the technical problem in the related art that after the digital shaping filter is designed, the hardware structure is determined. If the characteristics of the digital shaping filter are to be changed, the parameters need to be reselected, and then the hardware structure of the digital shaping filter needs to be re-layouted, which wastes a lot of time and resources. This further reduces resource waste, saves design costs, and makes the designed hardware module reusable. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0044] Figure 1 Schematically shows a block diagram of a digital shaping filter with a dynamically reconfigurable folding circuit structure according to an embodiment of the present disclosure;

[0045] Figure 2 A flowchart schematically illustrates a method for designing a digital shaping filter with a dynamically reconfigurable folding circuit structure according to an embodiment of the present disclosure; and

[0046] Figure 3 The flowchart of the design method of the digital shaping filter with dynamically reconfigurable folding circuit structure according to another embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0048] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0049] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0050] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0051] In related technologies, different systems require digital shaping filters with varying filtering characteristics, often requiring designers to redesign and verify the filters, a process that wastes considerable time and effort. This is particularly true in the design of application-specific integrated circuits (ASICs) or system-on-chips (SoCs), where these critical modules offer limited reusability. Furthermore, the use of field-programmable gate arrays (FPGAs) for designing digital shaping filters is increasingly common. However, once the parameters of FPGA-based digital shaping filters are selected, the circuit structure is fixed after synthesis and layout. Changing the characteristics requires reselecting the parameters, re-synthesizing, and re-layout, which also wastes considerable time.

[0052] In view of this, the present disclosure proposes a digital shaping filter with a dynamically reconfigurable folding circuit structure. The digital shaping filter is reconstructed by writing the order and impulse response coefficient of the digital shaping filter into an order reconstruction register unit and an impulse response coefficient register stack unit, respectively. When the reconstruction is completed, a signal is sent through the reconstruction completion flag register unit, causing the digital shaping filter to start calculation and output the result data through the control of the timing control logic unit. This reconstruction method can quickly generate a digital shaping filter without changing the hardware circuit, and can avoid repeated hardware design within the optional order range of the digital shaping filter. Therefore, it at least partially overcomes the technical problem in the related art that after the digital shaping filter is designed, the hardware structure is determined. If the characteristics of the digital shaping filter are to be changed, the parameters need to be reselected and the hardware structure of the digital shaping filter needs to be re-layouted, which wastes a lot of time and resources. This further reduces resource waste, saves design costs, and makes the designed hardware module reusable.

[0053] Figure 1The block diagram of a digital shaping filter 100 with a dynamically reconfigurable folding circuit structure according to an embodiment of the present disclosure is schematically shown.

[0054] like Figure 1 As shown, the digital shaping filter 100 includes a data redefinition logic unit 101, a data shift register unit 102, a first adder unit 103, an impulse response coefficient register stack unit 104, a reconstruction completion flag register unit 105, a multiplier unit 106, a second adder unit 107, an order reconstruction register unit 108, a timing control logic unit 109 and a selection output logic unit 110.

[0055] The data redefinition logic unit 101 is used to perform bit width conversion on input data.

[0056] The data shift register unit 102 is used to store the output data of the data redefinition logic unit. The data shift register unit includes a plurality of data shift registers. The output data of the data redefinition logic unit is stored in the plurality of data shift registers in sequence according to a time sequence.

[0057] The first adder unit 103 is configured to perform an addition operation on the output data of the data shift register unit according to the folding circuit structure.

[0058] The impulse response coefficient register file unit 104 is used to write the impulse response coefficients of the digital shaping filter.

[0059] The reconstruction completion flag register unit 105 is used to send a reconstruction completion signal when the order reconstruction register unit completes the reconstruction.

[0060] The multiplier unit 106 is configured to perform a multiplication operation on the output data of the first adder unit according to the impulse response coefficient and receive an output signal of the reconstruction completion flag register unit.

[0061] The second adder unit 107 is configured to perform an addition operation on the output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal.

[0062] The order reconstruction register unit 108 is used to write the order of the digital shaping filter.

[0063] The timing control logic unit 109 is used to control the selection output logic unit to select result data according to the order reconstruction register unit.

[0064] The selection output logic unit 110 is used to output result data according to the control of the timing control logic unit.

[0065] According to an embodiment of the present disclosure, the data redefinition logic unit 101 can perform bit-width conversion on received data. For example, if a 1-bit wide data "0" is received, the data redefinition logic unit 101 will convert the "0" into a 2-bit wide data "11." Alternatively, if a 1-bit wide data "1" is received, the data redefinition logic unit 101 will convert the "1" into a 2-bit wide data "01."

[0066] According to an embodiment of the present disclosure, the input end of the data shift register unit 102 is connected to the output end of the data redefinition logic unit 101, the data shift register unit 102 may include multiple data shift registers, and the output data of the data redefinition logic unit may be output in a time sequence and then stored in the corresponding data shift register in a time sequence.

[0067] According to an embodiment of the present disclosure, an input end of the first adder unit 103 is connected to an output end of the data shift register unit 102 , and the first adder unit 103 can perform an addition operation on the output data of the data shift register unit.

[0068] According to an embodiment of the present disclosure, the first adder unit 103 may perform addition operations through a folded circuit structure.

[0069] According to an embodiment of the present disclosure, the impulse response coefficients of the digital shaping filter may be written into the impulse response coefficient register file unit 104 by the processor.

[0070] According to an embodiment of the present disclosure, the reconstruction completion flag register unit 105 can send a reconstruction completion signal to the multiplier unit when the digital shaping filter order reconstruction register unit completes reconstruction. The reconstruction completion flag register unit can be invalid before the digital shaping filter is reconfigured, and the reconstruction completion flag register unit can send the reconstruction completion signal after the digital shaping filter configuration is completed.

[0071] According to an embodiment of the present disclosure, the input end of the multiplier unit 106 can be connected to the output ends of the impulse response coefficient register file unit 104 and the reconstruction completion flag register unit 105 , and the multiplier unit 106 can receive the output signal of the reconstruction completion flag register unit 105 .

[0072] According to an embodiment of the present disclosure, the multiplier unit 106 may perform a multiplication operation on the output data of the first adder unit according to the impulse response coefficient. For example, the multiplier unit 106 may multiply the output data of the first adder unit by the impulse response coefficient.

[0073] According to an embodiment of the present disclosure, an input terminal of the second adder unit 107 may be connected to an output terminal of the multiplier unit 106 , and the second adder unit 107 may perform an addition operation on output data of the multiplier unit.

[0074] According to an embodiment of the present disclosure, the order of the digital shaping filter may be written into the order reconstruction register unit 108 by a processor.

[0075] According to an embodiment of the present disclosure, the input end of the timing control logic unit 109 is connected to the output end of the order reconstruction register unit 108, and the order of the digital shaping filter can be determined by the order reconstruction register unit 108, and then the selection output logic unit is controlled to select the result data at the corresponding timing.

[0076] According to an embodiment of the present disclosure, the output logic unit 110 is selected to output result data according to the control of the timing control logic unit.

[0077] According to an embodiment of the present disclosure, the digital shaping filter is reconstructed by writing the order and impulse response coefficient of the digital shaping filter into the order reconstruction register unit and the impulse response coefficient register stack unit respectively. When the reconstruction is completed, a signal is sent through the reconstruction completion flag register unit, causing the digital shaping filter to start calculation and control the selection output logic unit to select the result data for output through the timing control logic unit. Through this reconstruction method, the digital shaping filter can be quickly generated without changing the hardware circuit, and hardware duplication can be avoided within the optional order range of the digital shaping filter. Therefore, it at least partially overcomes the technical problem in the related art that after the digital shaping filter is designed, the hardware structure is determined. If the characteristics of the digital shaping filter are to be changed, the parameters need to be reselected, and then the hardware structure of the digital shaping filter needs to be re-layouted, which wastes a lot of time and resources. This further reduces resource waste, saves design costs, and makes the designed hardware module reusable.

[0078] According to an embodiment of the present disclosure, the first adder unit is also used to perform an addition operation on the data stored in the Mth data shift register and the data stored in the Nth data shift register among multiple data shift registers according to a folding circuit structure when the order is 2i, wherein i is an integer greater than 0, M∈[1, i], N∈[i+1, 2i], M and N are both integers, and M+N=2i+1.

[0079] When the order is 2j-1, the data stored in the Xth data shift register and the data stored in the Yth data shift register in the multiple data shift registers are added according to the folding circuit structure, where j is an integer greater than 0, X∈[1, j-1], Y∈[j+1, 2j-1], X and Y are both integers, and X+Y=2j.

[0080] According to an embodiment of the present disclosure, for example, when the order of the digital shaping filter is 6, data can be stored in the data shift register unit through 6 data shift registers, and then the data stored in the 1st data shift register is added to the data stored in the 6th data shift register, the data stored in the 2nd data shift register is added to the data stored in the 5th data shift register, and the data stored in the 3rd data shift register is added to the data stored in the 4th data shift register through the first adder unit to obtain three groups of data.

[0081] For another example, when the order of the digital shaping filter is 7, the data shift register unit can store data through 7 data shift registers, and then the data stored in the 1st data shift register is added to the data stored in the 7th data shift register, the data stored in the 2nd data shift register is added to the data stored in the 6th data shift register, and the data stored in the 3rd data shift register is added to the data stored in the 5th data shift register through the first adder unit to obtain three sets of data.

[0082] According to an embodiment of the present disclosure, the multiplier unit is further configured to perform a multiplication operation on the data obtained by the addition operation performed by the first adder unit when the order is 2i and the data of the impulse response coefficient register file unit.

[0083] The data obtained by the addition operation of the first adder unit when the order is 2j-1 and the data in the j-th data shift register are multiplied with the data of the impulse response coefficient register file unit respectively.

[0084] According to an embodiment of the present disclosure, the data of the impulse response coefficient register file unit may be an impulse response coefficient.

[0085] According to an embodiment of the present disclosure, for example, when the order of the digital shaping filter is 6, three multiplication operations are required to multiply the three sets of data in the first adder by the impulse response coefficients. If the data in the data shift register unit is directly multiplied by the impulse response coefficients without passing through the folding circuit, six multiplication operations are required.

[0086] For another example, when the order of the digital shaping filter is 7, four multiplication operations are required to multiply the three sets of data in the first adder by the impulse response coefficients, and to multiply the data stored in the fourth data shift register by the impulse response coefficients, using the multiplier unit. If the data in the data shift register unit is directly multiplied by the impulse response coefficients without passing through the folding circuit, seven multiplication operations are required. This shows that the addition operation of the data shift register unit using the folding circuit structure reduces the multiplication logic resources by half, saving computing resources and improving computing efficiency.

[0087] According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine the maximum order of reconstruction of the digital shaping filter according to the hardware structure of the digital shaping filter.

[0088] According to the embodiments of the present disclosure, the hardware structure of the digital shaping filter determines the maximum order that it can reconstruct. The hardware structure of the digital shaping filter can be designed to be the maximum order and input into the order reconstruction register unit, so that the order can be dynamically reconfigured within a range less than the maximum order. Theoretically, the larger the maximum order of the digital shaping filter is designed, the larger the range of order selection will be during its implementation.

[0089] According to an embodiment of the present disclosure, the data transmission method of the folding circuit structure adopts a multi-stage data pipeline method, wherein the first adder unit, the multiplier unit, the second adder unit, and the selection output logic unit all include a register structure, so that the digital shaping filter can output the result data in each clock cycle.

[0090] According to the embodiments of the present disclosure, the first adder unit, the multiplier unit, the second adder unit, and the select output logic unit all include register structures, allowing the digital shaping filter to store data in each unit. The multi-stage data pipeline employed by the digital shaping filter allows each unit to perform calculations simultaneously, thereby outputting a new calculation result in each clock cycle. This improves the computational efficiency of the digital shaping filter and the speed of subsequent signal processing.

[0091] According to an embodiment of the present disclosure, the digital shaping filter further includes:

[0092] The impulse response coefficient is quantized at a fixed point and expressed as follows:

[0093]

[0094] Wherein, D1 represents the impulse response coefficient after quantization, D2 represents the impulse response coefficient before quantization, C is the quantization base, and K is the bit width of the quantization base.

[0095] According to an embodiment of the present disclosure, when the hardware circuit of the digital shaping filter is fixed-point designed, the impulse response coefficient needs to be fixed-point quantized. When the quantization bit number is higher than 16 bits, the mean value of the quantization error within the passband of the digital shaping filter is less than 0.1, which can meet the design requirements. In order to avoid unnecessary waste of bit width while ensuring the accuracy requirement, the impulse response coefficient can be quantized according to the following formula:

[0096]

[0097] Among them, D1 represents the impulse response coefficient after quantization, D2 represents the impulse response coefficient before quantization, C is the quantization base, the quantization base is the absolute value of the impulse response coefficient with the smallest absolute value among the impulse response coefficients, and K is the bit width of the quantization base. The wider the number of bits of the quantization base, the greater the accuracy.

[0098] According to an embodiment of the present disclosure, the data bit width stored in the order reconstruction register unit is configured to be determined according to the digital shaping filter.

[0099] The data bit width stored in the impulse response coefficient register file unit is configured to be determined according to the digital shaping filter.

[0100] The data bit width stored in the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit.

[0101] The data bit width stored in the first adder unit is configured to be one bit wider than the data bit width stored in the data shift register unit.

[0102] The data bit width stored in the multiplier unit is configured as the sum of the data bit width structure stored in the register in the first adder unit and the data bit width stored in the impulse response coefficient register file unit.

[0103] The bit width of the data stored in the second adder unit is configured to be determined by the bit width of the output data of the multiplier unit.

[0104] According to the embodiments of the present disclosure, the data bit width stored in the order reconstruction register unit and the data bit width stored in the impulse response coefficient register file unit can be set according to the characteristics and accuracy requirements of the digital shaping filter.

[0105] According to an embodiment of the present disclosure, the data bit width stored in the data shift register unit may be the same as the data bit width output by the data redefinition logic unit. For example, the data bit width output by the data redefinition logic unit is 2 bits, and the data bit width stored in the data shift register unit is also 2 bits.

[0106] According to an embodiment of the present disclosure, the data bit width stored in the first adder unit may be one bit wider than the data bit width stored in the data shift register unit. For example, the data bit width stored in the data shift register unit is 2 bits, and the data bit width stored in the first adder unit may be 3 bits.

[0107] According to an embodiment of the present disclosure, the data bit width stored in the multiplier unit may be the sum of the data bit widths stored in the register structure in the first adder unit and the impulse response coefficient register file unit.

[0108] According to an embodiment of the present disclosure, the data bit width stored in the second adder unit is configured to be the bit width of the output data of the multiplier unit plus the bit width of the output data of the multiplier unit. Wherein, H is the maximum order that the hardware structure of the shaping filter can support.

[0109] Figure 2 The flowchart of the design method of the digital shaping filter with dynamically reconfigurable folding circuit structure according to the embodiment of the present disclosure is schematically shown.

[0110] like Figure 2 As shown, the method includes operations S201 to S205.

[0111] In operation S201 , impulse response coefficients and reconfigurable orders are determined according to performance parameters of a digital shaping filter, and the impulse response coefficients are fixed-point quantized.

[0112] In operation S202 , the impulse response coefficients and orders after fixed-point quantization are input to a digital shaping filter.

[0113] In operation S203 , the impulse response coefficient register file unit and the order reconstruction register unit are reconfigured according to the bit width of the register in the digital shaping filter.

[0114] In operation S204 , a corresponding folding circuit structure is selected according to the order to perform calculations to obtain result data.

[0115] In operation S205 , the result data is output.

[0116] According to an embodiment of the present disclosure, the frequency response of the digital shaping filter satisfies the raised cosine characteristic. Matlab can be used to generate the impulse response coefficient and order of the corresponding characteristic. The digital shaping filter can be implemented using a finite unit impulse response (FIR) digital filter. When using Matlab for parameter generation, it should be noted that if the truncation length is L symbols, W samples are taken within each symbol interval T (determined by the sampling rate). In this case, a total of LW samples are used to represent the impulse response of the truncated filter. The truncation length L generated using Matlab's rcosine function is generally 4-10 symbols. It is necessary to ensure that L meets system performance requirements while also ensuring that the filter order is not too large to save resources.

[0117] According to an embodiment of the present disclosure, the order and impulse response coefficient of the digital shaping filter can be written into the order reconstruction register unit and the impulse response coefficient register stack unit by a processor. When the bit width of the written impulse response coefficient is smaller than the bit width of the designed impulse response coefficient register, the impulse response coefficient needs to be written to the high bit of the impulse response coefficient register stack unit, and the remaining low bits need to be written as 0.

[0118] According to an embodiment of the present disclosure, a corresponding folding circuit structure may be selected by performing parity judgment on data in an order reconstruction register.

[0119] According to an embodiment of the present disclosure, the digital shaping filter is reconstructed by writing the order and impulse response coefficient of the digital shaping filter into the order reconstruction register unit and the impulse response coefficient register stack unit respectively. When the reconstruction is completed, a signal is sent through the reconstruction completion flag register unit, causing the digital shaping filter to start calculation and control the selection output logic unit to select the result data for output through the timing control logic unit. Through this reconstruction method, the digital shaping filter can be quickly generated without changing the hardware circuit, and hardware duplication can be avoided within the optional order range of the digital shaping filter. Therefore, it at least partially overcomes the technical problem in the related art that after the digital shaping filter is designed, the hardware structure is determined. If the characteristics of the digital shaping filter are to be changed, the parameters need to be reselected, and then the hardware structure of the digital shaping filter needs to be re-layouted, which wastes a lot of time and resources. This further reduces resource waste, saves design costs, and makes the designed hardware module reusable.

[0120] According to an embodiment of the present disclosure, the calculation to obtain result data by selecting a corresponding folding circuit structure according to the order includes:

[0121] When the order is 2i, the first adder unit adds the data stored in the Mth data shift register and the data stored in the Nth data shift register in the multiple data shift registers according to the folding circuit structure, where i is an integer greater than 0, M∈[1, i], N∈[i+1, 2i], M and N are both integers, and M+N=2i+1.

[0122] When the order is 2j-1, the first adder unit performs an addition operation on the data stored in the Xth data shift register and the data stored in the Yth data shift register in the multiple data shift registers according to the folding circuit structure, where j is an integer greater than 0, X∈[1, j-1], Y∈[j+1, 2j-1], X and Y are both integers, and X+Y=2j.

[0123] According to an embodiment of the present disclosure, for example, when the order of the digital shaping filter is 6, data can be stored in the data shift register unit through 6 data shift registers, and then the data stored in the 1st data shift register is added to the data stored in the 6th data shift register, the data stored in the 2nd data shift register is added to the data stored in the 5th data shift register, and the data stored in the 3rd data shift register is added to the data stored in the 4th data shift register through the first adder unit to obtain three groups of data.

[0124] For another example, when the order of the digital shaping filter is 7, the data shift register unit can store data through 7 data shift registers, and then the data stored in the 1st data shift register is added to the data stored in the 7th data shift register, the data stored in the 2nd data shift register is added to the data stored in the 6th data shift register, and the data stored in the 3rd data shift register is added to the data stored in the 5th data shift register through the first adder unit to obtain three sets of data.

[0125] Figure 3 The flowchart of the design method of the digital shaping filter with dynamically reconfigurable folding circuit structure according to another embodiment of the present disclosure is schematically shown.

[0126] like Figure 3 As shown, the method can be applied to a signal processing system, a data transmission system, etc. The method includes operations S301 to S310.

[0127] In operation S301, characteristic parameters of the digital shaping filter are extracted according to the performance requirements of the system for the digital shaping filter.

[0128] In operation S302 , impulse response coefficients and orders corresponding to characteristic parameters are generated through Matlab.

[0129] In operation S303 , the impulse response coefficients are fixed-point quantized according to the accuracy requirement of the system.

[0130] In operation S304, the bit width of each unit of the digital shaping filter is determined and the hardware system structure is designed.

[0131] In operation S305 , an order register unit and an impulse response coefficient register file unit are configured.

[0132] In operation S306 , it is determined whether the order is an even number. If it is determined that the order is an even number, operation S307 is performed. If it is determined that the order is an odd number, operation S308 is performed.

[0133] In operation S307 , calculation is performed using an even-numbered corresponding folded circuit structure.

[0134] In operation S308 , calculation is performed using the odd-number corresponding folding circuit structure.

[0135] In operation S309 , it is determined whether the filter characteristics are changed after the parameter reconstruction is completed. If it is determined that the filter characteristics are changed, operation S305 is performed. If it is determined that the filter characteristics are not changed, operation S310 is performed.

[0136] In operation S310 , the system outputs result data corresponding to characteristics according to the configured parameters.

[0137] According to the embodiments of the present disclosure, the characteristics of the digital shaping filter are changed by reconstructing the parameters of the digital shaping filter, which is simple and flexible. The required digital shaping filter can be quickly generated without changing the hardware circuit, and can be adapted to systems with various frequencies and bandwidths, avoiding repeated design, reducing resource waste, saving design costs, and making the hardware module reusable.

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, program segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, as well as the combination of boxes in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or may be implemented using a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or coupled in various ways, and all such combinations and / or couplings fall within the scope of the present disclosure.

[0139] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A digital shaping filter with a dynamically reconfigurable folding circuit structure, comprising: Data redefinition logic unit, used to perform bit width conversion on input data; a data shift register unit, configured to store the output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to a time sequence; a first adder unit, configured to perform an addition operation on the output data of the data shift register unit according to a folding circuit structure; An impulse response coefficient register stack unit, used for writing impulse response coefficients of a digital shaping filter; The reconstruction completion flag register unit is used to send a reconstruction completion signal when the order reconstruction register unit completes the reconstruction; a multiplier unit, configured to perform a multiplication operation on the output data of the first adder unit according to the order and receive an output signal of the reconstruction completion flag register unit; a second adder unit, configured to perform an addition operation on output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal; An order reconstruction register unit, used for writing the order of the digital shaping filter; A timing control logic unit, configured to control the selection output logic unit to select result data according to the order reconstruction register unit; A selection output logic unit is used to output the result data according to the control of the timing control logic unit; The first adder unit is further configured to, when the order is 2i, perform an addition operation on the data stored in the Mth data shift register and the data stored in the Nth data shift register among the plurality of data shift registers according to the folding circuit structure, wherein i is an integer greater than 0, , , M and N are both integers, and M+N=2i+1; and When the order is 2j-1, the data stored in the Xth data shift register and the data stored in the Yth data shift register among the plurality of data shift registers are added according to the folding circuit structure, where j is an integer greater than 0. , , X and Y are both integers, and X + Y = 2j.

2. The digital shaping filter according to claim 1, The multiplier unit is further configured to perform a multiplication operation on the data obtained by the first adder unit through the addition operation when the order is 2i and the data of the impulse response coefficient register file unit; and The data obtained by the addition operation of the first adder unit when the order is 2j-1 and the data in the j-th data shift register are multiplied by the data of the impulse response coefficient register file unit respectively.

3. The digital shaping filter according to claim 1, The order reconstruction register unit is further used to determine the maximum order of reconstruction of the digital shaping filter according to the hardware structure of the digital shaping filter.

4. The digital shaping filter according to any one of claims 1 to 3, The data transmission mode of the folding circuit structure adopts a multi-stage data pipeline mode, wherein: The first adder unit, the multiplier unit, the second adder unit, and the selection output logic unit all include a register structure, so that the digital shaping filter can output the result data in each clock cycle.

5. The digital shaping filter according to any one of claims 1 to 3, further comprising: The impulse response coefficient is fixed-point quantized and expressed as follows: （1） in, represents the quantized impulse response coefficient, Represents the impulse response coefficient before quantization, C is the quantization radix, and K is the bit width of the quantization radix.

6. The digital shaping filter according to any one of claims 1 to 3, The data bit width stored in the order reconstruction register unit is configured to be determined according to the digital shaping filter; The data bit width stored in the impulse response coefficient register file unit is configured to be determined according to the digital shaping filter; The data bit width stored in the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit; The data bit width stored in the first adder unit is configured to be one bit wider than the data bit width stored in the data shift register unit; The data bit width stored in the multiplier unit is configured to be the sum of the data bit width stored in the register in the first adder unit and the data bit width stored in the impulse response coefficient register file unit; The bit width of the data stored in the second adder unit is configured to be determined by the bit width of the output data of the multiplier unit.

7. The digital shaping filter according to claim 6, wherein The data bit width stored in the second adder unit is configured to be equal to the bit width of the output data of the multiplier unit plus the bit width of the output data of the multiplier unit. , where H is the maximum order that the hardware structure of the shaping filter can support.

8. A design method for a digital shaping filter with a dynamically reconfigurable folding circuit structure, comprising: Determining an impulse response coefficient and a reconfigurable order according to performance parameters of the digital shaping filter, and performing fixed-point quantization on the impulse response coefficient; Inputting the fixed-point quantized impulse response coefficient and the order into the digital shaping filter; Reconstructing and configuring an impulse response coefficient register file unit and an order reconstruction register unit according to the bit width of the register in the digital shaping filter, wherein the impulse response coefficient register file unit is configured to write the impulse response coefficient of the digital shaping filter, and the order reconstruction register unit is configured to write the order of the digital shaping filter; Selecting a corresponding folding circuit structure according to the order to perform calculations to obtain result data; outputting the result data; The step of selecting a corresponding folding circuit structure according to the order to calculate and obtain result data includes: When the order is 2i, the first adder unit is used to perform an addition operation on the data stored in the Mth data shift register and the data stored in the Nth data shift register among the multiple data shift registers according to the folding circuit structure, where i is an integer greater than 0. , , M and N are both integers, and M+N=2i+1; and When the order is 2j-1, the data stored in the Xth data shift register and the data stored in the Yth data shift register among the plurality of data shift registers are added using the first adder unit according to the folding circuit structure, where j is an integer greater than 0. , , X and Y are both integers, and X + Y = 2j.

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