Monolithic LED pixel

Abstract

A method of forming a plurality of monolithic LED pixels (1) for a light emitting diode (LED) display is provided. The method includes forming a common (102) semiconductor layer comprising a Group III nitride on a sacrificial substrate and forming an array of light emitting diode (LED) sub-pixels on a surface of the common semiconductor layer. The method further includes forming a planarization dielectric layer on the array of LED sub-pixels. The array of LED sub-pixels is divided into a plurality of monolithic LED pixels by etching a grid of pixel defining trenches into the sacrificial substrate, wherein each monolithic LED pixel includes at least two LED sub-pixels. A sacrificial dielectric layer is formed on the pixel trenches to form a bonding surface. A handle substrate is bonded to the bonding surface, wherein a first portion of the sacrificial substrate is selectively removed to isolate each monolithic LED pixel. Light extraction features are formed for each monolithic LED pixel including: selectively removing a second portion of the sacrificial substrate aligned with each LED sub-pixel, and the sacrificial dielectric layer is removed to separate each monolithic LED pixel from the handle substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to Group III nitride semiconductors. In particular, the present disclosure relates to Light Emitting Diodes (LEDs) comprising Group III nitride semiconductors. BACKGROUND

[0002] Micro-LEDs are generally defined as LEDs having a size of 100 pm x 100 pm or less. Micro-LEDs can be arranged in an array to form a self-emissive micro-display / projector, which can be suitable for use in a variety of devices, such as smart watches, head-mounted displays, micro-projectors for AR and VR applications, and large area displays.

[0003] One known form of micro-LED array comprises a plurality of LEDs formed from Group III nitride. Group III nitride LEDs are inorganic semiconductor LEDs that contain GaN and its alloys with InN and AlN in the active light-emitting region. In contrast to conventional large area LEDs, such as Organic Light Emitting Diodes (OLEDs) in which the light-emitting layer is an organic compound, Group III nitride LEDs can be driven with a significantly higher current density and emit a higher optical power density. Thus, the higher luminance (brightness), which is defined as the amount of light emitted per unit area by a light source in a specified direction, makes micro-LEDs suitable for applications that require or benefit from high brightness.

[0004] Known micro-LED fabrication techniques include forming one or more GaN layers on a sapphire substrate to produce LEDs that emit blue or green light. For LEDs that emit red light, known fabrication techniques include forming one or more InAlGaP layers on a GaAs substrate.

[0005] In particular, for blue LEDs in the medium power range, LEDs comprising GaN layers formed on sapphire substrates have traditionally had a performance advantage over GaN LEDs formed on Si substrates due to the use of a Patterned Sapphire Substrate (PSS), which improves the Light Extraction Efficiency (LEE) of the LED. Furthermore, the performance advantage is extended due to the emission of light from 5 sides, which is advantageous when phosphor is used to convert blue light to white.

[0006] In the case of micro-LED technology for displays, volume emission is a disadvantage as it creates cross-talk between pixels, resulting in displays with low contrast. Therefore, laser liftoff must be used to remove the sapphire from the LED, which is not suitable for removing PSS substrates, meaning that the advantages of using PSS to manufacture micro-LEDs cannot be realised. This narrows the performance gap between PSS and Si-based InGaN LEDs.

[0007] GaN layers grown on sapphire substrates are approximately 6-9um thick. As micro-LEDs are reduced in size, it is advantageous to reduce the thickness of the GaN to aid process control and prevent side emission from relatively thick GaN layers. Conversely, GaN layers grown on silicon substrates are approximately 2.5-5um thick.

[0008] Large area displays comprising micro-LEDs can be formed from a plurality of red, green and blue micro-LEDs. For example, for a 4K resolution display, each display can provide approximately 8300000 pixels. Therefore, 8300000 red, green and blue LEDs can be provided to form a single display (i.e. a total of 24900000 LEDs per display). The red, green and blue LEDs can be assembled on a display substrate using pick and place technology. Pick and place technology includes imprint systems, laser assisted systems and fluidic assembly. Assembly speeds vary from 1000 to 10000 components per second. Therefore, assembly time for a 4K screen is approximately 1 hour.

[0009] It is an object of the present invention to provide an improved method of forming a plurality of monolithic light emitting diode (LED) pixels for an LED display. SUMMARY

[0010] The present inventors have recognised that it is desirable to reduce the assembly time of an LED display by reducing the number of components to be assembled to form the display. In particular, the present inventors have recognised that the assembly process of picking and placing individual red, green and blue LEDs for an RGB display is time consuming.

[0011] According to a first aspect of the present disclosure, there is provided a method of forming a monolithic LED pixel for an LED display. The method comprises:

[0012] i) forming a common semiconductor layer comprising a group III nitride on a sacrificial substrate;

[0013] ii) forming an array of light emitting diode (LED) sub-pixels on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite the sacrificial substrate, each LED sub-pixel of the array of LED sub-pixels comprising a stack of group III nitride layers;

[0014] iii) forming a planarization dielectric layer over the array of LED sub-pixels to provide a planarization dielectric surface that is substantially aligned with the surface of the common semiconductor layer;

[0015] iv) dividing the array of LED sub-pixels into a plurality of monolithic LED pixels by etching a grid of pixel-defining trenches from the planarization dielectric surface towards the sacrificial substrate, wherein each monolithic LED pixel comprises at least two LED sub-pixels of an array of LED devices formed monolithically on the common semiconductor layer;

[0016] v) forming a sacrificial dielectric layer over the pixel trenches and the planarization surface to form a bonding surface that is substantially aligned with the surface of the common semiconductor layer;

[0017] vi) bonding a handling substrate to the bonding surface of the sacrificial dielectric layer;

[0018] vii) selectively removing a first portion of the sacrificial substrate through the thickness of the sacrificial substrate that is aligned with the grid of pixel-defining trenches to isolate each of the monolithic LED pixels;

[0019] viii) forming a light extraction feature for each monolithic LED pixel comprising: selectively removing a second portion of the sacrificial substrate that is aligned with each of the LED sub-pixels; and

[0020] ix) removing the sacrificial dielectric layer to separate each monolithic LED pixel from the handling substrate.

[0021] According to the method of the first aspect, a plurality of monolithic LED pixels are formed. The monolithic LED pixels can each be suitable for assembly into an LED display. Each monolithic LED pixel comprises a plurality of LED sub-pixels, each LED sub-pixel of the monolithic LED pixel having an associated light extraction feature. Thus, each monolithic LED pixel can comprise a plurality of LED devices formed monolithically on a common semiconductor layer. Once isolated, the monolithic LED pixels can be assembled to form a display, for example using a pick and place method. By forming a plurality of LED devices (LED sub-pixels) monolithically, the number of discrete components to be assembled to form a display can be reduced.

[0022] The method of the first aspect forms a plurality of monolithic LED sub-pixels on a common semiconductor layer comprising a Group III nitride. The common semiconductor layer is formed on a sacrificial substrate. The method according to the first aspect provides for processing both major surfaces of the common semiconductor layer by providing a sacrificial substrate and a handling substrate. The sacrificial substrate provides an initial substrate on which the common semiconductor layer and LED sub-pixels can be formed. The LED sub-pixels can subsequently be attached to the handling substrate to allow for removal of portions of the sacrificial substrate in order to form light extraction features on opposite sides of the common semiconductor layer. By processing both major surfaces of the common semiconductor layer, a plurality of LED sub-pixels can be formed monolithically on the common semiconductor layer.

[0023] In the following, different aspects of the application are defined in more detail. Each aspect so defined can be combined with any other aspect or aspects unless clearly indicated to the contrary. In particular, any feature indicated to be optional can be combined with any other feature or features indicated to be optional or advantageous.

[0024] In some embodiments, the common semiconductor layer can comprise an n-type doped Group III nitride. For example, in some embodiments, the common semiconductor layer can comprise GaN and an n-type dopant, such as Si or Ge. The common semiconductor layer can have a thickness (in a direction perpendicular to the sacrificial substrate) of at least 500 nm. The thickness of the common semiconductor layer can be no greater than 5 pm (in a direction perpendicular to the sacrificial substrate).

[0025] The sacrificial substrate can be formed from a substrate configured to provide a sacrificial substrate surface having an in-plane lattice constant suitable for growth of a Group III nitride layer thereon. For example, the sacrificial substrate can comprise a sapphire or silicon substrate.

[0026] In some embodiments, each LED sub-pixel is configured to produce light having a first wavelength of at least 380 nm. Thus, each LED sub-pixel can produce visible light. In some embodiments, each LED sub-pixel is configured to produce light having a first wavelength of no greater than 490 nm. Thus, each LED sub-pixel can produce substantially blue visible light. In the present disclosure, where an LED is referred to as producing light of a particular wavelength, it will be understood that this refers to the peak wavelength of the light produced by the LED.

[0027] In some embodiments, each Group III nitride layer of each LED sub-pixel comprises one or more of AlInGaN, AlGaN, InGaN and GaN. As used herein, any reference to a species by its constituent components includes all available stoichiometries thereof. Thus, for example, AlGaN includes all alloys thereof, such as Al x Ga 1-xN, where x is not equal to 1 or 0. The stoichiometry of each layer can vary depending on the function of the particular layer.

[0028] For example, in some embodiments, each LED sub-pixel can comprise a superlattice of Ill-nitride layers, an active layer configured to generate light, an electron blocking layer, and one or more p-type semiconductor layers. The active layer can comprise one or more quantum well layers configured to generate light.

[0029] The array of LED sub-pixels can be formed as a regularly spaced array. The regularly spaced array can be similar to any configuration for a close packing of circles (or polygons), such as a square packing or a hexagonal packing. Each LED sub-pixel within the array can be elliptical or polygonal. In some embodiments, each LED sub-pixel can be a polygon having no more than six sides.

[0030] In some embodiments, the planarisation dielectric layer can be formed from a plurality of passivation layers. Each passivation layer can comprise a dielectric, such as silicon dioxide or silicon nitride. The planarisation dielectric layer can be subjected to a chemical mechanical polishing process to improve the smoothness (i.e. reduce the surface roughness) of the planarisation dielectric surface.

[0031] In some embodiments, after forming the planarisation dielectric layer, a third portion of the planarisation dielectric layer is selectively removed and an anode contact metallisation is formed between the anode of each LED sub-pixel and the planarisation dielectric surface. In some embodiments, after forming the planarisation dielectric layer, a fourth portion of the planarisation dielectric layer is selectively removed and a common cathode contact metallisation is formed for each monolithic LED pixel between the common semiconductor layer and the planarisation dielectric surface.

[0032] In some embodiments, the formation of the common cathode contact metallisation overlaps a portion of the surface of the planarisation dielectric surface with the formation of at least one LED sub-pixel of each monolithic LED pixel. Thus, each LED sub-pixel of a monolithic LED pixel can be provided with electrical contact in a space saving manner.

[0033] In some embodiments, one of the LED sub-pixels of each monolithic LED pixel has a larger surface area on the common semiconductor layer than the other LED sub-pixel of each monolithic LED pixel.

[0034] In some embodiments, the pixel-defining trenches can have a width (in a direction between adjacent monolithic LED pixels) of at least 500 nm on the surface of the sacrificial substrate. Thus, the pixel-defining trenches can separate each monolithic LED pixel on the sacrificial substrate from an adjacent monolithic LED pixel. Thus, the pixel-defining trenches can surround (i.e., enclose) a perimeter of each monolithic LED pixel on the sacrificial substrate.

[0035] In some embodiments, the sacrificial dielectric layer can include one or more of silicon dioxide or silicon nitride. The sacrificial dielectric layer can be formed as a substantially continuous gap-fill layer. Thus, the sacrificial dielectric layer can be disposed to fill any gaps or voids to provide a bonding surface. Thus, the bonding surface formed can be a substantially continuous planar surface aligned with the surface of the common semiconductor layer. In some embodiments, the bonding surface is parallel to the surface of the common semiconductor layer. In some embodiments, the sacrificial dielectric layer is formed such that it has a thickness of at least 500 nm on the planarized surface. It can be appreciated that the thickness of the sacrificial dielectric layer in other regions can be thicker (or thinner) due to the uneven nature of the intermediate structure. In some embodiments, the sacrificial dielectric layer is formed such that it has a thickness of no more than 2 pm on the planarized surface.

[0036] In some embodiments, each monolithic LED pixel includes at least three or at least four LED sub-pixels of a monolithically formed LED array on the common semiconductor layer. For example, in one embodiment, each monolithic LED pixel can include four LED sub-pixels of a square stacked array.

[0037] In some embodiments, the handling substrate can be bonded to the bonding surface of the sacrificial dielectric layer by direct bonding (i.e., fusion bonding). For example, the handling substrate can include a sacrificial handling dielectric layer that is in contact with the bonding surface to form the bond. For example, in some embodiments, the handling dielectric layer can include Si02or SiN x .

[0038] In some embodiments, the handling substrate is a test substrate. The test substrate can be configured to form an electrical connection to each LED sub-pixel such that each LED sub-pixel can be tested in parallel. For example, in some embodiments, the test substrate can include an electronic substrate including electronic test circuitry configured to provide electrical power to each monolithic electronic device of a monolithic electronic device array.

[0039] After the bonding process, the test substrate can be configured to test each LED sub-pixel by providing electrical power from the test substrate to the LED sub-pixel array to test each LED sub-pixel. Thus, each LED sub-pixel can be tested in parallel using a test process integrated into the method of forming the monolithic LED pixel.

[0040] In some embodiments, the handling substrate can be a reusable handling substrate (or a reusable test substrate). Thus, after removal of the sacrificial dielectric layer, the handling substrate can be used again in another method according to the first aspect. The handling substrate comprises a handling dielectric layer, which can be a sacrificial handling dielectric layer. Thus, the step of removing the sacrificial dielectric layer can also be a step of removing the sacrificial handling dielectric layer. Thus, by forming a new sacrificial handling dielectric layer on the handling substrate, the handling substrate can be further processed to make it reusable.

[0041] In some embodiments, forming light extraction features for each monolithic LED pixel comprises selectively removing a second portion of the sacrificial substrate aligned with each LED sub-pixel to form a container volume for each LED sub-pixel; providing a first color conversion layer in at least one container volume of each monolithic LED pixel. The first color conversion layer is configured to absorb light of a first wavelength and emit converted light of a first converted light wavelength that is longer than the first wavelength. In some embodiments, the first converted light wavelength is at least 500 nm. Thus, the monolithic LED pixel can comprise LED sub-pixels that emit light having the first wavelength and LED sub-pixels that emit light having the first converted light wavelength. In some embodiments, the first converted light wavelength can be no more than 650 nm. Thus, the monolithic pixel can be configured to provide visible light having a color selected from a red, green, or blue LED.

[0042] In some embodiments, a second color conversion layer is provided in at least one other container volume of the container volumes of each monolithic LED pixel, the second color conversion layer being configured to absorb light of the first wavelength and emit converted light of a second converted light wavelength that is longer than the first converted light wavelength. Thus, the monolithic LED pixel according to the first aspect can be configured to emit light comprising three different wavelengths (the first wavelength, the first converted light wavelength, the second converted light wavelength).

[0043] In some embodiments, the first color conversion layer and / or the second color conversion layer comprises a phosphor, an organic molecule, or a quantum dot. Thus, the first and / or second color conversion layer can be provided to convert light of the first wavelength, such that the monolithic pixel can emit light having a combination of different wavelengths.

[0044] In some embodiments, forming light extraction features for each monolithic LED pixel comprises selectively removing a second portion of the sacrificial substrate through a thickness of the sacrificial substrate such that a first portion of a surface of the common semiconductor layer is exposed. Thus, the sacrificial substrate can be selectively removed to form a light emitting side of the monolithic LED pixel.

[0045] In some embodiments, forming light extraction features for each monolithic LED pixel includes patterning a first portion of a surface of a common semiconductor layer with scattering features configured to increase light extraction efficiency of each LED sub-pixel. Thus, the common semiconductor layer can be further processed to improve the efficiency of the LED sub-pixels.

[0046] In some embodiments, each monolithic LED pixel formed can be a monolithic micro-LED pixel. Thus, each LED sub-pixel can be a micro-LED sub-pixel having dimensions no greater than 100 μm x 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than 100 μm x 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than 50 μm x 50 μm, 30 μm x 30 μm, 20 μm x 20 μm, or 10 μm x 10 μm.

[0047] According to a second embodiment of the present disclosure, a monolithic light emitting diode (LED) pixel for an LED display is provided. The monolithic LED pixel includes: a common semiconductor layer, a sacrificial substrate, an array of LED sub-pixels, a planarizing dielectric layer, and light extraction features. The common semiconductor layer includes a group III nitride disposed on the sacrificial substrate. The array of LED sub-pixels is disposed on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite to the sacrificial substrate. Each LED sub-pixel of the array of LED sub-pixels includes a stack of group III nitride layers. The planarizing dielectric layer is disposed on the array of LED sub-pixels to provide a planarized dielectric surface that is roughly aligned with the surface of the common semiconductor layer. The planarizing dielectric layer, the common semiconductor layer, and the sacrificial substrate define etched sidewalls that surround the light emitting surface of the monolithic LED pixel. The light extraction features include a first opening that is disposed through the thickness of the sacrificial substrate aligned with each LED sub-pixel.

[0048] Thus, a monolithic LED pixel according to the second aspect of the present disclosure may be formed by a method according to the first aspect.

[0049] In some embodiments, the light extraction features further include: a first opening forming a container volume for each LED subpixel; and a first color conversion layer disposed in at least one of the container volumes. The first color conversion layer is configured to absorb light of a first wavelength and emit converted light having a first converted light wavelength that is longer than the first wavelength. In some embodiments, the first converted light wavelength is at least 500 nm and / or no greater than 650 nm.

[0050] In some embodiments, a second color conversion layer is disposed in at least one other container volume of the monolithic LED pixel. In some embodiments, the second color conversion layer is configured to absorb light of the first wavelength and emit converted light of a second converted light wavelength that is longer than the first converted light wavelength. In some embodiments, the second converted light wavelength is at least 550 nm and / or no more than 680 nm.

[0051] In some embodiments, the first color conversion layer and / or the second color conversion layer comprises a phosphor, an organic molecule, or a quantum dot.

[0052] In some embodiments, each LED sub-pixel is configured to generate light having a first wavelength that is at least 380 nm and / or no more than 490 nm.

[0053] In some embodiments, the light extraction features for each monolithic LED pixel further comprise light scattering features formed on the first portion of the common semiconductor layer surface that is aligned with each first opening of the sacrificial substrate, the light scattering features configured to increase light extraction efficiency of each LED sub-pixel.

[0054] In some embodiments, the planarization dielectric layer comprises a second opening in which an anode contact metallization is disposed between the anode of each LED sub-pixel and the planarization dielectric surface. In some embodiments, the planarization dielectric layer comprises a third opening in which a common cathode contact metallization is disposed between the common semiconductor layer and the planarization dielectric surface.

[0055] In some embodiments, a surface of the common cathode contact metallization that forms a portion of the planarization dielectric surface overlaps at least one of the LED sub-pixels forming the monolithic LED pixel.

[0056] In some embodiments, one LED sub-pixel of the monolithic LED pixel has a greater surface area on the common semiconductor layer than another LED sub-pixel of the monolithic LED pixel.

[0057] In some embodiments, a surface area of each LED sub-pixel on the common semiconductor layer can define an area that is no more than 100 pm x 100 pm. Thus, in some embodiments, the monolithic LED pixel can be a monolithic micro-LED pixel. For example, in some embodiments, the monolithic micro-LED pixel can define a light emitting surface that is no more than 100 pm x 100 pm. BRIEF DESCRIPTION OF DRAWINGS

[0058] The present disclosure will now be described with reference to the following non-limiting drawings. Further advantages of the disclosure are apparent from the detailed description in conjunction with the drawings, which are not drawn to scale in order to more clearly show the details, in which like reference characters refer to like elements throughout the several views, and in which:

[0059] Figure 1 shows an isometric view of the light emitting side of a monolithic LED pixel according to an embodiment of the present disclosure;

[0060] Figure 2 shows a plan view of the contact side of a monolithic LED pixel according to Figure 1

[0061] Figure 3 shows a first intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0062] Figure 4 shows a second intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0063] Figure 5 shows a third intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0064] Figure 6 shows a fourth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0065] Figure 7 shows a fifth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0066] Figure 8 shows a sixth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0067] Figure 9 shows a seventh intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0068] Figure 10 shows an eighth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0069] Figure 11 shows a ninth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0070] Figure 12 shows a tenth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the present disclosure;

[0071] Figure 13 ​A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0072] Figure 14 A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0073] Figure 15 A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0074] Figure 16 A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0075] Figure 17 A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0076] Figure 18 A twelfth intermediate step in a method of forming a monolithic LED pixel according to an embodiment of the disclosure is shown;

[0077] Figure 19 A monolithic LED pixel according to an embodiment of the disclosure is shown;

[0078] Figure 20 An intermediate step corresponding to the intermediate step of Figure 4 is shown in cross-section along line B-B’;

[0079] Figure 21 An intermediate step corresponding to the intermediate step of Figure 5 is shown in cross-section along line B-B’;

[0080] Figure 22 An intermediate step corresponding to the intermediate step of Figure 7 is shown in cross-section along line B-B’;

[0081] Figure 23 An intermediate step corresponding to the intermediate step of Figure 9 is shown in cross-section along line B-B’;

[0082] Figure 24 An intermediate step corresponding to the intermediate step of Figure 10 is shown in cross-section along line B-B’;

[0083] Figure 25 An intermediate step corresponding to the intermediate step of Figure 10 is shown in cross-section along line B-B’, further comprising a sacrificial dielectric layer;

[0084] Figure 26 An intermediate step corresponding to the intermediate step of Figure 11a cross-section of the intermediate step along line B-B’ corresponding to the intermediate step of

[0085] Figure 27 shows a cross-section of the single LED pixel along line B-B’ corresponding to the processing the substrate step. Figure 13

[0086] Figure 28 shows a cross-section of the single LED pixel along line B-B’ corresponding to the processing the substrate step. Figure 14

[0087] Figure 29 shows a cross-section of the single LED pixel along line B-B’ corresponding to the processing the substrate step. Figure 17

[0088] Figure 30 shows a cross-section of the single LED pixel along line B-B’. DETAILED DESCRIPTION

[0089] According to a first embodiment of the present disclosure, a monolithic LED pixel 1 is provided. The monolithic LED pixel 1 can comprise a plurality of LED sub-pixels 10, 20, 30. Figure 1 A perspective view of the monolithic LED pixel of the first embodiment is shown in Figure 1 The monolithic LED pixel comprises three LED sub-pixels 10, 20 and 30. The three LED sub-pixels 10 and 20, 30 are each configured to emit light of a different (peak) wavelength.

[0090] Figure 2 A plan view of the monolithic LED pixel 1 is shown. The method of forming the monolithic LED pixel 1 will then be described with reference to Figures 3 to 19 and Figures 20 to 30 Figures 3 to 19 A cross-section of the monolithic LED pixel along line A-A’ shown in Figure 2 is shown during an intermediate step in the method of forming the monolithic LED pixel 1. Figures 20 to 30 A cross-section of the monolithic LED pixel along line B-B’ shown in Figure 2 is shown during an intermediate step in the method of forming the monolithic LED pixel 1.

[0091] The method of forming the monolithic LED pixel 1 according to the first embodiment comprises forming an intermediate array 100 of LED sub-pixels. The intermediate array 100 of LED sub-pixels comprises a plurality of LED sub-pixels 103 formed on a sacrificial substrate 101.

[0092] ​​​​To form the intermediate array 100 of LED sub-pixels, a common semiconductor layer 102 comprising a III-nitride is formed on the first major surface 131 of the sacrificial substrate 101. Thus, the method of forming monolithic LED pixels 1 comprises forming a common semiconductor 102 layer comprising a III-nitride compound on the sacrificial substrate 101.

[0093] The sacrificial substrate 101 can comprise a silicon substrate, a silicon carbide substrate or a sapphire substrate. In Figure 3 embodiments, the sacrificial substrate 101 comprises a silicon substrate on which a plurality of III-nitride buffer layers are formed.

[0094] As shown in Figure 3 , the common semiconductor layer 102 can be formed on the surface of the sacrificial substrate 101 as a substantially continuous film. Thus, the common semiconductor layer 102 substantially covers all of the surface of the sacrificial substrate 101. The common semiconductor layer 102 can comprise an n-type doped III-nitride semiconductor. For example, in Figure 3 embodiments, the common semiconductor layer 102 comprises GaN. Figure 3 The common semiconductor layer 102 in may be n-type doped with any suitable n-type dopant, such as Si or Ge. The common semiconductor layer 102 can be formed on the sacrificial substrate 101 by any suitable method for forming III-nitrides, such as metal-organochemical vapour deposition (MOCVD) or molecular beam epitaxy (MBE).

[0095] Next, an array of LED sub-pixels can be formed on the surface 132 of the common semiconductor layer 102. The array of LED sub-pixels is formed on the side of the common semiconductor layer 102 opposite the sacrificial substrate 101. Each LED sub-pixel 103 comprises a stack of III-nitride layers. Various methods for forming an array of LED sub-pixels are known to the skilled person.

[0096] In Figure 3 embodiments, the array of LED sub-pixels is formed from a continuous stack 140 of III-nitride layers. The as-deposited continuous stack 140 of III-nitride layers substantially covers all of the second major surface 132 of the common semiconductor layer 102. Subsequently, the continuous stack 140 of III-nitride layers can be patterned using a selective removal process to define the array of LED sub-pixels 103. One possible selective removal process comprises coating the continuous stack 140 of III-nitride layers with a mask layer using a photolithography process, and etching regions of the continuous stack 140 of III-nitride layers to be selectively removed. In the present disclosure,Figure 4 An example of a resulting array of LED sub-pixels 103 is shown in .

[0097] In some embodiments, for example, Figure 3 As shown, the continuous stack 140 of group III nitride layers may include a superlattice 155 of group III nitride layers, an active layer 156 configured to generate light, an electron blocking layer 157, and one or more p-type semiconductor layers 158. The active layer may include one or more quantum well layers configured to generate light. Figure 3 In an embodiment, the active layer of each LED sub-pixel is configured to generate light having a wavelength of at least 380 nm and no greater than 490 nm.

[0098] Thus, each LED sub-pixel 103 formed from a continuous stack 140 of Group III-nitride layers may include a superlattice 155 of Group III-nitride layers, an active layer 156 configured to generate light, an electron blocking layer 157, and one or more p-type semiconductor layers 158. The formation of each layer of an LED sub-pixel is known to the skilled person, for example, as further discussed in at least GB 1811109.6.

[0099] Although Figure 3 and Figure 4 The embodiments described herein use a selective removal process to define an array of LED sub-pixels, but it should be understood that the methods of the present disclosure are not limited to such LED sub-pixels. For example, a selective area growth method can be used to define an array of LED sub-pixels comprising a stack of Group III nitride layers. Further details of suitable selective area growth methods can be found in at least GB1811109.6.

[0100] like Figure 4 As shown, each LED sub-pixel 103 forms a mesa structure extending from the common semiconductor layer 102. Each LED sub-pixel 103 is spaced apart from other LED sub-pixels 103 on the common semiconductor layer 102. Figure 4 As shown in , the spacing between each LED sub-pixel 103 can be different. Figure 4 In the embodiment, the spacing between adjacent LED sub-pixels 103 forming the sub-pixels of the same monolithic LED pixel 1 may be smaller than the spacing between adjacent LED sub-pixels of different monolithic LED pixels.

[0101] After forming the plurality of LED sub-pixels 103, the intermediate array 100 can be further processed to include electrical contacts to each LED sub-pixel 103. It will be appreciated that the skilled person is aware of various methods for forming electrical contacts to semiconductor devices. Accordingly, the electrical contacts can be formed at different stages during the method of forming a monolithic LED pixel. Accordingly, the present disclosure relating to monolithically forming a monolithic LED pixel comprising a plurality of LED sub-pixels is not limited to any particular arrangement of electrical contacts or method of forming the electrical contacts.

[0102] As shown in Figure 5 , a plurality of first electrical contacts 106 can be formed on the common semiconductor layer 102. The first contact layer 106 is configured to provide electrical contact to the common semiconductor layer 102. In some embodiments, a single first contact layer (i.e. a common contact) can be provided for each monolithic LED pixel 1, or in some embodiments, a first contact layer 106 can be provided for each LED sub-pixel 103. As shown in Figure 5 , a first contact layer 106 is provided for each LED sub-pixel 103. The first contact layer 106 can comprise any suitable material for forming an ohmic contact to the common semiconductor layer 102. For example, the first contact layer 106 can comprise one or more of titanium, aluminium, titanium nitride, gold or copper. In Figure 5 embodiments, the first contact layer 106 can be deposited using thermal evaporation and patterned using photolithography such that the first contact layer 106 is disposed in the spaces between the LED sub-pixels 103 on the common semiconductor layer 102. In Figure 5 embodiments, the first contact layer 106 can be annealed after it is formed to improve the conductivity of the contact between the first contact layer 106 and the common semiconductor layer 102.

[0103] Next, a first passivation layer 107 can be formed over the plurality of LED sub-pixels 103. The first passivation layer 107 can comprise an insulating layer, for example a dielectric. For example, in Figure 5 embodiments, the first passivation layer 107 can comprise silicon dioxide or silicon nitride. The first passivation layer 107 can be formed using a plasma enhanced chemical vapour deposition process, a chemical vapour deposition process, a physical vapour deposition process, evaporation or atomic layer deposition.

[0104] After forming the first passivation layer 107, a plurality of openings can be formed through the first passivation layer 107 using a selective removal process such as photolithography and etching. The plurality of openings can be provided to provide an area for forming electrical connections to the common semiconductor layer 102 and the p-type semiconductor layer of the LED sub-pixels 103. For example, in Figure 5In an embodiment, a plurality of first openings 141 are provided in the first passivation layer 107 to allow formation of a cathode contact layer 109 in contact with the first contact layer 106 (i.e., and electrically connected to the common semiconductor layer 102), and a plurality of second openings 142 are formed to allow formation of an anode contact layer 108 in electrical contact with the p-type semiconductor layer of the LED sub-pixel 103.

[0105] The anode contact layer 108 can be formed in the second opening 142 on the p-type semiconductor layer of the LED sub-pixel 103. The anode contact layer 108 can be configured to form an ohmic contact with the p-type semiconducting layer of the LED sub-pixel 103. For example, in some embodiments, the anode contact layer can include one or more of nickel, silver, titanium, or titanium nitride. The second contact layer 108 can be formed using an evaporation technique and patterned using a photolithography method. Thus, the anode contact layer 108 can be arranged to align with the plurality of second openings 142 in the passivation layer, which are aligned with each p-type semiconductor layer of each LED sub-pixel 103.

[0106] In some embodiments, the common semiconductor layer 102 of each monolithic LED pixel 1 can be further processed to provide cross-talk reduction features. Figure 1 In the embodiment of the present invention, the common semiconductor layer 102 is subjected to a selective removal process to remove a portion of the common semiconductor layer 102 in a region between each LED sub-pixel in each monolithic LED pixel 1. Thus, the portion of the common semiconductor layer 102 between two adjacent LED sub-pixels 103 in the monolithic LED pixel 1 (i.e., the portion not covered by the adjacent LED sub-pixels 103) can be selectively removed. Figure 6 An example of such a crosstalk reduction feature is shown in FIG, where the crosstalk reduction trench 111 is formed by a selective removal process. Figure 6 As shown, a selective removal process (i.e., an etching process) is used to etch crosstalk reduction trenches 111 from the second surface 132 of the common semiconductor layer 102 toward the first surface 131 of the sacrificial substrate 101. The crosstalk reduction trenches 111 are disposed in regions between adjacent LED sub-pixels 103 that form portions of the monolithic LED pixel 1. Effectively, the crosstalk reduction trenches 111 serve to separate regions of the common semiconductor layer 102 corresponding to each sub-pixel 103. This, in turn, can prevent or reduce light from one LED sub-pixel 103 from traveling across the common semiconductor layer 102 and being emitted through the light extraction features of another LED sub-pixel 103.

[0107] The cross-talk reduction trenches 111 can be formed using any suitable lithography and etching techniques known to the skilled person, for example Reactive Ion Etching (RIE) or Inductively Coupled Plasma Etching (ICP).

[0108] After the optional cross-talk reduction features have been formed, a planarization dielectric layer is formed over the intermediate array of LED sub-pixels 100. The planarization dielectric layer can be formed in one or more process steps due to the topology of the intermediate array of LED sub-pixels (e.g. cross-talk reduction features, LED sub-pixels 130) and the process of forming electrical contacts. Figure 7 、 8 And 9 provide one example of a method of forming a planarization dielectric layer according to the first embodiment. The skilled person will appreciate that other methods of forming a planarization dielectric layer are known to the skilled person.

[0109] According to the first embodiment, the planarization dielectric layer can be formed over the intermediate array of LED pixels as shown in Figure 6 A second passivation layer 112 can be formed over the intermediate array of LED pixels as shown in Figure 1 1. The second passivation layer 112 can comprise an insulating dielectric, for example silicon dioxide or silicon nitride. The second passivation layer 112 can be formed in a similar manner to the first passivation layer 107. The second passivation layer 112 can be formed over the intermediate structure to provide a first planarization surface 215 that is approximately aligned with the first surface 131 of the sacrificial substrate 101 on which the monolithic LED pixel 1 is formed. The second passivation layer 112 can be formed in such a way as to fill the cross-talk reduction trenches 111 and also extend beyond the exposed surfaces of the LED sub-pixels 103.

[0110] After the second passivation layer 112 has been formed, a plurality of third openings 143 can be formed in the second passivation layer 112 to form first contact metallisations 114 to form electrical contacts to the anode and / or cathode contact layers 108, 109. The plurality of third openings can extend from the passivation surface 215 to the first and / or second contact layers 106, 108. Figure 8 An example of such first contact metallisations is shown in Figure 12, in which a first contact metallisation 114 is formed for each second contact layer 108.

[0111] As part of forming the planarization dielectric layer according to the first embodiment, a third passivation layer 115 is formed on the passivation surface 215, for example as shown in Figure 9 The third passivation layer 115 can be formed in a similar manner to the second passivation layer 112. The third passivation layer 115 provides a third passivation layer surface 217 on a side of the third passivation layer 115 opposite the second passivation layer 112.

[0112] Similar to the second passivation layer 112, the third passivation layer 115 may further include a plurality of fourth openings 144 aligned with each LED sub-pixel for providing contact metallization. The fourth openings 144 may then be filled with a second contact metallization 117 to form an electrical contact with the p-type semiconductor layer of each LED sub-pixel 103. Each second contact metallization 117 may include multiple stacks of conductive layers. For example, the second contact metallization 117 may include one or more of titanium, tungsten, gold, and copper.

[0113] After forming the third passivation layer 115 and the various contact metallizations, a polishing process such as chemical mechanical polishing can be used to further planarize the third passivation layer surface 217. Providing a CMP process can reduce the surface roughness of the third passivation layer surface 217 to improve the bonding of the intermediate array of LED sub-pixels 100 to the handle substrate 200. Thus, a chemical mechanical polishing process can be provided to improve the smoothness of the surface and reduce any defects or irregularities in the surface that may have formed due to the etching and contact metallization deposition processes.

[0114] Therefore, the Figure 7 , 8 and 9 provide a method for forming a planarized dielectric layer on an array of LED sub-pixels to provide a planarized dielectric surface (i.e., the third passivation layer surface 217) that is substantially aligned with the second surface 132 of the common semiconductor layer 102. Although the method according to the first embodiment of the present disclosure also includes forming an electrical contact for each LED sub-pixel 103, it should be understood that the formation of the electrical contact can be provided in various other ways known to those skilled in the art. For example, the formation of the electrical contact can be provided after the planarized dielectric layer is formed on the intermediate array 100 of LED sub-pixels.

[0115] After forming the planarized dielectric surface 217 over the plurality of LED sub-pixels 103, the intermediate array of LED sub-pixels 100 is partially divided into a plurality of monolithic LED pixels 1 by etching a grid of pixel-defining trenches 118. The pixel-defining trenches 118 are formed by selectively removing layers forming the planarized dielectric layer from the planarized dielectric surface 217 toward the sacrificial substrate 101. An example of forming the pixel-defining trenches 118 is described in detail in the present disclosure. Figure 10 As shown in Figure 10As shown, each monolithic LED pixel 1 includes at least two LED sub-pixels 103. The pixel-defining trenches 118 can be formed in a similar manner as the crosstalk-reducing trenches 111 described above. After the pixel-defining trenches 118 are formed, it will be appreciated that the plurality of monolithic LED pixels 1 remain in a fixed arrangement due to the presence of the sacrificial substrate 101. As such, the plurality of monolithic pixels 1 can still be processed and aligned as part of the intermediate array 100 of LED sub-pixels due to the presence of the sacrificial substrate 101.

[0116] After the pixel-defining trenches 118 are formed, a sacrificial dielectric layer 121 is formed over the pixel trenches and the planarized dielectric surface 217 to form a bonding surface 221 that is generally aligned with the surface of the common semiconductor layer 102.

[0117] In the method according to the first embodiment, an etch stop layer 119 can also be provided prior to forming the sacrificial dielectric layer 121. For example, as shown in FIG. 4A, the etch stop layer 119 is formed as a substantially continuous layer over the pixel-defining trenches 118 and the planarized dielectric surface 217. The etch stop layer 119 can have a plurality of fifth openings 145 formed therethrough. Each fifth opening 145 of the etch stop layer 119 can be aligned with any contact metallization 117 present at the planarized dielectric surface 217. In some embodiments, the etch stop layer 119 can include silicon dioxide or silicon nitride. The etch stop layer 119 can be configured to provide a dielectric layer that is resistant to a subsequent etching process in which the sacrificial dielectric layer 121 is to be removed. Thus, the etch stop layer 119 can increase process tolerance of the selective removal step in which the sacrificial dielectric layer 121 is to be subsequently removed. Figure 11

[0118] After the (optional) etch stop layer 119 is formed, a sacrificial dielectric layer 121 can be formed over the pixel-defining trenches 118 and the planarized surface to form a bonding surface. The formation of the sacrificial dielectric layer 121 can include a multi-stage process in which multiple layers are formed. The sacrificial dielectric layer 121 can include one or more of silicon dioxide and silicon nitride. As shown in FIG. 4B, the sacrificial dielectric layer 121 is formed as a substantially continuous layer over the pixel-defining trenches 118 and the planarized dielectric surface 217. The sacrificial dielectric layer 121 can have a plurality of sixth openings 146 formed therethrough. Each sixth opening 146 can extend from the bonding surface through a thickness of the sacrificial dielectric layer to an underlying layer (e.g., the contact metallization 117). The plurality of sixth openings 146 in the sacrificial dielectric layer 121 can be aligned with at least a portion of each contact metallization 117. Figure 11

[0119] ​​After forming the sacrificial dielectric layer 121, a chemical mechanical polishing process can be used to further planarize the bonding surface 221. Accordingly, the sacrificial dielectric layer 121 can provide a substantially flat surface aligned with the second surface 132 of the common semiconductor layer 102 for bonding the plurality of monolithic LED pixels 1 on the sacrificial substrate 101 to the handling substrate 200.

[0120] Figure 12 An example of a handle substrate 200 is shown in . The handle substrate 200 provides a surface to which the bonding surface 221 of the sacrificial dielectric layer 121 can be bonded.

[0121] According to a first embodiment of the present disclosure, a processing substrate 200 provides a processing substrate surface 210 to be connected to the processing substrate surface 210. Figure 11 The bonding surfaces 221 of the intermediate array 100 of LED sub-pixels are shown in contact.

[0122] In some embodiments, for example, Figure 12 As shown, the processing substrate 200 includes a first electronic wafer 201. In some embodiments, the first electronic wafer 201 may include a silicon wafer or any other substrate suitable for forming an electronic circuit. In some embodiments, for example Figure 12 In the illustrated embodiment, a plurality of electronic layers 202, 203, 204, 205 may be provided on the surface of a first electronic wafer 201. The plurality of electronic layers may include metal layers 202, 204 and insulating layers 203, 205 to form electrical connections and / or circuits on the first electronic substrate 201. Thus, in some embodiments, the processing substrate 200 may be a test substrate. The test substrate may be configured to provide testing of the circuitry of the monolithic LED pixel 1. The test substrate will be discussed in more detail below. The electronic layers 202, 203, 204, 205 may be deposited on the first electronic substrate 201 using any suitable technique, such as CVD, PECVD, thermal evaporation, PVD, or ALD.

[0123] In some embodiments, the handle substrate 200 can include a sacrificial handle dielectric layer 206. The sacrificial handle dielectric layer 206 can provide a handle substrate surface 210 of the handle substrate 200 for bonding. The sacrificial handle dielectric layer 206 can be configured to be at least partially removed along with the sacrificial dielectric layer 121 to separate the monolithic LED pixel 1 from the handle substrate 200.

[0124] In some embodiments, for example, Figure 12As shown, the process substrate 200 can also include a process etch stop layer 207. The process etch stop layer 207 can be disposed between the sacrificial process dielectric layer 206 and other layers 201, 202, 203, 204 of the process substrate 200. The process etch stop layer 207 can be configured to provide a surface that is more resistant to a selective removal process used to selectively remove the sacrificial process dielectric layer. Thus, the process etch stop layer 207 provides a layer configured to protect other layers of the process substrate 200 from the selective removal process. Accordingly, the process etch stop layer 207 can improve the reusability of the process substrate 200.

[0125] The sacrificial process dielectric layer 206 and the process etch stop layer 207 can be formed as a stack of dielectric layers including at least one or more of silicon dioxide and silicon nitride. The sacrificial process layer 206 can be formed to have a thickness of at least 50 nm in a direction normal to a surface of the first electronic substrate 201. In some embodiments, the thickness of the sacrificial process dielectric layer 206 can be no greater than 1 pm. The process etch stop layer 207 can have a thickness of at least 20 nm in a direction normal to a surface of the first electronic substrate 201. In some embodiments, the thickness of the process etch stop layer 207 can be no greater than 100 nm.

[0126] In some embodiments of the present disclosure, the process substrate 200 can provide a substrate on which the plurality of monolithic LED pixels 1 are held while the light emitting surface 130 of the sacrificial substrate 101 is further processed.

[0127] In some embodiments, such as the embodiments described in Figure 13 In some embodiments, such as the embodiments described in

[0128] After the bonding procedure, the test substrate can be configured to test each LED pixel 103 by providing power from the test substrate to the array of LED sub-pixels to test each LED sub-pixel. Thus, the test substrate can form an electrical circuit between the test substrate electrical contacts and the contact metallization of the intermediate array of LED sub-pixels. Thus, each LED sub-pixel can be tested in parallel using a testing procedure integrated into the method of forming monolithic LED pixels.

[0129] In such embodiments, an electrical connection can be formed between the handling substrate 200 and each monolithic LED pixel 1. Various methods of forming an electrical connection between two substrates to be formed in contact with one another are known to the skilled person. One example of such a method according to the first embodiment is shown in Figure 13 and Figure 14 .

[0130] As shown in Figure 13 , a plurality of seventh openings 212 can be formed in the handling substrate surface 210 of the handling substrate 200. Each seventh opening extends from the handling substrate surface 210 through one or more of the electronic layers 205, 203 of the handling substrate 200. The plurality of seventh openings 212 can each be aligned with one of the metal contacts of each LED sub-pixel 103. That is, the arrangement of openings 212 on the handling substrate 200 corresponds to the arrangement of sixth openings 146 provided on the intermediate array 100 of LED sub-pixels.

[0131] In some embodiments, for example as shown in Figure 13 , a plurality of electrically conductive contact portions 208 can be formed within the seventh openings 212 of the handling substrate 200. Each electrically conductive contact portion 208 can extend from the electronic layers 203, 205 beyond the handling surface 210 in a direction perpendicular to the handling substrate 200. Thus, the electrically conductive contact portions 208 can protrude from the handling surface 210. The electrically conductive contact portions 208 can be configured to extend from the handling surface 210 in such a way that, when the handling surface 210 is in contact with the bonding surface 121, the electrically conductive contact portions 212 form an electrical connection between the various contact metallization of the intermediate array 100 of LED sub-pixels and the second contacts of the handling substrate 200. In some embodiments, the electrically conductive contact portions 208 can comprise a metal contact, for example one or more of titanium, gold, copper or tin.

[0132] According to the method of forming the first embodiment of the present disclosure, the handling substrate 200 can be bonded to the bonding surface 221 of the sacrificial dielectric layer 121. Figure 14An example of processing a substrate 200 to the intermediate array 100 of LED sub-pixels is shown. The processing substrate 200 can be bonded to the bonding surface 221 using an alignment bonder (not shown). The alignment bonder enables the bonding surface 221 to be arranged parallel to the processing surface 210, and also enables the conductive contact portions 212 (if present) of the processing substrate 200 to be aligned with the sixth openings 146 of the sacrificial dielectric layer 121. The alignment bonder is then configured to enable the two surfaces to be brought into contact, such that the sacrificial dielectric layer 121 forms a bond with the processing substrate surface 210 of the processing substrate 200. In some embodiments, the alignment bonder can apply one or more of heat and pressure to improve the bond formed between the processing substrate surface 210 and the bonding surface 221.

[0133] For example, in some embodiments, the alignment bonder can apply a compressive force of at least 10 kN to bond the processing substrate 200 to the intermediate array 100 of LED sub-pixels. In some embodiments, the alignment bonder can apply a compressive force of at least 20 kN, 30 kN or 40 kN. By applying a greater compressive force, the reliability of the bond formed between the substrates can be improved. In some embodiments, the press can apply a compressive force of no more than 45 kN to reduce the risk of the substrates breaking or other undesirable deformation of the substrates during bonding.

[0134] In some embodiments, the alignment bonder can also be configured to heat the processing substrate 200 and / or the intermediate array 100 of LED sub-pixels. For example, the alignment bonder can be configured to heat the processing substrate 200 and / or the intermediate array 100 of LED sub-pixels to a temperature of at least 100 °C. In some embodiments, the alignment bonder can be configured to heat the processing substrate 200 and / or the intermediate array 100 of LED sub-pixels to a temperature of at least 200 °C, 300 °C, 400 °C or 500 °C. The alignment bonder can be configured to maintain the temperature under compression, and optionally for a period of time at the temperature. In some embodiments, the period of time can be at least: 1 minute, 2 minutes, 5 minutes, 10 minutes or 1 hour. Thus, the press can be used to improve the formation of direct fusion bonds at the interface between the processing substrate 200 and the intermediate array 100 of LED sub-pixels.

[0135] Various methods of bonding two substrates together are known. For example, in Figure 14In the embodiment of the present invention, the sacrificial dielectric layer 121 forms a direct bond with the sacrificial handle dielectric layer 206. In other embodiments, different bonding techniques and bonding layers can be provided on one or both of the handle substrate 200 and / or the intermediate array of LED sub-pixels 100 to bond the handle substrate 200 to the bonding surface 221. The alignment bonder can also be configured to form an electrical connection between the conductive contact portion 212 and the first and second contacts of each LED sub-pixel 103.

[0136] In the first embodiment, as Figure 14 As shown, it will be appreciated that the sacrificial dielectric layer 121 and the sacrificial handle dielectric layer 206 can extend as substantially continuous layers across the sacrificial substrate 101 and the first electronics wafer 201, respectively. Thus, the sacrificial dielectric layer 121 and the sacrificial handle dielectric layer 206 form a direct bond over a substantial portion of the bonding surface of the intermediate array 100 of LED sub-pixels, thereby securely bonding the wafers together. Furthermore, a low-resistance contact bond can be formed between the electronic layers 203, 205 of the handle substrate 200 and each LED sub-pixel 30 via the conductive contact portions 208.

[0137] Once the intermediate array of LED sub-pixels 100 is bonded to the processing substrate 200, the light emitting side of each monolithic LED pixel 1 can be further processed to separate each monolithic LED pixel 1 and form light extraction features for each monolithic LED pixel 1.

[0138] Thus, the method of forming the first embodiment further includes selectively removing a first portion of the sacrificial substrate 101 aligned with the grid of pixel-defining trenches 118 through the thickness of the sacrificial substrate 101 to separate each monolithic LED pixel. Figure 15 As shown, a first portion of the sacrificial substrate 101 is removed to define a plurality of eighth openings 148 through the thickness of the sacrificial substrate 101 in a direction perpendicular to the light emitting surface 130. The eighth openings can be formed using any selective removal process known to those skilled in the art, for example, including photolithography and etching processes on the sacrificial substrate 101. The pixel-defining trenches and the first portion of the sacrificial substrate 101 surround each monolithic LED pixel 1. Therefore, by removing the first portion of the sacrificial substrate 101 aligned with the pixel-defining trenches 118, the sacrificial substrate 101 no longer connects each monolithic LED pixel 1 together. Instead, the bond formed between the sacrificial dielectric layer 121 and the handling substrate 200 serves to maintain the relative position of each monolithic LED pixel 1 on the handling substrate 200.

[0139] The method forming the first embodiment further includes forming a light extraction feature for each monolithic LED pixel 1. In some embodiments, the light extraction feature of each monolithic pixel 1 can increase the efficiency of light extracted from each monolithic LED pixel. In some embodiments, the light extraction feature can modulate the light emitted by each monolithic LED pixel 1. For example, the light extraction feature can provide a color conversion layer to one or more LED sub-pixels of the monolithic LED pixel 1, such that the monolithic LED pixel 1 can output light having at least two different (peak) wavelengths.

[0140] In some embodiments, such as shown in FIG. 1A, the second portion of the sacrificial substrate 101 is selectively removed to form a first light extraction feature 151 for each sub-pixel of the monolithic LED pixel 1 by aligning each LED sub-pixel 103 with the second portion of the sacrificial substrate 101. Figure 15

[0141] The second portion of the sacrificial substrate can be selectively removed through the thickness of the sacrificial substrate 101 in a direction normal to the light emitting surface 130. Thus, the second portion of the sacrificial substrate 101 is removed to define a plurality of ninth openings 149 through the thickness of the sacrificial substrate 101. By removing the second portion of the sacrificial substrate 101, the light emitting area of each LED sub-pixel 103 can be able to more efficiently output light via the light emitting surface 130.

[0142] Each second portion of the sacrificial substrate 101 to be selectively removed is aligned with each LED sub-pixel 103. Thus, a plurality of second portions of the sacrificial substrate 101 of each monolithic LED pixel 1 can be selectively removed to define a plurality of ninth openings 149 through the thickness of the sacrificial substrate 101. The number of second portions selectively removed corresponds to the number of LED sub-pixels 103 of each monolithic LED pixel 1. As shown in FIG. 1A, the area of the ninth openings 149 can be at least as large as the light emitting area of each LED sub-pixel. Thus, the light produced by each LED sub-pixel can be directed through the respective ninth opening 149 of each LED sub-pixel. Figure 15

[0143] As shown in FIG. 1A, the remaining portion of the sacrificial substrate 101 effectively separates each light emitting surface of each LED sub-pixel from other light emitting surfaces of other LED sub-pixels 103. Thus, in some embodiments, the remaining portion of the sacrificial substrate 101 can reduce or eliminate cross-talk between LED sub-pixels. Figure 15 In embodiments such as shown in FIG. 1A, the second portion of the sacrificial substrate 101 can be selectively removed to form a container volume 151 for each LED sub-pixel. Thus, the container volume can correspond to the light emitting area of each LED sub-pixel 103.

[0144] Figure 15 In embodiments such as shown in FIG. 1A, the second portion of the sacrificial substrate 101 can be selectively removed to form a container volume 151 for each LED sub-pixel. Thus, the container volume can correspond to the light emitting area of each LED sub-pixel 103. Figure 15 ​​​A plurality of ninth openings 149 can be formed in the sacrificial dielectric layer 101. Each of the ninth openings 149 can be formed by a laser drilling process. The container volumes 151 can be defined by the ninth openings 149 and the exposed first portion 170 of the surface of the common semiconductor layer 102. Each of the container volumes 151 can be configured to provide a volume in which a color conversion layer can be provided.

[0145] In some embodiments, a first color conversion layer 160 can be provided in at least one of the container volumes 151 of each monolithic LED pixel 1, as shown, for example, in FIG. 1. Figure 16 The first color conversion layer 160 can be configured to absorb light of a first wavelength and emit converted light of a first converted light wavelength that is longer than the first wavelength. Thus, the first color conversion layer 160 can be configured to convert light emitted by the LED sub-pixel into different, longer wavelength light, the first color conversion layer 160 being disposed over the LED sub-pixel.

[0146] In some embodiments, the first color conversion layer 160 can comprise phosphor, organic molecules, or a plurality of quantum dots. For LED sub-pixel arrays having container volumes with a surface area exceeding 1 mm 2 A larger particle size of phosphor can be advantageous for LED sub-pixels having container volumes with a surface area of less than 1 mm 2 For LED sub-pixels having container volumes with a surface area of less than 1 mm

[0147] In some embodiments, the first color conversion layer 160 can completely fill the container volume 151 of the LED sub-pixel. In other embodiments, the first color conversion layer 160 can partially fill the container volume of the LED sub-pixel. For example, as shown in FIG. 1, the first color conversion layer 160 substantially fills the entire volume of the first container volume. Figure 16

[0148] In some embodiments, the first color conversion layer can be configured to convert light having a first wavelength of about 380 nm to 490 nm into first converted light having a first converted light wavelength of at least 500 nm to 650 nm. That is, the first color conversion layer 160 can be configured to convert substantially blue visible light generated by the LED sub-pixel 103 into substantially green visible light for output by the LED sub-pixel.

[0149] ​In some embodiments, each monolithic LED pixel 1 can further comprise a second color conversion layer 161, e.g. as shown in Figure 16 . The second color conversion layer 161 can be provided in at least one of the other container volumes of each monolithic LED pixel 1. The second color conversion layer 161 can be configured to absorb light of the first wavelength and emit converted light of a second converted light wavelength that is longer than the first converted light wavelength. Thus, in addition to the first color conversion layer 160, a second color conversion layer 161 can be provided in order to provide the monolithic LED pixel 1 with a further light color. That is, the monolithic LED pixel 1 comprises LED sub-pixels without a color conversion layer, LED sub-pixels comprising the first color conversion layer 160, and LED sub-pixels comprising the second color conversion layer 161, the monolithic LED pixel 1 can output light comprising three different peak wavelengths. For example, in Figure 16 embodiments, the monolithic LED pixel 1 can be configured to output visible light comprising substantially red, green and blue components.

[0150] The second color conversion layer 161 can comprise a phosphor or a plurality of quantum dots. Thus, the second color conversion layer 161 can be formed in a similar way as the first color conversion layer 160. In some embodiments, the second color conversion layer can be configured to convert first light having a wavelength of at least 380 nm and at most 490 nm into second converted light having a second converted light wavelength of at least 550 nm and not more than 680 nm.

[0151] Returning to Figure 1 and Figure 2 , it should be understood that Figures 3 to 16 the cross-section shown in Figure 16 illustrates two of the three LED sub-pixels comprised within the monolithic LED pixel 1. Thus, it should be understood that the other LED sub-pixel (not shown in

[0152] In some embodiments, the container volume 151 comprises a light scattering medium (not shown) instead of a color conversion layer. For example, in the embodiment shown in Figure 1 , the B sub-pixel is configured to emit light having a first wavelength. Thus, the container volume 151 of the B sub-pixel does not comprise a color conversion layer 160, 161. In the embodiment shown in Figure 1 , the container volume 151 of the B pixel comprises a light scattering medium. The light scattering medium can be configured to scatter light such that the light output by the B pixel can have a Lambertian light distribution, or a full width half max (FWHM) of 120 degrees (or wider). Thus, the light scattering medium can be provided to improve the light extraction efficiency and the viewing angle of the light emitted from the B LED sub-pixel.

[0153] In some embodiments, a second portion of the sacrificial substrate 101 can be selectively removed through the thickness of the sacrificial substrate, such that a first portion 170 of the surface of the common semiconductor layer 102 is exposed. In some embodiments, for example, as shown in Figure 16 a third light extraction feature can be formed for each monolithic LED pixel 1. The third light extraction feature can be formed by patterning the first portion 170 of the surface of the common semiconductor layer 102 to form light scattering features 171 configured to improve the light extraction efficiency of each LED sub-pixel.

[0154] For example, in Figure 16 embodiments, the light scattering features 171 are formed by selectively removing regions of the first portion 170 of the common semiconductor layer 102 to form a textured surface. Providing a textured surface at the interface between the common semiconductor layer 102 and each container volume can help to reduce total internal reflection that occurs at the interface between the common semiconductor layer 102 and the container volume 151. Thus, the light scattering features 171 formed by patterning the first portion 170 of the surface of the common semiconductor layer 102 are configured to improve the light extraction efficiency of each LED sub-pixel. That is, the amount of light output by each LED sub-pixel can be increased by reducing the proportion of light that is reflected at the interface between the common semiconductor layer 102 and the container volume. Although the first portion 170 of the surface of the common semiconductor layer 102 is patterned using a selective removal process in Figure 16 embodiments, in other embodiments, an anti-reflective coating or other similar optical coating intended to improve the light extraction efficiency from a light emitting diode can be provided.

[0155] In some embodiments, for example, as shown in Figure 17 a pump light reflector laminate 180 can be provided over some LED sub-pixels of each monolithic LED pixel 1. The pump light reflector laminate can be provided over the container volume of an LED sub-pixel that includes a first color conversion layer and / or a second color conversion layer 160, 161. The pump light reflector laminate can be configured to absorb pump light of a first wavelength and transmit light having a wavelength of the first wavelength color conversion wavelength and / or the second wavelength color conversion wavelength. Effectively, the pump light reflector laminate is a band reject filter configured to have a narrow wavelength rejection band including wavelengths of the first wavelength and a passband including the first conversion light wavelength and / or the second conversion light wavelength.

[0156] One example of a suitable pump light reflector laminate can be a distributed Bragg reflector. Examples of suitable distributed Bragg reflectors can be found in US 11 / 508166. Of course, it should be understood that for LED sub-pixels that do not include a color conversion layer (i.e., LED sub-pixels that emit a first wavelength, a pump light reflector laminate can not be disposed over the LED sub-pixels). In Figure 17 embodiments, a pump light reflector laminate 180 is provided across the reservoir volume 151 including the first color conversion layer 160 and the second color conversion layer 161. For example, in Figure 17 embodiments, the pump light reflector laminate can include alternating layers of Ti02 (with a refractive index of about 2.6) and Si02 (with a refractive index of about 1.5). In other embodiments, a different pump light reflector laminate can be provided for each reservoir volume 151.

[0157] After the light extraction features are formed, the sacrificial dielectric layer 121 can be selectively removed to separate each monolithic LED pixel 1 from the handling substrate 200. For example, as shown in Figure 18 the sacrificial handling dielectric layer 206 has also been selectively removed. The etch stop layer 119 and the handling etch stop layer 207 provide surfaces over which the selective removal process can more reliably end to protect the monolithic LED pixels 1 and other layers of the handling substrate 200.

[0158] It should be understood that after the sacrificial dielectric layer 121 is removed, each monolithic LED pixel includes a light emitting surface 130 and a planarized dielectric surface 217. The light emitting surface 130 is separated from the planarized dielectric surface by sidewalls defined by the sidewall surfaces of the planarized dielectric layer, the common semiconductor layer, and the sacrificial substrate. These sidewall surfaces are formed as a result of the previous etching processes performed during the method of forming the monolithic LED pixels 1. Thus, the planarized dielectric layer, the common semiconductor layer, and the sacrificial substrate define etched sidewalls around the light emitting surface of each monolithic LED pixel 1.

[0159] As shown in Figure 18 after the sacrificial dielectric layer 121 is removed, the monolithic LED pixels 1 can still be connected to the handling substrate by the plurality of conductive contact portions 208. It should be understood that the connection between the conductive contact portions 208 and each monolithic LED sub-pixel 1 can be relatively weak. Thus, as shown in Figure 18As shown, the monolithic LED sub-pixels 1 can be individually peeled from the handling substrate, resulting in a break in the contact between the conductive contact portion 208 and the monolithic LED pixel 1. For example, a pick-and-place mass transfer machine can sequentially remove each monolithic LED pixel 1. The spacing between each monolithic LED pixel 1 after removing the sacrificial dielectric layer 121 can provide space for the pick-and-place mass transfer machine to more easily manipulate each monolithic LED pixel 1.

[0160] Thus, according to a first embodiment of the present disclosure, a monolithic LED pixel 1 is provided. The LED pixel 1 includes a sacrificial substrate 101, a common semiconductor layer 102, an array of LED sub-pixels, and a planarizing dielectric layer. The common semiconductor layer 102 includes a group III nitride disposed on the sacrificial substrate 101. The array of LED sub-pixels is disposed on a surface of the common semiconductor layer 102 on a side of the common semiconductor layer 102 opposite the sacrificial substrate 101. Each LED sub-pixel of the array of LED sub-pixels includes a stack of group III nitride layers. The planarizing dielectric layer disposed on the array of LED sub-pixels provides a planarized dielectric surface 217 that is substantially aligned with the surface of the common semiconductor layer 102. The planarizing dielectric layer, the common semiconductor layer 102, and the sacrificial substrate 101 define etched sidewalls surrounding the light emitting surface of the monolithic LED pixel 103. The monolithic LED pixel 1 also includes a light extraction feature comprising a first opening disposed through the thickness of the sacrificial substrate aligned with each LED sub-pixel.

[0161] Figure 1 and Figure 2 An example of a monolithic LED pixel 1 according to a first embodiment is shown in FIG. Figure 19 A cross section of the monolithic LED pixel 1 along line AA' is shown. Further features of the monolithic LED pixel 1 will be apparent from the functionality of the various layers discussed above in relation to the method of forming the monolithic LED pixel 1 of the first embodiment.

[0162] Next, we will refer to Figure 2 A description of a method of forming a monolithic LED pixel 1 according to a first embodiment is provided with reference to a cross section along line BB' shown.

[0163] like Figure 2 As shown in the plan view of FIG, the monolithic LED pixel 1 includes four contact metallizations 117. Three of the contact metallizations 117 are anode contact metallizations A. R 、A G 、A B , each of the three LED sub-pixels 103 has an anode contact metallization. Therefore, a single LED pixel comprises Figure 2 The illustrated 1 includes one anode contact metallization A for each of the red, green and blue LED sub-pixels R, G, BR , A G , A B . An anode contact metallization A R , A G , A B Each of the anode contact metallization A C , the common cathode contact metallization C C and the common semiconductor layer 102 is configured to form an electrical connection with a respective anode of the three LED sub-pixels 103R, G and B.

[0164] Furthermore, as Figure 2 illustrated, the monolithic LED pixel 1 comprises a common cathode contact metallization C C . The common cathode contact metallization C C is configured to provide an electrical connection with each cathode of the LED sub-pixels 103. Thus, the common cathode contact metallization C C may be provided with a single contact point to the common semiconductor layer 102, or in some embodiments, such as in the first embodiment, with multiple contact points to the common semiconductor layer. Thus, the monolithic LED pixel 1 can be provided with a common cathode contact metallization C C and an anode contact metallization A R , A G , A B for each of the LED sub-pixels, such that each of the LED sub-pixels R, G, B can be controlled independently from the other LED sub-pixels R, G, B.

[0165] As Figure 2 illustrated, the contact metallization C C , A R , A G , A B is provided in a layer, such that as part of a pick-and-place procedure, the monolithic LED pixel 1 can be mounted on another substrate. Furthermore, in order to integrate the common cathode contact metallization C C into the monolithic LED pixel 1, the common cathode can be arranged to overlap one or more of the LED sub-pixels. An example of such an arrangement will now be described with reference to a cross-section along the line B-B’ as Figure 2 illustrated.

[0166] Figure 20 An intermediate step of a method of forming the first embodiment of the invention is illustrated along the line B-B’. As Figure 20 illustrated, a sacrificial substrate 101 is provided. On the sacrificial substrate 101, a common semiconductor layer 102 is provided. Then, a plurality of LED sub-pixels 103 is formed on the common semiconductor layer 102. Thus, Figure 20 the view is an alternative view to the view illustrated in Figure 4 . From the view of Figure 20 and Figure 1 it can be understood that Figure 20The LED sub-pixel 103 shown has a different surface area than the other LED sub-pixels 103 of the monolithic LED pixel 1. For example, Figure 20 The surface area of ​​the LED subpixel G shown in FIG is at least twice the surface area of ​​the LED subpixels R and B of the other monolithic LED pixels 1. The increase in the surface area of ​​the LED subpixel G is provided by extending a dimension of the LED subpixel G aligned with the surface of the common semiconductor layer 102 relative to the other LED subpixels R and B. In other words, Figure 20 The size of the LED subpixel 103 shown in FIG. 1 is different from the sizes of the other LED subpixels 103 forming the monolithic LED pixel 1. In the first embodiment, the LED subpixel 103G configured to output substantially green visible light is provided as the largest of the three LED subpixels 103.

[0167] Then, if Figure 21 As shown, a plurality of first electrical contacts 106 are formed on the common semiconductor layer 102 in the regions between the LED sub-pixels 103. The first contact layer 106 is configured to provide electrical connections to the common semiconductor layer 102. Figure 20 As shown, on either side of the LED sub-pixel 103 , a plurality of first contact layers are provided as one.

[0168] Furthermore, a first passivation layer 107 is formed over the plurality of LED sub-pixels 103. A plurality of first openings 141 are formed in the first passivation layer 107 aligned with each first contact layer 106. A cathode contact layer 109 is then formed within the first openings 141 of the first passivation layer 107. Thus, a cathode contact layer 109 is provided on each first contact layer 106. A plurality of second openings 142 are also formed in the first passivation layer 107. Each second opening is aligned with one of the LED sub-pixels 103. An anode contact layer 108 is formed in the plurality of second openings 142 to form an electrical connection to the anode of each LED sub-pixel 103. Thus, Figure 21 The intermediate structure shown in Figure 5 Alternative view of the intermediate structure shown in .

[0169] After forming the cathode contact layer 109 and the anode contact layer 108, a planarization dielectric layer is formed. As described above, in some embodiments, part of the process of forming the planarization dielectric layer may include forming contact metallization 117 to allow electrical connection to each LED sub-pixel 103 of each monolithic LED pixel 1. Figure 22 As shown in FIG, the planarization dielectric layer can be composed of multiple passivation layers. Figure 22As shown, a second passivation layer 112 is formed on the array of LED sub-pixels 103. A plurality of third openings 143 may then be formed in the second passivation layer 112 to allow for the formation of a first contact metallization 114 to form electrical connections to the anode contact layer 108 and the cathode contact layer 109. Figure 22 As shown in FIG, a plurality of first contact metallizations 114 are provided in the third openings 143. Figure 22 As shown in FIG, a plurality of first contact metallizations 114 extend through the second passivation layer 112 to the anode contact layer 108 , and another first contact metallization 114 extends through the second passivation layer 112 to the cathode contact layer 109 .

[0170] Then, if Figure 23 As shown, a third passivation layer 115 is formed on the second passivation layer 112. A fourth opening 144 is formed in the third passivation layer 115. The fourth opening 144 defines an area of ​​the third passivation layer in which a second contact metallization 117 is provided for each electrical contact with each LED sub-pixel 103 and the common cathode. Figure 23 As shown in the embodiment, a common cathode contact metallization C is provided in the fourth opening 144 of the third passivation layer 115. C , which overlaps the LED sub-pixel 103 in a plane perpendicular to the common semiconductor layer 102. By providing a common cathode contact metallization C that overlaps one or more LED sub-pixels C , a common cathode contact metallization can be provided in a more space-saving manner within a monolithic LED pixel 1. That is, the common cathode contact metallization C C overlaps a portion of the light emitting surface of the monolithic LED pixel 1. Thus, a larger proportion of the light emitting surface 130 of the monolithic LED pixel is occupied by the light emitting elements of each LED sub-pixel, rather than the non-light emitting surface portion that would otherwise need to be provided to provide for the common cathode contact metallization C C space.

[0171] Also like Figure 23 As shown in FIG, an anode contact metallization A is provided in another of the fourth openings 144. G , to form Figure 23 The anode contact metallization of the LED sub-pixel G is shown in FIG.

[0172] It should be understood that Figure 23 The structure shown in the Figure 9 The intermediate structure shown in FIG 1 shows the same intermediate structure viewed along line BB′. Thus, it can be understood that the third passivation layer 115 , the cathode contact metallization and the anode contact metallization form a planarized dielectric surface of the monolithic LED pixel 1 .

[0173] After forming the anode contact metallization and the cathode contact metallization, the method of forming the monolithic LED pixel 1 continues as described above with respect to Figure 10 and 11 Thus, as shown in Figure 24 the pixel defining trench 118 is formed. In Figure 25 the etch stop layer 119 and the sacrificial dielectric layer 121 are formed over the pixel defining trench 118 and the planarization dielectric layer to form the intermediate array 100 of LED sub-pixels as described above with respect to Figure 3 and Figure 11 .

[0174] Next, the intermediate array 100 of LED sub-pixels is bonded to the handling substrate 200 as described above. Figure 27 A cross-section of the handling substrate 200 is shown which corresponds to the portion of the handling substrate which is to be aligned with the B-B' line of the monolithic LED pixel 1. Thus, the handling substrate 200 comprises a first electronic wafer 201 and a plurality of electronic layers 202, 203, 204, 205. In the first embodiment, the handling substrate 200 further comprises a handling etch stop layer 207 and a sacrificial handling dielectric layer 206.

[0175] As shown in Figure 27 the handling substrate 200 is configured as a test substrate for testing each monolithic LED pixel 1. As shown in Figure 27 the plurality of electronic layers 202, 203, 204, 205 are arranged to provide electrical connections to the anode contact metallization A G , A B , A R and the cathode contact metallization C C .

[0176] For example, the handling substrate 200 comprises a first conductive layer 203 and a second conductive layer 205. Each conductive layer can comprise a conductive material, for example a metal such as gold, aluminium, copper or the like.

[0177] The test substrate can further comprise a first insulating layer 202 and a second insulating layer 204. The first insulating layer 202 and the second insulating layer 204 can comprise any suitable dielectric material, for example silicon dioxide. The first insulating layer 202 can provide a surface on which the first conductive layer 203 can be provided. The second insulating layer 204 can then be provided over the first conductive layer 203 so as to encapsulate the first conductive layer 203. The second conductive layer 205 can then be formed on the second insulating layer 204. Thus, the stack of electronic layers 202, 203, 204, 205 can be formed in a pattern to provide electrical connections to the anode contact metallization A G , A B , A R and the cathode contact metallization CC Thus, the plurality of electronic layers 202, 203, 204, 205 of the test substrate can be configured to provide an electrical test circuit for each LED sub-pixel that can be coupled to the intermediate array of LED sub-pixels 100. That is, when the test substrate is coupled to the intermediate array of LED sub-pixels 100, the plurality of electronic layers 202, 203, 204, 205 are configured to provide power to each LED sub-pixel 103.

[0178] like Figure 27 As shown, a plurality of seventh openings 212 are formed in the processing substrate surface 210, and the plurality of seventh openings 212 correspond to the anode contact metallization A disposed on the middle array 100 of LED sub-pixels. G 、A B 、A R Contact metallization C with cathode C Then, a plurality of conductive contact portions 208 are formed in each seventh opening 212 of the processing substrate 200 .

[0179] As described above, the intermediate array of LED sub-pixels 100 is configured to be bonded to a test substrate. A view of the bonded intermediate array of LED sub-pixels 100 and the test substrate along line BB' is shown in FIG. Figure 28 Therefore, from Figure 28 As can be seen in FIG, the cathode contact layer 109 is formed by the cathode contact metallization C C The anode contact layer 108 of the LED sub-pixel G is electrically connected to the first conductive layer 203 of the test substrate. G The second conductive layer 205 is electrically connected to the test substrate.

[0180] After bonding the intermediate array of LED sub-pixels 100 to the test substrate, the light emitting surface 130 of the intermediate array of LED sub-pixels 100 may be further processed to form light extraction features. Figure 29 As shown, a container volume 151 is formed in the sacrificial substrate 101. The container volume 151 is filled with a first color conversion material 160, and a pump light reflector 180 is arranged above the container volume 151. Figure 29 The structure shown is Figure 17 Different views of the structure shown.

[0181] Finally, for example, Figure 30 As shown, each monolithic LED pixel 1 can be removed from the test substrate, for example using a mass transfer pick and place machine.

[0182] In some embodiments, each LED sub-pixel can be tested before removing the sacrificial dielectric layer 121 and releasing each monolithic LED pixel 1 from the test substrate. As part of the testing procedure, the first conductive layer 203 and the second conductive layer 205 of the test substrate can be connected to a power source. Thus, a voltage can be applied across the first conductive layer 203 and the second conductive layer 205 to drive current through each LED sub-pixel in the intermediate array 100 of LED sub-pixels. The testing procedure is configured to turn on each LED in the intermediate array 100 of LED sub-pixels. A test analysis device (e.g., a camera or other light-sensitive sensor) can then detect light emitted from the LED sub-pixels in the intermediate array 100 of LED sub-pixels. A processor can then use the information recorded by the test analysis device (e.g., an image recorded by the camera) to determine whether any of the LED sub-pixels 103 are operational or inoperable. Any monolithic LED pixel 1 within the intermediate array 100 identified as including one or more inoperable LED sub-pixels 103 can be identified and exempted from any subsequent pick and place process. Thus, the test substrate 200 allows for parallel testing of an array of monolithic LED pixels 1. This parallel testing process is more efficient than testing each monolithic LED pixel 1 after it has been removed from the test substrate.

[0183] In addition, if Figure 30 As shown, after the monolithic LED pixel 1 is removed from the test substrate, the test circuitry of the test substrate remains substantially unchanged. Therefore, the test substrate can be reused in further manufacturing steps of the monolithic LED pixel 1. In some embodiments, the test substrate includes a surface for bonding the sacrificial process dielectric layer to the intermediate array 100 of LED sub-pixels, and it may be necessary to redeposit the sacrificial process dielectric layer on the test substrate before reusing the test substrate.

[0184] Thus, according to a first embodiment of the present disclosure, a monolithic LED pixel 1 is provided. In some embodiments, each monolithic LED pixel can be a monolithic micro-LED pixel. Thus, each LED sub-pixel can be a micro-LED sub-pixel having dimensions no greater than 100 μm x 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than 100 μm x 100 μm. In some embodiments, the surface area of ​​each LED sub-pixel on the common semiconductor layer can define an area no greater than 50 μm x 50 μm, 30 μm x 30 μm, 20 μm x 20 μm, or 10 μm x 10 μm.

[0185] Although preferred embodiments of the present invention have been described in detail herein, those skilled in the art will appreciate that changes may be made thereto without departing from the scope of the invention or the appended claims.

Claims

1. A method of forming a plurality of monolithic LED pixels for a light emitting diode (LED) display, the method comprising: forming a common semiconductor layer including a Group III nitride on a sacrificial substrate; forming an array of light emitting diode (LED) sub-pixels on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite the sacrificial substrate, each LED sub-pixel of the array of LED sub-pixels comprising a stack of Group III nitride layers; forming a planarized dielectric layer over the array of LED sub-pixels to provide a planarized dielectric surface aligned with a surface of the common semiconductor layer; dividing the array of LED sub-pixels into a plurality of monolithic LED pixels by etching a grid of pixel-defining trenches from the planarized dielectric surface into the sacrificial substrate, wherein each monolithic LED pixel comprises at least two LED sub-pixels of the array of LED sub-pixels monolithically formed on the common semiconductor layer; forming a sacrificial dielectric layer over the pixel-defining trenches and the planarized dielectric surface to form a bonding surface aligned with the surface of the common semiconductor layer; bonding a processing substrate to the bonding surface of the sacrificial dielectric layer; selectively removing a first portion of the sacrificial substrate aligned with the grid of pixel-defining trenches through the thickness of the sacrificial substrate to separate each of the monolithic LED pixels; and forming light extraction features for each of the monolithic LED pixels, comprising: selectively removing a second portion of the sacrificial substrate aligned with each of the LED sub-pixels; The sacrificial dielectric layer is removed to separate each monolithic LED pixel from the handle substrate.

2. The method according to claim 1, wherein Forming light extraction features for each of the monolithic LED pixels includes: selectively removing a second portion of the sacrificial substrate aligned with each of the LED sub-pixels to form a container volume for each LED sub-pixel; and A first color converting layer is provided in at least one of the container volumes of each monolithic LED pixel, the first color converting layer being configured to absorb light of a first wavelength and emit converted light of a first converted light wavelength that is longer than the first wavelength. The method of claim 2 , wherein the first converted light wavelength is at least 500 nm. The method according to claim 2 , wherein the first converted light wavelength is no greater than 650 nm.

5. The method according to any one of claims 2 to 4, wherein A second color converting layer is provided in at least another one of the container volumes of each monolithic LED pixel, the second color converting layer being configured to absorb light of a first wavelength and emit converted light of a second converted light wavelength longer than the first converted light wavelength.

6. The method according to any one of claims 2 to 4, wherein: The first color conversion layer includes phosphors, organic molecules or quantum dots.

7. The method according to claim 5, wherein: The first color conversion layer and / or the second color conversion layer include phosphors, organic molecules or quantum dots.

8. The method of any one of claims 1 to 4, wherein each LED sub-pixel is configured to generate light having a first wavelength of at least 380 nm.

9. The method of any one of claims 1 to 4, wherein each LED sub-pixel is configured to generate light having a first wavelength no greater than 490 nm.

10. The method according to any one of claims 1 to 4, wherein Forming light extraction features for each of the monolithic LED pixels includes: A second portion of the sacrificial substrate is selectively removed through the thickness of the sacrificial substrate such that a first portion of the surface of the common semiconductor layer is exposed.

11. The method of claim 10 , wherein forming light extraction features for each of the monolithic LED pixels comprises: The first portion of the surface of the common semiconductor layer is patterned with scattering features configured to increase light extraction efficiency of each LED sub-pixel.

12. The method according to any one of claims 1 to 4, wherein After forming the planarizing dielectric layer, selectively removing a third portion of the planarizing dielectric layer and forming an anode contact metallization between the anode of each LED sub-pixel and the planarizing dielectric surface, and A fourth portion of the planarized dielectric layer is selectively removed, and a common cathode contact metallization for each monolithic LED pixel is formed between the common semiconductor layer and the planarized dielectric surface.

13. The method according to claim 12, wherein: A surface of the common cathode contact metallization forming a portion of the planarized dielectric surface overlaps at least one of the LED sub-pixels forming each monolithic LED pixel.

14. The method according to any one of claims 1 to 4, wherein One of the LED sub-pixels of each monolithic LED pixel has a larger surface area on the common semiconductor layer than another LED sub-pixel of each monolithic LED pixel.

15. The method according to any one of claims 1 to 4, wherein The processing substrate is a test substrate configured to form an electrical connection with each LED sub-pixel when combined, so that each LED sub-pixel can be tested in parallel, The method further comprises: After bonding the test substrate to the bonding surface of the sacrificial dielectric layer, each of the LED sub-pixels is tested by providing power from the test substrate to the array of LED sub-pixels.

16. The method according to any one of claims 1 to 4, wherein The surface area of ​​each LED sub-pixel on the common semiconductor layer defines an area no greater than 100 μm x 100 μm.

17. A monolithic LED pixel for a light emitting diode (LED) display, comprising: a common semiconductor layer comprising a Group III nitride disposed on a sacrificial substrate; an array of light emitting diode (LED) sub-pixels disposed on a surface of the common semiconductor layer on a side of the common semiconductor layer opposite to the sacrificial substrate, each LED sub-pixel of the array of LED sub-pixels comprising a stack of Group III nitride layers; a planarizing dielectric layer disposed on the array of LED sub-pixels to provide a planarized dielectric surface aligned with the surface of the common semiconductor layer; wherein the planarized dielectric layer, the common semiconductor layer, and the sacrificial substrate define etched sidewalls of the monolithic LED pixel surrounding a light emitting surface of the monolithic LED pixel; and The monolithic LED pixel also includes light extraction features, including: A first opening is provided to pass through the thickness of the sacrificial substrate aligned with each of the LED sub-pixels.

18. The monolithic LED pixel of claim 17, wherein: The light extraction features further include: The first opening forms a container volume for each LED sub-pixel; and A first color converting layer is provided in at least one of the container volumes, the first color converting layer being configured to absorb light of a first wavelength and emit converted light of a first converted light wavelength that is longer than the first wavelength.

19. The monolithic LED pixel of claim 18, wherein the first converted light wavelength is at least 500 nm.

20. The monolithic LED pixel of claim 18, wherein the first converted light wavelength is no greater than 650 nm.

21. The monolithic LED pixel according to any one of claims 18 to 20, wherein A second color converting layer is provided in at least one other container volume of the monolithic LED pixel, the second color converting layer being configured to absorb light of a first wavelength and emit converted light of a second converted light wavelength that is longer than the first converted light wavelength.

22. The monolithic LED pixel of any one of claims 18 to 20, wherein: The first color conversion layer includes phosphors, organic molecules or quantum dots.

23. The monolithic LED pixel of claim 21 , wherein: The first color conversion layer and / or the second color conversion layer include phosphors, organic molecules or quantum dots.

24. The monolithic LED pixel according to any one of claims 17 to 20, wherein Each LED sub-pixel is configured to generate light having a first wavelength of at least 380 nm.

25. The monolithic LED pixel of any one of claims 17 to 20, wherein Each LED sub-pixel is configured to generate light having a first wavelength no greater than 490 nm.

26. The monolithic LED pixel of any one of claims 17 to 20, wherein: The light extraction features of each of the monolithic LED pixels further include: A light scattering feature is formed on a first portion of the surface of the common semiconductor layer, the first portion of the surface of the common semiconductor layer is aligned with each of the first openings of the sacrificial substrate, and the light scattering feature is configured to increase the light extraction efficiency of each LED sub-pixel.

27. The monolithic LED pixel of any one of claims 17 to 20, wherein: The planarized dielectric layer includes a second opening in which an anode contact metallization is disposed between the anode of each LED subpixel and the planarized dielectric surface, and The planarization dielectric layer includes a third opening in which a common cathode contact metallization is disposed between the common semiconductor layer and the planarization dielectric surface.

28. The monolithic LED pixel of claim 27, wherein: A surface of the common cathode contact metallization forming a portion of the planarized dielectric surface overlaps at least one of the LED sub-pixels forming each monolithic LED pixel.

29. The monolithic LED pixel of any one of claims 17 to 20, wherein One of the LED sub-pixels of the monolithic LED pixel has a larger surface area on the common semiconductor layer than another LED sub-pixel of the monolithic LED pixel.

30. The monolithic LED pixel of any one of claims 17 to 20, wherein The surface area of ​​each LED sub-pixel on the common semiconductor layer defines an area no greater than 100 μm x 100 μm.

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