Method, system, and computer program product for storing finite state machine state data

By introducing a finite state machine circuit and a storage buffer into the power system control device, the problem of inefficient storage and retrieval of state data in the prior art is solved, enabling rapid fault location and simplified debugging process.

CN115248627BActive Publication Date: 2026-06-12QUANTA COMPUTER INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
QUANTA COMPUTER INC
Filing Date
2021-08-24
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

During the power-on sequence of a computer system, existing technologies cannot effectively determine the stage at which a fault occurs, resulting in complex and time-consuming debugging procedures and an inability to efficiently store the state data of the finite state machine for retrieval by an external controller.

⚗Method used

By introducing a finite state machine circuit, a write controller, and a storage buffer into the power system control device, the state data of the finite state machine is recorded and transmitted to an external controller through a communication interface, thereby realizing the storage and retrieval of the state data.

🎯Benefits of technology

It improves troubleshooting efficiency, simplifies the fault diagnosis process, reduces debugging time, and enables rapid location of abnormalities in the power-on sequence.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present disclosure provides a method, system, and computer program product for storing finite state machine state data to record state data from a power system control device on a computer system. The computer system includes a power system that powers the computer system. The power system has a power-up sequence that has a plurality of phases. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit that has a plurality of states that correspond to the plurality of phases of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes state data of the finite state machine circuit to the storage buffer. An external controller is coupled to the communication interface and is operable to store the state data.
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