Integrated circuit layout structure

Abstract

An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes a plurality of first gate lines arranged along a first direction between two first cell boundaries, and includes a first gate line width and a default gate line pitch. The second standard cell is adjacent to a side of the first standard cell along a second direction and includes a plurality of second gate lines arranged along the first direction between two second cell boundaries, and includes a second gate line width and the default gate line pitch. The first gate line width is different from the second gate line width. A first cell width between the two first cell boundaries and a second cell width between the two second cell boundaries are integer multiples of the default gate line pitch, respectively. At least some of the second gate lines are aligned with at least some of the first gate lines along the second direction. The first direction and the second direction are perpendicular to each other.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor integrated circuit layout, and more particularly to an integrated circuit layout composed of different standard cells with the same gate line pitch but different gate line widths. BACKGROUND

[0002] With the increasing performance and various application requirements, the design of integrated circuits (IC) is becoming more and more complex, often containing hundreds of thousands or even millions of logic gates. For the convenience of design, the industry will first design the specific functions often used in integrated circuits (IC) using logic gates, and then manufacture them into standard cells, such as NAND, NOR, D-Flip-Flop, latch, input / output cell (I / O), amplifier (OP Amp), analog-to-digital converter (ADC), digital-to-analog converter (DAC), etc., and after the manufacturing process is verified to determine that they can be mass-produced, the standard cell library is authorized to chip designers for use. Using computer-aided design (CAD) tools such as circuit simulation (logic Simulator), logic circuit synthesis (Logic Synthesizer), automatic layout and routing (Automatic Placer & Router), etc., these standard cells can be arranged and combined to form the required circuit function, so that a complex and large integrated circuit system can be correctly constructed in a short time.

[0003] In order to provide greater design flexibility, the standard cell library (Standard cell library) usually contains standard cells of different levels (or different gate sizes) of different speeds or powers for chip designers to mix and use. However, if the size of these standard cells is not designed well, it is easy to cause idle layout area after combination, resulting in space waste and also leading to increased layout and routing complexity when mixed, thereby reducing the efficiency of automatic layout. In addition, in the layout modification stage after design tapeout, the layout modification such as optical proximity correction (OPC) will also cause a burden and is easy to produce an error pattern. SUMMARY

[0004] The present application relates to an integrated circuit layout and a design method thereof, and more particularly, to an integrated circuit layout including different standard cells with the same gate line pitch but different gate line widths and a design method thereof.

[0005] To achieve the above object, the present application provides an integrated circuit layout including a first standard cell and a second standard cell. The first standard cell includes a plurality of first gate lines arranged along a first direction between two first cell boundaries of the first standard cell, wherein the first gate lines include a first gate line width and are spaced apart by a default gate line pitch. The second standard cell is adjacent to a side of the first standard cell along a second direction and includes a plurality of second gate lines arranged along the first direction between two second cell boundaries of the second standard cell, wherein the second gate lines include a second gate line width and are spaced apart by the default gate line pitch, the first gate line width is different from the second gate line width, a first cell width between the two first cell boundaries and a second cell width between the two second cell boundaries are integer multiples of the default gate line pitch, and at least part of the second gate lines are aligned with at least part of the first gate lines along the second direction, the first direction and the second direction being perpendicular to each other. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A flow chart of a design method of an integrated circuit layout according to an embodiment of the present application;

[0007] Figures 2 to 4 A layout plan of a standard cell according to some embodiments of the present application;

[0008] Figures 5 to 8 A layout plan of an integrated circuit layout according to some embodiments of the present application.

[0009] Explanation of main element symbols

[0010] 10 Design method

[0011] 12 Step

[0012] 14 Step

[0013] 16 Step

[0014] 18 Step

[0015] 102 Gate line

[0016] 104 Cell boundary

[0017] 106 Cell boundary

[0018] 108 Active region pattern

[0019] 202 gate line

[0020] 204 cell boundary

[0021] 206 cell boundary

[0022] 208 active region pattern

[0023] 302 gate line

[0024] 304 cell boundary

[0025] 306 cell boundary

[0026] 308 active region pattern

[0027] 400 dummy gate line

[0028] 500 integrated circuit layout

[0029] 600 integrated circuit layout

[0030] 700 integrated circuit layout

[0031] 800 integrated circuit layout

[0032] 102a center line

[0033] 108a active region pattern width

[0034] 108b active region pattern pitch

[0035] 202a center line

[0036] 208a active region pattern width

[0037] 208b active region pattern pitch

[0038] 302a center line

[0039] 308a active region pattern width

[0040] 308b active region pattern pitch

[0041] 400a dummy gate line half

[0042] 400b dummy gate line half

[0043] Cell-A1 standard cell

[0044] Cell-A2 standard cell

[0045] Cell-B1 standard cell

[0046] Cell-B2 standard cell

[0047] Cell-C1 standard cell

[0048] Cell-C2 standard cell

[0049] LA gate line width

[0050] LB gate line width

[0051] LC gate line width

[0052] P preset gate line spacing

[0053] SA1 gate line spacing

[0054] SA2 dummy gate line spacing

[0055] SA3 dummy gate line spacing

[0056] SB1 gate line spacing

[0057] SB2 dummy gate line spacing

[0058] SB3 dummy gate line spacing

[0059] SC1 gate line spacing

[0060] SC2 dummy gate line spacing

[0061] SC3 dummy gate line spacing

[0062] Wa dummy gate line half width

[0063] Wb dummy gate line half width

[0064] WA1 cell width

[0065] WA2 cell width

[0066] WB1 cell width

[0067] WB2 cell width

[0068] WC1 cell width

[0069] WC2 cell width DETAILED DESCRIPTION

[0070] In order to enable a person skilled in the art to further understand the present application, several preferred embodiments of the present application are listed below, and the configuration content and the desired effects of the present application are described in detail with the help of the accompanying drawings. Without departing from the scope of the present application, modifications in structure, logic and electrical properties can be made, and applied to other embodiments. The drawings of the present application are only schematic drawings, and the detailed proportions can be adjusted according to the design requirements without departing from the present application.

[0071] Figure 1 A flow chart of the steps of the layout design method 10 of an integrated circuit according to an embodiment of the present application is shown. It should be appreciated by those skilled in the art that the design method 10 can be performed by any kind of computer system, such as a personal computer, a laptop computer, a workstation, a computer terminal, a network computer, or any kind of data processing system or device. As shown, Figure 1 The layout design method 10 of an integrated circuit according to the present application includes, as shown, first performing step 12 of setting a default gate line pitch P, a default gate line width L, and a variable (e.g. a first variable dl). Then performing step 14 of generating a set of first gate lines between two first cell boundaries according to the default gate line pitch P and the default gate line width L, and generating a set of second gate lines between two second cell boundaries according to the default gate line pitch P and the default gate line width L plus the variable (e.g. the first variable dl). Then performing step 16 of providing dummy gate lines on the two first cell boundaries and the two second cell boundaries, thereby obtaining first standard cells and second standard cells.

[0072] According to an embodiment of the present application, another variable (e.g. a second variable d2) can be set in step 12, and a set of third gate lines between two third cell boundaries can be generated in step 14 according to the default gate line pitch P and the default gate line width L plus the other variable (e.g. the second variable d2), and then performing step 16 of providing dummy gate lines on the two third cell boundaries, thereby obtaining third standard cells. It should be appreciated that more sets of variables can be set to generate more standard cells according to design requirements, which will not be further described herein for the sake of simplicity.

[0073] Please refer to Figure 2 , Figure 3 and Figure 4 , a flow chart of the steps of the layout design method 10 of an integrated circuit according to an embodiment of the present application is shown. It should be appreciated by those skilled in the art that the design method 10 can be performed by any kind of computer system, such as a personal computer, a laptop computer, a workstation, a computer terminal, a network computer, or any kind of data processing system or device. As shown, Figure 1The layout plan of some exemplary standard cells obtained by design method 10 is shown below. It should be noted that the standard cells shown in the upper and lower parts of each figure include the same gate line pitch (e.g., preset gate line pitch P) and gate line width, with the main difference being different circuit interconnect designs to provide different functions. The standard cells between figures include the same circuit design and the same gate line pitch (e.g., preset gate line pitch P) but different gate line widths, for example, gate line widths equal to preset gate line width L, preset gate line width L plus a first variable d1, and preset gate line width L plus a second variable d2, respectively, to provide the same function but different speeds or power. It should be noted that... Figure 2 , Figure 3 and Figure 4 The circuit design of the standard cell shown is merely an example, and the number of gate lines and active region patterns shown is for ease of drawing and illustration, and is not intended to limit the invention. The concept of the invention can be applied to any standard cell that includes multiple gate lines.

[0074] In detail, such as Figure 2 As shown, standard cells Cell-A1 and Cell-A2 each include a pair of cell boundaries 104 extending parallel to each other along a second direction D2, and another pair of cell boundaries 106 extending parallel to each other along a first direction D1, wherein the first direction D1 and the second direction D2 are perpendicular to each other; a plurality of active region patterns 108 extend along the first direction D1 and are arranged along the second direction D2; a plurality of gate lines 102 extend along the second direction D2 and are arranged along the first direction D1 between the cell boundaries 104; and two dummy gate lines 400 overlap with the cell boundaries 104, wherein a dummy gate line spacing SA2 and a dummy gate line spacing SA3 are respectively included between the edge of the dummy gate line 400 and the edge of the adjacent gate line 102. According to an embodiment of the present invention, as Figure 2As shown, the ends of the active region pattern 108 overlap with the gate line 102 or the dummy gate line 400 and are not exposed. The gate lines 102 of standard cells Cell-A1 and Cell-A2 have a gate line width LA and are spaced apart by a preset gate line spacing P, where the preset gate line spacing P is equal to the sum of a gate line width LA and a gate line space SA1 between the edges of adjacent gate lines 102. The active region patterns 108 of standard cells Cell-A1 and Cell-A2 both include an active region pattern width 108a and are spaced apart by an active region pattern spacing 108b. It is worth noting that the cell widths WA1 and WA2 between the cell boundaries 104 of standard cells Cell-A1 and Cell-A2 are integer multiples of the preset gate line spacing P, and their respective gate lines 102 are arranged between the cell boundaries 104 in a manner that evenly divides the cell widths WA1 and WA2. In other words, standard cells Cell-A1 and Cell-A2 can be divided into portions of equal width along the center line 102a of each gate line 102. It is also noteworthy that the cell boundary 104, approximately passing through the center line of the dummy gate line 400, divides the dummy gate line 400 into two dummy gate line halves 400a and 400b of equal width, each comprising a dummy gate line half width Wa and a dummy gate line half width Wb, respectively, and Wa and Wb are equal. From the above description, it can be seen that the dummy gate line spacing SA2 and SA3 are also equal, and the two cell boundaries 104 are equidistant from the adjacent gate lines 102.

[0075] like Figure 3 As shown, standard cells Cell-B1 and Cell-B2 each include a pair of cell boundaries 204 extending along a second direction D2 and parallel to each other, another pair of cell boundaries 206 extending along a first direction D1 and parallel to each other, a plurality of active region patterns 208 extending along the first direction D1 and arranged along the second direction D2, and a plurality of gate lines 202 extending along the second direction D2 and arranged along the first direction D1 between the cell boundaries 204. According to an embodiment of the present invention, Figure 3 Standard cell Cell-B1 and standard cell Cell-B2 and Figure 2Standard cells Cell-A1 and Cell-A2 include the same two dummy gate lines 400, wherein the dummy gate line 400 overlaps with the cell boundary 204, and the edges of the dummy gate lines 400 and adjacent gate lines 202 are respectively separated by dummy gate line spacing SB2 and dummy gate line spacing SB3. Similarly, the ends of the active region pattern 208 overlap with the gate line 202 or the dummy gate line 400 and are not exposed. The gate lines 202 of standard cells Cell-B1 and Cell-B2 have a gate line width LB and are spaced apart from each other by a preset gate line spacing P, wherein the gate line width LB is different from the gate line width LA, but the preset gate line spacing P is also equal to the sum of the gate line width LB and the gate line spacing SB1 between the edges of adjacent gate lines 202. The active region patterns 208 of standard cells Cell-B1 and Cell-B2 both include an active region pattern width 208a and are spaced apart by an active region pattern spacing 208b. According to one embodiment of the present invention, the active region pattern width 208a and the active region pattern width 108a are equal, and the active region pattern spacing 208b and the active region pattern spacing 108b are equal. It is worth noting that the cell widths WB1 and WB2 between the cell boundaries 204 of standard cells Cell-B1 and Cell-B2 are also integer multiples of the preset gate line spacing P, and their respective gate lines 202 are arranged between the cell boundaries 204 in a manner that evenly divides the cell widths WB1 and WB2. In other words, along the center line 202a of each gate line 202 of standard cells Cell-B1 and Cell-B2, standard cells Cell-B1 and Cell-B2 can be divided into portions of equal width. Cell boundary 204 roughly passes through the center line of dummy gate line 400, dividing dummy gate line 400 into two dummy gate line halves 400a and 400b of equal width, each including a dummy gate line half width Wa and a dummy gate line half width Wb, respectively, and Wa and Wb are equal. As can be seen from the above description, dummy gate line spacing SB2 and dummy gate line spacing SB3 are also equal, and the two cell boundaries 204 are equidistant from the adjacent gate lines 202.

[0076] like Figure 4 As shown, standard cells Cell-C1 and Cell-C2 each include a pair of cell boundaries 304 extending along a second direction D2 and parallel to each other, another pair of cell boundaries 306 extending along a first direction D1 and parallel to each other, a plurality of active region patterns 308 extending along the first direction D1 and arranged along the second direction D2, and a plurality of gate lines 302 extending along the second direction D2 and arranged along the first direction D1 between the cell boundaries 304. According to an embodiment of the present invention, Figure 4 Standard cell Cell-C1 and standard cell Cell-C2 andFigure 2 standard cell Cell-A1 and standard cell Cell-A2 of Figure 3 standard cell Cell-B1 and standard cell Cell-B2 include the same two dummy gate lines 400, which overlap the cell boundaries 304 and include the dummy gate line spacing SC2 and SC3 between the edges of the dummy gate lines 400 and the edges of the adjacent gate lines 302, respectively. Similarly, the ends of the active region patterns 308 overlap the gate lines 302 or the dummy gate lines 400 and are not shown. The gate lines 302 of the standard cell Cell-C1 and Cell-C2 have a gate line width LC and are separated by a predetermined gate line spacing P, wherein the gate line width LC is different from the gate line width LA and LB, but the predetermined gate line spacing P is equal to the sum of the gate line width LC and the gate line spacing SC1 between the edges of the adjacent gate lines 302. The active region patterns 308 of the standard cell Cell-C1 and Cell-C2 include an active region pattern width 308a and are separated by an active region pattern spacing 308b. According to an embodiment of the present application, the active region pattern width 308a is equal to the active region pattern width 208a and the active region pattern width 108a, and the active region pattern spacing 308b is equal to the active region pattern spacing 208b and the active region pattern spacing 108b. It is noted that the cell widths WC1 and WC2 between the cell boundaries 304 of the standard cell Cell-C1 and Cell-C2 are also integer multiples of the predetermined gate line spacing P, and their respective gate lines 302 are arranged between the cell boundaries 304 in a manner that equally divides the cell widths WC1 and WC2. In other words, along the center lines 302a of the respective gate lines 302 of the standard cell Cell-C1 and Cell-C2, the standard cell Cell-C1 and Cell-C2 can be divided into portions of equal width. The cell boundaries 304 substantially divide the dummy gate lines 400 into two dummy gate line halves 400a and 400b of equal width, including a dummy gate line half width Wa and Wb, respectively, and Wa and Wb are equal. As can be seen from the above description, the dummy gate line spacing SC2 and SC3 are also equal, and the two cell boundaries 304 are equidistant from the adjacent gate lines 302.

[0077] According to an embodiment of the present application, the gate line width LC can be equal to the predetermined gate line width L, the gate line width LA is equal to the predetermined gate line width L plus a first variable dl, and the gate line width LB is equal to the predetermined gate line width L plus a second variable d2.

[0078] The width of dummy gate line 400 (i.e., the sum of Waand Wb) can be equal to one of the preset gate line width L, the gate line width LC, the gate line width LB, and the gate line width LC. For example, the width of dummy gate line 400 can be equal to the preset gate line width L plus the first variable dl, i.e., equal to the gate line width LA.

[0079] According to an embodiment of the present application, when performing step 12 of design method 10, the preset gate line width L can be a minimum gate line width of a design rule of an integrated circuit, and the preset gate line pitch P can be a minimum gate line pitch that can be achieved by a manufacturing process resolution when the preset gate line width L is the minimum gate line width. For example, according to an embodiment of the present application, the preset gate line width L of step 12 can be set to 16 nm, the preset gate line pitch P can be set to 96 nm, the first variable dl can be set to 4 nm, and the second variable d2 can be set to 8 nm. Then, the standard cells Cell-A1, Cell-A2, Cell-B1, Cell-B2, Cell-C1, and Cell-C2 obtained in steps 14 and 16 can have the feature sizes shown in .

[0080] Table 1

[0081]

[0082] The above specific dimensions are for the purpose of helping understanding the present application and are not intended to limit the present application. In other embodiments, the values of the preset gate line width L, the preset gate line pitch P, the first variable dl, and the second variable d2 can be adjusted according to actual design requirements.

[0083] It is worth noting that although the standard cells of the present application have different gate line widths, the gate lines are arranged between the cell boundaries in a manner that the gate lines (the center lines of the gate lines) divide the standard cells into parts of the same width. Therefore, the gate line spacing of any two standard cells will differ by the variable of the gate line width. In addition, since the standard cells of the present application include the same dummy gate line, the dummy gate line spacing of any two standard cells will differ by 0.5 times the variable of the gate line width. According to an embodiment of the present application, the values of the preset gate line width L, the preset gate line pitch P, the first variable dl, and the second variable d2 are all even numbers, so that an all on-grid layout pattern can be obtained.

[0084] For example, referring to Table 1, the first variable dl between the gate line width LC of the standard cell Cell-C1 and the gate line width LA of the standard cell Cell-A1 is 4 nm, the dummy gate line spacing SC2 is 78 nm, the dummy gate line spacing SA2 is 76 nm, and the difference between the two is 2 nm.

[0085] For another example, the second variable d2 between the gate line width LC of the standard cell Cell-C1 and the gate line width LB of the standard cell Cell-B1 is 8 nm, the dummy gate line spacing SC2 is 78 nm, the dummy gate line spacing SB2 is 74 nm, and the difference between the two is 4 nm.

[0086] Please refer to Figure 1 After obtaining the first standard cell and the second standard cell, step 18 is performed to abut the first standard cell and the second standard cell to obtain an integrated circuit layout. According to an embodiment of the present application, step 18 can select at least two of the first standard cell, the second standard cell, and the third standard cell to abut to obtain the integrated circuit layout.

[0087] As mentioned above, the design of the standard cell provided by the present application includes at least the following features. First, different standard cells include the same preset gate line spacing. Second, the cell width of different standard cells is an integer multiple of the preset gate line spacing. Third, the gate lines of each standard cell are equidistantly arranged between the cell boundaries of the standard cell in a manner of evenly dividing the cell width. Fourth, different standard cells include the same dummy gate line, and the cell boundary passes through the center line of the dummy gate line.

[0088] Through the design of the standard cell described above, the integrated circuit layout provided by the present application can include at least the following features. First, when the cell boundaries of the standard cells adjacent along the first direction D1 overlap with each other, the dummy gate lines can completely overlap. In addition, the gate lines, the dummy gate lines, and the cell boundaries of the standard cells adjacent along the second direction D1 are aligned with each other along the second direction D1. Furthermore, when the standard cells include the same active region pattern width and the same active region pattern spacing, the active region patterns of the standard cells adjacent along the first direction D1 can be aligned with each other along the first direction D1. For the convenience of understanding, the features of the integrated circuit layout of the present application will be described below according to the embodiments of Figure 5 , Figure 6 , Figure 7 and Figure 8 .

[0089] Please refer to Figure 5, shown as a plan view of an integrated circuit layout 500 according to an embodiment of the present application. The integrated circuit layout 500 includes standard cells Cell-C1 and standard cells Cell-B1 arranged mixedly along a first direction D1 and a second direction D2, wherein the cell boundaries 304 and 204 of adjacent standard cells Cell-C1 and Cell-B1 along the first direction D1 overlap each other and share a dummy gate line 400. The cell boundaries 306 and 206 of adjacent standard cells Cell-C1 and Cell-B1 along the second direction D2 overlap each other. The standard cell Cell-C1 includes a plurality of gate lines 302 arranged along the first direction D1 between the two cell boundaries 304 of the standard cell Cell-C1 at a predetermined gate line pitch P and includes a gate line width LC (refer to Figure 4 ). The standard cell Cell-B1 includes a plurality of gate lines 202 arranged along the first direction D1 between the two cell boundaries 204 of the standard cell Cell-B1 at the predetermined gate line pitch P and includes a gate line width LB (refer to Figure 3 ). The gate line width LC is different from the gate line width LB by a variable (e.g., a second variable d2). The standard cell Cell-C1 includes a cell width WC1 between the cell boundaries 304, and the standard cell Cell-B1 includes a cell width WB1 between the cell boundaries 204, wherein the cell width WC1 can be equal to the cell width WB1 and is an integer multiple of the predetermined gate line pitch P, so that, as viewed along the second direction D2, the gate lines 302 and the gate lines 202 are aligned, the cell boundaries 204 and the cell boundaries 304 are aligned, and the dummy gate line 400 and the dummy gate line 400 are aligned.

[0090] Please refer to Figure 6 , shown as a plan view of an integrated circuit layout 600 according to an embodiment of the present application. The integrated circuit layout 600 includes standard cells Cell-C1 and standard cells Cell-B2 arranged mixedly along a first direction D1 and a second direction D2, wherein the cell boundaries 304 and 204 of adjacent standard cells Cell-C1 and Cell-B2 along the first direction D1 overlap each other and share a dummy gate line 400. The cell boundaries 306 and 206 of adjacent standard cells Cell-C1 and Cell-B2 along the second direction D2 overlap each other. The standard cell Cell-C1 includes a plurality of gate lines 302 arranged along the first direction D1 between the two cell boundaries 304 of the standard cell Cell-C1 at a predetermined gate line pitch P and includes a gate line width LC (refer to Figure 4). The standard cell Cell-B2 includes a plurality of gate lines 202 arranged along the first direction Dl between two cell boundaries 204 of the standard cell Cell-B2 at a predetermined gate line pitch P, and includes a gate line width LB (refer to Figure 3 ). The gate line width LC is different from the gate line width LB by a variable (e.g., a second variable d2). The standard cell Cell-C1 includes a cell width WC1 between the cell boundaries 304, and the standard cell Cell-B2 includes a cell width WB2 between the cell boundaries 204, wherein the cell width WC1 is not equal to the cell width WB2, and is an integer multiple of the predetermined gate line pitch P, respectively. Since the cell width WC1 is not equal to the cell width WB2, the cell boundaries 204 and 304 of the integrated circuit layout 600 can be staggered along the second direction D2, the gate lines 202 can be aligned with the partial gate lines 302 along the second direction D2, the cell boundaries 204 can be aligned with a gate line 302 or a cell boundary 304 along the second direction D2, and the partial dummy gate lines 400 can be aligned with the gate lines 202 and / or the gate lines 302 along the second direction D2.

[0091] Please refer to Figure 7 , which is a plan view of an integrated circuit layout 700 according to an embodiment of the present application. Figure 7 As compared with Figure 5 The main difference is that, Figure 7 The integrated circuit layout 700 includes three kinds of standard cells with the same cell width, the same gate line pitch (e.g., the predetermined gate line pitch P), but different gate line widths. For example Figure 7 As shown in FIG. 7, the integrated circuit layout 700 can include the standard cell Cell-C1, the standard cell Cell-B1, and the standard cell Cell-A1. As viewed along the second direction D2, the cell boundaries 304, the cell boundaries 204, and the cell boundaries 104 can be aligned with each other, the gate lines 302, the gate lines 202, and the gate lines 102 can be aligned with each other, and the dummy gate lines 400 can be aligned with each other.

[0092] Please refer to Figure 8 , which is a plan view of an integrated circuit layout 800 according to an embodiment of the present application. Figure 8 As compared with Figure 7 The main difference is that, Figure 8 The integrated circuit layout 800 includes three kinds of standard cells with the same gate line pitch (e.g., the predetermined gate line pitch P), but different gate line widths, and at least two of the standard cells include different cell widths. For example Figure 8As shown, the integrated circuit layout 800 can include a standard cell Cell-C1, a standard cell Cell-B2, and a standard cell Cell-A1, where a cell width WB2 of the standard cell Cell-B2 is different from a cell width WC1 of the standard cell Cell-C1 and a cell width WA1 of the standard cell Cell-A1. Thus, the cell boundaries 304, 204, 104 of the integrated circuit layout 800 can be staggered along the second direction D2, the partial gate lines 302 can be aligned with the partial gate lines 202 along the second direction D2, the partial gate lines 102 can be aligned with the partial gate lines 202 along the second direction D2, the cell boundaries 204 can be aligned with a gate line 302 or a cell boundary 304 along the second direction D2, and the partial dummy gate lines 400 can be aligned with the gate lines 202, the gate lines 302, and / or the gate lines 302 along the second direction D2.

[0093] Subsequently, the integrated circuit layout can be subjected to layout modifications, such as optical proximity correction (OPC), and the modified integrated circuit layout can be output from the computer system to a set of photomasks for fabricating an integrated circuit structure on a semiconductor wafer. For example, the gate lines 102, 202, 302 can be used to form gate structures, such as polysilicon gate or metal gate structures, on a semiconductor substrate. The active region patterns 108, 208, 308 can be used to form active regions, such as fin-type active regions, on the semiconductor substrate. The dummy gate lines 400 can be used to form dummy gates, such as polysilicon dummy gates fabricated concurrently with polysilicon gates or metal dummy gates fabricated concurrently with metal gates, on the semiconductor substrate. It should be understood that the standard cells and integrated circuit layouts provided by the present application can also include other patterns, such as contact plugs, dummy active region patterns, ion implantation patterns, etc., which are not shown in the figures for simplicity of illustration.

[0094] In summary, the various standard cells provided by the present application include the same gate line pitch but different gate line widths, wherein the cell width of each standard cell is an integer multiple of the gate line pitch, and the gate lines are equally spaced between the cell boundaries of the standard cells along the row direction (i.e., the first direction D1) in a manner that evenly divides the cell width. When these standard cells are mixedly arranged along the row direction (i.e., the first direction D1) and the column direction (i.e., the second direction D2) to construct an integrated circuit layout, the gate lines and dummy gate lines of these standard cells can also be aligned along the column direction. In addition, the present application allows the cell boundaries to pass through the center lines of the dummy gate lines, so that the standard cells arranged along the row direction do not need any size or pattern adjustment, and the dummy gate lines can be shared while maintaining the original design size of the standard cells, thereby avoiding idle layout areas between adjacent standard cells and improving the space utilization. Overall, the integrated circuit layout of the present application can have a more regular and predictable layout result, which not only reduces the burden of automated layout, but also shortens the time spent on layout correction after design tape out, such as optical proximity correction (OPC). Furthermore, the more regular pattern of the present application is also beneficial for process control during wafer manufacturing to obtain the desired layout pattern on the wafer.

[0095] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. An integrated circuit layout structure, characterized in that, include: A first standard cell includes a plurality of first gate lines arranged along a first direction between two first cell boundaries of the first standard cell, wherein the first gate line includes a first gate line width and is spaced apart by a preset gate line spacing. as well as The second standard cell includes a plurality of second gate lines arranged along the first direction between two second cell boundaries. Each second gate line has a second gate line width and is spaced apart by a preset gate line spacing. The width of the first gate line is different from the width of the second gate line. The width of the first cell between the two first cell boundaries and the width of the second cell between the two second cell boundaries are integer multiples of the preset gate line spacing. The second standard cell is adjacent to one side of the first standard cell along a second direction, and at least a portion of the second gate lines are aligned with at least a portion of the first gate lines along the second direction. The first direction and the second direction are perpendicular to each other. The center line of each first gate line of the first standard unit divides the first standard unit into equal parts, and the center line of each second gate line of the second standard unit divides the second standard unit into equal parts.

2. The integrated circuit layout structure as described in claim 1, wherein the boundaries of the two second cells are respectively aligned with one of the first gate lines, or aligned with one of the boundaries of the two first cells.

3. The integrated circuit layout structure as described in claim 1, wherein the boundaries of the two first units are equidistant from the first gate line, and the boundaries of the two second units are equidistant from the second gate line.

4. The integrated circuit layout structure as described in claim 1 further includes a plurality of dummy gate lines, which overlap with the two first unit boundaries and the two second unit boundaries respectively, wherein the dummy gate lines are aligned with the first gate lines or the second gate lines along the second direction.

5. The integrated circuit layout structure as claimed in claim 4, wherein each of the dummy gate lines is divided into two equal parts by the first cell boundary or the second cell boundary.

6. The integrated circuit layout structure as described in claim 4, wherein the width of the dummy gate line is equal to the width of the first gate line or the width of the second gate line.

7. The integrated circuit layout structure as described in claim 4, wherein the width of the dummy gate line is not equal to the width of the first gate line and the width of the second gate line.

8. The integrated circuit layout structure as described in claim 4, wherein: The width of the second gate line is equal to the width of the first gate line plus a variable; The edges of the first gate lines are separated by a first gate line spacing, and the edges of the second gate lines are separated by a second gate line spacing, the second gate line spacing being smaller than the first gate line spacing and differing by that variable; and The edge of the dummy gate line is separated from the edge of the adjacent first gate line by a first dummy gate line spacing, and the edge of the dummy gate line is separated from the edge of the adjacent second gate line by a second dummy gate line spacing. The second dummy gate line spacing is smaller than the first dummy gate line spacing by a factor of 0.

5.

9. The integrated circuit layout structure of claim 4, wherein the first standard unit includes a plurality of first active region patterns extending along the first direction and arranged in parallel along the second direction, the second standard unit includes a plurality of second active region patterns extending along the first direction and arranged in parallel along the second direction, and the ends of the first active region patterns and the second active region patterns respectively overlap with the first gate lines, the second gate lines or the dummy gate lines.

10. The integrated circuit layout structure of claim 9, wherein the first active region patterns and the second active region patterns have the same width along the second direction.

11. The integrated circuit layout structure as described in claim 1, further comprising: A third standard cell, adjacent to one side of the first standard cell along the first direction, includes a plurality of third gate lines disposed along the first direction between two third cell boundaries of the third standard cell, wherein each third gate line includes a third gate line width and is spaced apart by a preset gate line spacing, the third gate line width is different from the first gate line width, and the width of the third cell between the two third cell boundaries is an integer multiple of the preset gate line spacing; and A dummy gate line is located between the first standard cell and the third standard cell, wherein the boundary of the first cell overlaps with the boundary of the third cell and also overlaps with the dummy gate line.

12. The integrated circuit layout structure of claim 11, wherein the dummy gate line is divided into two equal parts by the overlapping first cell boundary and the third cell boundary.

13. The integrated circuit layout structure of claim 11, wherein the first standard unit includes a plurality of first active region patterns extending along the first direction and arranged in parallel along the second direction, and the third standard unit includes a plurality of third active region patterns extending along the first direction and arranged in parallel along the second direction, wherein the first active region patterns and the third active region patterns are aligned along the first direction.

14. The integrated circuit layout structure of claim 13, wherein the first active region patterns and the third active region patterns have the same width.

15. The integrated circuit layout structure of claim 11, wherein the dummy gate line is aligned with one of the second gate lines or one of the two second cell boundaries along a second direction.

16. The integrated circuit layout structure of claim 11, wherein the width of the dummy gate line is equal to the width of the first gate line or the width of the second gate line.

17. The integrated circuit layout structure of claim 11, wherein the width of the dummy gate line is not equal to the width of the first gate line and the width of the second gate line.

18. The integrated circuit layout structure of claim 11, wherein the width of the third gate line is equal to the width of the first gate line plus a variable, the spacing between the third gate lines is less than the spacing between the first gate lines and differs from the variable, and the spacing between the third cell boundary and the third gate line is less than the spacing between the first cell boundary and the first gate line and differs from the variable by 0.5 times.

19. The integrated circuit layout structure of claim 11, wherein the width of the second gate line is equal to the width of the third gate line.

20. The integrated circuit layout structure of claim 11, wherein the width of the second gate line is not equal to the width of the third gate line.

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