Etching method

Abstract

This invention relates to an etching method. The etching method of this invention includes: a resist pattern forming step, in which a resist pattern is formed on a workpiece by a resist layer made of resin; an etching step, in which the workpiece is etched through the resist layer having the resist pattern; and a resist protective film forming step, in which a resist protective film is formed on the resist layer. The etching step is repeated multiple times. After the etching step is repeated multiple times, the resist protective film forming step is performed.

Description

Technical Field

[0001] This invention relates to etching methods. In particular, it relates to suitable techniques used in etching methods employing photoresist. Background Technology

[0002] Conventionally, components such as semiconductor components for electronic devices or parts for micro-mechanical components are manufactured from silicon substrates. At that time, it was known to manufacture components by using chemical etching (attack) of plasma anisotropically, such as the so-called Bosch process (Patent Document 1).

[0003] In addition, Patent Document 2 describes the following objective: to minimize or eliminate the problem of RIE-lag when processing such a component with a high aspect ratio.

[0004] Sometimes, recesses such as vias or trenches with high aspect ratios are formed on silicon wafers through dry etching. In this case, when recesses are formed on the same wafer with a mixture of patterns of different aspect ratios, the etching rate is higher in the low aspect ratio patterns compared to the high aspect ratio patterns. Therefore, a depth difference problem known as RIE-lag (Reactive Ion Etch-lag) exists.

[0005] "RIE-lag" is a phenomenon where the etching rate differs due to the size of the opening in the mask used in plasma etching. This difference in etching rate depends on the aspect ratio (the ratio of the depth to the width of the groove) of a via or trench.

[0006] Patent Document 1: US Patent No. 5,501,893

[0007] Patent Document 2: Japanese Patent Publication No. 2002-033313

[0008] For example, there is a problem where the resin resist disappears during fluorine- and oxygen-containing etching or ashing processes, such as those used to eliminate RIE-lag.

[0009] Therefore, for example, when performing dry etching of silicon, there is a problem that the accuracy of the formed pattern cannot be maintained due to an insufficient selection ratio between the etched object and the resin resist.

[0010] To prevent this problem, a film layer, known as a hard mask layer, needs to be stacked on top of a resist layer such as resin. This hard mask layer is a protective film formed of metal or the like that is resistant to fluorine-based or oxygen-based plasma gases.

[0011] However, forming the same pattern as the resin resist layer on a hard mask layer via photolithography is very difficult. For example, to form a pattern on a hard mask layer, a vacuum apparatus different from the vacuum apparatus used for etching or ashing with fluorine or oxygen gases is required. Additionally, an apparatus is needed for stacking hard mask layers, such as metals, onto the resist layer. Furthermore, in addition to treating the resin resist layer, apparatus is needed for etching and cleaning processes to form the pattern on the hard mask layer.

[0012] Therefore, the number of processes required to form vias or holes on silicon substrates increases, necessitating multiple devices. Furthermore, there is the problem of having to move the silicon substrate between multiple devices in a state where there is a high possibility of contamination.

[0013] Moreover, the following problem exists: even when the hard mask layer is stacked on the resin resist layer, erosion of the sides of the resin resist layer will occur, and the accuracy of the pattern of the resin resist layer will decrease.

[0014] In particular, in order to minimize the occurrence of problems caused by RIE-lag as described in Patent Document 2, there is a need to solve the problems related to the resin resist layer due to the use of plasma treatment with fluorine or oxygen gases as described above. Summary of the Invention

[0015] The present invention was made in view of the above circumstances, and aims to achieve the following objectives.

[0016] 1. In plasma treatment using fluorine or oxygen gases, prevent the thickness of the resin-based resist layer from decreasing or disappearing.

[0017] 2. Maintain the accuracy of the pattern formed when processing silicon etching, conductors, insulators, etc.

[0018] 3. In multi-stage silicon etching processes such as the so-called Bosch process, prevent the consumption of resist patterns and maintain the accuracy of the patterns formed on the resist layer.

[0019] 4. Even in processes where fine patterns are formed on other conductors or other insulators, the consumption of the resist pattern is prevented, and the accuracy of the pattern formed on the resist layer is maintained.

[0020] An etching method according to one aspect of the present invention includes: a resist pattern forming step, wherein a resist pattern is formed on a resist layer made of resin on a workpiece; an etching step, wherein the workpiece is etched through the resist layer having the resist pattern; and a resist protective film forming step, wherein a resist protective film is formed on the resist layer. The etching step is performed repeatedly, and the resist protective film forming step is performed after each repeated etching step. This solves the aforementioned problem.

[0021] In one aspect of the etching method of the present invention, the resist protective film formation process may use plasma film formation.

[0022] In one aspect of the etching method of the present invention, the processing gas used in the resist protective film formation step may contain substances capable of forming Si. x O y α z The gas.

[0023] In one aspect of the etching method of the present invention, the resist protective film formation process may be skipped until the etched state of the workpiece obtained by the etching process reaches a predetermined state.

[0024] In one aspect of the etching method of the present invention, the resist protective film formation process can be performed after the workpiece has been etched to obtain a specified aspect ratio.

[0025] In one aspect of the etching method of the present invention, the object to be processed may be made of silicon.

[0026] The etching method according to one aspect of the present invention may further include: a deposition step performed before the etching step; and an ashing step performed after the etching step. In the deposition step, a deposition layer may be formed on the workpiece using a first gas according to the resist pattern. In the etching step, the workpiece may be dry-etched using a second gas according to the resist pattern. In the ashing step, a third gas may be used. In the deposition step, the first gas may contain a fluorocarbon compound. In the etching step, the second gas may contain sulfur fluoride and silicon fluoride. In the ashing step, the third gas may contain oxygen. In the ashing step, the surface of the workpiece may be subjected to anisotropic plasma treatment having anisotropy in the direction of forming the recessed pattern. In the anisotropic plasma treatment, an alternating voltage may be applied to electrodes disposed opposite to the workpiece to generate inductively coupled plasma. The frequency of the AC voltage applied to the electrode at a position corresponding to the central portion of the surface of the workpiece is different from the frequency of the AC voltage applied to the electrode at a position corresponding to the outer periphery of the surface of the workpiece.

[0027] The etching method involved in one aspect of the present invention can prepare a plasma processing apparatus. The plasma processing apparatus may include: a chamber having a top cover having a central portion and an outer peripheral portion located outside the central portion, and the chamber being configured to perform plasma processing on the workpiece in an internal space capable of depressurization; a flat first electrode disposed within the chamber and used to hold the workpiece; a first power source configured to apply a bias voltage of a first frequency λ1 to the first electrode; a helical second electrode disposed outside the chamber and located on the opposite side of the top cover from the first electrode, and the second electrode being disposed in the central portion; a helical third electrode disposed outside the chamber and located on the opposite side of the top cover from the first electrode, and the third electrode being disposed on the outer peripheral portion outside the second electrode; a second power source applying an alternating voltage of a second frequency λ2 to the second electrode; a third power source applying an alternating voltage of a third frequency λ3 to the third electrode; a gas introduction device for introducing a fluorine-containing process gas into the chamber; and a solid source located within the chamber between the top cover and the first electrode, and configured to be closer to the top cover than the first electrode, the solid source being used for sputtering. When performing the anisotropic plasma treatment, if the second frequency λ2 and the third frequency λ3 are in a relationship of λ2 > λ3, the gas introduction device can be disposed in the central part of the upper cover.

[0028] One aspect of the present invention relates to an etching method comprising: a resist pattern forming step, wherein a resist pattern is formed on a resist layer made of resin on the workpiece; an etching step, wherein the workpiece is etched through the resist layer having the resist pattern; and a resist protective film forming step, wherein a resist protective film is formed on the resist layer. The etching step is performed repeatedly multiple times, and the resist protective film forming step is performed after each repeated etching step.

[0029] Therefore, by forming a resist protective film, it is possible to prevent or suppress the reduction of the thickness of the resist layer with the resist pattern or the removal of the resist layer during the etching process. Thus, the accuracy of the etching process on the workpiece can be maintained. Therefore, the film thickness of the resist layer forming the resist pattern can be reduced. Thus, the workpiece can be processed with low load.

[0030] Furthermore, pattern accuracy can be improved by reducing the thickness of the resist layer. By reducing the thickness of the resist layer, the etching method according to one aspect of the present invention can be applied even in photolithography (exposure processing) using short-wavelength exposure light. Simultaneously, since the resist's resistance to plasma and the like can be improved, plasma processing can be performed even when using resists that are brittle for plasma processing, which are conventionally unsuitable for plasma processing.

[0031] In one aspect of the etching method of the present invention, the resist protective film formation process uses plasma film formation.

[0032] Plasma film deposition methods include, for example, plasma CVD. This allows for the formation of a resist protective film via plasma CVD. Therefore, a resist protective film can be formed within the same chamber as the plasma apparatus used for the etching process.

[0033] In one aspect of the etching method of the present invention, the processing gas used in the resist protective film formation step contains substances capable of forming Si. x O y α z The gas.

[0034] Therefore, a resist protective film composed of silicon oxyfluoride (SiOF) can be formed on the resist pattern, which can prevent or inhibit the reduction of the thickness of the resist layer with the resist pattern or the removal of the resist layer during the etching process.

[0035] In addition, by forming a resist protective film composed of silicon fluoride oxyfluoride (SiOF), protective performance can be obtained with almost no impact on the resist pattern.

[0036] Here, if the processing gas in the resist protective film formation process is capable of forming Si x O y α z If the gas or mixture of gases is used, then the type of gas being processed is not limited. For example, as a gas capable of forming Si... x O y α z Examples of gases include a mixture of oxygen and at least one of SiF4, SiCl4, and SiH4 gases, or TEOS (tetraethyl orthosilicate Si(OC2H5)4) gas.

[0037] In one aspect of the etching method of the present invention, the resist protective film formation process is not performed until the etched state of the workpiece obtained by the etching process becomes a predetermined state.

[0038] In etching processes, such as deep etching of silicon substrates, the etching process is sometimes repeated a predetermined number of times. In such a cyclical etching process, where damage is minimal, such as a reduction in the thickness of the resist layer with the resist pattern, especially after the initial etching stage, the formation of a resist protective film may not be necessary. Therefore, for example, in a process where etching is not progressing and the etching depth is small, a resist protective film will not form on the bottom surface being etched. That is, it is possible to prevent a reduction in etching progress due to the formation of a resist protective film on the bottom surface. Furthermore, for example, when etching is progressing and the etching depth increases, a resist protective film will not form on the bottom surface. Thus, etching can be performed without reducing the etching progress.

[0039] In one aspect of the etching method of the present invention, after the workpiece is etched to obtain a specified aspect ratio through the etching process, the resist protective film formation process is performed.

[0040] In etching processes, such as deep etching of silicon substrates, the etching process is sometimes repeated a predetermined number of times. In such a cyclical etching process, if the aspect ratio of the etched area is not large at the beginning of the etching process and the damage, such as the reduction in the thickness of the resist layer with the resist pattern, is minimal, the formation of a resist protective film may not be necessary. Therefore, for example, in a process where etching is not progressing and the aspect ratio is small, a resist protective film will not form on the bottom surface processed by etching. That is, it is possible to prevent a reduction in the etching progress due to the formation of a resist protective film on the bottom surface. Furthermore, for example, if etching is progressing and the aspect ratio increases, a resist protective film will not form on the processed bottom surface. Thus, etching can be performed without reducing the etching progress.

[0041] In one aspect of the etching method of the present invention, the object to be processed is made of silicon.

[0042] This can improve the processing accuracy in the manufacturing of semiconductors, MEMS and other components using silicon substrates, reduce the number of processing steps and reduce processing costs.

[0043] An etching method according to one aspect of the present invention includes: a deposition step performed before the etching step; and an ashing step performed after the etching step. In the deposition step, a deposition layer is formed on the workpiece using a first gas according to the resist pattern. In the etching step, the workpiece is dry-etched using a second gas according to the resist pattern. In the ashing step, a third gas is used. In the deposition step, the first gas contains a fluorocarbon compound. In the etching step, the second gas contains sulfur fluoride and silicon fluoride. In the ashing step, the third gas contains oxygen. In the ashing step, the surface of the workpiece is subjected to anisotropic plasma treatment having anisotropy in the direction of forming the recessed pattern. In the anisotropic plasma treatment, an alternating current voltage is applied to an electrode disposed opposite to the workpiece to generate inductively coupled plasma. The frequency of the alternating current voltage applied to the electrode at a position corresponding to the central portion of the surface of the workpiece is different from the frequency of the alternating current voltage applied to the electrode at a position corresponding to the outer periphery of the surface of the workpiece.

[0044] Therefore, after removing the deposited layer in the region near the inner periphery of the opening of the resist pattern through an ashing process, a recessed pattern can be formed on the surface of the silicon substrate by a dry etching process. Thus, it is possible to prevent the formation of a pointed shape where the etching width of the recessed pattern becomes thinner as the etching depth increases due to the deposited layer in the region near the inner periphery of the opening of the resist pattern.

[0045] Furthermore, sometimes the deposition layer is formed by increasing the thickness of the deposition layer adhering to the bottom during the deposition process in recessed patterns with large openings, while decreasing the thickness of the deposition layer adhering to the bottom during the deposition process in recessed patterns with small openings. Even when such opening patterns with different diameters are formed simultaneously, the depth dimensions of the recessed patterns can be made equal, preventing RIE-lag. Moreover, even when using a resist layer with a thin resist pattern, the thickness of the resist layer will not decrease, and the resist layer will not disappear, allowing for etching processing.

[0046] In other words, the aforementioned silicon dry etching method utilizes the etching stop effect caused by deposition accumulation. As a result, it is possible to reduce the depth difference of the recessed patterns (holes or trenches, etc.) formed on the silicon substrate and having different dimensions.

[0047] An etching method according to one aspect of the present invention prepares a plasma processing apparatus. The plasma processing apparatus comprises: a chamber having a top cover having a central portion and an outer peripheral portion located outside the central portion, and the chamber being configured to perform plasma processing on the workpiece in an internal space capable of depressurization; a flat first electrode disposed within the chamber and used to hold the workpiece; a first power source configured to apply a bias voltage of a first frequency λ1 to the first electrode; a helical second electrode disposed outside the chamber and located on the opposite side of the top cover from the first electrode, and the second electrode being disposed in the central portion; a helical third electrode disposed outside the chamber and located on the opposite side of the top cover from the first electrode, and the third electrode being disposed on the outer peripheral portion outside the second electrode; a second power source applying an alternating voltage of a second frequency λ2 to the second electrode; a third power source applying an alternating voltage of a third frequency λ3 to the third electrode; a gas introduction device for introducing a fluorine-containing process gas into the chamber; and a solid source located within the chamber between the top cover and the first electrode, and configured to be closer to the top cover than the first electrode, the solid source being used for sputtering. When performing the anisotropic plasma treatment, the gas introduction device is disposed in the central part of the upper cover when the second frequency λ2 and the third frequency λ3 are in a relationship of λ2 > λ3.

[0048] Therefore, a solid-state source for sputtering is disposed between the upper cover and the first electrode within the chamber. Consequently, insufficient elements, such as oxygen, are sequentially introduced into the plasma from the solid-state source. Thus, oxygen is uniformly supplied to the silicon substrate, which is the object being processed, in the radial direction of the substrate.

[0049] Therefore, as described above, anisotropic plasma treatment can be performed on the surface of the silicon substrate by generating inductively coupled plasma with high anisotropy in the direction of forming the recessed pattern. Consequently, the sidewall shape of the recessed pattern formed on the silicon substrate remains approximately straight in the depth direction of the recessed pattern. Therefore, in the direction along the surface of the silicon substrate, regardless of the radial direction of the silicon substrate, i.e., at the outer periphery as well as the central portion of the silicon substrate, it is possible to stably fabricate recessed patterns (holes and trenches, etc.) with vertical (straight) shapes obtained by etching at the same location as the central portion of the silicon substrate.

[0050] Therefore, regardless of the substrate size and shape, it is possible to create a vertically shaped recessed pattern across the entire processing surface of a silicon substrate through etching. The recessed pattern described above can be formed on a silicon substrate with low load and using a thin resist layer with a resist pattern. During the process of forming this recessed pattern, the thickness of the resist layer with the resist pattern does not decrease, the resist layer does not disappear, and etching can be performed.

[0051] According to the present invention, in plasma processing using fluorine-based or oxygen-based gases, it is possible to prevent the thickness of the resin-based resist layer with the resist pattern from decreasing or disappearing. Furthermore, it is possible to achieve the following effect: thinner resist patterns can be used, thereby improving processing accuracy with lower load. Attached Figure Description

[0052] Figure 1 This is a schematic cross-sectional view of a silicon substrate that is a processed object manufactured by the etching method according to the first embodiment of the present invention.

[0053] Figure 2 This is a flowchart illustrating the etching method according to the first embodiment of the present invention.

[0054] Figure 3 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0055] Figure 4 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0056] Figure 5 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0057] Figure 6 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0058] Figure 7 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0059] Figure 8 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0060] Figure 9 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0061] Figure 10 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0062] Figure 11 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0063] Figure 12 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0064] Figure 13 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0065] Figure 14 This is a cross-sectional view showing the process of the etching method according to the first embodiment of the present invention.

[0066] Figure 15 This is a schematic cross-sectional view showing the apparatus used in the etching method according to the first embodiment of the present invention.

[0067] Figure 16 It means in Figure 15 The diagram showing the device, with two spiral electrodes arranged on the inner and outer circumferential sides and a power supply providing power at different frequencies to the two spiral electrodes, is a top view illustrating the connection positions of the spiral electrodes and the power supply.

[0068] Figure 17 It means in Figure 15 A cross-sectional view showing the relationship between the first electrode (outer diameter D) and the second electrode (outer diameter d) in the device shown.

[0069] Figure 18 This is a schematic cross-sectional view illustrating other examples of the apparatus used in the etching method according to the first embodiment of the present invention.

[0070] Figure 19 This is a schematic cross-sectional view illustrating other examples of the apparatus used in the etching method according to the first embodiment of the present invention.

[0071] Figure 20 This is a schematic cross-sectional view illustrating other examples of the apparatus used in the etching method according to the first embodiment of the present invention.

[0072] Figure 21 This is a schematic cross-sectional view illustrating other examples of the apparatus used in the etching method according to the first embodiment of the present invention.

[0073] Figure 22 This is a schematic cross-sectional view illustrating other examples of the apparatus used in the etching method according to the first embodiment of the present invention.

[0074] Figure 23 This is a schematic cross-sectional view showing a substrate of a processed object manufactured by the etching method according to the second embodiment of the present invention.

[0075] Figure 24 This is a flowchart illustrating the etching method according to the second embodiment of the present invention.

[0076] Figure 25 This is a cross-sectional view showing the process of the etching method according to the second embodiment of the present invention.

[0077] Figure 26 This is a cross-sectional view showing the process of the etching method according to the second embodiment of the present invention.

[0078] Figure 27 This is a cross-sectional view showing the process of the etching method according to the second embodiment of the present invention.

[0079] Figure 28 This is a schematic cross-sectional view showing a recessed pattern obtained by the etching method according to an embodiment of the present invention.

[0080] Figure 29 This is a schematic cross-sectional view showing the recessed pattern obtained by the etching method of the comparative example. Detailed Implementation

[0081] The etching method according to the first embodiment of the present invention will now be described with reference to the accompanying drawings.

[0082] Figure 1 This is a schematic cross-sectional view showing a silicon substrate manufactured by the etching method involved in this embodiment. Figure 2 This is a flowchart illustrating the etching method involved in this embodiment. Figure 1 In the figure, reference numeral S denotes a silicon substrate. The silicon substrate is an example of the object being processed.

[0083] The etching method described in this embodiment is a dry etching method for silicon, in which a silicon substrate S is used as the workpiece and a resist such as a protective resin is used while etching is performed. Furthermore, the etching method of the present invention is not limited to the embodiments described later, as long as etching can be performed while protecting the resist.

[0084] In the dry etching method for silicon described in this embodiment, such as Figure 1 As shown, recessed patterns VS and VL are formed on the surface of silicon substrate S.

[0085] The recessed pattern VS has a diameter dimension φS. The recessed pattern VL has a diameter dimension φL. The diameter dimension φL is set to be larger than the diameter dimension φS.

[0086] The depths of the recessed patterns VS and VL are set to be equal.

[0087] The recessed patterns VS and VL are formed into shapes with a high aspect ratio, for example, about 4 to 8, more preferably about 8 to 14.

[0088] In addition, the recessed patterns VS and VL can also penetrate the silicon substrate S.

[0089] like Figure 2 As shown, the silicon dry etching method according to this embodiment includes: a pretreatment process S01, a resist pattern formation process S02, a deposition process S03, a dry etching process S04, an ashing process S05, a depth determination process S06a, a resist protection determination process S06, a resist protective film formation process S07, and a post-treatment process S08.

[0090] exist Figure 2 In the pretreatment process S01 shown, the silicon substrate S is pretreated by heat treatment at 200°C or above using a known lamp heater or the like.

[0091] Figure 3 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0092] exist Figure 2 In the resist pattern forming process S02 shown, as Figure 3 As shown, a patterned resist layer M is formed on the surface of a silicon substrate S. The resist layer M is an example of a mask layer.

[0093] The resist layer M can be formed from a known resin resist. The resist layer M can be formed to a specified thickness by appropriately selecting the positive and negative modes, exposure wavelength, coating method, film formation method, and other conditions. As examples of materials constituting the resist layer M, photosensitive insulators and other known materials can be cited.

[0094] Furthermore, in the resist pattern forming process S02, such as Figure 3As shown, opening patterns MS and ML are formed on the resist layer M. The opening pattern MS is a pattern for setting the opening of the processing area in a manner corresponding to the shape of the recessed pattern VS in the silicon substrate S. The opening pattern ML is a pattern for setting the opening of the processing area in a manner corresponding to the shape of the recessed pattern VL in the silicon substrate S. Each of the opening patterns MS and ML is an example of a mask pattern.

[0095] Specifically, in the resist patterning process S02, a resist layer M, which serves as a photoresist, is stacked on a silicon substrate S, and then subjected to processes such as exposure and development. Furthermore, the resist layer M is subjected to known processes such as wet etching and dry etching. Thus, a resist layer M having opening patterns MS and ML is formed on the silicon substrate S.

[0096] Figure 4 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0097] exist Figure 2 In the deposition process S03 shown, as Figure 4 As shown, an anisotropic plasma treatment is used to form a deposition layer D1 composed of polymers such as fluorocarbons on the entire surface of the silicon substrate S. The deposition layer D1 protects the sidewalls of the recessed patterns VS and VL from etching in the dry etching process S04.

[0098] Deposited layer D1 is formed to protect the sidewalls VSq and VLq of the recessed patterns VS and VL from etching and to define the bottom VSb and VLb of the recessed patterns VS and VL for etching. Thus, in the dry etching process S04, which is an etching process using fluorine compounds, vertical sidewalls VSq and VLq can be obtained.

[0099] Deposited layer D1 is stacked on the surface of resist layer M and at the bottom of recessed patterns VS and VL, VSb and VLb. Additionally, in Figure 4 In the diagram, the deposition layer D1 is shown in the sidewalls VSq and VLq of the recessed patterns VS and VL, but in reality, the deposition layer D1 hardly overlaps with the sidewalls VSq and VLq.

[0100] In the deposition process S03, plasma treatment is performed using perfluorinated hydrocarbon gases such as CHF3, C2F6, C2F4, or C4F8. Here, the plasma treatment apparatus 10, described later, is used.

[0101] At this time, in the plasma processing apparatus 10, the frequency λ2 (high frequency) of the power applied to the second electrode E2 (inner electrode) located on the inner periphery side (described later) can be set to be greater than the frequency λ3 (high frequency) of the power applied to the third electrode E3 (outer electrode) located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz. In the deposition process S03, the maximum power supplied to the electrodes located on the inner and outer periphery sides is the value of the power output by the power supply. As a result, the ashing rate can be improved.

[0102] Furthermore, in the plasma processing apparatus 10, the power with frequency λ2 applied to the second electrode E2 located on the inner periphery side, as described later, can be set to be less than the power values ​​in the dry etching process S04 and the ashing process S05, as described later. Additionally, in the plasma processing apparatus 10, a bias voltage can be omitted from the first electrode 12.

[0103] In the atmosphere of deposition step S03, a specified pressure is set for deposition treatment. Furthermore, in deposition step S03, a specified amount of rare gas such as Ar can also be added to the gas used for deposition treatment.

[0104] Regarding the film thickness of the deposited layer D1 formed in deposition process S03, the film thickness of the deposited layer D1 formed on the bottom VLb corresponding to the large-diameter opening pattern ML is greater than the film thickness of the deposited layer D1 formed on the bottom VSb corresponding to the small-diameter opening pattern MS. Furthermore, the film thickness of the deposited layer D1 on the bottom VLb of the opening pattern ML is equal to or smaller than the film thickness of the deposited layer D1 on the surface of the resist layer M located outside the opening patterns MS and ML.

[0105] That is, the thickness of the deposited layer D1 decreases in the following order: the thickness TD1 of the deposited layer D1 on the surface of the resist layer M outside the opening patterns MS and ML, the thickness TLD1 of the deposited layer D1 on the bottom VLb of the opening pattern ML, and the thickness TSD1 of the deposited layer D1 on the bottom VSb of the opening pattern MS.

[0106] In deposition step S03, by setting the deposition conditions as described above, the deposition coverage of the deposition layer D1 on the bottom VSb and VLb corresponding to the opening patterns MS and ML can be optimized. Here, the most ideal condition for forming the deposition coverage is to shorten the processing time for stacking the deposition layer D1 with the required film thickness on the bottom VSb and VLb. That is, the most ideal condition for forming the deposition coverage is to increase the film formation rate of stacking the deposition layer D1 on the bottom VSb and VLb.

[0107] Furthermore, the ideal conditions for forming the deposition cover are to adjust the deposition cover according to the etching depth and aspect ratio. That is, as described later, even when the aspect ratio changes corresponding to the depth variation of the bottom VSb and VLb, it is possible to form a deposition layer D1 with the desired thickness at a specified film formation rate.

[0108] Furthermore, the uniformity and reliability of the deposition layer D1 stacked on the bottom VSb and the uniformity and reliability of the deposition layer D1 stacked on the bottom VLb are improved respectively.

[0109] Figure 5 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0110] exist Figure 2 In the dry etching process S04 shown, as Figure 5 As shown, anisotropic plasma etching is used to excavate the bottom VSb and VLb corresponding to the opening patterns MS and ML to reduce the position of the bottom VSb and VLb, thereby forming the bottom VSb1 and VLb1.

[0111] At this time, based on the processing conditions in the dry etching process S04, the anisotropy of the plasma, and the thickness difference of the deposited layer D1 stacked through the deposition process S03, the depths of the bottom VSb1 corresponding to the opening pattern MS and the bottom VLb1 corresponding to the opening pattern ML formed in the dry etching process S04 are made uniform.

[0112] Specifically, the film thickness TSD1 of the deposited layer D1 stacked on the bottom VSb corresponding to the opening pattern MS is less than the film thickness TLD1 of the deposited layer D1 stacked on the bottom VLb corresponding to the opening pattern ML. Furthermore, the etching amount of the bottom VSb corresponding to the opening pattern MS is less than the etching amount of the bottom VLb corresponding to the opening pattern ML. Therefore, the film thickness formed by the above deposition and the etching amount performed by the above etching cancel each other out, and the depths of the bottom VSb1 corresponding to the opening pattern MS and the bottom VLb1 corresponding to the opening pattern ML become uniform.

[0113] Furthermore, in the dry etching process S04, the effects of etching on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML are greatly reduced due to the processing conditions, the anisotropy of the plasma, and the deposited layer D1. As a result, the sidewalls VSq and VLq are perpendicular to the surface of the silicon substrate S and are formed as approximately the same plane. Therefore, the sidewalls VSq and VLq, without any irregularities, are formed to extend in the depth direction.

[0114] That is, the bottom VSb1 and VLb1 are formed in such a way that the concave patterns VS and VL have uniform diameter dimensions.

[0115] To achieve this shape, in the dry etching process S04, a plasma processing apparatus 10, described later, is used to generate a plasma with high anisotropy.

[0116] At this time, in the plasma processing apparatus 10, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to a frequency λ3 greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0117] Furthermore, in the plasma processing apparatus 10, the value of the supply power at the frequency λ2 applied to the second electrode E2 located on the inner periphery side, as described later, can be set to be greater than the value of the supply power in the deposition process S03, and can be set to the same value as the value of the supply power in the ashing process S05.

[0118] Furthermore, in the plasma processing apparatus 10, the supply power at frequency λ2 applied to the second electrode E2 located on the inner periphery side, as described later, can be set to be the same as the supply power at frequency λ3 applied to the third electrode E3 located on the outer periphery side.

[0119] Furthermore, in the plasma processing apparatus 10, it is preferable to apply a bias voltage having a frequency λ1 to the first electrode 12. The frequency λ1 can be set to a value lower than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery. For example, the frequency λ1 can be 400 kHz.

[0120] Furthermore, in the anisotropic plasma etching process S04 of the dry etching step, Si is anisotropically etched by decomposing a mixture of SF6 and O2 using plasma. As a result, F radicals generated from the decomposition of SF6 etch Si (F + Si → SiF4). Since this etching reaction is isotropic, an insulating layer (protective film) can be attached to the sidewalls VSq and VLq to suppress the etching reaction on the sidewalls VSq and VLq in order to perform anisotropic etching.

[0121] In the SF6 / O2 mixed gas anisotropic plasma etching process S04, the deposited layer D1 is removed from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML to expose the sidewalls VSq and VLq.

[0122] Here, in the anisotropic plasma etching using a mixed gas of SF6 / O2 in the dry etching process S04, the sidewalls VSq and VLq can also be protected by forming an insulating layer. Simultaneously, the sidewalls VSq and VLq are oxidized by oxygen (O) and SiO2 is also protected. x The SiO2 film is deposited to protect the sidewalls VSq and VLq. xThe deposited film is generated by reacting Si and O obtained by the further decomposition of SiF4, which is an etching product.

[0123] In addition, in the dry etching process S04, SiF4 can be used as the etching gas to prevent insufficient SiF4 as the etching product.

[0124] Furthermore, in the dry etching process S04, SF6 or NF3 is used as the etching gas, and SiF4, as a silicon compound, is added to the etching gas, along with O2, N2, N2O, NO, and NO2 as reactants. x Or CO2. This allows for concentrated etching of the bottom VSb and VLb.

[0125] Furthermore, in the dry etching process S04, by using an electrostatic chuck with an internal coolant path for the first electrode 12 to set the temperature of the substrate being processed to a low temperature, the degree of anisotropy can be improved. For example, the temperature of the coolant flowing in the coolant path is set to below 10°C.

[0126] Figure 6 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0127] exist Figure 2 In the ashing process S05 shown, as Figure 6 As shown, the residual deposited layer D1 after the dry etching process S04 is removed.

[0128] In particular, in the ashing process S05, the ashing conditions are set in a way that the deposited layer D1 remaining in the area near the inner periphery of the opening pattern MS and the opening pattern ML of the resist layer M is reliably removed.

[0129] In the ashing process S05, the deposited layer D1 adhering to the surface of the resist layer M after the dry etching process S04, the deposited layer D1 remaining in the area near the inner periphery of the opening patterns MS and ML of the resist layer M, and the deposited layer D1 remaining on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML are removed. Additionally, if there is a deposited layer D1 remaining on the bottom VSb1 corresponding to the opening pattern MS and a deposited layer D1 remaining on the bottom VLb1 corresponding to the opening pattern ML, this residue is removed.

[0130] In the ashing process S05, sometimes the deposited layer D1 remaining at the inner periphery of the opening pattern MS and the opening pattern ML may not be completely removed. This is not preferable, as will be described later. Specifically, when performing the second cycle of the deposition process S03 in a series of cycles including deposition process S03, dry etching process S04, and ashing process S05 (first cycle, second cycle, etc.), sometimes a further deposited layer D2 may accumulate on the remaining deposited layer D1. In this case, the opening diameter (opening area) of the opening patterns MS and ML in the resist layer M will decrease.

[0131] As described above, if the opening diameters of the opening patterns MS and ML in the resist layer M are reduced, even in the dry etching process S04 of the second cycle following the ashing process S05 of the first cycle, where etching with increased anisotropy is performed, the etching plasma will still be hindered from reaching the bottom VSb1 and bottom VLb1 by the deposited layers D1 and D2. Therefore, etching in the bottom VSb1 and bottom VLb1 may not be performed properly. Consequently, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML become non-perpendicular, and the shapes of the recessed patterns VS and VL may become pointed.

[0132] In contrast, when no deposited layer D1 remains at the inner periphery of both the opening pattern MS and the opening pattern ML, in the second deposition cycle S03 following the first cycle, no further deposited layer D2 will be deposited on the remaining deposited layer D1. Therefore, the opening shapes of the opening patterns MS and ML in the resist layer M can be maintained in a manner where the opening diameters of the opening patterns MS and ML are of a predetermined size.

[0133] Then, in the dry etching process S04 of the second cycle, etching with increased anisotropy is performed so that the etching plasma is not hindered from reaching the bottom VSb1 and bottom VLb1 by the deposited layers D1 and D2. Therefore, by properly etching the bottom VSb1 and bottom VLb1, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML extend in a vertical state. Therefore, by preventing the shapes of the recessed patterns VS and VL from becoming pointed, each recessed pattern in the recessed patterns VS and VL with the same diameter can be formed in the depth direction with a high aspect ratio.

[0134] In the first cycle of the ashing process S05, as described above, in order to reliably remove the deposited layer D1 remaining at the inner periphery of the opening patterns MS and ML, it is necessary to subject the used gas O2 to plasma treatment with a high degree of dissociation. For this purpose, the plasma treatment apparatus 10, described later, is also used in the first cycle of the ashing process S05.

[0135] At this time, in the plasma processing apparatus 10 used in the first cycle of ashing process S05, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to a frequency λ3 greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0136] In addition, in the plasma processing apparatus 10 used in the ashing process S05 of the first cycle, the value of the supply power of the frequency λ2 applied to the second electrode E2 located on the inner periphery side, which will be described later, can be set to be greater than the value of the supply power in the deposition process S03, and can be set to be the same as or higher than the value of the supply power in the dry etching process S04.

[0137] Furthermore, in the plasma processing apparatus 10 used in the ashing process S05 of the first cycle, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner periphery side (described later) can be set to be the same as the supply power value of the frequency λ3 applied to the third electrode E3 located on the outer periphery side.

[0138] Furthermore, in the plasma processing apparatus 10 used in the first cycle of the ashing process S05, a bias voltage with a frequency λ1 is preferably applied to the first electrode 12. The frequency λ1 can be set to a frequency λ3 lower than the power applied to the third electrode E3 located on the outer periphery side. The power of the bias voltage in the first cycle of the ashing process S05 can be set to be equal to the power of the bias voltage in the first cycle of the dry etching process S04, or it can be set to be higher than the power of the bias voltage in the first cycle of the dry etching process S04.

[0139] In the first cycle of the ashing process S05, O2 gas is supplied for ashing. During the anisotropic plasma treatment using O2 gas, the deposited layer D1 is reliably removed from the portion near the inner periphery of the opening patterns MS and ML, and from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML, exposing the sidewalls VSq and VLq. Simultaneously, in the first cycle of the ashing process S05, O2 gas is supplied for ashing. In this process, the resin-based resist layer M is also partially removed, thereby reducing the film thickness of the resist layer M.

[0140] like Figure 2As shown, the silicon dry etching method involved in this embodiment includes a deposition process S03, a dry etching process S04, an ashing process S05, a depth determination process S06a, and a resist protection determination process S06.

[0141] In other words, the deposition process S03, the dry etching process S04, the ashing process S05, the depth determination process S06a, and the resist protection determination process S06 form a cycle. This cycle is sometimes referred to as a "repeated cycle." Alternatively, it can be called a "substrate processing cycle." In this embodiment, this cycle is repeated multiple times at a predetermined frequency. In other words, the dry etching process S04 is performed repeatedly. Since one cycle includes an etching process, it can also be called an etching cycle.

[0142] Based on the determination result of the depth determination process S06a, sometimes a resist protective film formation process S07 is performed after the end of the cycle. In other words, sometimes a resist protective film formation process S07 is performed after repeatedly performing multiple dry etching processes S04.

[0143] Therefore, in the dry etching method for silicon involved in this embodiment, not only can the depth of the recessed patterns VS and VL be increased through the steps S03, S04, and S05, but the depth of the recessed patterns VS and VL and whether a resist protective film is needed can also be determined.

[0144] In the depth determination process S06a, it is determined whether to proceed to the next resist protection determination process S06. At this time, the determination criteria in the depth determination process S06a are based on the depth of the recessed patterns VS and VL, in other words, based on the aspect ratio of the recessed patterns VS and VL.

[0145] If, in the depth determination process S06a, it is determined that the depth of the recessed patterns VS and VL is insufficient (determination result: No), it is determined that the next etching cycle is required, and the process proceeds to the resist protection determination process S06. In the resist protection determination process S06, it is determined whether to proceed to the resist protective film formation process S07, which will be described later.

[0146] On the other hand, when it is determined in the depth determination process S06a that the depth of the recessed patterns VS and VL is sufficient (determination result: yes), the etching ends and the process proceeds to the post-processing process S08.

[0147] In the resist protection judgment step S06, it is determined whether to proceed to the next cycle, which includes the next etching step, without performing the resist protection film formation step S07, or to proceed to the resist protection film formation step S07, which will be described later.

[0148] Here, as the judgment criterion in the resist protection judgment process S06, the judgment is based on the depth of the recessed patterns VS and VL.

[0149] When it is determined that the depth of the recessed patterns VS and VL is insufficient (determination result: no), the process proceeds to the deposition process S03, which is the initial process of the next cycle.

[0150] The reason for proceeding to the next cycle without performing the resist protective film formation process S07 is as follows.

[0151] When the depth of the recessed patterns VS and VL is insufficient, if the resist protective film Mm is formed in the resist protective film formation process S07 (described later), undesirable conditions may occur. Specifically, in the resist protective film formation process S07, the resist protective film Mm is formed not only on the surface of the resist layer M, but also at the bottom VSb and VLb of the opening patterns MS and ML. When the resist protective film Mm is formed at the bottom VSb and VLb of the opening patterns MS and ML, it may have an undesirable effect on the silicon substrate S, such as no etching progress at the bottom VSb and VLb, leading to undesirable etching conditions.

[0152] As the judgment criterion in the resist protection judgment process S06, the judgment is based on the depth of the recessed patterns VS and VL. In other words, the judgment is based on the aspect ratio of the recessed patterns VS and VL. Specifically, when the aspect ratio of the recessed patterns VS and VL is, for example, about 1 to 2 (judgment result: no), a cycle including the next etching process is performed.

[0153] When the aspect ratio of the recessed patterns VS and VL is approximately 3 to 4 (judgment result: yes), the process proceeds to the resist protective film formation step S07, which will be described later. That is, the resist protection judgment step S06 is performed based on the opening area of ​​the recessed patterns VS and VL and the etching amount of the bottom VSb and VLb in the first cycle of etching.

[0154] Furthermore, the judgment in the resist protection judgment step S06 can also be made after the first cycle, based on the results of measuring the depths of the recessed patterns VS and VL in the silicon substrate S. Additionally, the judgment in the resist protection judgment step S06 can also be used to determine the transition to the second cycle by analogy with the etching conditions in the first cycle. In the judgment based on etching conditions, an etching depth related to the specified conditions is preset for the judgment.

[0155] Next, we will explain the case where a second cycle is performed without the resist protective film formation process S07.

[0156] Figure 7This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0157] Figure 2 The second cycle deposition step S03 shown is performed after the depth determination step S06a and the resist protection determination step S06. In the second cycle deposition step S03, as... Figure 7 As shown, an anisotropic plasma treatment is used to form a deposition layer D2 composed of polymers such as fluorocarbons on the entire surface of the silicon substrate S. The sidewalls of the recessed patterns VS and VL are protected from etching during the dry etching process S04, which is performed after the second deposition process S03.

[0158] Deposited layer D2 is formed to protect the sidewalls VSq and VLq of the recessed patterns VS and VL from etching and to define the bottom VSb1 and VLb1 of the recessed patterns VS and VL for etching. Thus, in the dry etching process S04 performed after the second deposition process S03, the vertical sidewalls VSq and VLq can be obtained by etching using fluorine compounds.

[0159] Deposited layer D2 is stacked on the surface of resist layer M and at the bottom of recessed patterns VS and VL, VSb1 and VLb1. Additionally, in Figure 7 In the diagram, the deposition layer D2 is shown in the sidewalls VSq and VLq of the recessed patterns VS and VL, but in reality, the deposition layer D2 hardly overlaps with the sidewalls VSq and VLq.

[0160] The deposition process S03 in the second cycle is the same as that in the first cycle. That is, anisotropic plasma treatment is performed using perfluorinated hydrocarbon gas. In deposition process S03, the plasma treatment apparatus 10, described later, is used, just as in the first cycle.

[0161] For the second deposition process S03, in the plasma processing apparatus 10, the frequency λ2 of the power applied to the second electrode E2, the frequency λ3 of the power applied to the third electrode E3, and the atmospheric pressure, etc., can be set to be the same as in the first cycle of deposition process S03. Here, the processing conditions in the deposition process S03 performed after the second cycle can be the same as or different from those in the first cycle of deposition process S03.

[0162] Furthermore, the processing conditions in the second deposition process S03 can be the same as those in the first deposition process S03, but can also be those that take into account the decrease in deposition rate of the bottom VSb1 and VLb1 of the concave patterns VS and VL.

[0163] For example, the power applied to the second electrode E2 located on the inner periphery can be increased, the power applied to the third electrode E3 located on the outer periphery can be increased, and the power applied to electrodes E2 and E3 can also be increased. In order to introduce deposited particles into the silicon substrate S, a bias voltage can be applied to the first electrode 12.

[0164] The thickness of the deposited layer D2 formed in the second deposition cycle S03 is the same as that in the first deposition cycle S03. That is, the thickness of the deposited layer D2 formed on the bottom VLb1 corresponding to the large-diameter opening pattern ML is greater than the thickness of the deposited layer D2 formed on the bottom VSb1 corresponding to the small-diameter opening pattern MS. Furthermore, the thickness of the deposited layer D2 in the bottom VLb1 of the opening pattern ML is equal to or smaller than the thickness of the deposited layer D2 on the surface of the resist layer M located outside the opening patterns MS and ML.

[0165] That is, the thickness of the deposited layer D2 decreases in the following order: TD2 on the surface of the resist layer M located outside the opening patterns MS and ML, TLD2 on the bottom VLb1 of the opening pattern ML, and TSD2 on the bottom VSb1 of the opening pattern MS.

[0166] In the deposition process S03 of the second cycle, by setting the deposition conditions as described above, the deposition coverage of the deposition layer D2 on the bottom VSb1 and VLb1 corresponding to the opening patterns MS and ML can be optimized. Here, the most ideal condition for forming the deposition coverage is to shorten the processing time for stacking the deposition layer D2 with the required film thickness on the bottom VSb1 and VLb1. That is, the preferred condition for forming the deposition coverage is to increase the film formation rate of stacking the deposition layer D2 on the bottom VSb1 and VLb1.

[0167] In the second cycle's deposition process S03, the ideal conditions for forming the deposition cover are those that adjust the deposition cover according to the etching depth and aspect ratio. That is, as described later, the depths of the bottom VSb and VLb differ from the depths of the bottom VSb1 and VLb1, resulting in a change in the bottom depth. Even when the aspect ratio changes corresponding to this change in bottom depth, it is possible to form a deposition layer D2 with the desired thickness at a specified deposition rate.

[0168] Furthermore, the most ideal conditions for forming a sedimentary cover are to improve the uniformity and certainty of the sedimentary layer D2 superimposed on the bottom VSb1 and the sedimentary layer D2 superimposed on the bottom VLb1.

[0169] Furthermore, the processing time of the second cycle deposition step S03 can be made longer than that of the first cycle deposition step S03. This same processing time setting applies to deposition steps S03 performed after the third cycle.

[0170] Figure 8 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0171] exist Figure 2 In the second cycle of dry etching process S04 shown, as Figure 8 As shown, anisotropic plasma etching is used to excavate the bottom VSb1 and VLb1 corresponding to the opening patterns MS and ML to reduce the position of the bottom VSb1 and VLb1, thereby forming the bottom VSb2 and VLb2.

[0172] At this point, based on the processing conditions in the second cycle dry etching process S04, the anisotropy of the plasma, and the film thickness difference of the deposited layer D2 stacked through the second cycle deposition process S03, the depths of the bottom VSb2 corresponding to the opening pattern MS and the bottom VLb2 corresponding to the opening pattern ML formed in the dry etching process S04 are set to be uniform.

[0173] Specifically, the film thickness TSD2 of the deposited layer D2 stacked on the bottom VSb1 corresponding to the opening pattern MS is less than the film thickness TLD2 of the deposited layer D2 stacked on the bottom VLb1 corresponding to the opening pattern ML. Furthermore, the etching amount of the bottom VSb1 corresponding to the opening pattern MS is less than the etching amount of the bottom VLb1 corresponding to the opening pattern ML. Therefore, the film thickness formed by the above deposition and the etching amount performed by the above etching cancel each other out, and the depths of the bottom VSb2 corresponding to the opening pattern MS and the bottom VLb2 corresponding to the opening pattern ML become uniform.

[0174] Furthermore, in the second cycle's dry etching process S04, the impact of etching on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML is greatly reduced based on the processing conditions, plasma anisotropy, and the deposited layer D2. Consequently, the sidewalls VSq and VLq are perpendicular to the surface of the silicon substrate S and are formed as approximately the same plane. Therefore, the sidewalls VSq and VLq, without any irregularities, are formed extending in the depth direction.

[0175] That is, the bottom VSb2 and VLb2 are formed in such a way that the concave patterns VS and VL have uniform diameter dimensions.

[0176] To achieve this shape, a highly anisotropic plasma treatment is also performed in the second cycle of the dry etching process S04. The second cycle of the dry etching process S04 uses the plasma treatment apparatus 10 described later.

[0177] At this time, the processing conditions of the plasma processing device 10 used in the second cycle dry etching process S04 can be set to the same conditions as those in the first cycle dry etching process S04.

[0178] Furthermore, in the second cycle of dry etching process S04, the setting conditions of the plasma processing apparatus 10 are the same as those in the first cycle of dry etching process S04. That is, the value of the supply power of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to be greater than the value of the supply power in the second cycle of deposition process S03, and can be set to be the same as the value of the supply power in the second cycle of ashing process S05.

[0179] Furthermore, in the second cycle of dry etching process S04, the setting conditions of the plasma processing apparatus 10 are the same as those in the first cycle of dry etching process S04. That is, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner peripheral side, as described later, can be set to be the same as the supply power value of the frequency λ3 applied to the third electrode E3 located on the outer peripheral side.

[0180] Furthermore, in the second cycle of dry etching process S04, the settings of the plasma processing apparatus 10 are the same as in the first cycle of dry etching process S04. Preferably, a bias voltage with frequency λ1 is applied to the first electrode 12. Frequency λ1 can be set to a frequency λ3 lower than the power applied to the third electrode E3 located on the outer periphery. Frequency λ1 can be set, for example, to 400 kHz.

[0181] Furthermore, the anisotropic plasma etching in the dry etching process S04 of the second cycle is the same as in the first cycle. That is, anisotropic etching of Si is performed by decomposing the mixed gas of SF6 and O2 through plasma. As a result, the F radicals generated by the decomposition of SF6 etch Si (F + Si → SiF4). Since this etching reaction is isotropic, a protective film can be attached to the sidewalls VSq and VLq to suppress the etching reaction of the sidewalls VSq and VLq in order to perform anisotropic etching.

[0182] The anisotropic plasma etching using a mixed gas of SF6 / O2 in the second cycle's dry etching process S04 is the same as in the first cycle's dry etching process S04. That is, the deposited layer D2 is removed from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML to expose the sidewalls VSq and VLq.

[0183] Here, the anisotropic plasma etching using a mixed gas of SF6 / O2 in the second cycle's dry etching process S04 is the same as in the first cycle's dry etching process S04. That is, the sidewalls VSq and VLq can also be protected by forming an insulating layer. Simultaneously, the sidewalls VSq and VLq are oxidized by oxygen (O) and SiO2 is also present. x The SiO2 film is deposited to protect the sidewalls VSq and VLq. x The deposited film is generated by reacting Si and O obtained by the further decomposition of SiF4, which is an etching product.

[0184] In addition, in the second cycle of dry etching process S04, similar to the first cycle of dry etching process S04, SiF4 can also be used as etching gas to prevent insufficient SiF4 as the etching product.

[0185] Furthermore, the dry etching process S04 in the second cycle is the same as that in the first cycle. That is, SF6 or NF3 is used as the etching gas, SiF4 as a silicon compound is added to the etching gas, and O2, N2, N2O, NO, and NO are added as reactants. x Or CO2. This allows for concentrated etching of the bottom VSb1 and VLb1.

[0186] Furthermore, the processing time of the second cycle dry etching process S04 can be made longer than that of the first cycle dry etching process S04. This same processing time setting applies to the dry etching processes S04 performed after the third cycle.

[0187] Figure 9 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0188] exist Figure 2 In the second cycle of ashing process S05 shown, as Figure 9 As shown, the residual deposited layer D2 is removed after the dry etching process S04 in the second cycle.

[0189] In particular, in the ashing process S05 of the second cycle, the ashing conditions are set in a way that the deposited layer D2 remaining in the area near the inner periphery of the opening pattern MS and the opening pattern ML of the resist layer M is reliably removed.

[0190] The ashing process S05 of the second cycle is the same as that of the ashing process S05 of the first cycle. It removes the deposited layer D2 that adheres to the surface of the resist layer M after the dry etching process S04 of the second cycle, the deposited layer D2 that remains in the area near the inner periphery of the opening patterns MS and ML of the resist layer M, and the deposited layer D2 that remains on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML.

[0191] Furthermore, if there is a deposition layer D2 remaining on the bottom VSb2 corresponding to the opening pattern MS and a deposition layer D2 remaining on the bottom VLb2 corresponding to the opening pattern ML, then the deposition layer D2 is removed.

[0192] Here, the most important step is to remove the residual deposited layer D2 at the inner periphery of the opening pattern MS and the opening pattern ML. If the deposited layer D2 is not completely removed and remains, and the next deposition process S03 is performed in a repeated cycle, a further deposited layer D3 will be deposited on the remaining deposited layer D2. In this case, the opening diameter of the opening patterns MS and ML in the resist layer M will be reduced.

[0193] As described above, if the opening diameters of the opening patterns MS and ML in the resist layer M are reduced, even in the dry etching process S04, which is the third cycle after the second cycle and involves etching with increased anisotropy, the etching plasma will still be hindered from reaching the bottom VSb2 and bottom VLb2 due to the deposition layers D2 and D3. Therefore, etching in the bottom VSb2 and bottom VLb2 cannot be performed properly, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML become non-perpendicular, and the shapes of the recessed patterns VS and VL may become pointed.

[0194] In contrast, when no deposited layer D2 remains at the inner periphery of both the opening pattern MS and the opening pattern ML, in the third deposition process S03, which is performed after the second cycle in the repeated cycle, no further deposited layer D3 will be deposited on the remaining deposited layer D2. Therefore, the opening diameters of the opening patterns MS and ML in the resist layer M can be maintained at a predetermined size.

[0195] Therefore, in the dry etching process S04 of the third cycle in the repeated cycle, by performing etching with an increased degree of anisotropy, the etching plasma is not hindered from reaching the bottom VSb2 and bottom VLb2 by the deposited layers D2 and D3. Thus, by appropriately etching the bottom VSb2 and bottom VLb2, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML extend in a vertical state. Therefore, by preventing the recessed patterns VS and VL from becoming pointed, each recessed pattern in the recessed patterns VS and VL with the same diameter can be formed in the depth direction with a high aspect ratio.

[0196] In the second cycle of the ashing process S05, as described above, the deposited layer D2 remaining at the inner periphery of the opening patterns MS and ML is reliably removed. Therefore, similar to the first cycle of the ashing process S05, it is necessary to generate a plasma with high anisotropy. Therefore, in the second cycle of the ashing process S05, the plasma processing apparatus 10, described later, is also used.

[0197] At this time, the setting conditions of the plasma processing apparatus 10 used in the second cycle of ashing process S05 are the same as those in the first cycle of ashing process S05. That is, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to be greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0198] Furthermore, the plasma processing apparatus 10 used in the ashing process S05 of the second cycle is set under the same conditions as in the first cycle. That is, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to be greater than the supply power value in the deposition process S03, and can be set to be the same as the supply power value in the dry etching process S04 of the second cycle.

[0199] Furthermore, the setting conditions of the plasma processing apparatus 10 used in the second cycle ashing process S05 are the same as those in the first cycle ashing process S05. As will be described later, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner circumference side can be set to be the same as the supply power value of the frequency λ3 applied to the third electrode E3 located on the outer circumference side.

[0200] Furthermore, the setting conditions of the plasma processing apparatus 10 used in the second ashing process S05 are the same as those in the first ashing process S05. That is, it is preferable to apply a bias voltage of frequency λ1 to the first electrode 12. The frequency λ1 can be set to a value lower than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery. The frequency λ1 can be, for example, 400 kHz.

[0201] Furthermore, the plasma treatment apparatus 10 used in the second ashing process S05 is set under the same conditions as in the first ashing process S05. That is, it is preferable to apply a bias voltage to the first electrode 12. The power of the bias voltage in the second ashing process S05 can be set to be equal to or higher than the power of the bias voltage in the second dry etching process S04.

[0202] In the second cycle's ashing process S05, O2 gas is supplied for ashing. During the anisotropic plasma treatment using O2 gas, the deposited layer D2 is reliably removed from the portion near the inner periphery of the opening patterns MS and ML, and from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML, exposing the sidewalls VSq and VLq. Simultaneously, in the second cycle's ashing process S05, O2 gas is supplied for ashing. Therefore, in this process, the resin-based resist layer M is also partially removed, thereby reducing the thickness of the resist layer M.

[0203] At the end of the ashing process S05 in the second cycle, a judgment process S06a is performed, similar to the first cycle. Based on the judgment result of judgment process S06a, it is determined whether to proceed to the post-processing process S08 or to proceed to the resist protection judgment process S06 of the second cycle. Based on the judgment result of the resist protection judgment process S06, it is determined whether to proceed to the next cycle with the etching process or to proceed to the resist protective film formation process S07, which will be described later.

[0204] In the depth determination process S06a of the second cycle, it is determined whether to proceed to the next resist protection determination process S06. At this time, the determination criteria in the depth determination process S06a are based on the depth of the recessed patterns VS and VL, in other words, based on the aspect ratio of the recessed patterns VS and VL.

[0205] When the depth of the recessed patterns VS and VL is insufficient (judgment result: no), it is determined that the next etching cycle is required, and the process proceeds to the resist protection judgment step S06. In the resist protection judgment step S06, it is determined whether to proceed to the resist protective film formation step S07, which will be described later.

[0206] On the other hand, when it is determined in the depth determination process S06a that the depth of the recessed patterns VS and VL is sufficient (determination result: yes), the etching ends and the process proceeds to the post-processing process S08.

[0207] In the resist protection judgment step S06 of the second cycle, the judgment is made based on the depth of the recessed patterns VS and VL, just like in the first cycle. In other words, the judgment is made based on the aspect ratio of the recessed patterns VS and VL.

[0208] If the depth of the recessed patterns VS and VL is determined to be insufficient in the resist protection judgment step S06 of the second cycle (judgment result: no), the same as the resist protection judgment step S06 of the first cycle, the process proceeds to the deposition step S03, which is the initial step of the next cycle.

[0209] On the other hand, when the depth of the recessed patterns VS and VL is sufficient (judgment result: yes), and when the aspect ratio of the recessed patterns VS and VL is greater than the above range, the determination is made to form a resist protective film Mm in the resist protective film forming process S07.

[0210] That is, the resist protection judgment process S06 is performed based on the opening area of ​​the recessed patterns VS and VL and the etching amount of the bottom VSb1 and VLb1 in the second cycle etching process.

[0211] Furthermore, the judgment in the resist protection judgment process S06 can also be made after the second cycle based on the results of measuring the depth of the recessed patterns VS and VL in the silicon substrate S, or by analogy based on the etching conditions in the second cycle to determine the transition to the third cycle. In the judgment based on etching conditions, an etching depth related to the specified conditions is preset for judgment.

[0212] Furthermore, in the resist protection judgment process S06 of the second cycle, the judgment can also be made based on the following judgment criteria.

[0213] For example, if the thickness reduction of the resist layer M obtained through the ashing process S05 is less than the specified value, the resist protective film formation process S07 is not performed, and instead a cycle including the next etching process is initiated.

[0214] On the other hand, regarding the judgment criteria in the second cycle's resist protection judgment step S06, if the thickness reduction of the resist layer M obtained through the ashing step S05 is greater than a specified value, the judgment is made to proceed to the resist protection film formation step S07.

[0215] The reason for this judgment is that when the thickness of the resist layer M is reduced by more than the specified value, the thickness of the resist layer M may be insufficient when entering the third etching cycle, and the shape of the etching process cannot be maintained accurately.

[0216] Next, the situation in the resist protective film formation process S07 will be explained.

[0217] like Figure 2 As shown, the resist protective film formation process S07 is performed before the third cycle begins.

[0218] Figure 10 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0219] exist Figure 2 In the resist protective film formation process S07 shown, as Figure 10 As shown, an anisotropic plasma treatment is used to form a protective film Mm on the surface of the resist layer M.

[0220] The resist protective film Mm is a film that protects the resist layer M from etching during the dry etching process S04 and the ashing process S05, which are carried out after the third cycle.

[0221] In the resist protective film formation step S07, the deposition rate of the resist protective film Mm is set to be higher than that of the deposition layer D2. For example, the deposition rate of the resist protective film Mm is set to be approximately 1.5 times higher than that of the deposition layer D2. In the plasma CVD method used in the resist protective film formation step S07, a mixture of SiF4 and O2, a mixture of SiCl4 and O2, or a mixture of SiH4 and O2, or TEOS (Tetraethyl orthosilicate, Tetraethoxysilane), etc., which can form Si x O y α z The gas. Thus, a resist protective film Mm with a SiOF film structure can be formed. Plasma CVD is an example of plasma film formation methods.

[0222] Here, when a mixed gas of SiF4 and O2 is used in the resist protective film formation step S07, SiF4 can be used as the gas supplied in the dry etching step S04. In this case, it is preferable because the structure of the plasma processing apparatus related to the gas supply can be generalized.

[0223] SiOF films have a similar structure to SiO2 films. Therefore, the thickness of the resist protective film Mm is not reduced in the deposition process S03, dry etching process S04, and ashing process S05, which constitute an etching process that includes an etching process after the third cycle.

[0224] In other words, the resist protective film Mm can prevent the thickness of the resist layer M from decreasing in the deposition process S03, dry etching process S04 and ashing process S05, which constitute the etching process after the third cycle.

[0225] Although the resist protective film Mm is formed on the surface of the resist layer M through anisotropic plasma treatment, the resist protective film Mm is not formed on the sidewalls VSq and VLq of the recessed patterns VS and VL. Furthermore, the resist protective film Mm is not formed on the bottom VSb2 and VLb2 of the recessed patterns VS and VL. This is because, in the depth determination process S06a and the resist protection determination process S06, the aspect ratio of the recessed patterns VS and VL is set to a predetermined value or higher.

[0226] In the resist protective film formation process S07, which begins after the second cycle, a plasma treatment apparatus 10, described later, is used for plasma treatment with high anisotropy.

[0227] At this time, in the plasma processing apparatus 10 used in the resist protective film formation step S07, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to be greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz. Furthermore, if the resist protective film formation step S07 is performed after the third cycle, the same conditions as those for the resist protective film formation step S07 described above can be used.

[0228] The plasma treatment apparatus 10 used in the resist protective film formation step S07 is set under the same conditions as the dry etching step S04 and the ashing step S05. That is, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to be greater than the supply power value in the deposition step S03 of the second cycle, and can be set to be the same as the supply power value in the dry etching step S04 and the ashing step S05 of the second cycle.

[0229] In addition, for the resist protective film formation process S07, in the plasma processing apparatus 10, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner periphery side (described later) can be set to be the same as the supply power value of the frequency λ3 applied to the third electrode E3 located on the outer periphery side.

[0230] Furthermore, in the resist protective film formation process S07, similar to the deposition process S03, a bias voltage may not be applied. The atmosphere pressure in the resist protective film formation process S07 can be set to the same value as the atmosphere pressure in the dry etching process S04 and the ashing process S05 of the second cycle.

[0231] When the resist protective film Mm with a so-called SiOF structure is stacked on the surface of the resist layer M, the consumption of the resist layer M can be suppressed during the ashing process S05 after the third cycle.

[0232] However, the resist protective film Mm composed of SiOF is gradually consumed by the anisotropic plasma etching process, which utilizes CF-type gases such as CHF3, C2F6, C2F4, or C4F8 (perfluorinated hydrocarbon gases) used in the deposition process S03 after the third cycle, SF6 or NF3 (used as etching gases in the dry etching process S04), or SiF4 (as a silicon compound) and O2, N2, N2O, NO, NO (as reactants) added to the etching gas. x Or a gas formed from CO2, such as a mixture of SF6 and O2.

[0233] Therefore, the thickness of the resist protective film Mm is set in a manner that allows for a specified number of cycles, so that the recessed patterns VS and VL reach the desired depth.

[0234] Furthermore, upon reaching a predetermined number of cycles, as described later, in order to restore the thickness of the consumed resist protective film Mm, a further resist protective film forming process S07 is performed, thereby re-laminating the resist protective film Mm onto the surface of the resist layer M.

[0235] In the dry etching method for silicon described in this embodiment, such as Figure 2 As shown, the deposition process S03, the dry etching process S04, and the ashing process S05 are performed repeatedly as a cycle. This further increases the depth of the recessed patterns VS and VL. Furthermore, after cycling for a predetermined number of times, i.e., at a predetermined frequency, a resist protective film formation process S07 is performed, thereby stacking a resist protective film Mm on the surface of the resist layer M.

[0236] After the resist protective film formation process S07, the etching process proceeds to the next third cycle.

[0237] Next, we will explain the implementation of the third loop.

[0238] Figure 11This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0239] exist Figure 2 In the deposition process S03 of the third cycle shown, as Figure 11 As shown, an anisotropic plasma treatment is used to form a deposition layer D3 composed of polymers such as fluorocarbons on the surface of the resist protective film Mm. This allows the sidewalls of the recessed patterns VS and VL to be protected from etching during the dry etching process S04, which is performed after the deposition process S03 in the third cycle.

[0240] At this point, although the thickness of the resist protective film Mm will be reduced to some extent, almost no resist protective film Mm remains in the deposition process S03.

[0241] The deposited layer D3 is formed to protect the sidewalls VSq and VLq of the recessed patterns VS and VL from etching and to define the bottom VSb2 and VLb2 of the recessed patterns VS and VL for etching. Thus, in the dry etching process S04, which is an etching process using fluorine compounds, vertical sidewalls VSq and VLq can be obtained.

[0242] Deposited layer D3 is stacked on the surface of the resist protective film Mm and at the bottom of the recessed patterns VS and VL, VSb2 and VLb2. Additionally, in Figure 11 In the diagram, the deposition layer D3 is shown in the sidewalls VSq and VLq of the recessed patterns VS and VL, but in reality, the deposition layer D3 hardly overlaps with the sidewalls VSq and VLq.

[0243] The deposition process S03 in the third cycle is the same as that in the second cycle. That is, anisotropic plasma treatment is performed using perfluorinated hydrocarbon gases such as CHF3, C2F6, C2F4, or C4F8. In deposition process S03, the plasma treatment apparatus 10, described later, is used to perform plasma treatment with high anisotropy.

[0244] For the deposition process S03 in the third cycle, in the plasma processing apparatus 10, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to be greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0245] At this time, the setting conditions for the third cycle deposition process S03 in the plasma processing apparatus 10 can also be the same as those for at least one of the deposition processes in the first cycle deposition process S03 and the second cycle deposition process S03.

[0246] Furthermore, for the deposition process S03 in the third cycle, in the plasma processing apparatus 10, the power value with frequency λ2 applied to the second electrode E2 located on the inner periphery side can be set to be lower than the power values ​​in the dry etching process S04 and the ashing process S05 described later. Additionally, in the plasma processing apparatus 10, a bias voltage can be omitted from the first electrode 12.

[0247] In the atmosphere of the third cycle deposition process S03, a predetermined pressure is set for deposition treatment. Furthermore, in the third cycle deposition process S03, the same setting conditions as at least one of the deposition processes in the first cycle deposition process S03 and the second cycle deposition process S03 may be used.

[0248] The thickness of the deposited layer D3 formed in the third deposition cycle S03 is the same as that in the second deposition cycle S03. That is, the thickness of the deposited layer D3 formed on the bottom VLb2 corresponding to the large-diameter opening pattern ML is greater than the thickness of the deposited layer D3 formed on the bottom VSb2 corresponding to the small-diameter opening pattern MS. Furthermore, the thickness of the deposited layer D3 on the bottom VLb2 of the opening pattern ML is equal to or smaller than the thickness of the deposited layer D3 on the surface of the resist protective film Mm located outside the opening patterns MS and ML.

[0249] That is, the thickness of the deposited layer D3 decreases in the following order: TD3 on the surface of the resist protective film Mm located outside the opening patterns MS and ML, TLD3 on the bottom VLb2 of the opening pattern ML, and TSD3 on the bottom VSb2 of the opening pattern MS.

[0250] In the third cycle deposition step S03, by setting the deposition conditions as described above, the deposition coverage of the deposition layer D3 on the bottom VSb2 and VLb2 corresponding to the opening patterns MS and ML can be optimized. Here, the most ideal condition for forming the deposition coverage is to shorten the processing time for stacking the deposition layer D3 with the required film thickness on the bottom VSb2 and VLb2. That is, the most ideal condition for forming the deposition coverage is to increase the film formation rate of stacking the deposition layer D3 on the bottom VSb2 and VLb2.

[0251] Furthermore, in the third cycle deposition process S03, the ideal conditions for forming the deposition cover are to adjust the deposition cover according to the etching depth and aspect ratio. That is, as described later, even when the aspect ratio changes according to the depth variation from the bottom VSb1, VLb1 to the bottom VSb2, VLb2, it is possible to form a deposition layer D3 with the desired thickness at a specified film formation rate.

[0252] Furthermore, the uniformity and reliability of the deposition layer D3 stacked on the bottom VSb2 and the deposition layer D3 stacked on the bottom VLb2 are improved respectively.

[0253] Furthermore, the third cycle deposition process S03 can be performed in the same manner as at least one of the deposition processes in the first cycle and the second cycle.

[0254] Figure 12 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0255] exist Figure 2 In the third cycle of dry etching process S04 shown, as Figure 12 As shown, anisotropic plasma etching is used to excavate the bottom VSb2 and VLb2 corresponding to the opening patterns MS and ML to reduce the position of the bottom VSb2 and VLb2, thereby forming the bottom VSb3 and VLb3.

[0256] At this point, although the thickness of the resist protective film Mm will be reduced to some extent, the resist protective film Mm will almost remain in the dry etching process S04.

[0257] At this time, based on the processing conditions in the third cycle dry etching process S04, the anisotropy of the plasma, and the film thickness difference of the deposited layer D3 stacked through the third cycle deposition process S03, the depths of the bottom VSb3 corresponding to the opening pattern MS and the bottom VLb3 corresponding to the opening pattern ML formed in the dry etching process S04 are set to be uniform.

[0258] Specifically, the film thickness TSD3 of the deposited layer D3 stacked on the bottom VSb2 corresponding to the opening pattern MS is less than the film thickness TLD3 of the deposited layer D3 stacked on the bottom VLb2 corresponding to the opening pattern ML. Furthermore, the etching amount of the bottom VSb2 corresponding to the opening pattern MS is less than the etching amount of the bottom VLb2 corresponding to the opening pattern ML. Therefore, the film thickness formed by the above deposition and the etching amount performed by the above etching cancel each other out, and the depths of the bottom VSb3 corresponding to the opening pattern MS and the bottom VLb3 corresponding to the opening pattern ML become uniform.

[0259] Furthermore, in the third cycle's dry etching process S04, the impact of etching on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML can be greatly reduced by considering the processing conditions, plasma anisotropy, and the deposited layer D3. Consequently, the sidewalls VSq and VLq are perpendicular to the surface of the silicon substrate S and are formed as approximately the same plane. Therefore, the sidewalls VSq and VLq, without any irregularities, extend in the depth direction.

[0260] That is, the bottom VSb3 and VLb3 are formed in such a way that the concave patterns VS and VL have uniform diameter dimensions.

[0261] To achieve this shape, in the third cycle of dry etching process S04, a plasma treatment apparatus 10, described later, is used for plasma treatment with high anisotropy.

[0262] At this point, the processing conditions of the plasma processing apparatus 10 used in the third cycle of dry etching process S04 are the same as those in the second cycle of dry etching process S04. That is, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to be greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0263] Furthermore, in the dry etching process S04 of the third cycle, the settings of the plasma processing apparatus 10 are the same as in the second cycle. That is, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to be greater than the supply power value in the deposition process S03 of the third cycle, and can be set to be the same as the supply power value in the ashing process S05 of the third cycle.

[0264] Furthermore, in the dry etching process S04 of the third cycle, the setting conditions of the plasma processing apparatus 10 are the same as in the second cycle. That is, the supply power value of the frequency λ2 applied to the second electrode E2 located on the inner peripheral side, as described later, can be set to be the same as the supply power value of the frequency λ3 applied to the third electrode E3 located on the outer peripheral side.

[0265] Furthermore, in the third cycle of dry etching process S04, the setting conditions of the plasma processing apparatus 10 are the same as those in the second cycle of dry etching process S04. Preferably, a bias voltage with frequency λ1 is applied to the first electrode 12. The frequency λ1 can be set to a frequency λ3 lower than the power applied to the third electrode E3 located on the outer periphery side. For example, the frequency λ1 can be 400 kHz.

[0266] Furthermore, the anisotropic plasma etching in the third cycle's dry etching process S04 is the same as that in the second cycle's dry etching process S04. That is, anisotropic etching of Si is performed by decomposing the SF6 and O2 mixture using plasma. As a result, the F radicals generated from the decomposition of SF6 etch Si (F + Si → SiF4). Since this etching reaction is isotropic, a protective film can be attached to the sidewalls VSq and VLq to suppress the etching reaction at these sidewalls in order to perform anisotropic etching.

[0267] The anisotropic plasma etching using a mixed gas of SF6 / O2 in the third cycle's dry etching process S04 is the same as in the second cycle's dry etching process S04. That is, the deposited layer D3 is removed from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML to expose the sidewalls VSq and VLq.

[0268] Here, the SF6 / O2 mixed gas anisotropic plasma etching in the third cycle's dry etching process S04 is the same as in the second cycle's dry etching process S04. That is, the sidewalls VSq and VLq can also be protected by forming an insulating layer. Simultaneously, the sidewalls VSq and VLq are oxidized by oxygen (O) and SiO2 is also used. x The SiO2 film is deposited to protect the sidewalls VSq and VLq. x The deposited film is generated by reacting Si and O obtained by the further decomposition of SiF4, which is an etching product.

[0269] In addition, in the third cycle of dry etching process S04, similar to the second cycle of dry etching process S04, SiF4 can also be used as a gas to prevent insufficient SiF4 as the etching product.

[0270] Furthermore, the dry etching process S04 in the third cycle is the same as that in the second cycle. That is, SF6 or NF3 is used as the etching gas, SiF4 as a silicon compound is added to the etching gas, and O2, N2, N2O, NO, and NO are added as reactants. x Or CO2. This allows for concentrated etching of the bottom VSb2 and VLb2.

[0271] Furthermore, the processing time of the third cycle dry etching process S04 can be made longer than the processing time of at least one of the first cycle dry etching process S04 and the second cycle dry etching process S04.

[0272] Figure 13 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0273] exist Figure 2 In the third cycle of ashing process S05 shown, as Figure 13 As shown, the residual deposit layer D3 is removed after the dry etching process S04 in the third cycle.

[0274] In particular, in the ashing process S05 of the third cycle, the ashing conditions are set in a way that the deposited layer D3 remaining in the area near the inner periphery of the opening pattern MS and the opening pattern ML and in the area near the surface of the resist protective film Mm is effectively removed.

[0275] The ashing process S05 of the third cycle is the same as at least one of the ashing processes S05 of the first cycle and S05 of the second cycle. It removes the deposited layer D3 adhering to the surface of the resist protective film Mm after the dry etching process S04 of the third cycle, the deposited layer D3 remaining in the area near the inner periphery of the openings of the opening patterns MS and ML, and the deposited layer D3 remaining on the sidewalls VSq and VLq corresponding to the opening patterns MS and ML.

[0276] Furthermore, in the ashing process S05 of the third cycle, if there is a deposited layer D3 remaining on the bottom VSb3 corresponding to the opening pattern MS and a deposited layer D3 remaining on the bottom VLb3 corresponding to the opening pattern ML, then the deposited layer D3 is removed.

[0277] At this point, the thickness of the resist protective film Mm did not change, and in the third cycle of the ashing process S05, the resist protective film Mm was almost completely retained.

[0278] Here, the most important step is to remove the residual deposited layers D3 at the inner periphery of the opening pattern MS and ML. If these deposited layers D3 are not completely removed and remain, a further deposited layer D4 will be deposited on the remaining deposited layer D3 in the deposition process S03 performed after the fourth cycle in the repeated cycles. In this case, the opening diameters of the opening patterns MS and ML in the resist layer M and the resist protective film Mm will be reduced.

[0279] As described above, if the opening diameters of the opening patterns MS and ML in the resist layer M are reduced, even in the dry etching process S04, which is the fourth cycle after the third cycle and involves etching with increased anisotropy, the etching plasma will be hindered from reaching the bottom VSb3 and bottom VLb3 by the deposited layers D3 and D4. Therefore, etching in the bottom VSb3 and bottom VLb3 cannot be performed properly, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML become non-perpendicular, and the shapes of the recessed patterns VS and VL may become pointed.

[0280] In contrast, when no deposited layer D3 remains at the inner periphery of both the opening pattern MS and the opening pattern ML, in the fourth deposition process S03, which is performed after the third cycle in the repeated cycle, no further deposited layer D4 will be deposited on the remaining deposited layer D3. Therefore, the opening diameters of the opening patterns MS and ML in the resist layer M and the resist protective film Mm can be maintained at a predetermined size.

[0281] Therefore, in the dry etching process S04 of the fourth cycle in the repeated cycle, by performing etching with an increased degree of anisotropy, the etching plasma is not hindered from reaching the bottom VSb3 and bottom VLb3 by the deposited layers D3 and D4. Thus, by appropriately etching the bottom VSb3 and bottom VLb3, the sidewalls VSq and VLq corresponding to the opening patterns MS and ML extend in a vertical state. Therefore, by preventing the recessed patterns VS and VL from becoming pointed, each recessed pattern in the recessed patterns VS and VL with the same diameter can be formed in the depth direction with a high aspect ratio.

[0282] At the same time, it is important to maintain a sufficient thickness of the resist protective film Mm so that the resist layer M does not disappear during the ashing process S05.

[0283] In the third cycle ashing process S05, as described above, the deposited layer D3 remaining at the inner periphery of the opening patterns MS and ML is reliably removed. Therefore, similar to the ashing processes S05 in the first and second cycles, it is necessary to generate a plasma with high anisotropy. Therefore, in the third cycle ashing process S05, the plasma processing apparatus 10, described later, is also used.

[0284] At this time, the setting conditions of the plasma processing apparatus 10 used in the third cycle ashing process S05 are the same as those of at least one of the ashing processes in the first cycle and the second cycle. That is, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side can be set to be greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz and the frequency λ3 can be 2 MHz.

[0285] Furthermore, the setting conditions of the plasma processing apparatus 10 used in the third cycle ashing process S05 are the same as those of at least one of the ashing processes in the first cycle ashing process S05 and the second cycle ashing process S05. That is, the supply power of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to a value greater than the supply power in the deposition process S03, and can be set to the same value as the supply power in the dry etching process S04 of the third cycle.

[0286] Furthermore, the setting conditions of the plasma processing apparatus 10 used in the third cycle ashing process S05 are the same as those of at least one of the ashing processes in the first cycle ashing process S05 and the second cycle ashing process S05. That is, the supply power of the frequency λ2 applied to the second electrode E2 located on the inner circumference side, as described later, can be set to the same value as the supply power of the frequency λ3 applied to the third electrode E3 located on the outer circumference side.

[0287] Furthermore, the setting conditions of the plasma processing apparatus 10 used in the third cycle ashing process S05 are the same as those in at least one of the ashing processes in the first cycle S05 and the second cycle S05. That is, it is preferable to apply a bias voltage of frequency λ1 to the first electrode 12. The frequency λ1 can be set to a value lower than the frequency λ3 of the power applied to the third electrode E3 located on the outer peripheral side. The frequency λ1 can be, for example, 400 kHz.

[0288] Furthermore, the plasma processing apparatus 10 used in the third ashing process S05 is configured under the same conditions as at least one of the ashing processes in the first and second cycles. That is, a bias voltage is preferably applied to the first electrode 12. The power of the bias voltage in the third ashing process S05 can be set to be equal to or higher than the power of the bias voltage in the third dry etching process S04.

[0289] In the third cycle ashing process S05, O2 gas is supplied for ashing. During the anisotropic plasma treatment using O2 gas, the deposited layer D3 is reliably removed from the portion near the inner periphery of the opening patterns MS and ML, and from the sidewalls VSq and VLq corresponding to the opening patterns MS and ML, exposing the sidewalls VSq and VLq. Simultaneously, O2 gas is supplied for ashing in the third cycle ashing process S05. Therefore, since a resist protective film Mm is stacked on the resist layer M, the resist layer M is not removed by the O2 plasma.

[0290] like Figure 2As shown, the silicon dry etching method of this embodiment repeatedly performs a deposition process S03, a dry etching process S04, and an ashing process S05 to form a cycle. This further increases the depth of the recessed patterns VS and VL.

[0291] Furthermore, regarding the dry etching method for silicon involved in this embodiment, at the end of the third cycle of deposition process S03 to ashing process S05, as follows: Figure 2 As shown, it has a depth determination process S06a and a resist protection determination process S06.

[0292] In the depth determination process S06a of the third cycle, it is determined whether to proceed to the next resist protection determination process S06. At this time, the determination criteria in the depth determination process S06a are based on the depth of the recessed patterns VS and VL, in other words, based on the aspect ratio of the recessed patterns VS and VL.

[0293] If, in the depth determination process S06a, it is determined that the depth of the recessed patterns VS and VL is insufficient (determination result: No), it is determined that the next etching cycle is required, and the process proceeds to the resist protection determination process S06. In the resist protection determination process S06, it is determined whether to proceed to the resist protective film formation process S07, which will be described later.

[0294] On the other hand, when it is determined in the depth determination process S06a that the depth of the recessed patterns VS and VL is sufficient (determination result: yes), the etching ends and the process proceeds to the post-processing process S08.

[0295] In the resist protection judgment step S06 of the third cycle, it is determined whether to proceed to the next cycle, which includes the etching process, without performing the resist protection film formation step S07, or to proceed to the resist protection film formation step S07, which will be described later.

[0296] Here, the judgment criteria in the resist protection judgment process S06 of the third cycle are based on the depth of the recessed patterns VS and VL and the etching degree of the resist protective film Mm (that is, based on the degree of reduction in the thickness of the resist protective film Mm).

[0297] The depth or aspect ratio of the recessed patterns VS and VL is sufficient at the end of the ashing process S05, which is performed after the third cycle. Therefore, the judgment criterion in the resist protection judgment process S06, which is performed after the third cycle, is based on the degree of etching of the resist protective film Mm, that is, based on the degree of reduction in the thickness of the resist protective film Mm.

[0298] In the resist protection judgment step S06 of the third cycle, the judgment is made at the end of the deposition step S03 to the ashing step S05 of the third cycle. Specifically, if it is determined that the resist protective film Mm maintains a sufficient film thickness and maintains sufficient protection capability (i.e., etch resistance) for the resist layer M in the deposition step S03 and dry etching step S04 of the next cycle, a judgment is made to proceed to the fourth cycle as the next cycle.

[0299] In addition, if it is anticipated that in the resist protection judgment step S06 of the third cycle, the resist protection film Mm will not maintain a sufficient film thickness and will not have sufficient protection against the resist layer M, i.e., it will not have sufficient etch resistance, a judgment is made to proceed to the resist protection film formation step S07.

[0300] Furthermore, regarding the judgment in the resist protection judgment step S06, the judgment can be made after the third cycle based on the result of measuring the film thickness of the resist protection film Mm, or the transition to the fourth cycle can be determined by analogy to the etching conditions in the second cycle, assuming the resist protection film Mm maintains a sufficient film thickness. In the judgment based on etching conditions, the degree of reduction in the thickness of the resist protection film Mm related to the specified conditions is preset, and the judgment is made based on this preset value.

[0301] Furthermore, in the typical processing steps of the silicon substrate S, when a cycle is formed by the deposition process S03, the dry etching process S04 and the ashing process S05 as described above, after 5 to 20 cycles, preferably after about 8 to 12 cycles, a resist protective film formation process S07 can be inserted between cycles.

[0302] Next, we will explain the fourth cycle.

[0303] Figure 14 This is a cross-sectional view showing the process of the dry etching method for silicon according to this embodiment.

[0304] exist Figure 2 In the fourth cycle deposition process S03 shown, as Figure 14 As shown, a deposition layer D4 composed of polymers such as fluorocarbons is formed on the surface of the resist protective film Mm by anisotropic plasma treatment. The sidewalls of the raised pattern VS and the recessed pattern VL are protected from etching during the dry etching process S04, which is performed after the fourth deposition cycle S03.

[0305] At this point, although the thickness of the resist protective film Mm will be reduced to some extent, almost no resist protective film Mm remains in the deposition process S03.

[0306] The deposited layer D4 is formed to protect the sidewalls VSq and VLq of the recessed patterns VS and VL from etching and to define the bottom VSb3 and VLb3 of the recessed patterns VS and VL for etching. Thus, in the dry etching process S04, which is an etching process using fluorine compounds, vertical sidewalls VSq and VLq can be obtained.

[0307] Deposited layer D4 is stacked on the surface of the resist protective film Mm and at the bottom of the recessed patterns VS and VL, VSb3 and VLb3. Additionally, in Figure 14 In the diagram, the deposition layer D4 is shown in the sidewalls VSq and VLq of the recessed patterns VS and VL, but in reality, the deposition layer D4 hardly overlaps with the sidewalls VSq and VLq.

[0308] The fourth deposition process S03 is the same as the third deposition process S03. That is, anisotropic plasma treatment is performed using perfluorinated hydrocarbon gases such as CHF3, C2F6, C2F4, or C4F8. In deposition process S03, the plasma treatment apparatus 10, described later, is used to perform plasma treatment with high anisotropy.

[0309] For the fourth deposition cycle S03, in the plasma processing apparatus 10, the frequency λ2 of the power applied to the second electrode E2 located on the inner periphery side (described later) can be set to a frequency λ3 greater than the frequency λ3 of the power applied to the third electrode E3 located on the outer periphery side. Specifically, the frequency λ2 can be 13.65 MHz, and the frequency λ3 can be 2 MHz.

[0310] At this time, the setting conditions for the deposition process S03 of the fourth cycle in the plasma processing apparatus 10 can also be the same as those for any of the deposition processes S03 of the first to third cycles.

[0311] Furthermore, for the deposition process S03 in the fourth cycle, in the plasma processing apparatus 10, the power value of the frequency λ2 applied to the second electrode E2 located on the inner periphery side (described later) can be set to be lower than the power values ​​in the dry etching process S04 and the ashing process S05 (described later). Additionally, in the plasma processing apparatus 10, a bias voltage can be omitted from the first electrode 12.

[0312] In the atmosphere of the fourth deposition cycle S03, a predetermined pressure is set for deposition processing. Furthermore, in the fourth deposition cycle S03, the same setting conditions as any of the deposition cycles S03 of the first to third cycles can be used.

[0313] The thickness of the deposited layer D4 formed in the fourth deposition cycle S03 is the same as that in any of the first to third deposition cycles S03. That is, the thickness of the deposited layer D4 formed on the bottom VLb3 corresponding to the large-diameter opening pattern ML is greater than the thickness of the deposited layer D4 formed on the bottom VSb3 corresponding to the small-diameter opening pattern MS. Furthermore, the thickness of the deposited layer D4 on the bottom VLb3 of the opening pattern ML is equal to or less than the thickness of the deposited layer D4 on the surface of the resist protective film Mm located outside the opening patterns MS and ML.

[0314] That is, the thickness of the deposited layer D4 decreases in the following order: TD4 on the surface of the resist protective film Mm located outside the opening patterns MS and ML, TLD4 on the bottom VLb3 of the opening pattern ML, and TSD4 on the bottom VSb3 of the opening pattern MS.

[0315] In the fourth cycle deposition step S03, by setting the deposition conditions as described above, the deposition coverage of the deposited layers on the bottom VSb3 and VLb3 corresponding to the opening patterns MS and ML can be optimized. Here, the most ideal condition for forming the deposition coverage is to shorten the processing time for stacking the deposition layer D4 with the required film thickness on the bottom VSb3 and VLb3. That is, the most ideal condition for forming the deposition coverage is to increase the film formation rate of stacking the deposition layer D4 on the bottom VSb3 and VLb3.

[0316] Furthermore, in the fourth cycle deposition process S03, the ideal conditions for forming the deposition cover are adjusted according to the etching depth and aspect ratio. That is, as described later, even when the aspect ratio changes due to the depth variation from the bottom VSb2, VLb2 to the bottom VSb3, VLb3, a deposition layer D4 with the desired thickness can be formed at a specified film formation rate.

[0317] Furthermore, the uniformity and reliability of the deposition layer D4 stacked on the bottom VSb3 and the deposition layer D4 stacked on the bottom VLb3 are improved respectively.

[0318] Next, as Figure 2 The fourth cycle of dry etching process S04, as shown, uses anisotropic plasma etching to excavate the bottom VSb3 and VLb3 corresponding to the opening patterns MS and ML, thereby lowering the position of the bottom VSb3 and VLb3. Thus, a bottom is formed in the opening patterns MS and ML at a depth deeper than the bottom VSb3 and VLb3.

[0319] At this point, although the thickness of the resist protective film Mm will be reduced to some extent, the resist protective film Mm will almost remain in the dry etching process S04.

[0320] Next, as Figure 2 The fourth cycle, S05, shown, involves ashing to remove the residual deposit layer D4.

[0321] At this point, the thickness of the resist protective film Mm will decrease to some extent.

[0322] Further, a fourth cycle depth determination step S06a and a resist protection determination step S06 are performed. Based on the thickness of the resist protection film Mm, it is determined whether a resist protection film formation step S07 should be inserted between cycles after the above cycles are performed at a predetermined frequency. Regardless of whether the resist protection film formation step S07 is performed or not, a cycle including a dry etching step S04 is performed.

[0323] Thus, on the surface of the silicon substrate S, a recessed pattern VS with a diameter of φS and a recessed pattern VL with a diameter of φL are formed at the same depth.

[0324] Furthermore, in Figure 2 In the post-processing step S08 shown, a process similar to the dry etching step S04 is performed as needed to remove the resist protective film Mm. Further, the resist layer M is removed by performing a wet etching step or a process similar to the ashing step S05. This concludes the dry etching method for silicon according to this embodiment.

[0325] In addition, in the dry etching method for silicon described in this embodiment, approximately 50 cycles can be used.

[0326] In the dry etching method for silicon in this embodiment, such as Figure 2 As shown, the deposition process S03, the dry etching process S04, and the ashing process S05 are performed repeatedly as a cycle. Further, after repeated cycles at a predetermined frequency, a resist protective film formation process S07 is inserted between cycles. That is, the resist protective film formation process S07 is performed between cycles. Thus, recessed patterns VS and VL with different diameters can be formed with the same depth. That is, recessed patterns VS and VL with high aspect ratios can be formed. The recessed patterns VS and VL can be formed on the silicon substrate S using a simple structure where a resist layer M made of resin is patterned on the silicon substrate S, without using a hard mask (HDM) such as a metal mask.

[0327] Furthermore, the number of etching cycle times can be arbitrarily determined based on the depth of the formed recessed patterns VS and VL. Alternatively, the ashing process S05 can be omitted in each cycle. In this case, the degree of residue of the deposited layer formed on the inner periphery of the opening patterns MS and ML in each cycle is determined in the resist protection judgment process S06. Based on the judgment result, it can be simultaneously determined whether to perform the ashing process S05.

[0328] Next, the plasma processing apparatus used in the dry etching method for silicon according to this embodiment will be described with reference to the accompanying drawings.

[0329] Figure 15 This is a schematic cross-sectional view showing the plasma processing apparatus used in the dry etching method for silicon according to this embodiment. Figure 16 It means in Figure 15 The diagram shows a top view of two spiral electrodes arranged on the inner and outer circumferential sides of the device, and a power supply that outputs power at different frequencies to the two spiral electrodes. Figure 16 This is a top view illustrating the position of the spiral electrode connected to the power source. Figure 17 It means in Figure 15 A cross-sectional view showing the relationship between the first electrode (outer diameter D) and the second electrode (outer diameter d) in the illustrated device. Figure 15 In the figure, reference numeral 10 indicates a plasma processing device.

[0330] The plasma processing apparatus 10 includes a control unit 5. The control unit 5 is, for example, a computer equipped with a circuit board on which electronic circuitry is formed. The electronic circuitry is, for example, an integrated circuit such as an LSI (Large-scale Integrated Circuit) or an ASIC (Application Specific Integrated Circuit). The control unit 5 includes a recording medium 6 and a processor 7. The recording medium 6 stores the execution... Figure 2 The flowchart shown illustrates a computer program for multiple steps. The processor 7 processes various information according to the steps shown in the flowchart. Therefore, the control unit 5 uniformly controls the operation of the plasma processing apparatus 10, executing each step of the etching method described in the above embodiment. For example, the control unit 5 controls the operation of components and devices constituting the plasma processing apparatus 10, such as the power supply A, B, C, and the exhaust device TMP, which will be described later.

[0331] Processor 7 performs the determination in the depth determination step S06a and the resist protection determination step S06. Specifically, processor 7 calculates the determination result in the depth determination step S06a. Here, based on the calculated determination result, processor 7 causes the processing step to proceed to the resist protection determination step S06 or the post-processing step S08.

[0332] Processor 7 calculates the determination result in the resist protection determination step S06. Here, based on the calculated determination result, processor 7 causes the processing step to proceed to the resist protective film formation step S07 or the deposition step S03 of the next cycle.

[0333] The following Figures 18-22 The plasma processing device shown may also include a control unit 5.

[0334] In this embodiment, the plasma processing device 10 is a dual-frequency inductively coupled plasma (ICP) spectrometer. For example... Figure 15 As shown, the plasma processing apparatus 10 includes a chamber 11 that can be depressurized by an exhaust device TMP such as a vacuum pump, and is an apparatus for performing plasma processing on a silicon substrate S (the object to be processed) within the chamber 11.

[0335] The plasma processing apparatus 10 includes: a top cover 13, a solid-state source 20a (20), a first electrode 12, a second electrode E2 (electrode, antenna AT2), and a third electrode E3 (electrode, antenna AT3). The top cover 13 is disposed at the upper end of the chamber 11. A gas inlet is formed in the central portion 15a (13) of the top cover 13. A gas inlet device 30 is connected to the gas inlet via a pipe or the like. The solid-state source 20a is disposed inside the chamber 11 opposite to the top cover 13. The second electrode E2 and the third electrode E3 are located above the top cover 13 outside the chamber 11. The second electrode E2 is disposed in the inner region of the top cover 13. The third electrode E3 is disposed in the outer region (outer periphery) of the top cover 13. The plasma processing apparatus 10 includes a gas inlet device 30. The gas inlet device 30 is disposed in the central portion 15a (15) of the top cover 13.

[0336] In the plasma processing apparatus 10, a solid-state source 20a is disposed within a chamber 11. When viewed from the vertical direction of the upper cover 13, a third electrode E3 is configured to overlap with the solid-state source 20a. Furthermore, the solid-state source 20a is configured to cover at least a portion of the third electrode E3. The solid-state source 20a is configured to be separate from the upper cover 13 of the chamber 11. The material of the solid-state source 20a includes, for example, silicon oxide.

[0337] The third electrode E3 is an electrode that supplies power at a frequency lower than the frequency at which the power is applied to the second electrode E2. In other words, the second electrode E2 is an electrode that supplies power at a frequency higher than the frequency at which the power is applied to the third electrode E3. That is, the second frequency λ2 and the third frequency λ3 of the plasma processing device 10 have a relationship of λ2 > λ3.

[0338] In the plasma processing apparatus 10, the second electrode E2 is an electrode that applies power for forming plasma and power for controlling plasma distribution, and the third electrode E3 is an electrode that heats the electron temperature of the formed plasma.

[0339] In the plasma processing apparatus 10, the gas introduction device 30 is disposed in the center of the upper cover 13.

[0340] The first electrode 12 disposed within the chamber 11 of the plasma processing apparatus 10 is a flat plate electrode. The first electrode 12 functions as a support for supporting the silicon substrate S. Alternatively, the first electrode 12 may also be referred to as a substrate stage. The plasma processing apparatus 10 includes: a high-frequency power supply A (first power supply) electrically connected to the first electrode 12; a high-frequency power supply B (second power supply) electrically connected to the spiral-shaped second electrode E2; and a high-frequency power supply C (third power supply) electrically connected to the spiral-shaped third electrode E3.

[0341] The high-frequency power supply A can apply a bias voltage of frequency (first frequency) λ1 to the first electrode 12.

[0342] Both the spiral-shaped second electrode E2 and the spiral-shaped third electrode E3 are disposed outside the chamber 11 and are positioned opposite the first electrode 12, separated by a quartz plate forming the upper cover 13 of the chamber 11. The spiral-shaped second electrode E2 is disposed along the upper cover 13 at the central portion. The spiral-shaped third electrode E3 is disposed along the upper cover 13 at a position closer to the outer periphery than the second electrode E2.

[0343] High-frequency power supply B can apply an AC voltage with frequency (second frequency) λ2 to the second electrode E2 (refer to...). Figure 15 The second electrode E2 has a first portion and a second portion. The first portion is disposed at the inner peripheral end of the spiral-shaped second electrode E2. High-frequency power output from the high-frequency power supply B is applied to the first portion. The second portion is disposed at the outer peripheral end of the spiral-shaped second electrode E2. The second portion is grounded (see reference). Figure 16 ).

[0344] The high-frequency power supply C can apply an AC voltage with a frequency (third frequency) λ3 to the third electrode E3 (refer to...). Figure 15 The third electrode E3 has a third portion and a fourth portion. The third portion is located at the inner circumferential end of the spiral-shaped third electrode E3. High-frequency power output from the high-frequency power supply C is applied to the third portion. The fourth portion is located at the outer circumferential end of the spiral-shaped third electrode E3. The fourth portion is grounded (see reference). Figure 16 ).

[0345] High-frequency power supply B applies an AC voltage with a second frequency λ2 to the second electrode E2. High-frequency power supply C applies an AC voltage with a third frequency λ3 to the third electrode E3.

[0346] The gas introduction device 30 in the plasma processing apparatus 10 introduces process gas G containing fluorine (F) into the chamber 11 through a gas inlet formed on the upper cover 13.

[0347] The plasma processing apparatus 10 has a solid-state source 20 for sputtering, which is disposed within the chamber 11 closer to the upper cover 13 than the first electrode 12, and is positioned opposite to the first electrode 12. In particular, in the plasma processing apparatus 10, when viewed from the vertical direction of the upper cover 13, the solid-state source 20 and the third electrode E3 are arranged in such a way that the area where the solid-state source 20 is disposed overlaps with the area where the third electrode E3 is disposed (the outer region of the upper cover 13).

[0348] Inside the chamber 11 of the plasma processing apparatus 10 having the above-described structure, plasma P2, generated by the second electrode E2, and plasma P3, generated by the third electrode E3, are generated in the space (region) near the upper cover 13. In the plasma processing apparatus 10, since the solid-state source 20 and the third electrode E3 are arranged such that the region where the solid-state source 20 is disposed overlaps with the region where the third electrode E3 is disposed on the outer side of the upper cover 13, the solid-state source 20 is primarily sputtered by plasma P3. Since the solid-state source 20 comprises silicon oxide, oxygen, for example, is sequentially introduced from the solid-state source 20 into the plasma (especially plasma P3). Therefore, the oxygen content in the plasma (especially plasma P3) is not insufficient.

[0349] Here, in order to set the luminescence intensity of oxygen (O) and fluorine (F) and the relationship between the ratio of oxygen (O) and fluorine (F) to be in a specified state, the power supply of the high frequency (13.56MHz) can be fixed at 2kW, and the power supply of the low frequency (2MHz) can be varied in the range of 0W to 3kW.

[0350] In the plasma processing device 10, such as Figure 17 As shown, the relationship between the first electrode 12 (outer diameter D) used to mount the silicon substrate S and the second electrode E2 (outer diameter d) disposed at a position that does not overlap with the solid source 20 (disposed in the inner region of the upper cover 13) is defined.

[0351] When the diameter d of the second electrode (antenna AT2) is less than half the diameter D of the first electrode 12, which serves as a support (substrate stage) for supporting the silicon substrate S, the plasma density at the outer periphery of the first electrode 12 decreases, and the generation of F free radicals is significantly reduced. Therefore, the outer periphery of the silicon substrate S cannot be etched in the same manner as the central portion of the silicon substrate S.

[0352] When the diameter d of the second electrode is more than 1.3 times the diameter D of the first electrode 12, which serves as a support for the silicon substrate S, even if low-frequency power is applied to the third electrode E3 (antenna AT3) and oxygen is supplied to the silicon substrate S from the solid source 20, the etching effect will not affect the outer periphery of the silicon substrate S because the solid source 20 is far away from the silicon substrate S.

[0353] Therefore, when oxygen is supplied from the solid source 20 to the silicon substrate S in the plasma processing apparatus 10 of this embodiment, it is preferable to satisfy the relationship D / 2≤d≤D.

[0354] In the dry etching method for silicon according to this embodiment, the etching stop effect generated by depositing layers D1 to D4 is utilized. This suppresses RIE lag in the silicon substrate S. Furthermore, even when forming recessed patterns VS and VL such as holes or trenches with different diameters (φS, φL, etc.), a gas of the same type as that used in the etching process can be used to form a resist protective film Mm on the resist layer M, such as resin. This enables the aforementioned dry etching process.

[0355] Furthermore, since no hard mask made of metal or the like is used, there is no need for a metal film-forming process, nor for specialized metal-specific processes and equipment such as chambers, patterning, and cleaning for metal film formation. Therefore, it is possible to reduce the number of processes, the necessary equipment, and manufacturing costs.

[0356] Furthermore, by repeatedly performing the deposition layer formation in deposition process S03 and the etching in dry etching process S04, an ashing process S05 is added to remove the deposition layers D1 to D4, thereby removing the deposition layers in each cycle. Thus, during etching, the C-shaped deposits attached to the sidewalls VSq and VLq corresponding to the areas of the opening patterns MS and ML are removed. x F y The polymer-like deposition layers D1 to D4 were also removed.

[0357] Furthermore, in the dry etching process S04, a dual-frequency inductively coupled plasma spectrometer (e.g., composed of 13.56 MHz and 2 MHz) from the plasma processing apparatus 10 is used. This allows for the active dissociation of the added gas O2, thereby ensuring that SiO2 is always formed on the sidewalls VSq and VLq. x Protective film.

[0358] The resist protective film formation process S07, the ashing process S05, the deposition process S03, and the dry etching process S04 are performed in the same chamber 11. Thus, as an in-situ process, dry etching can be performed with the deposited layers D1 to D4 in the region near the inner periphery of the opening of the resist protective film Mm attached to the opening patterns MS and ML removed.

[0359] Furthermore, through the resist protective film formation process S07, a resist protective film Mm is formed that can protect the resist layer M from ashing and etching, thereby suppressing the reduction in the thickness of the resist layer M. Thus, hard masks such as metals and silicon oxide are not required.

[0360] Therefore, additional processes and equipment such as hard mask layer formation, etching, and cleaning are not required. Furthermore, a common gas can be used in the resist protective film formation process S07 and the dry etching process S04.

[0361] Furthermore, the plasma processing apparatus 10 in this embodiment may also adopt the following structure.

[0362] Figure 18 This is a schematic cross-sectional view illustrating other examples of plasma devices used in this embodiment.

[0363] In the plasma processing device 10 of this example, such as Figure 18 As shown, the gas introduction device 30 is connected to the central portion 15a of the upper cover 13. When viewed from the vertical direction of the upper cover 13, the area for configuring the solid source 20b (20) is located at a position overlapping with the two electrodes (second electrode E2 and third electrode E3).

[0364] That is, in having Figure 18 In the plasma processing apparatus 10 with the structure shown, the region where the solid-state source 20b is disposed within the chamber 11 is located at a position overlapping with the second electrode E2 and the third electrode E3. Furthermore, when viewed from the direction from the first electrode 12 toward the upper cover 13, the solid-state source 20b is configured to cover the second electrode E2 and the third electrode E3. The solid-state source 20b is configured to be separate from the upper cover 13 of the chamber 11.

[0365] According to this structure, Figure 18 In the plasma processing apparatus shown, the solid source 20b (20) is preferentially sputtered in plasma P3 (low-frequency plasma) generated by the third electrode E3. Therefore, oxygen is supplied to the silicon substrate S, which is the object to be processed, in a manner that increases the oxygen content in the radial direction of the silicon substrate S.

[0366] Therefore, in Figure 18 The plasma processing device shown also includes... Figure 15Similarly, the plasma processing apparatus shown can improve the degree of anisotropy in plasma processing throughout the entire region from the center to the outer periphery of the silicon substrate S. The side shape of the recessed pattern formed on the silicon substrate remains approximately straight in the depth direction of the recessed pattern.

[0367] Figure 19 This is a schematic cross-sectional view illustrating other examples of plasma devices used in this embodiment.

[0368] In the plasma processing device 10 of this example, such as Figure 19 As shown, it is possible to obtain the same as Figure 18 The plasma processing device shown has the same effect. Based on this, Figure 19 In the plasma processing apparatus, the cover connected to the chamber 11 is a solid-state source. Therefore, it is not necessary to maintain a solid-state source structure within the chamber. Furthermore, since the cover connected to the chamber 11 is constructed of a solid-state source, the discharge states of the plasmas P2 and P3 generated within the chamber can be further stabilized.

[0369] Therefore, in Figure 19 In plasma processing devices, also with Figure 15 Similarly, in the plasma processing apparatus shown, the side shape of the recessed pattern formed on the silicon substrate S remains approximately straight in the depth direction of the recessed pattern throughout the entire region from the center to the outer periphery of the silicon substrate S.

[0370] Figure 20 This is a schematic cross-sectional view illustrating other examples of plasma devices used in this embodiment.

[0371] In the plasma processing device 10 of this example, such as Figure 20 As shown, the gas introduction device 30 is connected to the side wall portion 15b (11) of the chamber 11. When viewed from the vertical direction of the top cover 13, the area for configuring the solid source 20d (20) is located at a position overlapping with the electrode (second electrode E2) on the inner peripheral side.

[0372] In the plasma processing apparatus 10 of this example, the frequency λ2 of the power applied to the second electrode E2 is lower than the frequency of the power applied to the third electrode E3. That is, Figure 20 The second frequency λ2 and the third frequency λ3 of the plasma processing device 10 shown have a relationship of λ2 < λ3. The gas introduction device 30 is connected to the side wall portion 15b (11) of the chamber 11.

[0373] exist Figure 20In the plasma processing apparatus 10 shown, when the gas introduction device 30 is disposed in the side wall portion 15b(11) of the chamber 11, there is a tendency for defects to occur at the center of the silicon substrate S. Therefore, in the plasma processing apparatus 10 of this example, as Figure 20 As shown, the solid source 20d (20) is positioned at a location overlapping with the electrode (second electrode E2) on the inner circumferential side.

[0374] Therefore, it is possible to Figure 20 The center portion of the silicon substrate S in the plasma processing apparatus shown is obtained in Figure 15 The plasma processing apparatus shown has an effect on the outer periphery of the silicon substrate S.

[0375] Therefore, in Figure 20 The plasma processing device shown also includes... Figure 15 Similarly, in the plasma processing apparatus shown, the side shape of the recessed pattern formed on the silicon substrate S remains approximately straight in the depth direction of the recessed pattern throughout the entire region from the center to the outer periphery of the silicon substrate S.

[0376] Figure 21 This is a schematic cross-sectional view illustrating other examples of plasma devices used in this embodiment.

[0377] In the plasma processing device 10 of this example, such as Figure 21 As shown, the gas introduction device 30 is connected to the side wall portion 15b (11) of the chamber 11. When viewed from the vertical direction of the top cover 13, the area for configuring the solid source 20e (20) is located at a position overlapping with the two electrodes (second electrode E2, third electrode E3).

[0378] That is, in having Figure 21 In the plasma processing apparatus with the structure shown, the region where the solid-state source 20e is disposed within the chamber 11 is located at a position overlapping with the second electrode E2 and the third electrode E3, and is positioned to cover both electrodes. The solid-state source 20e is configured to be separate from the upper cover 13.

[0379] According to this structure, Figure 21 In the plasma processing apparatus shown, the solid source 20e(20) is preferentially sputtered in a low-frequency plasma P2. Therefore, oxygen is supplied to the silicon substrate S, which is the object being processed, in a manner that increases the oxygen content in the radial direction of the silicon substrate S.

[0380] Therefore, in Figure 21 The plasma processing device shown also includes... Figure 20Similarly, in the plasma processing apparatus shown, the side shape of the recessed pattern formed on the silicon substrate S remains approximately straight in the depth direction of the recessed pattern throughout the entire region from the center to the outer periphery of the silicon substrate S.

[0381] Figure 22 This is a schematic cross-sectional view illustrating other examples of plasma devices used in this embodiment.

[0382] In the plasma processing device 10 of this example, such as Figure 22 As shown, the top cover of the chamber is constructed from a solid source 20f(20).

[0383] thus, Figure 22 The plasma processing device 10 shown is capable of obtaining plasma with... Figure 21 The plasma processing device 10 shown has the same effect.

[0384] Based on this, Figure 22 In the plasma processing apparatus 10 shown, since the upper cover of the chamber is a solid-state source, it is not necessary to maintain a solid-state source structure inside the chamber. Furthermore, because the upper cover of the chamber is constructed of a solid-state source, the discharge states of plasmas P2 and P3 within the chamber can be further stabilized.

[0385] Therefore, in Figure 22 The plasma processing device shown also includes... Figure 21 Similarly, in the plasma processing apparatus shown, the side shape of the recessed pattern formed on the substrate remains approximately straight in the depth direction of the recessed pattern throughout the entire region from the center to the outer periphery of the silicon substrate S.

[0386] The etching method according to the second embodiment of the present invention will now be described with reference to the accompanying drawings.

[0387] Figure 23 This is a schematic cross-sectional view showing a substrate manufactured by the etching method involved in this embodiment. Figure 24 This is a flowchart illustrating the etching method involved in this embodiment.

[0388] like Figure 23 As shown, the etching method described in this embodiment forms a pattern on a polyimide layer P stacked on a silicon substrate S.

[0389] like Figure 24 As shown, the etching method involved in this embodiment includes a pretreatment step S11, a resist pattern formation step S12, a resist protective film formation step S17, a dry etching step S14, and a post-treatment step S18.

[0390] exist Figure 24In the pretreatment step S11 shown, a polyimide layer P of a specified thickness is formed on the entire surface of a silicon substrate S made of a conductor, insulator or semiconductor.

[0391] Figure 25 This is a cross-sectional view showing the process of the etching method involved in this embodiment.

[0392] exist Figure 24 In the resist pattern forming process S12 shown, as Figure 25 As shown, a resist layer M is formed on the surface of the polyimide layer P.

[0393] The resist layer M can be formed using a known resin resist. Film formation conditions can be appropriately selected from factors such as positive and negative modes, exposure wavelength, coating method, and film formation method to form the resist layer M with a specified thickness. Regarding the material constituting the resist layer M, examples include photosensitive insulators and other known materials.

[0394] Furthermore, in the resist pattern forming process S12, such as Figure 25 As shown, an opening pattern (mask pattern) is formed on the resist layer M, which defines the processing area for the polyimide layer P. The opening pattern in this embodiment corresponds, for example, to the opening pattern MS described in the embodiments above. The shape of the opening pattern in the resist layer M corresponds to the shape of the recessed pattern PS formed on the polyimide layer P.

[0395] Specifically, in the resist pattern forming process S12, a resist layer M, which is a photoresist, is stacked on a polyimide layer P, and the photoresist is exposed and developed. Furthermore, a resist layer M with an opening pattern is formed by performing known removal processes such as wet etching and dry etching.

[0396] Figure 26 This is a cross-sectional view showing the process of the etching method involved in this embodiment.

[0397] exist Figure 24 In the resist protective film formation process S17 shown, as Figure 26 As shown, a resist protective film Mm is formed on the surface of the resist layer M by anisotropic plasma treatment. Furthermore, the resist protective film formation step S17 can also be performed in a different processing chamber than the dry etching step S14, which is performed after the resist protective film formation step S17.

[0398] The resist protective film Mm is a film that can protect the resist layer M from etching during the dry etching process S14.

[0399] In the plasma CVD method used in the resist protective film formation process S17, a mixture of SiF4 and O2, SiCl4 and O2, or SiH4, TEOS, etc., with O2 is supplied to the chamber to form Si. x O y α z The plasma CVD method is performed using a gas. This allows a resist protective film Mm, composed of a SiOF film, to be formed on the resist layer M.

[0400] The SiOF film has a similar structure to the SiO2 film. Therefore, the thickness of the SiOF film will not decrease in the dry etching process S14, which is performed after the resist protective film formation process S17.

[0401] A resist protective film Mm is formed on the surface of the resist layer M by anisotropic plasma treatment. The thickness of the resist protective film Mm formed on the sidewalls of the opening pattern in the resist layer M differs from the thickness of the resist protective film Mm formed on the surface of the resist layer M. Furthermore, the thickness of the resist protective film Mm formed at the bottom of the opening pattern in the resist layer M differs from the thickness of the resist protective film Mm formed on the surface of the resist layer M. This is because the step coverage of the resist protective film Mm is small.

[0402] In the resist protective film formation process S17 of this embodiment, the plasma treatment apparatus 10 described above is used in the same way as the resist protective film formation process S07 of the first embodiment in order to perform plasma treatment with high anisotropy.

[0403] In the resist protective film formation process S17 of this embodiment, the same conditions are set as in the resist protective film formation process S07 of the first embodiment.

[0404] For example, the same conditions as those in the first embodiment can be cited as conditions for the plasma CVD method.

[0405] Figure 27 This is a cross-sectional view showing the process of the etching method involved in this embodiment.

[0406] exist Figure 24 In the dry etching process S14 shown, as Figure 27 As shown, anisotropic plasma etching is used to excavate the polyimide layer P corresponding to the opening pattern of the resist layer M, forming a recessed pattern PS.

[0407] Examples of etching conditions in the dry etching process S14 include gas type, gas flow rate, power, pressure, temperature, distance from the plasma, and time.

[0408] Furthermore, in Figure 24 In the post-processing step S18 shown, the resist protective film Mm is removed as needed by a wet etching process or a process similar to that in the first embodiment. Further, the resist layer M is removed by performing a wet etching process or a process similar to that in the dry etching process S14, thereby concluding the etching method involved in this embodiment.

[0409] In this embodiment, the same effects as those in the embodiments described above can be achieved.

[0410] [Example]

[0411] The embodiments of the present invention will now be described.

[0412] Here, as a specific example of the etching method in this invention, a confirmation test will be described.

[0413] <Experimental Example 1>

[0414] As mentioned above, using Figure 18 The plasma processing apparatus 10 shown, as in the first embodiment, has recessed patterns VS and VL formed on a silicon substrate S. When forming the recessed patterns VS and VL, a resist layer M and a resist protective film Mm made of resin are used.

[0415] Here, a via with a diameter of 3 μm and a depth of 26 μm is formed as a recessed pattern VS. A via with a diameter of 5 μm and a depth of 26 μm is formed as a recessed pattern VL. At this time, the deposition process S03, the dry etching process S04, and the ashing process S05 are performed as a cycle, and this cycle is repeated 50 times (cycles). Furthermore, a resist protective film formation process S07 is performed every 10 cycles. In other words, the resist protective film formation process S07 is inserted between the 10th and 11th cycles.

[0416] • Deposition process S03: A deposition process for forming carbon-containing thin films.

[0417] • Dry etching process S04: Etching the bottom insulating layer of the TSV using a carbon-containing thin film as a mask

[0418] • Ashing process S05: Ashing process for removing carbon-containing film

[0419] • Resist protective film formation process S07: The process of forming a SiOF film (the resist protective film formation process is performed after the 10th cycle).

[0420] Post-processing step S08: The process of forming through electrodes on a silicon substrate.

[0421] The following describes the conditions for forming a via.

[0422] exist Figure 18 In the plasma processing apparatus 10 shown, the diameter D [mm] of the first electrode 12, which serves as a support for supporting the silicon substrate, is fixed at 400 mm, and the diameter d [mm] of the second electrode E2 is fixed at 400 mm.

[0423] Conditions in deposition process S03

[0424] Supply gas: C4F8

[0425] Gas flow rate: C4F8 200 sccm

[0426] Handling atmosphere pressure: 9 Pa

[0427] Power supplied to the second electrode E2: 1500W

[0428] The frequency λ2 of the power supplied by the second electrode E2 is 13.56MHz.

[0429] Power supplied to the third electrode E3: 2000W

[0430] The frequency λ3 of the power supplied by the third electrode E3 is 2MHz.

[0431] Bias power: 0W

[0432] Processing time: 14 seconds

[0433] Conditions in dry etching process S04

[0434] Supply gases: SF6, O2, SiF4

[0435] Gas flow rates: SF6 275 sccm, O2 40 sccm, SiF4 50 sccm

[0436] Handling atmosphere pressure: 9 Pa

[0437] Power supplied to the second electrode E2: 2000W

[0438] The frequency λ2 of the power supplied by the second electrode E2 is 13.56MHz.

[0439] Power supplied to the third electrode E3: 2000W

[0440] The frequency λ3 of the power supplied by the third electrode E3 is 2MHz.

[0441] Bias power: 100~200W

[0442] The bias power frequency λ1: 400kHz

[0443] Processing time: 10 seconds

[0444] Conditions in ashing process S05

[0445] Gas supplied: O2

[0446] Gas flow rate: O2 450 sccm

[0447] Handling atmosphere pressure: 9 Pa

[0448] Power supplied to the second electrode E2: 2000W

[0449] The frequency λ2 of the power supplied by the second electrode E2 is 13.56MHz.

[0450] Power supplied to the third electrode E3: 2000W

[0451] The frequency λ3 of the power supplied by the third electrode E3 is 2MHz.

[0452] Bias power: 200W

[0453] The bias power frequency λ1: 400kHz

[0454] Processing time: 20 seconds

[0455] Photoresist layer material: PMER series chemically amplified photoresist (manufactured by Tokyo Ohka Kogyo Co., Ltd.)

[0456] Resist layer thickness: 5μm

[0457] Conditions in resist protective film formation process S07

[0458] Implement every 10 cycles

[0459] Supply gases: O2, SiF4

[0460] Gas flow rates: O2 160 sccm, SiF4 200 sccm

[0461] Handling atmosphere pressure: 9 Pa

[0462] Power supplied to the second electrode E2: 2000W

[0463] The frequency λ2 of the power supplied by the second electrode E2 is 13.56MHz.

[0464] Power supplied to the third electrode E3: 2000W

[0465] The frequency λ3 of the power supplied by the third electrode E3 is 2MHz.

[0466] Bias power: 0W

[0467] Processing time: 10 seconds

[0468] Figure 28 It is a schematic cross-sectional view of the concave patterns VS and VL formed based on the above conditions.

[0469] Figure 29 This is a schematic cross-sectional view showing the recessed pattern obtained by the etching method of the comparative example. In the comparative example, the recessed pattern is formed without forming a SiOF film.

[0470] Based on the above results, it is important to set the processing conditions in the following manner in this invention.

[0471] First, a resist pattern forming process is performed, which forms a resin resist with a resist pattern.

[0472] Next, a silicon dry etching process is performed to eliminate RIE-lag by repeatedly performing a total of three steps, which are carried out during C... x F y Following the deposition step, an etching step is performed, followed by a deposition-ashing step. This resist patterning process enables precise silicon dry etching.

[0473] The process of forming a SiOF film involves repeatedly performing the following three steps within the same process chamber. These three steps are performed during the C… x F y After the deposition step, an etching step is performed, followed by a deposition-ashing step.

[0474] Therefore, since the silicon substrate does not move between the multiple chambers, the amount of particles can be reduced.

[0475] Industrial availability

[0476] As an example of the application of the present invention, the present invention can be used to achieve protection of the device layer formed on the substrate and protection of the resist material that does not have resistance.

[0477] Explanation of reference numerals in the attached figures

[0478] D1, D2, D3, D4… sedimentary layers

[0479] M…Resist layer (mask layer)

[0480] Mm…Resistant protective film

[0481] MS, ML... Opening patterns (mask patterns)

[0482] VS, VL…recessed patterns

[0483] VSq, VLq... sidewalls

[0484] VSb, VLb, VSb1, VLb1, VSb2, VLb2, VSb3, VLb3...bottom

[0485] A… High-frequency power supply (primary power supply)

[0486] B…High-frequency power supply (secondary power supply)

[0487] C…High-frequency power supply (third power supply)

[0488] E2…Second Electrode

[0489] E3…Third electrode

[0490] G…process gases

[0491] M / B… Matching Box

[0492] S…The substrate being processed (silicon substrate)

[0493] TMP…exhaust system

[0494] λ1…frequency (first frequency)

[0495] λ2…frequency (second frequency)

[0496] λ3… frequency (third frequency)

[0497] 10…Plasma processing device

[0498] 11…chamber

[0499] 12…First electrode (support part)

[0500] 13…Top Cover

[0501] 20, 20a, 20b, 20c, 20d, 20e, 20f… Solid-state source

[0502] 30…Gas introduction device

Claims

1. An etching method, comprising: The resist pattern forming process forms a resist pattern on a resist layer made of resin on the workpiece. The etching process involves etching the workpiece through the resist layer having the resist pattern; as well as In the resist protective film formation process, a plasma film deposition method is used to form a resist protective film on the resist layer. The etching process is repeated multiple times. After repeatedly performing the etching process, the resist protective film formation process is performed. The resist protective film formation process is not performed until the etched state of the workpiece obtained through the etching process reaches the specified state.

2. The etching method according to claim 1, wherein, The processing gas used in the resist protective film formation process includes gases capable of forming Si. x O y α z The gas.

3. The etching method according to claim 1, wherein, After the workpiece is etched to a specified aspect ratio, the resist protective film formation process is performed.

4. The etching method according to claim 1, wherein, The object being processed is made of silicon.

5. The etching method according to claim 4, comprising: The deposition process performed prior to the etching process; and The ashing process performed after the etching process, In the deposition process, a first gas is used to form a deposition layer on the workpiece according to the resist pattern. In the etching process, the workpiece is dry-etched using a second gas according to the resist pattern. In the ashing process, a third gas is used. In the deposition process, the first gas contains fluorocarbons. In the etching process, the second gas contains sulfur fluoride and silicon fluoride. In the ashing process, the third gas contains oxygen. In the ashing process, the surface of the workpiece is subjected to anisotropic plasma treatment with anisotropy in the direction of forming the recessed pattern. In the anisotropic plasma treatment, an alternating voltage is applied to electrodes positioned opposite to the workpiece to generate inductively coupled plasma. The frequency of the AC voltage applied to the electrode at a position corresponding to the central portion of the surface of the workpiece is different from the frequency of the AC voltage applied to the electrode at a position corresponding to the outer periphery of the surface of the workpiece.

6. The etching method according to claim 5, wherein, Prepare a plasma processing apparatus, the plasma processing apparatus having: A chamber having a top cover having a central portion and an outer peripheral portion located outside the central portion, and the chamber being configured to perform plasma treatment on the subject in an internal space capable of depressurization; A flat first electrode is disposed within the cavity and used to hold the object to be processed. The first power source is configured to apply a bias voltage of a first frequency λ1 to the first electrode; A spiral-shaped second electrode is disposed outside the chamber and on the opposite side of the first electrode relative to the upper cover, and the second electrode is disposed in the central portion; A spiral-shaped third electrode is disposed outside the chamber and on the opposite side of the first electrode relative to the upper cover, and the third electrode is disposed on the outer periphery outside the second electrode; The second power source applies an AC voltage with a second frequency λ2 to the second electrode; The third power source applies an AC voltage of a third frequency λ3 to the third electrode; A gas introduction device introduces a process gas containing fluorine into the chamber; as well as A solid-state source, located within the cavity between the upper cover and the first electrode, and configured to be closer to the upper cover than the first electrode, is used for sputtering. During the anisotropic plasma treatment, When the second frequency λ2 and the third frequency λ3 are in a relationship of λ2 > λ3. The gas inlet device is disposed in the central part of the upper cover.

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