One-time programmable memory elements

Abstract

The present invention discloses a one-time programmable memory device. The semiconductor device mainly includes an input / output region, a one-time programmable capacitor region, and a core region defined on a substrate. A first metal gate is disposed in the input / output region and the first metal gate includes a first high-k dielectric layer. A second metal gate is disposed in the one-time programmable capacitor region and a third metal gate is disposed in the core region. The third metal gate includes a third high-k dielectric layer and the first high-k dielectric layer, and the third high-k dielectric layer includes an I-shape.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a one-time programmable memory device comprising a metal gate. Background Art

[0002] Semiconductor memory devices have been widely used in various electronic devices. For example, non-volatile memory is widely used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, and other applications. Generally speaking, non-volatile memory mainly includes multi-time programmable (MTP) memory and one-time programmable (OTP) memory. Compared with rewritable memory, one-time programmable memory has the advantages of lower manufacturing cost and less loss of stored data. However, one-time programmable memory can only perform one-time data burning. Once the bits of specific memory cells in a specified memory block are rewritten through a one-time data writing program, those specific memory cells in the specified memory block cannot be burned again.

[0003] Since existing one-time programmable memory devices still have disadvantages such as weak read current in read mode and long stress time in program mode, how to improve the existing one-time programmable memory device architecture to solve the above problems is an important issue today. Summary of the Invention

[0004] One embodiment of the present invention discloses a semiconductor device, which mainly includes an input / output region, a one-time programmable capacitor region, and a core region defined on a substrate. A first metal gate is disposed in the input / output region and the first metal gate includes a first high-k dielectric layer. A second metal gate is disposed in the one-time programmable capacitor region and a third metal gate is disposed in the core region, wherein the third metal gate includes a third high-k dielectric layer and the first high-k dielectric layer, and the third high-k dielectric layer includes an I-shape.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes an input / output region, a one-time programmable capacitor region, and a core region defined on a substrate, a first metal gate disposed in the input / output region and comprising a first high-k dielectric layer, a second metal gate disposed in the one-time programmable capacitor region, and a third metal gate disposed in the core region, wherein the third metal gate comprises a third high-k dielectric layer and the first high-k dielectric layer, and the third high-k dielectric layer comprises a U-shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a top view of a semiconductor device according to an embodiment of the present invention;

[0007] Figures 2 to 4 for Figure 1 A schematic cross-sectional view of the semiconductor components fabricated in each region;

[0008] Figure 5 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;

[0009] Figure 6 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention;

[0010] Figure 7 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Description of main component symbols

[0012] 12: Base

[0013] 14: Input / Output Area

[0014] 16: Core Area

[0015] 18: One-time programmable capacitance area

[0016] 20 static random access memory area

[0017] Unit 22

[0018] 24: Surrounding area

[0019] 26: Unit Area

[0020] 28: Surrounding area

[0021] 30: Shallow Trench Isolation

[0022] 32: Gate structure

[0023] 34: Gate structure

[0024] 36: Gate structure

[0025] 38: Gate structure

[0026] 40: Gate dielectric layer

[0027] 42: High dielectric constant dielectric layer

[0028] 44: Gate material layer

[0029] 46: gap wall

[0030] 48: doping area

[0031] 50: interlayer dielectric layer

[0032] 52: Work function metal layer

[0033] 54: Low impedance metal layer

[0034] 56: Hard mask

[0035] 58: interlayer dielectric layer

[0036] 60: Contact plug DETAILED DESCRIPTION

[0037] Please refer to Figures 1 to 4 , Figures 1 to 4 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 1 A top view of a semiconductor device according to an embodiment of the present invention is shown. Figures 2 to 4 Then Figure 1 Schematic diagram of the cross section of semiconductor components made in each area. Figures 1 to 2 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and an input / output region 14, a core region 16, a one-time programmable capacitor region 18, and a static random access memory region 20 are defined on the substrate. The one-time programmable capacitor region 18 may further include a cell region 22 and a peripheral region 24, and the static random access memory region 20 may also include a cell region 26 and a peripheral region 28.

[0038] In this embodiment, in subsequent fabrication processes, metal oxide semiconductor (MOS) transistors, for example, are preferably fabricated in the I / O region 14 and the core region 16, while an integrated structure of a MOS transistor and a STP capacitor is preferably fabricated in the STP capacitor region 18. Furthermore, since the present invention focuses on integrating metal gate structures into the I / O region 14, the core region 16, and the STP capacitor region 18, the elements of the SRAM region 20 are preferably not included in subsequent fabrication processes. Shallow trench isolation (STI) 30 is then formed in the substrate 12 within the I / O region 14, the core region 16, and the STP capacitor region 18. An ion implantation process is then performed to implant N-type or P-type dopants into the substrate 12, thereby forming well regions within the substrate 12 in each region.

[0039] Then, a gate structure 32 is formed in the input / output region 14, a gate structure 34 is formed in the core region 16, and gate structures 36 and 38 are formed in the one-time programmable capacitor region 18. In the present embodiment, the gate structures 32, 34, 36, and 38 can be manufactured by a gate-first manufacturing process, a gate-last manufacturing process of a high-k first manufacturing process, and a gate-last manufacturing process of a high-k last manufacturing process according to the manufacturing process requirements. Taking the high-k first manufacturing process of the present embodiment as an example, a silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiO) can be sequentially formed. A gate dielectric layer 40 or dielectric layer composed of SiO2 (SiO2), a high-k dielectric layer 42, a gate material layer 44 composed of polysilicon, and an optional hard mask (not shown) are formed on the substrate 12. A pattern transfer process is performed using a patterned photoresist (not shown) as a mask. A single etching or sequential etching steps are used to remove portions of the gate material layer 44, portions of the high-k dielectric layer 42, and portions of the gate dielectric layer 40. The patterned photoresist is then stripped to form gate structures 32, 34, 36, and 38 composed of the patterned gate dielectric layer 40, the patterned high-k dielectric layer 42, and the patterned gate material layer 44 on the substrate 12.

[0040] In the present embodiment, the high-k dielectric layer 42 includes a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), and strontium bismuth tantalum oxide (SrTiO3). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0041] It is noteworthy that in this embodiment, the gate dielectric layer 40 in the core region 16 and the one-time programmable capacitor region 18 preferably has the same thickness, but both thicknesses are less than the thickness of the gate dielectric layer 40 in the input / output region 14. For example, the thickness of the gate dielectric layer 40 in the input / output region 14 is preferably between approximately 25 angstroms and 45 angstroms, or preferably approximately 35 angstroms, while the thickness of the gate dielectric layer 40 in the core region 16 is between approximately 10 angstroms and 20 angstroms, or preferably approximately 15 angstroms. The thickness of the gate dielectric layer 40 in the one-time programmable capacitor region 18 is also between approximately 10 angstroms and 20 angstroms, or preferably approximately 15 angstroms. Furthermore, the high-k dielectric layer 40 in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18 preferably has the same thickness, for example, but not limited to, between 13 angstroms and 23 angstroms, or preferably 18 angstroms.

[0042] According to one embodiment of the present invention, the steps of forming the gate dielectric layers 40 having different thicknesses in the aforementioned regions can be performed by first forming a gate dielectric layer (not shown) entirely over the I / O region 14, the core region 16, and the one-time programmable capacitor region 18, forming a patterned mask (not shown) covering the core region 16 and the one-time programmable capacitor region 18, and then forming another gate dielectric layer over the gate dielectric layer in the I / O region 14. In this way, the overall gate dielectric layer thicknesses in the core region 16 and the one-time programmable capacitor region 18 are respectively thinner than the overall gate dielectric layer 40 thickness in the I / O region 14. Furthermore, according to another embodiment of the present invention, a gate dielectric layer (not shown) may be formed entirely over the I / O region 14, the core region 16, and the one-time programmable capacitor region 18. A patterned mask (not shown) may then be formed to cover the I / O region 14. An etching process, for example, may then be used to remove portions of the gate dielectric layer in the core region 16 and the one-time programmable capacitor region 18 so that the remaining gate dielectric layer thicknesses in the core region 16 and the one-time programmable capacitor region 18 are respectively thinner than the gate dielectric layer 40 in the I / O region 14. These variations are all within the scope of the present invention.

[0043] Then, at least one spacer 46 is formed on the sidewalls of each gate structure 32, 34, 36, 38, and a doped region 48 or source / drain region is formed in the substrate 12 on one side or both sides of the gate structure 32, 34, 36, 38. In the present embodiment, the spacer 46 may be a single spacer or a composite spacer, for example, it may include an offset spacer and a main spacer in detail. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The doped region 48 or source / drain region may include different dopants depending on the conductivity type of the transistor to be prepared, for example, it may include P-type dopants or N-type dopants.

[0044] It should be noted that although the above embodiment preferably forms the doped region 48 after forming the gate structures 32, 34, 36, and 38, in order to allow the doped region 48 to extend further to the position directly below the gate structure 38, other embodiments of the present invention may choose to first form the gate structures 32, 34, and 36, and then form the doped region 48 on both sides of the gate structures 32, 34, and 36 before forming the gate structure 38. In addition, according to another embodiment of the present invention, the gate structures 32, 34, 36, and 38 may be formed, a patterned mask (not shown) may be formed to cover the gate structures 32, 34, and 36, and ions may be implanted into the substrate 12 directly below the gate structure 38 using an oblique angle ion implantation process to form a portion of the doped region 48. The patterned mask may then be removed, and another ion implantation process may be performed to form all of the doped regions 48 in the substrate 12 on both sides of the gate structures 32, 34, and 36. These variations are all within the scope of the present invention.

[0045] like Figure 3 As shown, an interlayer dielectric layer 50 is then formed on the gate structures 32, 34, 36, 38 and the shallow trench isolation 30, and a planarization process is performed, such as chemical mechanical polishing (CMP) to remove a portion of the interlayer dielectric layer 50 and expose the gate material layer 44 composed of polysilicon material, so that the upper surface of each gate material layer 44 is flush with the upper surface of the interlayer dielectric layer 50. A metal gate replacement process is then performed to convert the gate structures 32, 34, 36, 38 into metal gates. For example, a patterned mask (not shown) may be selectively formed to cover the gate structures 32, 34, 36, and 38. A selective dry or wet etching process may then be performed, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH), to remove the gate material layer 44 from the gate structures 32, 34, 36, and 38, thereby forming a recess (not shown) in the interlayer dielectric layer 50. A conductive layer comprising a work function metal layer 52 and a low-resistance metal layer 54 is then sequentially formed within the recess, and a planarization process is then performed to ensure that the surfaces of the U-shaped work function metal layer 52 and the low-resistance metal layer 54 are flush with the surface of the interlayer dielectric layer 50.

[0046] In this embodiment, the work function metal layer 52 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low resistance metal layer 54, wherein the barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The low resistance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. Since converting a dummy gate into a metal gate based on a metal gate replacement process is a well-known technique in this field, it will not be described in detail here. Subsequently, a portion of the work function metal layer 52 and a portion of the low resistance metal layer 54 may be removed to form a groove (not shown), and then a hard mask 56 may be filled in the groove and made flush with the surface of the interlayer dielectric layer 50. The hard mask 56 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0047] like Figure 4As shown, another interlayer dielectric layer 58 may then be optionally formed on the gate structures 32, 34, 36, 38 and the interlayer dielectric layer 50 formed by the metal gates. A pattern transfer process may then be performed. For example, a patterned mask may be used to remove portions of the interlayer dielectric layers 58 and 50 adjacent to the gate structures 32, 34, 36 and the interlayer dielectric layer 58 and hard mask 56 on top of the gate structure 38 to form a plurality of contact holes (not shown) and expose the doped regions 48 and the top of the low-resistance metal layer 54. Each contact hole is then filled with a desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. Then, a planarization process is performed, such as chemical mechanical polishing to remove part of the conductive material to form contact plugs 60 to contact and electrically connect each doped region 48 and the gate structure 38. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0048] Please refer to Figure 4 , Figure 4 FIG. 1 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention. Figure 4 As shown, the I / O region 14 preferably includes a metal gate transistor, the core region 16 includes another metal gate transistor, and the one-time programmable capacitor region 18 includes two metal gates together forming a one transistor and one capacitor (1T1C) structure. In this structure, the doped region 48 directly beneath the gate structure 38 serves as a capacitor bottom electrode, the gate dielectric layer 40 in the gate structure 38 serves as a capacitor dielectric layer, and the work function metal layer 52 and the low resistance metal layer 54 in the gate structure 38 serve as capacitor top electrodes. As previously described, the thickness of the gate dielectric layer 40 of the metal gate in the core region 16 is preferably equal to the thickness of the gate dielectric layer 40 of the metal gate in the one-time programmable capacitor region 18. Furthermore, the thickness of the gate dielectric layer 40 in the core region 16 and the one-time programmable capacitor region 18 is preferably less than the thickness of the gate dielectric layer 40 of the metal gate in the I / O region 14. According to a preferred embodiment of the present invention, a thinner gate dielectric layer 40 is provided in the one-time programmable capacitor region 18 to effectively reduce the voltage required for programming the capacitor and thereby improve device performance.

[0049] Please continue to refer to Figure 5 , Figure 5 FIG. 1 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention. Figure 5 As shown, the present invention can be based on the above Figure 2In the embodiment, when performing the high-k dielectric layer fabrication process, a gate dielectric layer 40 and a high-k dielectric layer 42 are first formed in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18. The high-k dielectric layer 42 in the one-time programmable capacitor region 18 is removed, but the high-k dielectric layer 42 in the input / output region 14 and the core region 16 is retained. A gate material layer 44 is formed in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18. A pattern transfer process is then used to remove portions of the gate material layer 44, the high-k dielectric layer 42, and the gate dielectric layer 40 to form gate structures 32, 34, 36, and 38 in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18. Thereafter, spacers 46 and doped regions 48 are formed, and then, as described above, the gate material layer 44, the high-k dielectric layer 42, and the gate dielectric layer 40 are removed. Figure 3 The fabrication process converts each polysilicon gate into a metal gate using a metal gate replacement process. Compared to the previous embodiment in which the I-shaped high-k dielectric layer 42 in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18 all directly contacts the work function metal layer 52, in this embodiment, since the high-k dielectric layer 42 in the metal gate of the one-time programmable capacitor region 18 has been completely removed, the metal gate of the one-time programmable capacitor region 18 preferably contacts the work function metal layer 52 via the gate dielectric layer 40, while the metal gates in the input / output region 14 and the core region 16 still directly contact the work function metal layer 52 via the I-shaped high-k dielectric layer 42.

[0050] Please refer to Figure 6 , Figure 6 FIG. 1 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention. Figure 6 As shown, compared to the aforementioned embodiment in which the metal gates in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18 are prepared by first using a high-k dielectric layer fabrication process, the present invention can also choose to use a later high-k dielectric layer fabrication process to fabricate metal gates in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18. From a structural point of view, since the high-k dielectric layer 42 is filled into the groove after the gate material layer 44 is hollowed out during the metal gate fabrication process, the high-k dielectric layer 42 formed in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18 preferably includes a U-shaped cross-section. In addition, as mentioned above Figure 4 and Figure 5 In the embodiment of the present embodiment, the thickness of the gate dielectric layer 40 of the metal gate in the core region 16 is preferably equal to the thickness of the gate dielectric layer 40 of the metal gate in the one-time programmable capacitor region 18. At the same time, the thickness of the gate dielectric layer 40 in the core region 16 and the one-time programmable capacitor region 18 are respectively smaller than the thickness of the gate dielectric layer 40 of the metal gate in the input / output region 14.

[0051] Please refer to Figure 7 , Figure 7 FIG. 1 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention. Figure 7 As shown, the present invention can be combined with Figure 5 and Figure 6 In the embodiment, a U-shaped high-k dielectric layer 42 is first formed in the input / output region 14, the core region 16, and the one-time programmable capacitor region 18 using a subsequent high-k dielectric layer fabrication process. The high-k dielectric layer 42 in the one-time programmable capacitor region 18 is removed, but the high-k dielectric layer 42 in the input / output region 14 and the core region 16 is retained. A work function metal layer 52 and a low-resistance conductive layer 54 are then formed on the high-k dielectric layer 42 in the input / output region 14 and the core region 16, and on the gate dielectric layer 40 in the one-time programmable capacitor region 18. In addition, as previously described, Figures 4 to 6 In this embodiment, the thickness of the gate dielectric layer 40 of the metal gate in the core region 16 is preferably equal to the thickness of the gate dielectric layer 40 of the metal gate in the one-time programmable capacitor region 18. Furthermore, the thickness of the gate dielectric layer 40 in both the core region 16 and the one-time programmable capacitor region 18 is preferably less than the thickness of the gate dielectric layer 40 of the metal gate in the input / output region 14. As described in the previous embodiment, providing a thinner gate dielectric layer 40 in the one-time programmable capacitor region 18 can reduce the voltage required for programming the capacitor and thereby improve device performance.

[0052] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: Include: a substrate, comprising an input / output region, a core region, and a one-time programmable capacitor region; A first metal gate is disposed in the input / output region, wherein the first metal gate comprises a first high-k dielectric layer; A second metal gate is disposed in the core region, wherein the second metal gate comprises a second high-k dielectric layer and the first high-k dielectric layer and the second high-k dielectric layer comprise an I-shape; A third metal gate is disposed in the one-time programmable capacitor region, wherein the third metal gate comprises a third high-k dielectric layer; as well as The fourth metal gate is disposed in the one-time programmable capacitor region and is located on one side of the third metal gate, wherein a portion of the fourth metal gate is located on the shallow trench isolation in the substrate, and another portion is located on the doped region in the substrate. 2 . The semiconductor device as claimed in claim 1 , wherein the third metal gate comprises a third high-k dielectric layer, and the third high-k dielectric layer comprises an I-shape. 3 . The semiconductor device of claim 1 , wherein the first metal gate comprises a first gate dielectric layer, the second metal gate comprises a second gate dielectric layer, and the third metal gate comprises a third gate dielectric layer. 4 . The semiconductor device as claimed in claim 3 , wherein the thickness of the second gate dielectric layer is smaller than the thickness of the first gate dielectric layer. The semiconductor device as claimed in claim 3 , wherein the thickness of the third gate dielectric layer is smaller than the thickness of the first gate dielectric layer. The semiconductor device as claimed in claim 3 , wherein the thickness of the second gate dielectric layer is equal to the thickness of the third gate dielectric layer.

7. A semiconductor element, characterized in that: Include: a substrate, comprising an input / output region, a core region, and a one-time programmable capacitor region; A first metal gate is disposed in the input / output region, wherein the first metal gate comprises a first high-k dielectric layer; A second metal gate is disposed in the core region, wherein the second metal gate comprises a second high-k dielectric layer and the first high-k dielectric layer and the second high-k dielectric layer comprise a U-shape; A third metal gate is disposed in the one-time programmable capacitor region, wherein the third metal gate comprises a third high-k dielectric layer; as well as The fourth metal gate is disposed in the one-time programmable capacitor region and is located on one side of the third metal gate, wherein a portion of the fourth metal gate is located on the shallow trench isolation in the substrate, and another portion is located on the doped region in the substrate. 8 . The semiconductor device as claimed in claim 7 , wherein the third metal gate comprises a third high-k dielectric layer, and the third high-k dielectric layer comprises a U-shape. 9 . The semiconductor device of claim 7 , wherein the first metal gate comprises a first gate dielectric layer, the second metal gate comprises a second gate dielectric layer, and the third metal gate comprises a third gate dielectric layer. 10 . The semiconductor device as claimed in claim 9 , wherein a thickness of the second gate dielectric layer is smaller than a thickness of the first gate dielectric layer. The semiconductor device as claimed in claim 9 , wherein the thickness of the third gate dielectric layer is smaller than the thickness of the first gate dielectric layer. 12 . The semiconductor device as claimed in claim 9 , wherein a thickness of the second gate dielectric layer is equal to a thickness of the third gate dielectric layer.

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