Thin film transistor, display panel and display device

Abstract

The present disclosure relates to the field of display technology, and proposes a thin film transistor, a display panel and a display device. The thin film transistor includes: a semiconductor material layer, a first insulating layer, and a gate layer. The semiconductor material layer is located on one side of a substrate, and the semiconductor material layer includes a first channel portion, a first doping portion, and a second channel portion connected in sequence; the first insulating layer is located on the side of the semiconductor material layer away from the substrate; the gate layer is located on the side of the first insulating layer away from the semiconductor material layer, and the gate layer includes: a first gate portion and a second gate portion, the orthographic projection of the first gate portion on the substrate coincides with the orthographic projection of the first channel portion on the substrate, and the first gate portion is used to receive a gate drive signal; the orthographic projection of the second gate portion on the substrate coincides with the orthographic projection of the second channel portion on the substrate, and the second gate portion is suspended. The thin film transistor has a small leakage current.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor, a display panel and a display device. Background Art

[0002] Thin film transistors are usually used as switching devices in various electrical appliances. However, thin film transistors are prone to generate leakage current in the off state, thereby affecting the normal operation of the electrical appliances.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0004] Public Content

[0005] According to one aspect of the present disclosure, a thin film transistor is provided, which includes: a semiconductor material layer, a first insulating layer, and a gate layer. The semiconductor material layer is located on one side of a substrate, and the semiconductor material layer includes a first channel portion, a first doping portion, and a second channel portion connected in sequence. The first insulating layer is located on the side of the semiconductor material layer away from the substrate. The gate layer is located on the side of the first insulating layer away from the substrate, and the gate layer includes: a first gate portion and a second gate portion. The orthographic projection of the first gate portion on the substrate covers the orthographic projection of the first channel portion on the substrate, and the first gate portion is used to receive a gate drive signal; the orthographic projection of the second gate portion on the substrate covers the orthographic projection of the second channel portion on the substrate, and the second gate portion is suspended.

[0006] In an exemplary embodiment of the present disclosure, the orthographic projection of the first channel portion on the substrate is a rectangle, the orthographic projection of the first doped portion on the substrate is a rectangle, and the orthographic projection of the second channel portion on the substrate is a rectangle; the orthographic projection of the first channel portion on the substrate, the orthographic projection of the first doped portion on the substrate, and the orthographic projection of the second channel portion on the substrate are distributed sequentially along a first direction; and the orthographic projection of the first channel portion on the substrate, the orthographic projection of the first doped portion on the substrate, and the orthographic projection of the second channel portion on the substrate combine to form a rectangle.

[0007] In an exemplary embodiment of the present disclosure, a size of the first channel portion in the first direction of the orthographic projection of the substrate is S1, and a size of the second channel portion in the first direction of the orthographic projection of the substrate is S2; wherein the value of S1 / S2 is 3-15.

[0008] In an exemplary embodiment of the present disclosure, a size of the first doping portion in the first direction of the orthographic projection of the substrate is L; wherein the value of S1 / L is 3-15.

[0009] In an exemplary embodiment of the present disclosure, S1 is equal to 2.8-3.2 microns, S2 is equal to 0.2-0.8 microns, and L is equal to 0.2-0.8 microns.

[0010] In an exemplary embodiment of the present disclosure, the material of the semiconductor material layer is polycrystalline silicon semiconductor.

[0011] In an exemplary embodiment of the present disclosure, the semiconductor material layer further includes: a second doping portion and a third doping portion, the second doping portion is connected to the first channel portion; the third doping portion is connected to the second channel portion. The thin film transistor further includes a second insulating layer and a source / drain layer, the second insulating layer is located on the side of the gate layer away from the substrate; wherein the first insulating layer and the second insulating layer are formed with a first via hole penetrating the first insulating layer and the second insulating layer, and a second via hole penetrating the first insulating layer and the second insulating layer, the orthographic projection of the first via hole on the substrate substrate is located on the orthographic projection of the second doping portion on the substrate substrate, and the orthographic projection of the second via hole on the substrate substrate is located on the orthographic projection of the third doping portion on the substrate substrate. The source / drain layer is located on the side of the second insulating layer away from the substrate substrate, and the source / drain layer includes: a first conductive portion and a second conductive portion, the first conductive portion is connected to the second doping portion through the first via hole, for forming the first pole of the thin film transistor; the second conductive portion is connected to the third doping portion through the second via hole, for forming the second pole of the thin film transistor.

[0012] In an exemplary embodiment of the present disclosure, the semiconductor material layer further includes: a fourth doping portion and a third channel portion, wherein the fourth doping portion is connected between the first channel portion and the second doping portion; and the third channel portion is connected between the second doping portion and the fourth doping portion. The gate layer further includes: a third gate portion, wherein the orthographic projection of the third gate portion on the substrate covers the orthographic projection of the third channel portion on the substrate, and the third gate portion is connected to the first gate portion.

[0013] In an exemplary embodiment of the present disclosure, the semiconductor material layer further includes: a fourth doping portion and a third channel portion, wherein the fourth doping portion is connected between the second channel portion and the third doping portion; and the third channel portion is connected between the third doping portion and the fourth doping portion. The gate layer further includes: a third gate portion, wherein the orthographic projection of the third gate portion on the substrate covers the orthographic projection of the third channel portion on the substrate, and the third gate portion is connected to the first gate portion.

[0014] According to one aspect of the present disclosure, a display panel is provided, comprising at least one thin film transistor as described above.

[0015] In an exemplary embodiment of the present disclosure, at least one of the thin film transistors includes a first transistor, the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and the first transistor, the first electrode of the first transistor is connected to the gate of the driving transistor, and the first transistor forms the thin film transistor.

[0016] In an exemplary embodiment of the present disclosure, the second electrode of the first transistor is connected to the initial signal terminal, at least one of the thin film transistors further includes a second transistor, the pixel driving circuit further includes a second transistor, the second electrode of the second transistor is connected to the gate of the driving transistor, and the first electrode is connected to the first electrode of the driving transistor.

[0017] In an exemplary embodiment of the present disclosure, the display panel includes: a substrate, an active layer, a first conductive layer, and a second conductive layer. The active layer is located on one side of the substrate, and the active layer includes: a first active portion and a second active portion, wherein the first active portion is used to form a first channel portion of the first transistor; the second active portion is used to form a second channel portion of the first transistor, and the first active portion and the second active portion are distributed along a fourth direction in the orthogonal projection of the substrate and the orthogonal projection of the substrate. The first conductive layer is located on the side of the active layer away from the substrate, and the first conductive layer includes: a first gate line and a third conductive portion, wherein the orthogonal projection of the first gate line on the substrate covers the orthogonal projection of the first active portion on the substrate, and a portion of the first gate line is used to form a first gate of the first transistor, and the third direction intersects with the fourth direction; the orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the second active portion on the substrate, and is used to form the second gate of the first transistor. The second conductive layer is located on a side of the first conductive layer away from the base substrate, and the second conductive layer includes a second gate line, which is used to provide the initial signal end; wherein the orthographic projection of the third conductive portion on the base substrate is located on a side of the orthographic projection of the first gate line on the base substrate away from the orthographic projection of the second gate line on the base substrate.

[0018] In an exemplary embodiment of the present disclosure, the first transistor is the thin film transistor according to claim 8, the active layer further includes: a third active portion and a fourth active portion, the third active portion is used to form a third channel portion of the first transistor; the fourth active portion is used to form a fourth doped portion of the first transistor, the orthographic projection of the fourth active portion on the substrate is located on the side of the orthographic projection of the first gate line on the substrate substrate away from the orthographic projection of the third conductive portion on the substrate substrate; wherein the orthographic projection of the first gate line on the substrate substrate also covers the orthographic projection of the third active portion on the substrate substrate, and part of the first gate line is used to form a third gate of the first transistor; the second electrode of the driving transistor is connected to a first power supply terminal, the display panel further includes a third conductive layer, the third conductive layer is located on the side of the second conductive layer away from the substrate substrate, the third conductive layer includes a power supply line, the power supply line is used to provide the first power supply terminal, the orthographic projection of the power supply line on the substrate substrate extends along the fourth direction, and the orthographic projection of the first active portion on the substrate substrate is located on the side of the orthographic projection of the third active portion on the substrate substrate away from the orthographic projection of the power supply line on the substrate substrate.

[0019] In an exemplary embodiment of the present disclosure, an orthographic projection of the second gate line on the base substrate at least partially overlaps with an orthographic projection of the fourth active portion on the base substrate.

[0020] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power supply terminal, and the active layer also includes: a fifth active portion and a sixth active portion, the fifth active portion is used to form the first channel portion of the second transistor; the sixth active portion is used to form the second channel portion of the second transistor; the first conductive layer also includes: a third gate line, a fourth conductive portion, and a fifth conductive portion, the third gate line extends along the third direction in the orthographic projection of the substrate, and the orthographic projection of the third gate line on the substrate covers the orthographic projection of the fifth active portion on the substrate, and part of the third gate line is used to form the first gate of the second transistor; the orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the sixth active portion on the substrate, and is used to form the second gate of the second transistor; the fifth conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor. The second conductive layer also includes a sixth conductive portion, the orthographic projection of the sixth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fifth conductive portion on the substrate, and is used to form a second electrode of the capacitor, and the orthographic projection of the sixth conductive portion on the substrate is located on the side of the orthographic projection of the third gate line on the substrate away from the orthographic projection of the first gate line on the substrate; wherein the orthographic projection of the fourth conductive portion on the substrate is located between the orthographic projection of the third gate line on the substrate and the orthographic projection of the first gate line on the substrate.

[0021] In an exemplary embodiment of the present disclosure, the third direction is a row direction, the display panel also includes a first pixel driving circuit and a second pixel driving circuit adjacent to each other in the row direction, and the second conductive layer also includes: a first connecting portion, the first connecting portion and the driving transistor in the first pixel driving circuit are connected to the same power line; wherein the first connecting portion at least partially overlaps with the orthographic projection of the first gate of the second transistor in the second pixel driving circuit on the substrate.

[0022] In an exemplary embodiment of the present disclosure, the first gate line, the third gate line, the third conductive portion, and the fourth conductive portion are formed in the same layer by using an optical proximity correction mask technology.

[0023] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0026] Figure 1 A top view of an exemplary embodiment of a thin film transistor disclosed herein;

[0027] Figure 2 for Figure 1 A cross-sectional view at the position of the dotted line A;

[0028] Figure 3 It is a schematic structural diagram of another exemplary embodiment of a thin film transistor disclosed in the present invention;

[0029] Figure 4 is a top view of another exemplary embodiment of a thin film transistor disclosed in the present invention;

[0030] Figure 5 for Figure 4 A cross-sectional view at the position of the dotted line B;

[0031] Figure 6 is a top view of another exemplary embodiment of a thin film transistor disclosed in the present invention;

[0032] Figure 7 for Figure 6 A cross-sectional view at the position of the dashed line C;

[0033] Figure 8 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0034] Fig. 9 for Figure 8 A timing diagram of each node in a driving method of a pixel driving circuit;

[0035] Fig.10 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0036] Fig.11 for Fig.10 The structural layout of the active layer in the

[0037] Fig.12 for Fig.10 A structural layout of the first conductive layer;

[0038] Fig.13 for Fig.10 The structural layout of the second conductive layer;

[0039] Fig.14 for Fig.10 The structural layout of the third conductive layer;

[0040] Fig.15 for Fig.10 A structural layout of an active layer and a first conductive layer;

[0041] Fig.16 for Fig.10 A structural layout of an active layer, a first conductive layer, and a second conductive layer;

[0042] Fig.17 A partial structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0043] Fig.18 A partial structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0044] Fig.19 for Fig.10 A partial cross-sectional view at the dotted line A;

[0045] Fig. 20 It is a structural schematic diagram of another exemplary embodiment of the display panel disclosed in the present invention;

[0046] Fig.21 It is a partial structural schematic diagram of a mask in the optical proximity correction mask technology disclosed in the present invention;

[0047] Fig. 22 The figure is a curve showing the relationship between the leakage current and the gate-source voltage difference of the second transistor in the display panel of the present disclosure. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0050] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0051] This exemplary embodiment first provides a thin film transistor, such as Figure 1 , 2 As shown, Figure 1 is a top view of an exemplary embodiment of a thin film transistor disclosed in the present invention, Figure 2 for Figure 1 The cross-sectional view at the dotted line A. Figure 1 Only the structural layout of the semiconductor material layer in the thin film transistor is shown. The thin film transistor may include: a semiconductor material layer, a first insulating layer 3, and a gate layer. The semiconductor material layer is located on one side of a substrate 1, and the semiconductor material layer may include a first channel portion 21, a first doping portion 23, and a second channel portion 22 connected in sequence. The first insulating layer 3 may be located on the side of the semiconductor material layer away from the substrate 1. The gate layer is located on the side of the first insulating layer 3 away from the substrate 1. The gate layer may include: a first gate portion 41 and a second gate portion 42. The orthographic projection of the first gate portion 41 on the substrate 1 may cover the orthographic projection of the first channel portion 21 on the substrate 1, and the first gate portion 41 is used to receive a gate drive signal; the orthographic projection of the second gate portion 42 on the substrate 1 may cover the orthographic projection of the second channel portion 22 on the substrate 1, and the second gate portion is suspended. The second gate portion is suspended, which can be understood as that when the thin film transistor is placed or working independently, the second gate portion is not electrically connected to any conductive structure.

[0052] When the thin film transistor is working, only the first gate portion 41 is connected to the control signal terminal, and the second gate portion 42 is not connected to any signal terminal. When the thin film transistor needs to be turned on, the first gate portion 41 receives the turn-on signal, and the first channel portion 21 and the second channel portion 22 can generate a conductive channel under the action of the electric field of the first gate portion 41. In addition, the voltage of the second gate portion 42 can change under the coupling action of the first gate portion 41, so that the second channel portion 22 can further enhance the conductivity of its conductive channel under the action of the electric field of the second gate portion 42. When the thin film transistor needs to be turned off, under the dual action of the first channel portion 21 and the second channel portion 22, the leakage current of the thin film transistor is small. In addition, when the thin film transistor is turned off, the second gate portion 42 will affect the electric field between the source and drain of the thin film transistor, and the influence includes: the second gate portion 42 will induce an internal electric field opposite to the source and drain electric field in the source and drain electric field, that is, the second gate portion 42 will reduce the electric field between the source and drain of the thin film transistor, thereby reducing the leakage current between the source and drain.

[0053] In this exemplary embodiment, the orthographic projection of the second gate portion on the substrate may coincide with the orthographic projection of the second channel portion on the substrate. The orthographic projection of the first gate portion on the substrate may coincide with the orthographic projection of the first channel portion on the substrate.

[0054] In this exemplary embodiment, the thin film transistor may be an N-type transistor or a P-type transistor. This exemplary embodiment may be described by taking a P-type transistor as an example. The material of the semiconductor material layer may be a polycrystalline silicon semiconductor, wherein the first doped portion 23 may be a polycrystalline silicon conductor formed by doping polycrystalline silicon semiconductor with ions, and the first channel portion 21 and the second channel portion 22 may be undoped polycrystalline silicon semiconductors. In addition, the doped portions mentioned below may all be polycrystalline silicon conductors formed by doping polycrystalline silicon semiconductor with ions, and the channel portions may all be undoped polycrystalline silicon semiconductors. The thin film transistor may be a low-temperature polycrystalline silicon transistor. In the related art, low-temperature polycrystalline silicon transistors have high carrier mobility and reaction speed, however, the process difficulty that is difficult to overcome in low-temperature polycrystalline silicon transistors is that they have a large off-leakage current. The thin film transistor provided in the present disclosure may be a low-temperature polycrystalline silicon transistor, which may overcome the technical difficulty of its large leakage current. It should be understood that in other exemplary embodiments, the semiconductor material layer may also be formed of other materials, for example, the semiconductor material layer may be formed of a metal oxide semiconductor, for example, the semiconductor material layer may be formed of indium gallium zinc oxide.

[0055] In this exemplary embodiment, Figure 1 , 2As shown, the orthographic projection of the first channel portion 21 on the substrate 1 may be a rectangle, the orthographic projection of the first doping portion 23 on the substrate 1 may be a rectangle, and the orthographic projection of the second channel portion 22 on the substrate 1 may be a rectangle; the orthographic projection of the first channel portion 21 on the substrate 1, the orthographic projection of the first doping portion 23 on the substrate 1, and the orthographic projection of the second channel portion 22 on the substrate 1 are sequentially distributed along the first direction X; and the orthographic projection of the first channel portion 21 on the substrate 1, the orthographic projection of the first doping portion 23 on the substrate 1, and the orthographic projection of the second channel portion 22 on the substrate 1 may be combined to form a rectangle. It should be understood that in other exemplary embodiments, the orthographic projection of the first channel portion 21 on the substrate 1, the orthographic projection of the first doping portion 23 on the substrate 1, and the orthographic projection of the second channel portion 22 on the substrate 1 may also be other shapes, for example, the orthographic projection of the first channel portion 21 on the substrate 1, the orthographic projection of the first doping portion 23 on the substrate 1, and the orthographic projection of the second channel portion 22 on the substrate 1 may be a trapezoid, etc. The pattern formed by the orthographic projection of the first channel portion 21 on the base substrate 1, the orthographic projection of the first doping portion 23 on the base substrate 1, and the orthographic projection of the second channel portion 22 on the base substrate 1 may also be other shapes, which all fall within the protection scope of the present disclosure.

[0056] In this exemplary embodiment, the larger the size of the second channel portion 22 projected on the first direction X by the substrate 1, the smaller the leakage current of the thin film transistor when it is turned off, and the larger the absolute value of its threshold voltage. The larger the size of the first doping portion projected on the first direction X by the substrate 1, the smaller the leakage current of the thin film transistor when it is turned off, and the larger the absolute value of its threshold voltage. In this exemplary embodiment, the size of the first channel portion 21 projected on the first direction X by the substrate 1 is S1, and the size of the second channel portion 22 projected on the first direction X by the substrate 1 is S2; wherein the value of S1 / S2 can be 3-15. The size of the first doping portion projected on the first direction by the substrate 1 is L; wherein the value of S1 / L can be 3-15. When the size of the first doping portion projected on the first direction by the substrate 1 and the size of the second channel portion 22 projected on the first direction X by the substrate 1 are the above values, the thin film transistor has a lower leakage current and a closer threshold voltage than the structure without the second channel portion and the second gate portion. Specifically, in this exemplary embodiment, S1 may be equal to 2.8-3.2 microns, for example, S1 may be equal to 2.8 microns, 3 microns, or 3.2 microns; S2 may be equal to 0.2-0.8 microns, for example, S2 may be equal to 0.2 microns, 0.3 microns, 0.5 microns, or 0.8 microns; L may be equal to 0.2-0.8 microns, for example, L may be equal to 0.2 microns, 0.3 microns, 0.5 microns, or 0.8 microns. Among them, S2 may be equal to L, for example, S2 and L may both be equal to 0.5 microns.

[0057] In this exemplary embodiment, Figure 1 , 2As shown, the semiconductor material layer may further include: a second doping portion 24 and a third doping portion 25, wherein the second doping portion 24 may be connected to the first channel portion 21; and the third doping portion 25 may be connected to the second channel portion 22. The thin film transistor may further include a second insulating layer 5 and a source / drain layer, wherein the second insulating layer 5 is located on the side of the gate layer away from the base substrate 1. A first via hole 51 penetrating the first insulating layer and the second insulating layer, and a second via hole 52 penetrating the first insulating layer and the second insulating layer are formed on the first insulating layer 3 and the second insulating layer 5, wherein the orthographic projection of the first via hole 51 on the base substrate may be located on the orthographic projection of the second doping portion 24 on the base substrate 1, and the orthographic projection of the second via hole 52 on the base substrate may be located on the orthographic projection of the third doping portion 25 on the base substrate. The source / drain layer can be located on the side of the second insulating layer 5 away from the base substrate, and the source / drain layer may include: a first conductive portion 61 and a second conductive portion 62. The first conductive portion 61 can be connected to the second doped portion 24 through the first via 51 to form the first electrode of the thin film transistor; the second conductive portion 62 can be connected to the third doped portion 25 through the second via 52 to form the second electrode of the thin film transistor.

[0058] In this exemplary embodiment, Figure 3 FIG. 2 is a schematic diagram of another exemplary embodiment of a thin film transistor of the present disclosure. A buffer layer 7 may be provided on one side of the substrate 1 , and the thin film transistor may be provided on the side of the buffer layer 7 away from the substrate 1 .

[0059] In this exemplary embodiment, Figure 4 , 5 As shown, Figure 4 is a top view of another exemplary embodiment of a thin film transistor disclosed in the present invention, Figure 5 for Figure 4 The cross-sectional view at the dotted line B. Figure 4 Only the structural layout of the semiconductor material layer in the thin film transistor is shown. The semiconductor material layer may also include: a fourth doping portion 26 and a third channel portion 27, wherein the fourth doping portion 26 may be connected between the first channel portion 21 and the second doping portion 24; and the third channel portion 27 may be connected between the second doping portion 24 and the fourth doping portion 26. The gate layer may also include: a third gate portion 43, wherein the orthographic projection of the third gate portion 43 on the substrate may cover the orthographic projection of the third channel portion on the substrate, and the third gate portion 43 may be electrically connected to the first gate portion 41.

[0060] When the thin film transistor is working, the first gate portion 41 and the third gate portion 43 can be connected to the control signal terminal at the same time. Among them, the third channel portion 27 can further reduce the leakage current when the thin film transistor is turned off.

[0061] In this exemplary embodiment, Figure 6 , 7 As shown, Figure 6 is a top view of another exemplary embodiment of a thin film transistor disclosed in the present invention, Figure 7 for Figure 6 The cross-sectional view at the dotted line C. Figure 6 Only the structural layout of the semiconductor material layer in the thin film transistor is shown. The semiconductor material layer may also include: a fourth doping portion 26 and a third channel portion 27, wherein the fourth doping portion 26 is connected between the second channel portion 22 and the third doping portion 25; the third channel portion 27 may be connected between the third doping portion 25 and the fourth doping portion 26. The gate layer may also include: a third gate portion 43, wherein the orthographic projection of the third gate portion 43 on the substrate may cover the orthographic projection of the third channel portion 27 on the substrate, and the third gate portion 43 may be electrically connected to the first gate portion 41.

[0062] When the thin film transistor is working, the first gate portion 41 and the third gate portion 43 can be connected to the control signal terminal at the same time. Among them, the third channel portion 27 can further reduce the leakage current when the thin film transistor is turned off.

[0063] The present exemplary embodiment also provides a display panel including at least one of the above-mentioned thin film transistors.

[0064] like Figure 8FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the second electrode of the first transistor T1 is connected to the node N, the first electrode is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first electrode of the second transistor T2 is connected to the first electrode of the driving transistor T3, the second electrode is connected to the node N; the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the gate driving signal terminal Gate; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the reset signal terminal Re; the first electrode of the capacitor C is connected to the gate of the driving transistor T3, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED, used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the transistors T1 - T7 may all be P-type transistors.

[0065] like Fig. 9 As shown, Figure 8A timing diagram of each node in a driving method of a pixel driving circuit. Wherein, Gate represents the timing of the gate driving signal terminal Gate, Re represents the timing of the reset signal terminal Re, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the reset signal terminal Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal terminal Vinit inputs an initial signal to the node N and the second electrode of the sixth transistor T6. In the compensation stage t2: the gate driving signal terminal Gate outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Da outputs a driving signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3. Light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0066] In the light-emitting stage, the node N in the pixel driving circuit is prone to leakage through the first transistor T1 and the second transistor T2, thereby affecting normal display. The first transistor T1 and the second transistor T2 in the pixel driving circuit can adopt the structure of the above-mentioned thin film transistor, so that the leakage current of the node N through the first transistor T1 and the second transistor T2 can be reduced. In addition, the transistor in the pixel driving circuit can be a low-temperature polysilicon transistor. Low-temperature polysilicon transistors have high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio.

[0067] It should be understood that in other exemplary embodiments, the above-mentioned thin film transistor can also be applied to other circuit structures in the display panel, for example, the above-mentioned thin film transistor can also be applied to the gate driving circuit in the display panel. The pixel driving circuit in the display panel can also be other circuit structures, and accordingly, the above-mentioned thin film transistor can be applied to a transistor connected to the gate of the driving transistor. Among them, the driving transistor can refer to a transistor in the pixel driving circuit that provides a driving current to the light-emitting unit according to a data signal.

[0068] In this exemplary embodiment, the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence, wherein the active layer is disposed on one side of the base substrate, the first conductive layer is disposed on a side of the active layer away from the base substrate, the second conductive layer is disposed on a side of the first conductive layer away from the base substrate, the second conductive layer is disposed on a side of the first conductive layer away from the base substrate, and the third conductive layer is disposed on a side of the second conductive layer away from the base substrate. Figure 10-16 As shown, Fig.10 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Fig.11 for Fig.10 The structural layout of the active layer, Fig.12 for Fig.10 The structural layout of the first conductive layer in Fig.13 for Fig.10 The structural layout of the second conductive layer in Fig.14 for Fig.10 The structural layout of the third conductive layer in Fig.15 for Fig.10 The structural layout of the active layer and the first conductive layer, Fig.16 for Fig.10 The structural layout of the active layer, the first conductive layer and the second conductive layer.

[0069] like Fig.10 , 11As shown in , 15 and 16, the active layer may include: a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710 and an eleventh active portion 711. Among them, the first active portion 71 may be used to form the first channel portion of the first transistor T1; the second active portion 72 may be used to form the second channel portion of the first transistor T1. The orthographic projection of the first active portion 71 on the substrate and the orthographic projection of the second active portion 72 on the substrate may be distributed along the fourth direction Y. The third active portion 73 may be used to form the third channel portion of the first transistor T1; the fourth active portion 74 may be used to form the fourth doped portion of the first transistor T1. The fifth active portion 75 may be used to form the first channel portion of the second transistor T2; the sixth active portion 76 may be used to form the second channel portion of the second transistor T2. The seventh active portion 77 may be used to form a channel portion of the seventh transistor T7, the eighth active portion 78 may be used to form a channel portion of the fifth transistor T5, the ninth active portion 79 may be used to form a channel portion of the fourth transistor T4, the tenth active portion 710 may be used to form a channel portion of the driving transistor T3, and the eleventh transistor T11 may be used to form a channel portion of the sixth transistor T6.

[0070] like Fig.10 , 12 As shown in Figures 15 and 16, the first conductive layer may include a first gate line Re, a third conductive portion 13, a third gate line Gate, a fourth conductive portion 14, a fifth gate line EM, and a fifth conductive portion 15. The first gate line Re is used to provide Figure 8 The reset signal terminal Re in the substrate, the orthogonal projection of the first gate line Re on the substrate can extend along the third direction X, and the orthogonal projection of the first gate line Re on the substrate can cover the orthogonal projection of the first active portion 71 on the substrate, and part of the first gate line Re can be used to form the first gate of the first transistor T1, and the third direction X and the fourth direction Y can intersect, for example, the third direction X and the fourth direction Y are perpendicular. The orthogonal projection of the first gate line Re on the substrate can also cover the orthogonal projection of the third active portion 73 on the substrate, and part of the first gate line Re can be used to form the third gate of the first transistor T1. The third gate line Gate can be used to provide Figure 8In the gate driving signal terminal Gate, the orthographic projection of the third gate line Gate on the substrate can extend along the third direction X, and the orthographic projection of the third gate line Gate on the substrate can cover the orthographic projection of the fifth active portion 75 on the substrate, and part of the third gate line Gate can be used to form the first gate of the second transistor T2. The orthographic projection of the third conductive portion 13 on the substrate can cover the orthographic projection of the second active portion 72 on the substrate, and the third conductive portion 13 can be used to form the second gate of the first transistor T1. The orthographic projection of the fourth conductive portion 14 on the substrate can cover the orthographic projection of the sixth active portion 76 on the substrate, and the fourth conductive portion 14 can be used to form the second gate of the second transistor T2. The fifth conductive portion 15 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. Wherein, as Fig.10 , 12 As shown in FIGS. 15 and 16 , the gate of the seventh transistor T7 may share a partial structure of the first gate line Re in the previous pixel row.

[0071] like Fig.10 , 13 As shown in Figures 1 and 16, the second conductive layer may include: a sixth conductive portion 56, a first connecting portion 55, and a second gate line Vinit. The orthographic projection of the sixth conductive portion 56 on the substrate may at least partially overlap with the orthographic projection of the fifth conductive portion 15 on the substrate, and the sixth conductive portion 56 may be used to form a second electrode of the capacitor C. An opening 561 may be provided on the sixth conductive portion 56. The second gate line Vinit may be used to provide Figure 8 The initial signal terminal Vinit in the second gate line Vinit can extend along the third direction X in the positive projection of the substrate.

[0072] like Fig.17 FIG. 1 is a partial structural layout diagram of another exemplary embodiment of the display panel of the present disclosure, wherein the second transistor T2 may be a dual-gate structure, that is, in addition to the fourth conductive portion 14 for forming the second gate thereof, the second transistor T2 may also include a gate 121 and a gate 122, and accordingly, the second transistor T2 includes two channel portions corresponding to the gate 121 and the gate 122, respectively. The gate 121 and the gate 122 may be located in the first conductive layer, and the two channel portions corresponding to the gate 121 and the gate 122 may be located in the active layer. The second transistor T2 of the dual-gate structure may have a smaller leakage current.

[0073] like Fig.18As shown in FIG. 1 , a partial structural layout diagram of another exemplary embodiment of the display panel of the present disclosure is shown. The first transistor T1 may further include another gate 17 disposed in suspension. Accordingly, the first transistor T1 includes a semiconductor channel portion corresponding to the gate 17. The semiconductor channel portion may be located in the active layer, and the orthographic projection of the semiconductor channel portion on the substrate may coincide with the orthographic projection of the gate 17 on the substrate. Fig.18 As shown, two floating gates may be provided in the first transistor T1, so that the first transistor T1 has a smaller leakage current.

[0074] It should be understood that in other exemplary embodiments, the second gate of the transistor may also be located in other conductive layers, for example, the fourth conductive portion 14 as the second gate of the second transistor T2 may be located in the second conductive layer. In addition, in other exemplary embodiments, when the display panel includes other conductive layers, the second gate of the transistor may also be located in other conductive layers. For example, when the display panel includes one or more layers of a multi-layer gate layer, a multi-layer source / drain layer, a light-shielding metal layer, and an anode layer, the second gate of the transistor may be located in any one of the above conductive layers. Among them, the light-shielding metal layer may be located on the side of the active layer close to the substrate, and is used to shield the channel portion of the transistor. In other exemplary embodiments, the transistor may also include a plurality of floating gates, and the positive projection of the plurality of floating gates on the substrate substrate may coincide with the positive projection of the second channel of the transistor on the substrate substrate. For example, the floating gate of the transistor may adopt a double-layer structure, that is, the plurality of floating gates may include two conductive portions, and the two conductive portions may be respectively arranged on both sides or one side of the second channel portion of the transistor in the stacking direction. In addition, the orthographic projections of the multiple floating gates of the transistor on the substrate can also be located at different positions. Accordingly, the transistor can also include multiple semiconductor channel parts arranged corresponding to the floating gates, and the orthographic projections of the semiconductor channel parts on the substrate can overlap with the orthographic projections of the corresponding floating gates on the substrate. The orthographic projection of the floating gate on the substrate can be located on one side or both sides of the orthographic projection of the normal gate of the transistor on the substrate, wherein the normal gate of the transistor can refer to the gate that receives the gate drive signal.

[0075] It should be understood that in other exemplary embodiments, one of the first transistor T1 and the second transistor T2 may be a metal oxide transistor, and the other may be a low-temperature polysilicon transistor. Metal oxide transistors have a small leakage current. The display panel may include a first active layer, a first gate layer, a second active layer, and a second gate layer stacked in sequence. Among them, the first active layer may be formed of polycrystalline silicon, and part of the first active layer may be used as a channel portion of a low-temperature polysilicon transistor; the second active layer may be formed of a metal oxide (for example, indium gallium zinc oxide IGZO), and part of the second active layer may be used as a channel portion of a metal oxide transistor; part of the first gate layer may be used to form the gate of a low-temperature polysilicon transistor, part of the first gate layer may be used to form the bottom gate of a metal oxide transistor, and part of the second gate layer may be used to form the top gate of a metal oxide transistor. Among them, the floating gate of the low-temperature polysilicon transistor may be formed by one or more of the conductorized part of the second active layer, part of the first gate layer, and part of the second gate layer.

[0076] like Fig.10 , 14 As shown, the third conductive layer may include a data line Da, a power line VDD, a second connection portion 32, and a third connection portion 33. The data line Da may be used to provide Figure 8 The data signal terminal Da in the data line Da, the positive projection of the data line Da on the substrate can extend along the fourth direction Y. The power line VDD can be used to provide Figure 8 The first power supply terminal VDD in the substrate, the positive projection of the power supply line VDD on the substrate can extend along the fourth direction Y. Among them, the data line Da is connected to the ninth active part 79 through the via 91 to connect the data signal terminal and the first pole of the fourth transistor T4. The power supply line VDD can be connected to the eighth active part 78 through the via 92 to connect the first power supply terminal and the first pole of the fifth transistor T5. The power supply line VDD is also connected to the sixth conductive part 56 through the via 93 to connect the second electrode part of the capacitor C and the first power supply terminal. The power supply line VDD is also connected to the first connecting part 55 through the via 94. The second connecting part 32 can be connected to the second active part 72 through the via 95, and connected to the second gate line Vinit through the via 96 to connect the second pole of the first transistor T1 and the initial signal terminal. The third connecting part 33 can be connected to the fifth conductive part 15 through the via 97, and connected to the sixth active part 76 through the via 98 to connect the second pole of the second transistor T2 and the gate of the driving transistor T3. The orthographic projection of the via hole 97 on the base substrate may be located within the orthographic projection of the opening 561 on the base substrate.

[0077] like Fig.10 , 15As shown in 16, the positive projection of the third conductive part 13 on the substrate substrate can be located on the side where the positive projection of the first gate line Re on the substrate substrate is far away from the positive projection of the second gate line Vinit on the substrate substrate. On the one hand, this setting can reserve sufficient layout space for the third conductive part 13; on the other hand, the second gate line Vinit can output an initial signal of a stable voltage, and the second gate line Vinit has a voltage stabilizing effect on the third conductive part 13. When the first transistor T1 needs to be turned on, the second gate line Vinit will reduce the voltage change of the third conductive part 13 with the first gate line Re, thereby reducing the conduction degree of the first transistor T1. In this embodiment, the third conductive part 13 is set away from the second gate line Vinit, which can reduce the voltage stabilizing effect of the second gate line Vinit on the third conductive part 13, thereby reducing the influence of the second gate line Vinit on the conduction degree of the first transistor. It should be understood that in other exemplary embodiments, the positive projection of the third conductive part 13 on the substrate substrate can also be located on the side where the positive projection of the first gate line Re on the substrate substrate is close to the positive projection of the second gate line Vinit on the substrate substrate, which all belong to the protection scope of the present disclosure.

[0078] like Fig.10 , 11 , 15, and 16, the fourth active portion 74 will be coupled with the first gate line Re, and the voltage of the fourth active portion 74 will change with the potential change of the first gate line Re, thereby causing the fourth active portion 74 to leak to the source / drain of the first transistor T1. In this exemplary embodiment, the orthographic projection of the fourth active portion 74 on the substrate substrate may be located on the side of the orthographic projection of the first gate line Re on the substrate substrate away from the orthographic projection of the third conductive portion 13 on the substrate substrate. The orthographic projection of the second gate line Vinit on the substrate substrate may at least partially overlap with the orthographic projection of the fourth active portion 74 on the substrate substrate. The second gate line Vinit can stabilize the fourth active portion 74, thereby preventing the fourth active portion 74 from leaking to the source / drain of the first transistor T1.

[0079] like Fig.10 , 11As shown in 14, the orthographic projection of the first active portion 71 on the substrate substrate can be located on the side of the orthographic projection of the third active portion 73 on the substrate substrate away from the orthographic projection of the power line VDD on the substrate substrate. On the one hand, this arrangement can reserve sufficient layout space for the third conductive portion 13; on the other hand, since the power line VDD can output a stable voltage, when the first transistor T1 needs to be turned on, the power line VDD will reduce the voltage change of the third conductive portion 13 with the first gate line Re, thereby reducing the conduction degree of the first transistor T1. In this exemplary embodiment, the third conductive portion 13 is arranged away from the power line VDD, which can reduce the voltage stabilizing effect of the power line VDD on the third conductive portion 13, thereby reducing the influence of the power line VDD on the conduction degree of the first transistor. It should be understood that in other exemplary embodiments, the orthographic projection of the first active portion on the substrate substrate can also be located on the side of the orthographic projection of the third active portion 73 on the substrate substrate close to the orthographic projection of the power line VDD on the substrate substrate, all of which belong to the protection scope of the present disclosure.

[0080] In this exemplary embodiment, the sixth conductive part 56 may be located on the side of the third gate line Gate on the substrate substrate away from the first gate line Re on the substrate substrate; wherein the fourth conductive part 14 may be located between the third gate line Gate on the substrate substrate and the first gate line Re on the substrate substrate. On the one hand, this arrangement may reserve sufficient layout space for the fourth conductive part 14; on the other hand, since the sixth conductive part 56 is connected to the power line VDD, during the conduction phase of the second transistor T2, the sixth conductive part 56 may reduce the voltage change of the fourth conductive part 14 with the third gate line Gate, thereby reducing the conduction degree of the second transistor T2. In this exemplary embodiment, the fourth conductive part 14 is arranged away from the sixth conductive part 56, which may reduce the voltage stabilizing effect of the sixth conductive part 56 on the fourth conductive part 14, thereby reducing the influence of the sixth conductive part 56 on the conduction degree of the second transistor. It should be understood that in other exemplary embodiments, the fourth conductive portion 14 may be located between the orthographic projection of the third gate line Gate on the substrate and the orthographic projection of the sixth conductive portion 56 on the substrate.

[0081] like Fig.19 As shown, Fig.10Partial cross-sectional view at the dotted line A. The display panel may also include a buffer layer 111, a first insulating layer 112, a second insulating layer 113, and a dielectric layer 114. The substrate 1, the active layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the dielectric layer, and the third conductive layer are stacked in sequence. The insulating layer may be a silicon oxide layer, and the dielectric layer may be a silicon nitride layer. The material of the buffer layer may be silicon nitride or silicon oxide. The material of the active layer may be polycrystalline silicon. The first conductive layer, the second conductive layer, and the third conductive layer may all be formed by at least one metal layer. The substrate may be formed by an insulating material, for example, the substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer arranged in sequence. The second transistor T2 may also include another floating gate located on the side of the buffer layer 111 facing the substrate 1, and the orthographic projection of the floating gate on the substrate 1 may overlap with the orthographic projection of the fourth conductive portion 14 on the substrate 1. The display panel can further reduce the leakage current of the first transistor T1 and the second transistor T2 by partially thinning the thickness of the first insulating layer 112. The orthographic projection of the thinned portion on the base substrate can overlap with the orthographic projection of the floating gate (eg, the fourth conductive portion 14) on the base substrate.

[0082] In this exemplary embodiment, Fig. 20 As shown, it is a schematic diagram of the structure of another exemplary embodiment of the display panel of the present disclosure. The third direction X can be a row direction, and the display panel can include a first pixel driving circuit 81 and a second pixel driving circuit 82 arranged adjacent to each other in the row direction. Among them, the first connecting portion 55 is connected to the same power line VDD as the driving transistor in the first pixel driving circuit 01. The positive projection of the first connecting portion 55 on the substrate substrate can at least partially overlap with the positive projection of the first gate of the second transistor T2 in the second pixel driving circuit 82 on the substrate substrate. Among them, the first connecting portion 55 can play a signal shielding role for the gate of the second transistor T2.

[0083] In this exemplary embodiment, the first conductive layer can be formed by a patterning process (including photolithography, development, and etching). However, in the photolithography process, due to the diffraction effect of light, the pattern projected by the mask onto the photoresist changes, such as changes in line width, rounding of corners, shortening of line length, etc. As a result, the pattern formed by the first conductive layer is different from the preset pattern. In this exemplary embodiment, the first conductive layer can be formed by optical proximity correction mask technology (OPC, Optical Proximity Correction), that is, the first gate line Re, the third gate line Gate, the third conductive portion 13, and the fourth conductive portion 14 can be formed by a single patterning process using optical proximity correction mask technology. Optical proximity correction mask technology is to pre-compensate the shape of the mask so that the pattern projected by the mask onto the photoresist is the same as the preset image. Fig.21 As shown in FIG. 1 , it is a schematic diagram of a partial structure of a mask in the optical proximity correction mask technology disclosed in the present invention. Among them, region 2 can represent the location of the active layer partial structure, the location of the shielding portion 901 can be used to form the third gate line, and the location of the shielding portion 902 can be used to form the fourth conductive portion 14. Fig.21 As shown, the mask pre-compensates the shielding parts 901 and 902, so that the mask can form Fig.10 The third gate line and the fourth conductive portion are shown, wherein the fourth conductive portion 14 may be rectangular in the orthographic projection on the substrate, and the size of the fourth conductive portion 14 in the orthographic projection on the substrate in the first direction X may be equal to the size of the sixth active portion 76 in the orthographic projection on the substrate in the first direction X.

[0084] In addition, it should be noted that during the manufacturing process of the display panel provided by this exemplary embodiment, the active layer can be doped using the first conductive layer as a mask, that is, the portion of the active layer covered by the first conductive layer can form a polycrystalline silicon semiconductor, and the portion of the active layer not covered by the first conductive layer can form a doped polycrystalline silicon conductor.

[0085] like Fig. 22 As shown, it is a curve showing the relationship between the leakage current and the gate-source voltage difference of the second transistor in the display panel of the present disclosure. The horizontal axis represents the gate-source voltage difference of the second transistor, and the vertical axis represents the leakage current of the second transistor. Curves 101, 102, and 103 respectively represent the leakage current curves of the second transistor under different structures and sizes. Curve 101 represents the leakage current of the second transistor in conventional technology, and the second transistor does not have a second gate and a second channel portion, wherein the length and width of the channel portion of the second transistor can both be 3 microns. Curve 102 represents the addition of a second gate and a second channel portion structure on the basis of the second transistor shown in curve 101, and the structure of the second transistor can be as follows Figure 1 , 2As shown in FIG. 1 , the dimension S2 of the first channel portion of the second transistor in the orthogonal projection of the substrate in the first direction is 0.2 micrometers, and the dimension L of the first doped portion in the orthogonal projection of the substrate in the first direction is 0.3 micrometers. Curve 103 represents the addition of a second gate and a second channel portion structure on the basis of the second transistor shown in curve 101. The structure of the second transistor can be as follows: Figure 1 , 2 As shown, the dimension S2 of the first channel portion in the second transistor in the first direction of the orthogonal projection of the substrate is 0.5 micrometers, and the dimension L of the first doped portion in the first direction of the orthogonal projection of the substrate is 0.5 micrometers. Fig. 22 As shown, when the dimension S2 of the first channel portion in the second transistor in the orthogonal projection of the substrate in the first direction is 0.5 microns, and the dimension L of the first doped portion in the orthogonal projection of the substrate in the first direction is 0.5 microns, the second transistor has a smaller leakage current, and the second transistor corresponding to curve 103 has a similar threshold voltage to the second transistor corresponding to curve 101. Compared with curve 101, the second transistor corresponding to curve 103 can reduce the leakage current in the off stage by one order of magnitude.

[0086] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone or a tablet computer.

[0087] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0088] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A thin film transistor, wherein: include: A semiconductor material layer is located on one side of a substrate, and the semiconductor material layer includes a first channel portion, a first doping portion, and a second channel portion which are connected in sequence; A first insulating layer, located on a side of the semiconductor material layer facing away from the substrate; A gate layer is located on a side of the first insulating layer away from the base substrate, and the gate layer includes: A first gate portion, wherein an orthographic projection of the first gate portion on the base substrate covers an orthographic projection of the first channel portion on the base substrate, and the first gate portion is used to receive a gate driving signal; A second gate portion, wherein the orthographic projection of the second gate portion on the base substrate covers the orthographic projection of the second channel portion on the base substrate, and the second gate portion is suspended.

2. The thin film transistor according to claim 1, wherein: The orthographic projection of the first channel portion on the base substrate is a rectangle, the orthographic projection of the first doped portion on the base substrate is a rectangle, and the orthographic projection of the second channel portion on the base substrate is a rectangle; The orthographic projection of the first channel portion on the base substrate, the orthographic projection of the first doping portion on the base substrate, and the orthographic projection of the second channel portion on the base substrate are sequentially distributed along a first direction.

3. The thin film transistor according to claim 2, wherein: The size of the first channel portion in the first direction when projected on the base substrate is S1, and the size of the second channel portion in the first direction when projected on the base substrate is S2; Among them, the value of S1 / S2 is 3-15.

4. The thin film transistor according to claim 3, wherein: The dimension of the first doped portion projected on the base substrate in the first direction is L; Among them, the value of S1 / L is 3-15.

5. The thin film transistor according to claim 4, wherein: S1 is equal to 2.8-3.2 microns, S2 is equal to 0.2-0.8 microns, and L is equal to 0.2-0.8 microns.

6. The thin film transistor according to claim 1, wherein: The semiconductor material layer is made of polycrystalline silicon semiconductor.

7. The thin film transistor according to any one of claims 1 to 6, wherein: The semiconductor material layer further comprises: a second doped portion connected to the first channel portion; a third doped portion connected to the second channel portion; The thin film transistor further comprises: A second insulating layer, located on a side of the gate layer away from the substrate; A first via hole penetrating the first insulating layer and the second insulating layer, and a second via hole penetrating the first insulating layer and the second insulating layer are formed on the first insulating layer and the second insulating layer; The orthographic projection of the first via hole on the base substrate is located on the orthographic projection of the second doped portion on the base substrate, and the orthographic projection of the second via hole on the base substrate is located on the orthographic projection of the third doped portion on the base substrate; A source / drain layer is located on a side of the second insulating layer away from the substrate, and the source / drain layer includes: a first conductive portion, connected to the second doped portion through the first via hole, and used to form a first electrode of the thin film transistor; The second conductive portion is connected to the third doped portion through the second via hole and is used to form a second electrode of the thin film transistor.

8. The thin film transistor according to claim 7, wherein: The semiconductor material layer further comprises: a fourth doping portion connected between the first channel portion and the second doping portion; a third channel portion connected between the second doped portion and the fourth doped portion; The gate layer further comprises: A third gate portion, wherein an orthographic projection of the third gate portion on the base substrate covers an orthographic projection of the third channel portion on the base substrate, and the third gate portion is connected to the first gate portion.

9. The thin film transistor according to claim 7, wherein: The semiconductor material layer further comprises: a fourth doping portion connected between the second channel portion and the third doping portion; a third channel portion connected between the third doped portion and the fourth doped portion; The gate layer further comprises: A third gate portion, wherein an orthographic projection of the third gate portion on the base substrate covers an orthographic projection of the third channel portion on the base substrate, and the third gate portion is connected to the first gate portion.

10. A display panel, wherein: The invention comprises at least one thin film transistor according to any one of claims 1 to 9.

11. The display panel according to claim 10, wherein: At least one of the thin film transistors includes a first transistor, the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and the first transistor, a first electrode of the first transistor is connected to a gate of the driving transistor, and the first transistor forms the thin film transistor.

12. The display panel according to claim 11, wherein: The second electrode of the first transistor is connected to the initial signal terminal, at least one of the thin film transistors further includes a second transistor, the pixel driving circuit further includes a second transistor, the second electrode of the second transistor is connected to the gate of the driving transistor, and the first electrode is connected to the first electrode of the driving transistor.

13. The display panel according to claim 12, wherein: The display panel comprises: substrate substrate; An active layer is located on one side of the substrate, and the active layer includes: a first active portion, used to form a first channel portion of the first transistor; A second active portion, used to form a second channel portion of the first transistor, wherein the first active portion and the second active portion are distributed along a fourth direction in an orthographic projection on the substrate; A first conductive layer is located on a side of the active layer away from the substrate, and the first conductive layer includes: a first gate line, wherein the orthographic projection of the first gate line on the substrate extends along a third direction, and the orthographic projection of the first gate line on the substrate covers the orthographic projection of the first active portion on the substrate, a portion of the first gate line is used to form a first gate of the first transistor, and the third direction intersects the fourth direction; A third conductive portion, wherein the third conductive portion covers the orthographic projection of the second active portion on the substrate, and is used to form a second gate of the first transistor; The second conductive layer is located on a side of the first conductive layer away from the substrate, and the second conductive layer includes: A second gate line, used for providing the initial signal terminal; The orthographic projection of the third conductive portion on the base substrate is located on a side where the orthographic projection of the first gate line on the base substrate is away from the orthographic projection of the second gate line on the base substrate.

14. The display panel according to claim 13, wherein: The first transistor is the thin film transistor according to claim 8, and the active layer further comprises: a third active portion, used to form a third channel portion of the first transistor; a fourth active portion, used to form a fourth doped portion of the first transistor, wherein an orthographic projection of the fourth active portion on the substrate is located on a side of the orthographic projection of the first gate line on the substrate away from an orthographic projection of the third conductive portion on the substrate; The orthographic projection of the first gate line on the substrate also covers the orthographic projection of the third active portion on the substrate, and part of the first gate line is used to form the third gate of the first transistor; The second electrode of the driving transistor is connected to the first power supply terminal. The display panel further includes a third conductive layer, which is located on a side of the second conductive layer away from the base substrate. The third conductive layer includes: A power line is used to provide the first power end, the orthographic projection of the power line on the substrate extends along the fourth direction, and the orthographic projection of the first active part on the substrate is located on the side of the orthographic projection of the third active part on the substrate away from the orthographic projection of the power line on the substrate.

15. The display panel according to claim 14, wherein: The orthographic projection of the second gate line on the base substrate at least partially overlaps with the orthographic projection of the fourth active portion on the base substrate.

16. The display panel according to claim 14, wherein: The pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, a second electrode of the capacitor is connected to the first power supply terminal, and the active layer further includes: a fifth active portion, configured to form a first channel portion of the second transistor; a sixth active portion for forming a second channel portion of the second transistor; The first conductive layer comprises: a third gate line, wherein the orthographic projection of the third gate line on the substrate extends along the third direction, and the orthographic projection of the third gate line on the substrate covers the orthographic projection of the fifth active portion on the substrate, and a portion of the third gate line is used to form a first gate of the second transistor; a fourth conductive portion, wherein an orthographic projection of the fourth conductive portion on the base substrate covers an orthographic projection of the sixth active portion on the base substrate, and is used to form a second gate of the second transistor; a fifth conductive portion, used to form a gate of the driving transistor and a first electrode of the capacitor; The second conductive layer further comprises: a sixth conductive portion, wherein the orthographic projection of the sixth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fifth conductive portion on the substrate, and is used to form a second electrode of the capacitor, and the orthographic projection of the sixth conductive portion on the substrate is located on a side of the orthographic projection of the third gate line on the substrate away from the orthographic projection of the first gate line on the substrate; The orthographic projection of the fourth conductive portion on the base substrate is located between the orthographic projection of the third gate line on the base substrate and the orthographic projection of the first gate line on the base substrate.

17. The display panel according to claim 16, wherein: The third direction is a row direction, the display panel further includes a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction, and the second conductive layer further includes: A first connecting portion connected to the same power line as the driving transistor in the first pixel driving circuit; The orthographic projection of the first connecting portion on the base substrate at least partially overlaps with the orthographic projection of the first gate of the second transistor in the second pixel driving circuit on the base substrate.

18. The display panel according to claim 16, wherein: The first gate line, the third gate line, the third conductive part and the fourth conductive part are formed in the same layer by using an optical proximity correction mask technology.

19. A display device, wherein: A display panel comprising any one of claims 10-18.

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