Wake-up recognition circuit and vehicle

Abstract

The present invention discloses a wake-up recognition circuit, comprising: a signal receiving module, a plurality of signal processing modules and a controller; wherein, the signal receiving module includes an OR gate circuit, and multiple input ends of the OR gate circuit are respectively connected to multiple wake-up signal output ends correspondingly; each of the signal processing modules includes a first switching element, a second switching element, a first capacitor, a second capacitor and a voltage stabilizing unit; the controller includes multiple input ends, and the multiple input ends of the controller are respectively connected to output ends of the second switching elements in the multiple signal processing modules correspondingly. The signal processing module in this circuit can identify the wake-up source that arrives first in a competitive wake-up application scenario, facilitating an immediate response to an external wake-up event. In case of an emergency, it can accelerate the response speed to the external wake-up source, improve the accuracy, reduce the complexity of software implementation, and enhance the reliability.

Description

Technical Field

[0001] The present invention relates to the field of new energy vehicle electronic control, and particularly to a wake-up recognition circuit and a vehicle. Background Art

[0002] In recent years, the production and sales volume of automobiles in China has been increasing year by year. The controller of an automobile is the core unit of the vehicle, which directly affects the reliability, safety, comfort, etc. of the vehicle.

[0003] Among them, for the controller to transition from the sleep state to the normal working state, it requires stimulation from a wake-up source, which can be divided into external stimulation and internal stimulation. For external wake-up stimulation, generally, a level wake-up or a rising edge can wake up the controller. In order to identify which controller is being woken up, generally, the method of collecting the level of the wake-up port is used for judgment.

[0004] In actual scenarios, there is a situation where multiple wake-up sources almost reach the wake-up port simultaneously. However, after the controller enters the normal working state and collects the levels of each wake-up port, it is found that there are wake-up levels for all of them. Therefore, at this time, the method of collecting the level of the wake-up port simply cannot distinguish the true wake-up source, that is, the first-arriving wake-up signal. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to propose a wake-up recognition circuit that can output a wake-up trigger signal only for the first-arriving wake-up signal, enabling the controller to obtain the true external wake-up source without the need to combine logical judgments.

[0006] To achieve the above purpose, an embodiment of the present invention provides a wake-up recognition circuit, which includes a signal receiving module, multiple signal processing modules, and a controller. Among them, the signal receiving module includes an OR gate circuit, and multiple input ends of the OR gate circuit are respectively connected to multiple wake-up signal output ends. Each signal processing module includes a first switching element, a second switching element, a first capacitor, a second capacitor, and a voltage stabilizing unit; a first end of the first capacitor is connected to the output end of the OR gate circuit, and a second end of the first capacitor is grounded; a control end of the first switching element is connected to the first end of the first capacitor, an input end of the first switching element is connected to the output end of the OR gate circuit, and an output end of the first switching element is grounded through the voltage stabilizing unit; a control end of the second switching element is connected to the output end of the first switching element, an input end of the second switching element is connected to the corresponding input end in the OR gate circuit, and an output end of the second switching element is grounded through the second capacitor.

[0007] The controller includes multiple input ends, and multiple input ends of the controller are respectively connected to output ends of the second switching elements in multiple signal processing modules.

[0008] Among them, only the second switching element that first receives the wake-up signal can output a wake-up trigger signal to the controller.

[0009] According to an embodiment of the present invention, the first switching element is an NPN-type triode, and the second switching element is a PNP-type triode.

[0010] According to an embodiment of the present invention, the capacitance value of the second capacitor is greater than that of the first capacitor.

[0011] According to an embodiment of the present invention, each signal processing module further includes a first resistor, and the first resistor is connected between the output end of the OR gate circuit and the control end of the first switching element.

[0012] According to an embodiment of the present invention, each signal processing module further includes a second resistor, and the second resistor is connected between the output end of the OR gate circuit and the input end of the first switching element.

[0013] According to an embodiment of the present invention, the voltage stabilizing unit includes a third resistor or a voltage stabilizing diode.

[0014] According to an embodiment of the present invention, the controller further includes an initialization port, and the initialization port is connected to the output end of the OR gate circuit.

[0015] The wake-up recognition circuit provided by the present invention has the beneficial effect that the signal receiving module receives the wake-up signal sent by the wake-up source and transmits the wake-up signal to the multiple signal processing modules. Among the multiple signal processing modules, only the signal processing module that first receives the corresponding wake-up signal can output a wake-up trigger signal to the controller. Thus, the controller can obtain the real external wake-up source without combining logical judgment.

[0016] Another embodiment of the present invention further provides a vehicle, and the electronic control unit of the vehicle includes the above-mentioned wake-up recognition circuit.

[0017] To make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and cooperates with the attached drawings to make a detailed description as follows. Description of the Drawings

[0018] The drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments in line with the present invention, and are used together with the specification to explain the principles of the present invention. To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 The structural schematic diagram of the wake-up recognition circuit according to the first embodiment of the present invention;

[0020] Figure 2 The structural schematic diagram of the wake-up recognition circuit according to the second embodiment of the present invention;

[0021] Figure 3 The timing diagram of each node of the wake-up recognition circuit according to the second embodiment of the present invention;

[0022] The realization, functional features and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0023] To further elaborate on the technical means and effects adopted by the present invention to achieve the expected purpose, the following will refer to the accompanying drawings and preferred embodiments to describe in more detail the specific implementation manners, methods, steps, structures, features, etc. of the wake-up recognition circuit proposed according to the present invention.

[0024] In each of the accompanying drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. However, as those skilled in the art can understand, the present invention can be implemented without these specific details. In addition, some well-known parts may not be shown in the drawings.

[0025] It should be noted that the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes and cannot be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature.

[0026] First embodiment

[0027] Please refer to Figure 1 , which is the structural schematic diagram of the wake-up recognition circuit according to the first embodiment of the present invention. As Figure 1 shown, the wake-up recognition circuit 10 includes: a signal receiving module 101, a plurality of signal processing modules 102, 103, 104 (3 are shown in the figure, but the present invention is not limited thereto), and a controller 105.

[0028] Among them, the signal receiving module 101 is used to receive and transmit multiple wake-up signals a, b, c (3 are shown in the figure, but the present invention is not limited thereto) sent from the wake-up source 20. Specifically, the signal receiving module 101 includes an OR gate circuit 1011. Multiple input terminals of the OR gate circuit 1011 respectively receive the first wake-up signal a, the second wake-up signal b, and the third wake-up signal c sent from the wake-up source 20. The OR gate circuit 1011 outputs a high-level signal when any one of the wake-up messages is at a high level.

[0029] Among them, the number of multiple signal processing modules is the same as and corresponds one-to-one with the number of wake-up signals. Each signal processing module 102 / 103 / 104 is connected to the output terminal of the OR gate circuit 1011 and is also connected to the wake-up signal output terminal corresponding to the wake-up source 20. Specifically, the first signal processing module 102 includes a first switching element 1021, a second switching element 1022, a first capacitor 1023, a second capacitor 1024, and a voltage stabilizing unit 1015. Among them, the control terminal of the first switching element 1021 is connected to the first end of the first capacitor 1023, and the output terminal of the first switching element 1021 is connected to the first end of the voltage stabilizing unit 1023. The control terminal of the second switching element 1022 is connected to the output terminal of the first switching element 1021. The input terminal of the second switching element 1022 is connected to the first wake-up signal a, and the output terminal of the second switching element 1022 is connected to the first end of the second capacitor 1024. The second end of the first capacitor 1023, the second end of the second capacitor 1024, and the second end of the voltage stabilizing unit 1025 are connected.

[0030] In an embodiment, the second signal processing module 103 and the third signal processing module 104 have the same constituent elements as the first signal processing module 102, and the connection relationship between the elements is also the same. Only the second switching element in the second signal processing module 103 is connected to receive the second wake-up signal b output from the wake-up source 20, and the second switching element in the third signal processing module 104 receives the third wake-up signal c output from the wake-up source 20.

[0031] Among them, the controller 105 includes multiple input terminals. The multiple input terminals of the controller 105 are respectively connected to the output terminals of the second switching elements 1021 in the multiple signal processing modules 102, 103, 104.

[0032] Among them, when the wake-up source 20 issues multiple wake-up signals a, b, and c, only the second switching element that first receives the wake-up signal can output a wake-up trigger signal to the controller 105. For example, when the first wake-up signal a of the wake-up source 20 first issues a high level, the second switching element 1022 of the first signal processing module 102 is the second switching element that first receives the wake-up signal. At this time, since the second switching element 1022 is in a conducting state, the output terminal of the second switching element 1022 of the first signal processing module 102 outputs a high-level first wake-up trigger signal to the controller 105, while the second switching elements of other signal processing modules, such as the second signal processing module 102 or the third signal processing module 103, do not receive the second wake-up signal b or the third wake-up signal c. Therefore, the signals at the output terminals of the second switching elements of the second signal processing module 102 or the third signal processing module 103 still remain at a low level. In addition, since the OR gate circuit 1011 receives the first wake-up signal a and outputs a high-level signal, the first capacitor of each signal processing module is charged. When the first capacitor is charged for a certain period of time such that the level at the control terminal of the first switching element changes from low level to high level, the first switching element conducts, causing the control terminal of the second switching element to start charging through the conducting first switching element. Subsequently, when the control terminal of the second switching element changes from low level to high level, the second switching element changes from conducting to cutoff. Therefore, even if the wake-up source 20 subsequently outputs a high-level second wake-up signal b or third wake-up signal c, the second signal processing module 103 or the third signal processing module 104 cannot output a high-level wake-up trigger signal.

[0033] Second Embodiment

[0034] Please refer to Figure 2 , which is a schematic structural diagram of the wake-up recognition circuit for implementing the second embodiment of the present invention. As Figure 2 shown, the wake-up recognition circuit is basically the same as the wake-up recognition circuit shown in Figure 1 . The differences include that the first signal processing module 102' further includes at least one of a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the output terminal of the OR gate circuit 1011 and the control terminal of the first switching element T1. The second resistor R2 is connected between the output terminal of the OR gate circuit 1011 and the input terminal of the first switching element T1. In addition, in this embodiment, the voltage stabilizing unit is a third resistor R3.

[0035] In this embodiment, the controller 105' includes four ports, a first input terminal A, a second input terminal B, a third input terminal C, and an initialization port wk. The initialization port wk is connected to the output terminal of the OR gate circuit 1011; the first input terminal A is connected to the output terminal of the second switching element T2. The second input terminal B and the third input terminal C are respectively connected to the output terminals of the second switching elements in the third signal processing module 104' and the second signal processing module 103'. Specifically, in this embodiment, taking the first switching element T1 as an NPN-type triode and the second switching element T2 as a PNP-type triode as an example, the principle of the wake-up recognition circuit will be described. Please refer to Figure 3 and the following table, Figure 3 which is the timing diagram of each node of the wake-up recognition circuit according to the second embodiment of the present invention, and the following table is Figure 3 the corresponding timing logic table.

[0036]

[0037] According to Figure 2 as shown, the node where the first resistor R1, the first capacitor C1, and the first switching element T1 intersect is the Q point, the node where the first resistor R1, the second resistor R2, and the output terminal of the OR gate circuit intersect is the M point, the node where the output terminal of the first switching element T1 and the control terminal of the second switching element T2 intersect is the N point, and the node where the output terminal of the second switching element T2 and the first input terminal A intersect is the P point.

[0038] In the original state, the state of the first wake-up signal a is low level, both the first switching element T1 and the second switching element T2 are in the off state, and the states of the M point, Q point, N point, and P point are all low level;

[0039] At an arbitrary first moment t1, the first wake-up signal a generates a wake-up high level earlier than the second wake-up signal b and the third wake-up signal c. From the first moment t1 to the second moment t2, the level state of the first wake-up signal a changes from low to high, the level state of point M changes from low to high, the first capacitor C1 starts to charge, the level state of point Q slowly rises, the first switching element T1 is in the off state, the state of point N is low level, the second capacitor C2 quickly charges to a high level, the second switching element T2 is in the on state, and the level state of point P quickly rises. Further, from the first moment t1 to the second moment t2, the wake-up high level generated by the first wake-up signal a outputs a high-level signal through the output terminal of the OR gate circuit 1011. This high-level signal is transmitted to the initialization port WK of the controller 105’, initializing and activating the controller 105’. At the same time, the wake-up high level generated by the first wake-up signal a outputs a wake-up trigger signal through the second switching element T2 and transmits it to the first output terminal A of the controller 105’. The first output terminal A of the controller 105’ quickly determines the external real wake-up source based on this first wake-up trigger signal a and makes a corresponding wake-up action;

[0040] From the second moment t2 to the third moment t3, the state of the first wake-up signal a is high level, the state of point M is high level, the first capacitor C1 is slowly charging to the balanced state, the level state of point Q is slowly rising, the first switching element T1 is in the on state, the level state of point N changes from low to high, the second switching element T2 is in the cut-off state, the second capacitor C2 starts to discharge, and the level state of point P changes from high to low. Further, the wake-up high level generated by the first wake-up signal a outputs a high-level signal through the OR gate circuit 1011. After being delayed by the first resistor R1 and the first capacitor C1, the first switching element T1 is turned on. The elevation of the level at the output terminal of the first switching element T1 causes the second switching element T2 to be cut off, and the level state of point P starts to change from high to low. Further, at this time, regardless of whether the second wake-up signal b or the third wake-up signal c generates a wake-up high level, the state of the corresponding point M in each signal processing module 102’ / 103’ / 104’ is high level, the second switching element T2 is in the cut-off state, and the subsequent wake-up signals cannot be transmitted to the corresponding ports of the controller 105’;

[0041] From the third moment t3 to the fourth moment t4, the level state of the first wake-up signal a changes from high to low, the level state of point M changes from high to low, the first capacitor C1 starts to discharge, the state of point Q is high level, the first switching element T1 is in the on state, the state of point N is high level, the second switching element T2 is in the cut-off state, and the level state of point P changes from high to low;

[0042] After the fourth moment t4, the state of point a of the first wake-up signal is low level, the first switching element T1 and the second switching element T2 are in the cut-off state, and the states of points M, Q, and P are low level. Further, the signal processing module 102' gradually returns to the initial state.

[0043] In summary, in the wake-up recognition circuit provided by the present invention, only the second switching element that first receives the wake-up signal can output a wake-up trigger signal to the controller, so that the signal processing module in the circuit can identify the first-arriving wake-up source in the competitive wake-up application scenario, facilitating an immediate response to an external wake-up event. In an emergency, it can accelerate the response speed to the external wake-up source, improve accuracy, reduce the complexity of software implementation, and enhance reliability.

[0044] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A wake-up recognition circuit, characterized in that, it includes a signal receiving module, multiple signal processing modules and a controller; the signal receiving module includes an OR gate circuit, and multiple input ends of the OR gate circuit are respectively connected to multiple wake-up signal output ends; the number of the multiple signal processing modules is the same as the number of the multiple wake-up signals; each signal processing module includes a first switching element, a second switching element, a first capacitor, a second capacitor, and a voltage stabilizing unit; a first end of the first capacitor is connected to an output end of the OR gate circuit, and a second end of the first capacitor is grounded; a control end of the first switching element is connected to the first end of the first capacitor, an input end of the first switching element is connected to the output end of the OR gate circuit, and an output end of the first switching element is grounded through the voltage stabilizing unit; a control end of the second switching element is connected to the output end of the first switching element, an input end of the second switching element is connected to a corresponding input end in the OR gate circuit, and an output end of the second switching element is grounded through the second capacitor; the first switching element is an NPN-type triode, and the second switching element is a PNP-type triode; the controller includes multiple input ends, and the multiple input ends of the controller are respectively connected to output ends of second switching elements in the multiple signal processing modules; wherein, only the second switching element that first receives the wake-up signal can output a wake-up trigger signal to the controller.

2. The wake-up recognition circuit according to claim 1, characterized in that, a capacitance value of the second capacitor is greater than a capacitance value of the first capacitor.

3. The wake-up recognition circuit according to claim 1, characterized in that, each signal processing module further includes a first resistor, and the first resistor is connected between an output end of the OR gate circuit and a control end of the first switching element.

4. The wake-up recognition circuit according to claim 1, characterized in that, each signal processing module further includes a second resistor, and the second resistor is connected between an output end of the OR gate circuit and an input end of the first switching element.

5. The wake-up recognition circuit according to claim 1, characterized in that, the voltage stabilizing unit is a third resistor.

6. The wake-up recognition circuit according to claim 1, characterized in that, the voltage stabilizing unit is a voltage stabilizing diode.

7. The wake-up recognition circuit according to claim 1, characterized in that, the controller further includes an initialization port, and the initialization port is connected to an output end of the OR gate circuit.

8. A vehicle, characterized in that, it includes the wake-up recognition circuit according to any one of claims 1 to 7.

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