A method for sequencing chip surface chemical treatment and package bonding

Abstract

The application discloses a method for sequencing chip surface chemical treatment and packaging bonding. The method comprises the following steps: punching a wafer substrate, etching a flow channel structure on a wafer cover plate, bonding the punched wafer substrate and the etched wafer cover plate, obtaining a bonded wafer, performing surface treatment on the bonded wafer, and cutting to obtain the sequencing chip. The application performs packaging bonding and surface treatment at the wafer level, and finally performs cutting and assembly of single chips, so that the related technical problems existing in the preparation of the sequencing chip can be solved, the operation process is simplified, the process cost is reduced, and the production efficiency and capacity are significantly improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of gene sequencing, and relates to a method for surface chemical treatment and packaging bonding of a sequencing chip. BACKGROUND

[0002] Gene sequencing is a new type of gene detection technology. The entire platform system comprises a sequencing instrument, biochemical reaction reagents and a gene sequencing chip and the like, and completes the whole sequencing process through mutual cooperation. The sequencing chip is an important consumable and carrier of the gene sequencing system. The surface of the sequencing chip needs to be chemically modified to form a specific group. This chemical group can capture the DNA fragments to be detected and can stably fix the DNA fragments on the surface. At the same time, the sequencing chip can form a specific cavity inside through a special packaging bonding process. Under the driving of the liquid system of the sequencing instrument, the biochemical reaction reagents will enter the chip flow channel in sequence according to the fluid timing. The reagents and the DNA on the surface of the chip react. The sequencing instrument can obtain the biological information of the DNA fragments by detecting the optical and electrical signals carried on the DNA fragments, thereby completing the whole sequencing process.

[0003] At present, the processing and treatment processes of most sequencing chips are basically similar. First, surface chemical treatment is performed on the chip substrate material. The conventional treatment methods mainly include chemical vapor deposition and liquid immersion method. The surface uniformity and stability obtained by chemical vapor deposition are relatively good. However, the cost of chemical vapor deposition is relatively high. The liquid immersion method is low in cost, but its uniformity and stability are slightly poor. Compared with the liquid immersion method, the surface chemical treatment method of most mass-produced sequencing chips currently adopts the chemical vapor deposition method.

[0004] After the surface chemical treatment of the chip substrate material, the treated substrate material needs to be packaged and bonded with glass to form a sealed cavity. The main packaging and bonding methods at present include the bonding of double-sided adhesive PSA, the bonding of liquid glue (such as UV glue and heat-curing glue), and the adhesive packaging and bonding process is relatively complicated and high in cost. Moreover, the surface of the chip substrate has been subjected to surface chemical treatment and cannot withstand high temperature, which means that the chip packaging cannot adopt high-temperature bonding processes such as anodic bonding. Therefore, the bonding method of most mass-produced sequencing chips at present is mainly the adhesive method. After the above-mentioned surface chemical treatment of the chip substrate material, the adhesive packaging and bonding, and then the subsequent assembly of the single chip, the whole process has many procedures, which leads to complicated operation and low yield. Moreover, the packaging and bonding of the chip is based on a single chip, and the overall production capacity is also limited.

[0005] In summary, based on the technical problems existing in the development and production of gene sequencing chips, there is an urgent need to develop a new method for preparing sequencing chips to improve the production capacity of gene sequencing chips and reduce the cost of gene sequencing chips. SUMMARY

[0006] In view of the deficiencies of the prior art and actual needs, the present application provides a method for surface chemical treatment and packaging bonding of sequencing chips, which redesigns the method for preparing sequencing chips, simplifies the operation process, reduces the process cost, and realizes the standardized and batch production and processing of sequencing chips.

[0007] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0008] In a first aspect, the present application provides a method for surface chemical treatment and packaging bonding of sequencing chips, which comprises:

[0009] The wafer substrate is punched, the wafer cover plate is etched to form a flow channel structure, the punched wafer substrate and the etched wafer cover plate are bonded to obtain a bonded wafer, the bonded wafer is surface treated, and then cut to obtain the sequencing chip.

[0010] In the present application, the process flow for preparing sequencing chips is redesigned, the packaging bonding is performed at the wafer level, then the chemical surface treatment is performed at the wafer level, and finally the single chip is cut and assembled, which can significantly simplify the operation process, improve the production efficiency and reduce the production cost.

[0011] In the present application, the wafer substrate and the wafer cover plate are the core components of the entire chip, one of the functions of the wafer cover plate is to etch to form a specific flow channel, and the main function of the wafer substrate and the wafer cover plate is to capture DNA through specific surface properties, then make the DNA react with the reagent in the chip, and finally the instrument detects the signal on the substrate or cover plate, the performance of the wafer substrate and the wafer cover plate directly affects the biochemical reaction effect and the test result.

[0012] Preferably, the material of the wafer substrate and the wafer cover plate is independently selected from any one or a combination of at least two of quartz glass, ordinary glass or silicon wafer.

[0013] Preferably, the thickness of the wafer substrate is 0.5mm-1mm, including but not limited to 0.6mm, 0.7mm, 0.8mm or 0.9mm.

[0014] Preferably, the thickness of the wafer cover plate is 0.1mm-0.5mm, including but not limited to 0.2mm, 0.3mm or 0.4mm.

[0015] Preferably, the method further comprises a step of cleaning the wafer substrate and the wafer cover plate respectively before the drilling and etching.

[0016] In the present application, the purpose of drilling is to connect the sequencing chip and the sequencing instrument, forming the liquid inlet hole and the liquid outlet hole of the chip, and the cleaning function is to remove the impurities on the substrate to provide a clean surface for subsequent surface treatment.

[0017] Preferably, the cleaning method includes immersion cleaning, ultrasonic cleaning or plasma cleaning.

[0018] Preferably, the cleaning solution used in the cleaning process includes ultrapure water.

[0019] Preferably, the cleaning process further comprises a step of blowing dry with inert gas.

[0020] Preferably, the inert gas includes nitrogen.

[0021] Preferably, the drilling method includes laser drilling, mechanical drilling or sandblasting drilling.

[0022] Preferably, the drilling includes forming a liquid inlet hole and a liquid outlet hole.

[0023] Preferably, the diameter of the liquid inlet hole and the liquid outlet hole is independently 0.5mm-2.0mm, including but not limited to 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm or 1.9mm.

[0024] Preferably, the drilling process further comprises a step of ultrasonic cleaning.

[0025] In the present application, the flow channel structure can be designed according to the requirements, and the fluid simulation can be used for calculation analysis and optimization, and the fluid simulation can be carried out by using Comsol and Ansys software, and the structure distribution of the chip on the wafer is confirmed, and the corresponding optical mask is designed according to the flow channel structure design and the distribution of the chip on the wafer.

[0026] Preferably, the etching includes designing an optical mask according to the required flow channel structure, and etching the wafer cover plate by using the optical mask.

[0027] Preferably, the etching method includes wet etching or dry etching.

[0028] Preferably, the depth of the flow channel structure is 0.05mm-0.1mm, including but not limited to 0.06mm, 0.07mm, 0.08mm or 0.09mm.

[0029] In the present application, the depth tolerance control of the etching process of the flow channel of the wafer cover plate by using the mask can be + / - 0.5um, + / - 1um or + / - 2um, etc.

[0030] In the present application, the etched wafer cover plate and the punched wafer substrate are bonded, and the whole bonding process needs to be performed in sequence, i.e., the alignment of the wafer cover plate and the wafer substrate, the lamination of the wafer cover plate and the wafer substrate, the bonding of the wafer cover plate and the wafer substrate, and the specific operation process of the alignment and lamination of the wafer cover plate and the wafer substrate can be performed on the wafer aligner, and the bonding of the wafer substrate and the wafer cover plate can be performed on the bonder.

[0031] Preferably, the bonding method includes anodic bonding, laser bonding or hot-press bonding.

[0032] Preferably, the temperature of the anodic bonding is 200-400℃, including but not limited to 201℃, 202℃, 203℃, 205℃, 210℃, 250℃, 260℃, 280℃, 300℃, 350℃, 360℃, 370℃, 380℃ or 390℃.

[0033] Preferably, the surface treatment method includes chemical vapor deposition treatment or liquid immersion treatment.

[0034] In the present application, the reagent in the chemical vapor deposition equipment can diffuse into the cavity inside the bonded wafer through the inlet and outlet liquid holes on the wafer substrate, so as to produce a chemical reaction inside the cavity and deposit on the surface, achieving the effect of surface chemical modification.

[0035] In the present application, the surface treatment effect forms a hydrophilic surface, a hydrophobic surface or a surface with a specific functional group according to specific requirements, and the specific functional group can be amino, hydroxyl, carboxyl, ether bond, aldehyde group, carbonyl or other silane group.

[0036] Preferably, the temperature of the chemical vapor deposition treatment is 25-50℃, including but not limited to 26℃, 27℃, 28℃, 29℃, 30℃, 31℃, 35℃, 36℃, 40℃, 42℃, 44℃, 46℃, 48℃ or 49℃, and the time is 5-60min, including but not limited to 6min, 7min, 8min, 9min, 10min, 15min, 20min, 22min, 26min, 28min, 40min, 45min, 49min, 50min, 52min, 54min, 55min, 56min, 58min or 59min.

[0037] Preferably, the method further includes the step of assembling the chip frame for the sequencing chip obtained after cutting.

[0038] In the present invention, the chip frame not only serves as a connection between the chip and the instrument platform, but also provides support and protection for the chip. In addition, the chip frame structure can be loaded with labels, marks or product information according to actual needs. The chip frame can be transparent or opaque, and the processing method can be mechanical processing or mold injection molding.

[0039] In the present invention, the chip frame is also cleaned before use.

[0040] The chip frame is made of any one of plastic, ceramic or metal.

[0041] In the present invention, the cutting method can be laser cutting, knife cutting or other mechanical cutting methods.

[0042] The present invention also involves subsequent processes for the single sequencing chip formed after cutting, which may include assembling the chip shell, testing the complete chip, vacuum packaging of the chip, etc. The inspection items may include appearance inspection, size inspection, chip flow channel gap inspection, etc.

[0043] As a preferred technical solution, the method includes the following steps:

[0044] (1) Ultrasonic cleaning of the wafer substrate and wafer cover;

[0045] (2) drilling holes in the wafer substrate and performing ultrasonic cleaning;

[0046] (3) designing an optical mask according to the desired flow channel structure, and etching the wafer cover plate using the optical mask;

[0047] (4) bonding the punched wafer substrate and the etched wafer cover plate to obtain a bonded wafer;

[0048] (5) performing chemical vapor deposition treatment or liquid immersion treatment on the bonded wafer;

[0049] (6) Cutting the bonded wafer processed in step (5) and assembling the chip frame to obtain a sequencing chip.

[0050] In a second aspect, the present invention provides a sequencing chip, which is prepared by the method described in the first aspect.

[0051] In the present invention, the sequencing chip has broad application prospects, such as gene sequencing, hybridization and disease diagnosis.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] (1) The sequencing chip preparation method of the present invention is based on a wafer-level process flow. Compared with the traditional single chip processing method, the overall efficiency is improved by nearly dozens of times, the operation is simple, the cost is low, and the preparation of sequencing chips is standardized, and the detection and quality control methods are more accurate;

[0054] (2) The packaging of the sequencing chip of the present invention adopts a bonding method instead of the traditional gluing method, which significantly simplifies the process and reduces costs. In addition, the bonding step of the chip is performed before the surface chemical treatment, which can prevent the chemical substances on the chip surface from being damaged during the bonding process.

[0055] (3) The present invention can further control the chip surface treatment method to be chemical vapor deposition treatment, and the chemical substances can diffuse into the chip cavity through the liquid inlet and outlet, further improving the uniformity and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 Figure 1 is a top view of an 8-inch wafer substrate. Figure 1 shows the wafer substrate. Figure 2 shows the distribution of the substrates of a single sequencing chip on the 8-inch wafer substrate. Figure 3 shows the substrate of a single sequencing chip. One wafer substrate can be cut into substrates for 36 sequencing chips. Figure 4 shows the liquid inlet or outlet on the substrate. The liquid inlet and outlet are diagonally distributed on the substrate of each sequencing chip.

[0057] Figure 2 for Figure 1 A side view of a single sequencing chip substrate, wherein 3 represents the substrate of a single sequencing chip;

[0058] Figure 3 Figure 5 is a top view of an 8-inch wafer cover plate of the present invention. Figure 5 is the wafer cover plate, Figure 6 shows the distribution of the cover plates of a single sequencing chip on the 8-inch wafer cover plate, Figure 7 is the cover plate of a single sequencing chip. One wafer cover plate can be cut into cover plates for 36 sequencing chips. Figure 8 shows the shape of the flow channel cavity etched inside the cover plate of a single sequencing chip. Each sequencing chip cover plate has a flow channel cavity.

[0059] Figure 4 for Figure 3 Figure 7 shows a side view of a single sequencing chip cover, where 7 represents the cover of a single sequencing chip, and 8 represents the flow channel cavity of a single sequencing chip;

[0060] Figure 5Figure 9 shows the wafer after anodically bonding. Figure 10 shows the distribution of individual sequencing chips on an 8-inch wafer. Figure 11 shows a single sequencing chip. One wafer can be cut into 36 sequencing chips. Figure 12 shows the flow channel cavity inside a single sequencing chip. Figure 13 shows the liquid inlet or outlet of a single sequencing chip.

[0061] Figure 6 for Figure 5 Figure 11 represents a single sequencing chip, Figure 12 is the flow channel cavity inside a single sequencing chip, and Figure 13 is the liquid inlet or outlet of a single sequencing chip;

[0062] Figure 7 This is a top view of a single sequencing chip after being assembled with a chip frame. 14 in the figure represents a complete chip assembled with a chip frame, and 15 in the figure represents the chip frame;

[0063] Figure 8 This is the pressure distribution diagram inside the flow channel of the sequencing chip;

[0064] Figure 9 This is the stress distribution map on the surface of the sequencing chip;

[0065] Figure 10 This is a physical picture of the sequencing chip product. DETAILED DESCRIPTION

[0066] To further illustrate the technical means and effects of the present invention, the present invention is further described below with reference to the embodiments and drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention.

[0067] If no specific techniques or conditions are specified in the examples, the experiments were carried out according to the techniques or conditions described in the literature in the field or according to the product instructions. If no manufacturer is specified for the reagents or instruments used, they are all conventional products that can be purchased through regular channels.

[0068] In the present invention, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; they may refer to mechanical connection, direct connection, or indirect connection through an intermediate medium; they may refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0069] In the embodiment of the present application, the method for processing and preparing the sequencing chip mainly comprises the structure design of the internal flow channel of the chip, the punching of the wafer substrate, the flow channel etching of the wafer cover plate, the anodic bonding of the wafer substrate and the wafer cover plate, the surface chemical treatment of the bonded wafer and the cutting of the wafer, etc.

[0070] In the embodiment of the present application, the functions of the chip frame are firstly to provide support and protection for the main body part of the sequencing chip, and secondly to serve as the connecting part for contacting the sequencing chip and the sequencing instrument.

[0071] In the embodiment of the present application, the material of the chip frame can be engineering plastic, and the types thereof can be polyether ether ketone (PEEK), polyetherimide (PEI), polycarbonate (PC), polyphenylene sulfide (PPS), polyoxymethylene (POM), polyphenyl ether (PPO), etc.

[0072] In the embodiment of the present application, the sequencing chip substrate has a liquid inlet and a liquid outlet, and the number of the liquid inlet and the liquid outlet is not limited to one, but can also be two, three or more than three.

[0073] In the embodiment of the present application, the shape of the liquid inlet and the liquid outlet on the sequencing chip substrate can be circular, elliptical, square, rectangular, triangular or polygonal.

[0074] In the embodiment of the present application, the liquid inlet and the liquid outlet on the sequencing chip substrate can be located on the bottom surface.

[0075] In the embodiment of the present application, the material of the substrate of the sequencing chip can be quartz glass, silicon wafer or ordinary glass.

[0076] In the embodiment of the present application, the internal flow channel cavity of the sequencing chip can have a certain flow channel design structure, and the shape of this structure is calculated and simulated by theory and verified by specific experiments, which can effectively solve and improve the uniformity of fluid flow and distribution, thereby improving the replacement ratio of reagents and the reaction efficiency.

[0077] In the embodiment of the present application, the shape of the flow channel of the sequencing chip can have a streamline structure, wherein the streamline structure is not limited to having a circular arc surface on both sides or both ends of the flow channel, and the shape thereof can also be circular, elliptical, parabolic, smooth curve, etc.

[0078] In the embodiment of the present application, the number of the flow channel of the sequencing chip is not limited to one, but can also be two, three or more than three.

[0079] In the embodiment of the present application, the cleaning of the wafer substrate and the wafer cover plate can be ultrasonic cleaning, centrifugal oscillation method, plasma cleaning method, buffer solution immersion cleaning method, etc.

[0080] In the embodiment of the present application, the wafer substrate needs to be further punched after cleaning, and the punching method includes laser punching, sand blasting punching, mechanical drilling, etc.

[0081] In the embodiment of the present application, the purpose of punching on the wafer substrate is to serve as the liquid inlet hole and the liquid outlet hole of the sequencing chip, and the size of the hole diameter is 0.5mm-2mm.

[0082] In the embodiment of the present application, the wafer cover plate needs to be further etched after cleaning, the flow channel shape of the wafer cover plate is designed by a mask plate to form a specific flow channel structure, and the depth of the flow channel is formed by etching to form a flow channel with a specific depth. The etching method of the wafer cover plate can include wet etching, dry etching, etc.

[0083] In the embodiment of the present application, the etching of the wafer cover plate forms the flow channel cavity of the sequencing chip, and the etching depth of the flow channel can be 50μm-100μm.

[0084] In the embodiment of the present application, the wafer cover plate after etching and the wafer substrate after punching are bonded, and the main steps include wafer alignment, wafer bonding and wafer bonding, etc.

[0085] In the embodiment of the present application, the specific bonding method can be anode bonding, hot-press bonding and laser bonding, etc.

[0086] In the embodiment of the present application, the flow channel cavity formed after the wafer substrate and the wafer cover plate are bonded, and the sealed flow channel cavity has a height range of 50μm-100μm.

[0087] In the embodiment of the present application, the wafer after bonding needs to be further surface treated to form an amino group surface structure. In other embodiments, the surface treatment of the wafer substrate and the wafer cover plate can form specific functional groups, including hydroxyl, carboxyl, ether bond, aldehyde group, carbonyl, etc.

[0088] In the embodiment of the present application, the surface treatment method of the wafer substrate and the wafer cover plate can be chemical vapor deposition (CVD), which can ensure that the surface of the wafer substrate and the wafer cover plate forms a uniform distribution of the required functional groups, and has good stability. In addition, the surface treatment method of the wafer substrate and the wafer cover plate after bonding can also be a liquid immersion method. Therefore, the surface treatment method of the wafer substrate and the wafer cover plate mainly includes chemical vapor deposition, liquid immersion, etc.

[0089] In the embodiment of the present application, the bonded wafer can be further detected after surface treatment. The detection method can be to test the contact angle of the surface. This method needs to destroy part of the sequencing chip by sampling inspection. The contact angle of the wafer substrate and the wafer cover plate surface represents the surface tension and surface energy of water. The contact angle can indirectly reflect the degree and quality of the surface treatment effect. In addition to the method of indirectly measuring the surface treatment effect by using the contact angle, the method of directly loading nucleic acid can also be used to test whether the chip surface has the desired functional group and the density of the surface functional group according to the captured nucleic acid.

[0090] In the embodiment of the present application, the bonded wafer is cut to form a single sequencing chip. The cutting method can be laser cutting, knife cutting and mechanical cutting.

[0091] In the embodiment of the present application, the above-mentioned theoretical simulation calculation method of the chip internal fluid, wherein the fluid flow includes laminar flow, turbulent flow, turbulent flow and the like, and the uniformity of the fluid flow and distribution, the method is mainly calculation is not limited to the flow rate and the distribution of the flow line inside the flow channel, the distribution of the pressure inside the flow channel, the stress distribution inside the flow channel and the chip cover plate.

[0092] In the embodiment of the present application, the design of the flow channel of the sequencing chip will affect the flow and distribution of the reagent. If the structure design of the flow channel is unreasonable or the surface treatment is uneven, sometimes the fluid will flow along the local flow to form dead volume and bubbles during the fluid flow. The existence of the dead volume will cause the residue and pollution of the reagent. The formation of the bubbles will affect the biochemical reaction. The dead volume and the bubbles will seriously affect the overall test effect. Therefore, the dead volume and the bubbles are the key factors considered in the flow channel design process.

[0093] In addition, unreasonable flow channel design will affect the replacement ratio of the sequencing reagent in the sequencing chip, thereby indirectly causing the increase of the reagent consumption, the extension of the liquid pumping time of the sequencing instrument and the decline of the sequencing efficiency. Therefore, the flow channel structure design inside the sequencing chip is crucial to the overall performance of the sequencing chip and system.

[0094] Example 1

[0095] The present application provides a method for surface chemical treatment and packaging bonding of a sequencing chip. The steps of the method are as follows:

[0096] (1) ultrasonic cleaning of the chip frame, using ultrapure water during the cleaning process, and then blowing the surface of the wafer dry with high-purity nitrogen after cleaning;

[0097] (2) ultrasonic cleaning of the wafer substrate (quartz glass material, thickness 0.5 mm) and the wafer cover plate (ordinary glass material, thickness 0.1 mm), using ultrapure water during the cleaning process, and after cleaning, using high-purity nitrogen to dry the surface of the wafer, and storing the wafer in a nitrogen cabinet;

[0098] (3) punching processing of the wafer substrate, specifically using laser punching to punch two holes, each with a diameter of 0.5 mm, which can be used as liquid inlet or outlet, and the holes are diagonally distributed on the substrate of each sequencing chip, and after punching, the wafer is subjected to ultrasonic cleaning and high-purity nitrogen drying treatment;

[0099] (4) design of the flow channel structure of the sequencing chip, with a depth of 0.05 mm, and calculation and optimization of the flow channel structure using fluid simulation, and confirmation of the distribution of the chip on the wafer;

[0100] (5) design of the corresponding optical mask according to the chip flow channel structure design and the distribution of the chip on the wafer, and processing and preparation of the mask;

[0101] (6) etching processing of the wafer cover plate using the above-mentioned mask, using wet etching method, with an etching depth of about 50 μm, and an etching precision tolerance of + / - 2 μm;

[0102] (7) anodic bonding of the etched wafer cover plate and the punched wafer substrate, the entire bonding process needs to be performed in sequence, i.e. alignment of the wafer cover plate and the wafer substrate, lamination of the wafer cover plate and the wafer substrate, bonding of the wafer cover plate and the wafer substrate, and specific operation process of the alignment and lamination of the wafer cover plate and the wafer substrate is performed on a wafer aligner, the alignment method mainly uses the marks on the wafer cover plate and the wafer substrate, and the bonding of the wafer cover plate and the wafer substrate is performed on a bonder, and the anodic bonding temperature is 200°C;

[0103] (8) surface chemical treatment of the bonded wafer, specifically placing the bonded wafer in a card slot, and placing the card slot containing the wafer into a surface treatment device, and the surface treatment method is to form an amino group surface structure by chemical vapor deposition, and the chemical vapor deposition treatment temperature is 25°C, and the time is 60 min;

[0104] (9) laser cutting of the bonded and chemical vapor deposition surface treated wafer to form a single sequencing chip;

[0105] (10) subsequent processes of the single sequencing chip formed after cutting, including assembly of the chip frame, complete chip detection (testing the surface contact angle, the surface contact angle is 80°), and vacuum packaging of the chip, and finally obtaining the finished chip as Figure 10as shown.

[0106] Example 2

[0107] The present application provides a method for sequencing chip surface chemical treatment and packaging bonding, the method steps are:

[0108] (1) ultrasonic cleaning of the chip frame, using ultrapure water during the cleaning process, after cleaning, using high-purity nitrogen to dry the surface of the wafer;

[0109] (2) ultrasonic cleaning of the wafer substrate (silicon material, thickness 0.8mm) and wafer cover plate (ordinary glass material, thickness 0.4mm), using ultrapure water during the cleaning process, after cleaning, using high-purity nitrogen to dry the surface of the wafer, the wafer is stored in the nitrogen cabinet;

[0110] (3) punching processing of the wafer substrate, the specific method is laser punching, 2 holes are punched, the hole diameter is 0.9mm, which can be used as liquid inlet or liquid outlet, and is diagonally distributed on the substrate of each sequencing chip, after punching, ultrasonic cleaning and high-purity nitrogen blowing are carried out again;

[0111] (4) design the flow channel structure of the sequencing chip, the depth of the flow channel structure is 0.07mm, and the fluid simulation is used for calculation analysis and optimization, at the same time, the structure distribution of the chip on the wafer is confirmed;

[0112] (5) according to the chip flow channel structure design and the distribution of the chip on the wafer, the corresponding optical mask is designed, and the mask is processed and prepared;

[0113] (6) using the above-mentioned mask to etch the wafer cover plate, the etching method is wet etching, the etching depth is about 50μm, and the etching precision tolerance can be controlled within + / - 2μm;

[0114] (7) anodically bonding the etched wafer cover plate and the punched wafer substrate, the whole bonding process needs to be carried out in sequence, the wafer cover plate and the wafer substrate are aligned, the wafer cover plate and the wafer substrate are attached, the wafer cover plate and the wafer substrate are bonded, and the specific operation process of the wafer cover plate and the wafer substrate alignment and attachment is carried out on the wafer aligner, the alignment method mainly uses the marks on the wafer cover plate and the wafer substrate, the bonding of the wafer substrate and the wafer cover plate is carried out on the bonding machine, and the anodic bonding temperature is 300℃;

[0115] (8) surface chemical treatment of the bonded wafer, specifically, the bonded wafer is placed in a card slot, the card slot with the wafer is placed into a surface treatment device, a surface structure of an amino group is formed by chemical vapor deposition, the temperature of the chemical vapor deposition treatment is 45°C, and the time is 20 minutes;

[0116] (9) laser cutting of the wafer after the bonding and the chemical vapor deposition surface treatment, thereby forming a single sequencing chip;

[0117] (10) subsequent processes of the single sequencing chip after the cutting, including assembling a chip frame, detecting a complete chip (testing a contact angle of a surface, the contact angle of the surface is 120°), and vacuum packaging of the chip.

[0118] Embodiment 3

[0119] The present application provides a method for surface chemical treatment and packaging bonding of a sequencing chip, and the steps of the method are as follows:

[0120] (1) ultrasonic cleaning of a chip frame, ultrapure water is used in the cleaning process, and after the cleaning, high-purity nitrogen is used to dry the surface of the wafer;

[0121] (2) ultrasonic cleaning of a wafer substrate (ordinary glass material, thickness 1 mm) and a wafer cover plate (quartz glass material, thickness 0.5 mm), ultrapure water is used in the cleaning process, and after the cleaning, high-purity nitrogen is used to dry the surface of the wafer, and the wafer is stored in a nitrogen cabinet;

[0122] (3) punching processing of the wafer substrate, specifically, laser punching is used, two holes are punched, the hole diameter is 2 mm, and the holes can be used as liquid inlets or outlets, and the holes are diagonally distributed on the substrate of each sequencing chip, and after the punching, ultrasonic cleaning and high-purity nitrogen drying treatment are performed;

[0123] (4) design of a flow channel structure of the sequencing chip, the depth of the flow channel structure is 0.1 mm, and calculation, analysis and optimization are performed by using fluid simulation, and at the same time, the structure distribution of the chip on the wafer is confirmed;

[0124] (5) design of a corresponding optical mask according to the chip flow channel structure design and the distribution of the chip on the wafer, and processing and preparation of the mask are performed;

[0125] (6) etching processing of the wafer cover plate by using the mask, wet etching is used for the etching, the etching depth is about 50 μm, and the etching precision tolerance can be controlled within + / - 2 μm;

[0126] (7) the etched wafer cover plate and the punched wafer substrate are anodically bonded, the whole bonding process needs to be performed in sequence of wafer cover plate and wafer substrate alignment, wafer cover plate and wafer substrate adhesion, wafer cover plate and wafer substrate bonding, and the specific operation process of wafer cover plate and wafer substrate alignment and adhesion is performed on a wafer aligner, the alignment mode mainly adopts the marks on the wafer cover plate and the wafer substrate, and the wafer substrate and the wafer cover plate are bonded on a bonder, and the anodic bonding temperature is 400 DEG C;

[0127] (8) the bonded wafer is subjected to surface chemical treatment, specifically, the bonded wafer is placed in a card slot, the card slot loaded with the wafer is placed into a surface treatment device, and a surface treatment method is chemical vapor deposition to form an amino group surface structure, the chemical vapor deposition treatment temperature is 50 DEG C, and the time is 5 min;

[0128] (9) the wafer after bonding and chemical vapor deposition surface treatment is subjected to laser cutting, so as to form a single sequencing chip;

[0129] (10) the single sequencing chip formed after cutting is subjected to subsequent processes, including assembling a chip frame, detecting a complete chip (testing a surface contact angle, and the surface contact angle is 60 DEG) and vacuum packaging the chip.

[0130] Combining Figures 1-7 the sequencing chip preparation is further described, Figure 1 is a plan view of an 8-inch wafer substrate, wherein 1 represents a wafer substrate, 2 represents the distribution of a single sequencing chip substrate on the 8-inch wafer substrate, 3 represents a single sequencing chip substrate, one wafer substrate can cut out 36 sequencing chip substrates, 4 represents a liquid inlet or outlet on the substrate, and the liquid inlet and outlet are diagonally distributed on each sequencing chip substrate; Figure 1 is a side view of the single sequencing chip substrate in the figure, wherein 3 represents a single sequencing chip substrate; Figure 3 is a plan view of an 8-inch wafer cover plate of the application, wherein 6 represents the distribution of a single sequencing chip cover plate on the 8-inch wafer cover plate, 7 represents a single sequencing chip cover plate, one wafer cover plate can cut out 36 sequencing chip cover plates, and 8 represents the etched flow channel cavity shape inside the single sequencing chip cover plate, and each sequencing chip cover plate has one flow channel cavity; Figure 4 is a side view of the single sequencing chip cover plate in the figure, wherein 7 represents a single sequencing chip cover plate, and 8 represents a single sequencing chip flow channel cavity; Figure 3 is a side view of the single sequencing chip cover plate in the figure, wherein 7 represents a single sequencing chip cover plate, and 8 represents a single sequencing chip flow channel cavity; Figure 5Figure 10 shows the distribution of sequencing chips on an 8-inch wafer after anodically bonding the wafer substrate and wafer cover. Figure 11 shows a single sequencing chip; a single wafer can produce 36 sequencing chips. Figure 12 shows the flow channel cavity inside a single sequencing chip. Figure 13 shows the liquid inlet or outlet of a single sequencing chip. Figure 6 for Figure 5 Figure 11 represents a single sequencing chip, Figure 12 is the flow channel cavity inside a single sequencing chip, and Figure 13 is the liquid inlet or outlet of a single sequencing chip; Figure 7 This is a top view of a single sequencing chip after being assembled with a chip frame. 14 in the figure represents a complete chip assembled with a chip frame, and 15 in the figure represents the chip frame.

[0131] In addition, the pressure distribution inside the flow channel of the prepared sequencing chip and the stress distribution on the chip surface were analyzed. Figure 8 and Figure 9 As shown in the figure, the pressure distribution inside the chip flow channel is represented by different color depths. Figure 8 As can be seen from the figure, the pressure distribution mainly increases from the liquid inlet to the liquid outlet. This is due to the negative pressure pumping mode of the sequencing instrument itself. However, the difference between the maximum pressure and the minimum pressure in the chip flow channel is very small. A small pressure difference can reduce the load on the sequencing instrument flow channel. At the same time, the uniform pressure inside the chip can reduce the difference in the reaction of biochemical reagents in different areas of the chip surface. The stress distribution on the chip surface uses different color depths to represent the magnitude of the stress. Figure 9 It can be seen from the figure that, except for the edge position, the stress distribution in other positions inside the chip flow channel is very uniform. The stress at the edge position is relatively large, which is mainly due to the multiphase interface formed by the chip substrate, chip cover, pressure-sensitive adhesive, and liquid reagent under the action of external force. However, the area at the edge position with relatively large stress is smaller, which also means that the affected area is smaller.

[0132] The method for preparing a sequencing chip of the present invention has a simple process, can perform batch surface treatment and packaging, significantly improves production efficiency and capacity, and reduces costs. The flow channel design of the present invention is relatively reasonable, which can effectively reduce the edge effect of the chip flow channel, reduce the deformation of the chip cover and flow channel, and reduce the differences in biochemical reactions at the chip liquid inlet, liquid outlet, and different areas, thereby improving the overall performance of the sequencing chip.

[0133] In summary, the present invention performs packaging, bonding, and surface treatment at the wafer level, and finally cuts and assembles individual chips, which can solve the relevant technical problems existing in the preparation of sequencing chips. On this basis, it simplifies the operation process, reduces process costs, and significantly improves production efficiency and capacity.

[0134] Applicants declare that the detailed methods of the present application are illustrated by the above examples, but the present application is not limited to the above detailed methods, i.e. it is not meant that the present application must rely on the above detailed methods to be implemented. It should be understood by those skilled in the art that any improvement on the present application, equivalent replacement of each raw material of the product of the present application, addition of auxiliary ingredients, selection of specific methods, etc. all fall within the protection scope and disclosure scope of the present application.

Claims

1. A method for surface chemical treatment and encapsulation bonding of a sequencing chip, characterized in that: The method comprises: Punching a hole in a wafer substrate, etching a flow channel structure on a wafer cover plate, bonding the punched wafer substrate and the etched wafer cover plate to obtain a bonded wafer, performing surface treatment on the bonded wafer, and cutting the bonded wafer to obtain the sequencing chip; The etching includes designing an optical mask according to the required flow channel structure, and etching the wafer cover plate using the optical mask; the depth of the flow channel structure is 0.05mm to 0.1mm; the depth tolerance of the etching process of the flow channel on the wafer cover plate using the mask is controlled to be + / -0.5μm, + / -1μm or + / -2μm; The shape of the sequencing chip flow channel has a streamlined structure, wherein the streamlined structure is a shape with smooth curves on both sides or both ends of the flow channel; The bonding method is anodic bonding at 200°C to 400°C; The surface treatment method is chemical vapor deposition treatment at 25°C to 50°C for 5min to 60min; The method further comprises the step of assembling a chip frame onto the sequencing chip obtained after cutting.

2. The method according to claim 1, characterized in that The materials of the wafer substrate and the wafer cover are independently selected from any one of quartz glass, ordinary glass or silicon wafer, or a combination of at least two of them.

3. The method according to claim 1, characterized in that The thickness of the wafer substrate is 0.5 mm to 1 mm.

4. The method according to claim 1, wherein The thickness of the wafer cover plate is 0.1 mm to 0.5 mm.

5. The method according to claim 1, wherein The method further comprises the steps of cleaning the wafer substrate and the wafer cover plate respectively before drilling and etching.

6. The method according to claim 5, characterized in that The cleaning method includes immersion cleaning, ultrasonic cleaning or plasma cleaning.

7. The method according to claim 5, characterized in that The cleaning liquid used in the cleaning comprises ultrapure water.

8. The method according to claim 5, characterized in that After the cleaning, the method further comprises the step of drying with an inert gas.

9. The method according to claim 8, characterized in that The inert gas includes nitrogen.

10. The method according to claim 1, characterized in that The punching method includes laser punching, mechanical punching or sandblasting punching.

11. The method according to claim 1, characterized in that The punching includes forming a liquid inlet hole and a liquid outlet hole.

12. The method according to claim 11, characterized in that The apertures of the liquid inlet and outlet holes are independently 0.5 mm to 2.0 mm.

13. The method according to claim 1, wherein The method further comprises the step of performing ultrasonic cleaning after the punching.

14. The method according to claim 1, wherein The etching method includes wet etching or dry etching.

15. The method according to claim 1, wherein The chip frame is made of any one of plastic, ceramic or metal.

16. The method according to claim 1, wherein The method comprises the following steps: (1) Ultrasonic cleaning of the wafer substrate and wafer cover; (2) drilling holes in the wafer substrate and performing ultrasonic cleaning; (3) designing an optical mask according to the desired flow channel structure, and etching the wafer cover plate using the optical mask; (4) bonding the punched wafer substrate and the etched wafer cover plate to obtain a bonded wafer; (5) performing chemical vapor deposition on the bonded wafer; (6) Cutting the bonded wafer processed in step (5) and assembling the chip frame to obtain a sequencing chip.

17. A sequencing chip, characterized in that: The sequencing chip is prepared by the method according to any one of claims 1 to 16.

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