A Software Hardening Method for Missile-Borne Computers Against Single-Event Upsets with Dynamic Refresh

Abstract

The present invention relates to a software hardening method for a missile-borne computer against single-event upsets with dynamic refresh, belonging to the field of missile-borne computers. The missile-borne computer of the present invention includes a DSP processor (1) and a non-volatile memory (2), and the DSP processor (1) is connected to the non-volatile memory (2) through an EMIF bus (3). The DSP processor (1) first partitions the protected data and calculates its CRC16-CCITT checksum, and then backs up these protected data and the CRC checksum in the non-volatile memory (2). During the operation of the missile-borne computer, the DSP processor (1) periodically performs CRC checks on the protected data located in its internal storage unit to identify whether an SEU occurs. When an SEU occurs, the backup data stored in the non-volatile memory (2) is updated to the internal storage unit of the DSP processor (1) to achieve error correction, thereby suppressing the influence of SEUs.

Description

Technical Field

[0001] The invention belongs to the field of missile-borne computers, and in particular relates to a dynamically refreshed missile-borne computer anti-single-particle upset software reinforcement method. Background Art

[0002] The missile-borne computer usually uses a high-performance digital signal processor (DSP) for signal processing, communication and flight control. In the space radiation environment, it is easily bombarded by radiation forms such as space high-energy plasma, protons, electrons and heavy ions, which causes the internal storage unit state of the DSP processor (1) to change and the stored data to flip, that is, single event upset (SEU). When SEU accumulates to a certain extent or occurs in the state machine of key components such as DSP fetch, instruction decoding and pipeline execution, it may cause DSP function abnormality.

[0003] The general method of current SEU software reinforcement is to use the "triple redundancy" technology for the protected data, that is, to store the same data in different locations of the internal storage unit of the DSP processor (1). When in use, the three sets of data are read out simultaneously for comparison, and the technology of using two sets of the same data is used.

[0004] The existing technology can suppress the harm of SEU to a certain extent, but it has the following defects:

[0005] Significantly increase the DSP internal storage space requirements, which is three times the requirements before reinforcement;

[0006] Since each data read or write operation requires reading or writing three times and making decisions, the computing load will increase significantly, causing the actual computing performance of the DSP to decline;

[0007] When the three sets of data are different from each other, it is impossible to determine which set of data is correct, that is, the SEU reinforcement fails. Summary of the invention

[0008] 1. Technical issues to be resolved

[0009] The technical problem to be solved by the present invention is how to provide a dynamically refreshed missile-borne computer anti-single-particle upset software reinforcement method to solve the problems that the existing anti-single-particle upset software reinforcement method significantly increases the internal storage space requirement of DSP, greatly increases the computing load, causes the actual computing performance of DSP to decline, and causes SEU reinforcement failure.

[0010] (II) Technical solution

[0011] To solve the above technical problems, the present invention proposes a software hardening method for dynamic refresh of an on-board computer against single event upsets. This method is applied to an on-board computer, which includes a DSP processor (1) and a non-volatile memory (2). The DSP processor (1) is connected to the non-volatile memory (2) through an EMIF bus (3). The software adopting the SEU software hardening method runs in the DSP processor (1). The non-volatile memory (2) is used to back up the protected data, and the EMIF bus is responsible for supporting data interaction between the DSP processor (1) and the non-volatile memory (2). During system initialization, the DSP processor (1) first partitions the protected data and calculates its CRC checksum, and then backs up the protected data and the CRC checksum in the non-volatile memory (2). During the operation of the on-board computer, the DSP processor (1) periodically performs CRC check on the protected data located in its internal storage unit to identify whether an SEU occurs. When an SEU occurs, the backup data stored in the non-volatile memory (2) is updated to the internal storage unit of the DSP processor (1) to achieve error correction.

[0012] Further, the protected data is protected data with a total length of L, which is divided into n data blocks according to a length of k bytes. Each data block is respectively called B1, B2, B3, …, Bn.

[0013] Further, the CRC checksum is calculated by using the CRC16-CCITT check algorithm.

[0014] Further, the operation steps of this software hardening method include:

[0015] The first step: The on-board computer is powered on, and the program of the DSP processor (1) starts to run; the protected data with a total length of L is divided into n data blocks according to a length of k bytes. Each data block is respectively called B1, B2, B3, …, Bn.

[0016] The second step: In a certain order, use the CRC16-CCITT check algorithm to calculate the CRC checksums of the data blocks B1, B2, B3, …, Bn, which are called R1, R2, R3, …, Rn.

[0017] The third step: The partitioned protected data and the CRC checksum are backed up in the non-volatile memory (2) in order.

[0018] The fourth step: Configure the DSP timer and set the timing interrupt to m milliseconds.

[0019] Step 5: When the timer interrupt is triggered, read the data of one data block each time from the internal storage unit of the DSP processor (1) in the order of B1, B2, B3, …, Bn, then calculate its CRC checksum using the CRC16-CCITT checksum algorithm, and then compare it with the CRC checksums R1, R2, R3, …, Rn stored in the non-volatile memory;

[0020] Step 6: If the CRC checksum of the internal data of the DSP processor (1) in Step 5 is equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that the current data block has not suffered from SEU, and jump back to Step 5 to continue reading the next data block; if the CRC checksum of the internal data of the DSP processor (1) is not equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that the current data block has suffered from SEU, and continue to execute Step 7;

[0021] Step 7: Read the backup corresponding to the data block that has suffered from SEU currently from the non-volatile memory (2), refresh the data in the internal storage unit of the DSP processor (1) to the correct value, and then jump back to Step 5 to continue reading the next data block until all data blocks have been compared.

[0022] Further, in Step 3, the protected data and the CRC checksum are stored in the non-volatile memory (2) in the order of B1, R1, B2, R2, B3, R3, …, Bn, Rn.

[0023] Further, in Step 3, the protected data and the CRC checksum are stored in the non-volatile memory (2) in the order of Bn, Rn, Bn-1, Rn-1, …, B1, R1.

[0024] Further, after n times of checksum refresh operations, the protected data inside the DSP processor (1) is the same as the data backed up in the non-volatile memory (2).

[0025] Further, adjust the value of the length k of each data block according to the different influence intensities of SEU, so as to adjust the time consumed for each CRC calculation and the time consumed for the refresh operation.

[0026] Further, adjust the trigger interval m of the timer interrupt according to the time slice division of the DSP calculation operation.

[0027] Further, perform the checksum refresh operation when the DSP is idle.

[0028] (3) Beneficial effects

[0029] The present invention proposes a software hardening method for anti-single event upset of a missile-borne computer with dynamic refresh. The technical problems that can be solved by the software hardening method for anti-SEU of the missile-borne computer with dynamic refresh proposed in this application are:

[0030] Do not increase the internal storage space requirement of the DSP;

[0031] By using the CRC16-CCITT check algorithm to check the correctness of the data, identify the data block where SEU occurs, and then dynamically refresh the data in the internal storage unit of the DSP processor (1) according to the check result, the execution time of the SEU hardening processing operation is less, and the calculation resource occupancy rate is lower;

[0032] Execute the SEU hardening process at a certain time period, and the DSP computing resources are time-division multiplexed, which has less impact on the normal program execution flow;

[0033] The length of the data block and the period of executing the SEU hardening process can be flexibly adjusted, and a balance can be achieved between the calculation resource occupancy and the SEU hardening effect. Description of the Drawings

[0034] Figure 1 It is the connection schematic diagram of the DSP of the missile-borne computer and the non-volatile memory;

[0035] Figure 2 It is the flow chart of the software hardening method for anti-SEU of the missile-borne computer with dynamic refresh;

[0036] Figure 3 It is the schematic diagram of the non-volatile memory backup data. Detailed Embodiment

[0037] To make the purpose, content and advantages of the present invention clearer, the following combines the drawings and embodiments to further describe the detailed embodiments of the present invention.

[0038] The purpose of the present invention is to propose a method that neither increases the internal storage space occupancy of the DSP, does not significantly reduce the actual computing performance of the DSP, and can significantly reduce the harm of single event upset.

[0039] The software hardening method for anti-SEU of the missile-borne computer with dynamic refresh proposed by the present invention is applied in a missile-borne computer. The missile-borne computer includes a DSP processor (1) and a non-volatile memory (2), and the DSP processor (1) is connected to the non-volatile memory (2) through an EMIF bus (3). The schematic diagram is as Figure 1 shown. The software adopting the SEU software hardening method of the present invention runs in the DSP processor (1), the non-volatile memory (2) is used to back up the protected data, and the EMIF bus is responsible for supporting the data interaction between the DSP processor (1) and the non-volatile memory (2).

[0040] When the system is initialized, the DSP processor (1) first partitions the protected data and calculates its CRC16-CCITT checksum, and then backs up these protected data and CRC checksum in the non-volatile memory (2). During the operation of the missile-borne computer, the DSP processor (1) periodically performs CRC checks on the protected data located in its internal storage unit to identify whether an SEU occurs. When an SEU occurs, the backup data stored in the non-volatile memory (2) is updated to the internal storage unit of the DSP processor (1) to achieve error correction, thereby suppressing the impact of SEUs. Its flowchart is as Figure 2 shown.

[0041] The detailed operation steps are as follows:

[0042] The first step: When the missile-borne computer is powered on, the program of the DSP processor (1) starts to run. The protected data with a total length of L is divided into n data blocks according to the length of k bytes. Each data block is respectively called B1, B2, B3, ……, Bn.

[0043] The second step: In a certain order, use the CRC16-CCITT checksum algorithm to calculate the CRC checksums of the data blocks B1, B2, B3, ……, Bn respectively, which are called R1, R2, R3, ……, Rn.

[0044] The third step: The partitioned protected data and CRC checksums are backed up in the non-volatile memory (2) in order.

[0045] As Figure 3 shown, the protected data and CRC checksums are stored in the non-volatile memory (2) in the order of B1, R1, B2, R2, B3, R3, …, Bn, Rn.

[0046] In another embodiment, the protected data and CRC checksums can also be stored in the non-volatile memory (2) in the order of Bn, Rn, Bn-1, Rn-1, …, B1, R1.

[0047] The fourth step: Configure the DSP timer and set the timer interrupt to m milliseconds.

[0048] The fifth step: When the timer interrupt is triggered, read the data of one data block at a time from the internal storage unit of the DSP processor (1) in the order of B1, B2, B3, ……, Bn, then use the CRC16-CCITT checksum algorithm to calculate its CRC checksum, and then compare it with the CRC checksums R1, R2, R3, ……, Rn stored in the non-volatile memory.

[0049] Step 6: If the CRC checksum of the internal data of the DSP processor (1) in Step 5 is equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that the current data block has not suffered from SEU, and the process jumps back to Step 5 to continue reading the next data block; if the CRC checksum of the internal data of the DSP processor (1) is not equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that the current data block has suffered from SEU, and Step 7 is continued.

[0050] Step 7: Read the backup corresponding to the data block that has suffered from SEU currently from the non-volatile memory (2), refresh the data in the internal storage unit of the DSP processor (1) to the correct value, and then jump back to Step 5 to continue reading the next data block until all data blocks have been compared.

[0051] After n times of checksum refresh operations, the protected data inside the DSP processor can be the same as the data backed up in the non-volatile memory, thus achieving the purpose of reducing the harm of single-event upsets.

[0052] According to the different influence intensities of SEU, the value of the length k of each data block can be flexibly adjusted, so as to flexibly adjust the time consumed for each CRC calculation and the time consumed for the refresh operation.

[0053] According to the time slice division of the DSP calculation operation, the triggering interval m of the timer interrupt is flexibly adjusted.

[0054] Select to perform the checksum refresh operation when the DSP is idle, further reducing the impact on the DSP calculation performance and achieving the balance between the computing resource occupancy and the SEU hardening effect.

[0055] The technical problems that can be solved by the anti-SEU software hardening method of the missile-borne computer with dynamic refresh proposed by the present invention are:

[0056] Do not increase the internal storage space requirement of the DSP;

[0057] By using the CRC16-CCITT check algorithm to check the correctness of the data, identify the data block suffering from SEU, and then dynamically refresh the data in the internal storage unit of the DSP processor (1) according to the check result, the execution time of the SEU hardening processing operation is less and the computing resource occupancy rate is lower;

[0058] Execute the SEU hardening processing according to a certain time period, and the DSP computing resources are time-division multiplexed, with less impact on the normal program execution flow;

[0059] The length of the data block and the period of executing the SEU hardening processing can be flexibly adjusted, and a balance can be achieved between the computing resource occupancy and the SEU hardening effect.

[0060] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A software hardening method for a missile-borne computer against single event upsets with dynamic refresh, characterized in that This method is applied to an on-board computer, which includes a DSP processor (1) and a non-volatile memory (2). The DSP processor (1) is connected to the non-volatile memory (2) through an EMIF bus (3). The software adopting the SEU software hardening method runs in the DSP processor (1). The non-volatile memory (2) is used to back up the protected data. The EMIF bus is responsible for supporting data interaction between the DSP processor (1) and the non-volatile memory (2). During system initialization, the DSP processor (1) first partitions the protected data and calculates its CRC checksum, and then backs up the protected data and the CRC checksum in the non-volatile memory (2). During the operation of the on-board computer, the DSP processor (1) periodically performs CRC check on the protected data located in its internal storage unit to identify whether SEU occurs. When SEU occurs, the backup data stored in the non-volatile memory (2) is updated to the internal storage unit of the DSP processor (1) to achieve error correction; Among them, The operation steps of this software hardening method include: The first step: When the on-board computer is powered on, the program of the DSP processor (1) starts to run. The protected data with a total length of L is divided into n data blocks according to the length of k bytes. Each data block is respectively called B1, B2, B3, …, Bn; The second step: In a certain order, use the CRC16-CCITT check algorithm to calculate the CRC checksums of the data blocks B1, B2, B3, …, Bn, which are called R1, R2, R3, …, Rn; The third step: Back up the partitioned protected data and the CRC checksums in the non-volatile memory (2) in order; The fourth step: Configure the DSP timer and set the timing interrupt to m milliseconds; The fifth step: When the timing interrupt is triggered, read the data of one data block each time from the internal storage unit of the DSP processor (1) in the order of B1, B2, B3, …, Bn, then use the CRC16-CCITT check algorithm to calculate its CRC checksum, and then compare it with the CRC checksums R1, R2, R3, …, Rn stored in the non-volatile memory; The sixth step: If the CRC checksum of the internal data of the DSP processor (1) in the fifth step is equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that no SEU has occurred in the current data block, and jump back to the fifth step to continue reading the next data block; if the CRC checksum of the internal data of the DSP processor (1) is not equal to the CRC checksum backed up in the non-volatile memory (2), it is considered that SEU has occurred in the current data block, and continue to execute the seventh step; The seventh step: Read the backup corresponding to the data block where SEU has occurred currently from the non-volatile memory (2), refresh the data in the internal storage unit of the DSP processor (1) to the correct value, and then jump back to the fifth step to continue reading the next data block until all data blocks have been compared.

2. The software hardening method for dynamic refresh of on-board computer against single event upset according to claim 1, characterized in that The protected data is protected data with a total length of L, divided into n data blocks by length k bytes, and each data block is respectively called B1, B2, B3, …, Bn.

3. The software hardening method for dynamic refresh of an on-board computer against single-event upsets according to claim 1, characterized in that The CRC checksum is calculated by using the CRC16-CCITT check algorithm.

4. The method for software hardening of an on-board computer against single event upsets with dynamic refresh as claimed in claim 1, wherein In the third step, the protected data and the CRC checksum are stored in the non-volatile memory (2) in the order of B1, R1, B2, R2, B3, R3, …, Bn, Rn.

5. The method for software hardening of an on-board computer against single event upsets with dynamic refresh according to claim 1, characterized in that, In the third step, the protected data and the CRC checksum are stored in the non-volatile memory (2) in the order of Bn, Rn, Bn-1, Rn-1, …, B1, R1.

6. The method for software hardening of a missile-borne computer against single event upsets with dynamic refresh as claimed in claim 1, characterized in that After n checksum refresh operations, the protected data inside the DSP processor (1) is the same as the data backed up in the non-volatile memory (2).

7. The software hardening method for dynamic refresh of an on-board computer against single event upsets as claimed in claim 1, characterized in that Adjust the value of the length k of each data block according to the different influence intensities of SEU, so as to adjust the time consumed for each CRC calculation and the time consumed for the refresh operation.

8. The method for software hardening of a missile-borne computer against single event upsets with dynamic refresh as claimed in claim 1, wherein Adjust the trigger interval m of the timing interrupt according to the time slice division of the DSP calculation operation.

9. The software hardening method for dynamic refresh of on-board computer against single event upset according to claim 1, characterized in that, Perform the checksum refresh operation when the DSP is idle.

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