A method for verifying SVF files for chip debugging functions implemented based on Python

Abstract

The present invention discloses a method for implementing an SVF file for verifying the chip debugging function based on Python, which includes: S1: Complete the initialization of the test register content and store it in a dictionary; S2: Determine the number of test access interfaces and the data width of each test access interface; S3: Integrate the results obtained in S1 and S2 to form a complete main data chain required for the SVF file of the chip to be verified, as the default initial value of the SVF file; S4: Complete the configuration file of the target device according to the requirements of the debugging operation; S5: Apply the configuration file generated in S4 to the content of S1, replace the corresponding data in the dictionary according to the configuration file, and convert the debugging operation of the target device into an operation on the corresponding register; S6: Replace the corresponding content of the data chain in S3 according to the position of the test access interface of the target device on the data chain, and update the main data chain of the SVF file; S7: Add the commands defined by SVF to complete the SVF file of the required use case.

Description

Technical Field

[0001] The present invention relates to the field of chip debugging verification, and in particular, to a method for implementing an SVF file for verifying chip debugging functions based on Python. Background Art

[0002] The full name of SVF is Serial Vector Format, which is a serial vector format and is part of IEEE 1149.1. JTAG (Joint Test Action Group) device and software providers have adopted SVF as a standard for data exchange. SVF is mainly used to control the JTAG for data reception and transmission. Since JTAG is serial, reception and transmission occur simultaneously. Using SVF can control the JTAG transmitter without considering the details of the JTAG TAP (Test Access Port) state machine. SVF describes JTAG chain operations in a compact and portable form. The SVF file records JTAG operations by describing the information that needs to be shifted into the device chain, thereby implementing the debugging function of JTAG devices.

[0003] Generally, during the chip development stage, the SVF method can be used to verify multiple JTAG devices. SVF supports a chain structure composed of multiple JTAG devices and can flexibly select a certain device for debugging. At the same time, during the test stage after chip production, the SVF file format is mostly used for testing at present. Many third-party programming tools use the SVF file as input and program the devices on the JTAG chain using the information contained in the SVF file. Therefore, the SVF file plays a key role in the verification stage during chip development and the chip production test stage. Moreover, the SVF file can be reused, reducing repetitive work and shortening the chip development cycle. At the same time, the SVF file configuration is flexible, facilitating the addition or reduction of debugging devices.

[0004] Furthermore, Python is a commonly used scripting language at present. Its greatest advantage lies in being easy to learn, having a high degree of integration, extensive library support, a short development cycle, and flexibility. Therefore, designing a method for implementing an SVF file based on Python to verify chip debugging functions has become a demand in the industry. Summary of the Invention

[0005] To solve the above problems, the present invention provides a method for implementing an SVF file for verifying chip debugging functions based on Python. When testing a chip through a JTAG interface, the SVF file implemented by a Python script during the simulation verification stage in the development period can be directly applied to the test in the chip factory stage, achieving the sharing of test cases through one design, saving test time and the development cost of test cases.

[0006] To achieve the above object, the present invention provides a method for implementing an SVF file for verifying the debugging function of a chip based on Python, which is used to verify the debugging function of the chip, and includes the following steps:

[0007] Step S1: According to the description of the debugging-related test registers in the chip manual, complete the initialization of the test register content and store it in a dictionary. Each chip to be verified contains multiple devices with JTAG test access interfaces;

[0008] Step S2: According to the information in the chip manual, determine the number of test access interfaces and the data width of each test access interface;

[0009] Step S3: Integrate the results obtained in Step S1 and Step S2 to form a complete main data chain required for the SVF file of the chip to be verified, as the default initial value of the SVF file. The SVF file contains all the information of all devices with JTAG test access interfaces on the chip to be verified;

[0010] Step S4: According to the requirements of the debugging operation, complete the configuration file of the target device. The configuration file includes the test access interface information of the target device and the read and write operation information of the test register;

[0011] Step S5: Apply the configuration file generated in Step S4 to the content of Step S1, replace the corresponding data in the dictionary according to the configuration file, and convert the debugging operation of the target device into an operation on the corresponding register;

[0012] Step S6: According to the position of the test access interface of the target device on the data chain, replace the corresponding content of the data chain in Step S3, and update the main data chain of the SVF file;

[0013] Step S7: Add the commands defined by the SVF to the result of Step S6 to complete the SVF file of the required use case.

[0014] In an embodiment of the present invention, specifically, Step S1 is as follows: Each device with a JTAG test access interface is defined with debugging information in the chip manual. The debugging information includes the specific description of the internal test register of the corresponding device, specifically including: the test register address, data width, the meaning of each data bit, and the read and write attributes of each data bit; Store the debugging information of each device in a dictionary defined by the Python scripting language, and map each device to the dictionary according to its built-in ID one by one.

[0015] In an embodiment of the present invention, specifically, Step S2 is as follows:

[0016] Determine the number of JTAG test access interfaces according to the information of JTAG devices and JTAG device chains in the chip manual;

[0017] Determine the data width of the corresponding JTAG test access interface according to the instruction register and data register inside each JTAG test access interface.

[0018] In an embodiment of the present invention, the complete main data chain in step S3 is formed by linking the JTAG test access interfaces of multiple devices inside the chip to be verified through the JTAG device chain.

[0019] In an embodiment of the present invention, step S3 further includes a process for determining debug commands, which is implemented through shift operations to ensure data integrity. Specifically:

[0020] The JTAG test access interface sends the debug commands in the form of serial data to the corresponding data chain through the data lines at the JTAG interface data input end.

[0021] Select the device to be debugged by shifting the corresponding data width according to the position of the test access interface of the device to be debugged in the entire data chain.

[0022] In an embodiment of the present invention, step S4 is specifically:

[0023] Modify the content of the corresponding registers and the corresponding read / write operation attributes in the dictionary of the target device in step S1 according to the cases required for chip verification or the cases required for the test process, and generate a configuration file for the target device.

[0024] In an embodiment of the present invention, step S7 is specifically:

[0025] Add commands according to the SVF specification to obtain the SVF file of the required cases. The added commands include:

[0026] DELAY: A command used to delay the start of the test and wait for the start process of the device under test to complete;

[0027] ENDIR IRPAUSE: A command to configure the default end state of the instruction register scan operation;

[0028] ENDDR DRPAUSE: A command to configure the default end state of the data register scan operation; and

[0029] STATE IDLE: A command to configure to stay in the idle state after the test is completed.

[0030] The method for implementing an SVF file for verifying the chip debugging function based on Python provided by the present invention, compared with the prior art, can be flexibly applied to different test and debugging scenarios by modifying the configuration file, and is convenient to modify and use, saving the script development cost and test time. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a flowchart of the method according to an embodiment of the present invention;

[0033] Figure 2 It is a schematic diagram of the complete data chain of the SVF file in an embodiment of the present invention. Detailed Embodiments

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0035] Figure 1 It is a flowchart of the method according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for implementing an SVF file for verifying the chip debugging function based on Python, which is used to verify the debugging (DEBUG) function of the chip, and includes the following steps:

[0036] Step S1: According to the description of the debugging (DEBUG) related test registers in the chip manual, complete the initialization of the test register content and store it in a dictionary. Among them, each chip to be verified contains multiple devices with JTAG test access ports (TAP, test access port, defined by the JTAG standard IEEE1149.1).

[0037] In this embodiment, step S1 is specifically as follows: Each device containing a JTAG test access interface defines debug information in the chip manual. The debug information includes specific descriptions of the internal test registers of the corresponding device, specifically including: test register address, data width, meaning of each data bit, read / write attributes of each data bit, etc.; The debug information of each device is stored in the form of a dictionary defined by the Python scripting language. Since each device's test access port (TAP) is set with a unique ID (ID Code), each device is thus mapped to the dictionary one by one according to its built-in ID.

[0038] Since initializing the content of the test register can clarify the default value of the test register, thereby reducing the complexity of processing in subsequent steps.

[0039] Step S2: According to the information in the chip manual, determine the number of test access ports (TAPs) and the data width of each test access port (TAP);

[0040] In this embodiment, step S2 is specifically as follows:

[0041] According to the information of the JTAG devices and the JTAG device chain in the chip manual, determine the number of JTAG test access ports (TAPs);

[0042] According to the instruction register (IR, instruction register) and data register (DR, data register) inside each JTAG test access port (TAP), determine the data width of the corresponding JTAG test access port (TAP).

[0043] The method of this embodiment takes the test access port (TAP) as a unit, so the width of the internal data can be flexibly changed.

[0044] Step S3: Integrate the results obtained in step S1 and step S2 to form a complete main data chain required for the corresponding SVF file of the chip to be verified, as the default initial value of the SVF file. The SVF file contains all the information of all devices on the corresponding chip to be verified that contain JTAG test access ports (TAPs);

[0045] In this embodiment, the complete main data chain in step S3 is formed by linking the JTAG test access ports (TAPs) of multiple devices inside the chip to be verified through the JTAG device chain to form a complete data chain. The test cases used in the chip verification process and the test process are actually to edit the default initial value of the obtained SVF file to be applicable to different test cases.

[0046] Figure 2Schematic diagram of the complete data chain of the SVF file in an embodiment of the present invention, as Figure 2 shown. In this embodiment, it is exemplified that there are 5 JTAG devices in the chip, but the number of JTAG devices is not limited, and the number can be other values. The figure is only used to illustrate the data chain form. In this embodiment, each JTAG device corresponds to a test access port (TAP) and a test register. First, the content of the test register inside each device is described and stored in the form of a dictionary (step S1). Then, the test access port (TAP) of each device is described (including the number and data width) (step S2). Next, all the devices on the entire system are connected through the test access port (TAP) to form a complete data chain, which is used as the default initial value of the SVF file (step S3). According to the JTAG IEEE1149.1 standard, TCK is the JTAG interface data shift clock, TMS is the interface data control signal, TDI is the JTAG interface data input terminal, and TDO is the JTAG interface data output terminal. The default initial value of the SVF file obtained in this way can be applied to different test cases.

[0047] In this embodiment, step S3 further includes a determination process of the debug command, which is implemented through a shift operation to ensure the integrity of the data. Specifically:

[0048] The JTAG test access port (TAP) sends the debug command in the form of serial data to the corresponding data chain through the data line of the JTAG interface data input terminal (TDI);

[0049] According to the position of the test access port (TAP) of the device to be debugged on the entire data chain, the device to be debugged is selected by shifting the corresponding data width, so that the data will not be lost.

[0050] Combined with Figure 2 Specifically described, Figure 2 there are 5 JTAG devices to be debugged, and each JTAG device corresponds to a test access port (TAP). Taking the selection of the device as an example, device 2 is used as the target device. The debug command is input into the entire SVF data chain from device 1 (regarded as the head of the data chain). Since device 2 is in the second device position, the debug command is shifted by the data width of 2 test access ports, so as to correctly send the debug command to device 2.

[0051] Step S4: Complete the configuration file of the target device according to the requirements of the debug (DEBUG) operation. Among them, the configuration file includes the test access port (TAP) information of the target device, the read and write operation information of the test register, etc.;

[0052] In this embodiment, step S4 is specifically:

[0053] Modify the content of the corresponding register in the dictionary of the target device and the corresponding read / write operation attributes in step S1 according to the test cases required for chip verification or the test cases required for the test process, and generate a configuration file for the target device. That is to say, if the content of a certain register needs to be modified according to the application case requirements, the corresponding content is modified in the corresponding dictionary during configuration. If the read / write operation attributes of a certain register need to be edited according to the application case requirements, the corresponding control bit of the register is modified in the corresponding dictionary. The configuration file obtained in this way corresponds to the application case requirements and is used for subsequent invocation when executing the corresponding application case. The configuration of the debug (DEBUG) operation is flexible and can be applied to different scenarios. Only the configuration file needs to be adjusted, and there is no need to care too much about the details in the initialization file.

[0054] Step S5: Apply the configuration file generated in step S4 to the content of step S1, replace the corresponding data in the dictionary according to the configuration file, and convert the debug (DEBUG) operation of the target device into an operation on the corresponding register;

[0055] Since the configuration file contains the content that needs to be modified, the default value of the dictionary in step S1 can be modified according to the configuration file, that is, extract the register name, the corresponding modified content and the operation attributes of a certain data bit in the configuration file, and replace the corresponding content in step S1. Through the characteristics of the python dictionary, the test register operation can be conveniently and quickly changed into the serial data required by JTAG.

[0056] Step S6: According to the position of the test access port (TAP) of the target device on the data link, replace the corresponding content of the data link in step S3, and update the main data link of the SVF file;

[0057] Step S6 is to replace the default initial value of the SVF file generated in step S3 with the result of step S5 according to the position of the test access port (TAP) of the target device on the data link, so as to update the content of the main data link of the SVF file. In this step, only the debug (DEBUG) operation of the test access port (TAP) of the target device needs to be changed, and it has no impact on the test registers corresponding to the test access ports (TAPs) of other devices.

[0058] Step S7: Add the commands defined by SVF to the result of step S6 to complete the SVF file of the required test cases.

[0059] In this embodiment, specifically, step S7 is as follows:

[0060] Add commands according to the SVF specification (Serial Vector Specification) to obtain the SVF file of the required test cases. The commands added include:

[0061] DELAY: A command used to delay the start of a test and wait for the startup process of the device under test to complete;

[0062] ENDIR IRPAUSE: A command to configure the default end state of the instruction register (IR) scan operation;

[0063] ENDDR DRPAUSE: A command to configure the default end state of the data register (DR) scan operation;

[0064] STATE IDLE: A command to configure to stay in the idle state after the test is completed.

[0065] The obtained SVF file can be directly used for debugging and test execution in the corresponding scenarios, with a high reuse rate. When the requirements of the test cases change, only the corresponding configuration file needs to be modified according to the above process.

[0066] The above method of the present invention can be at least commonly used in the following scenarios:

[0067] Scenario 1: In the chip development stage, JTAG VIP (a library used for JTAG module verification, which can implement some basic JTAG debugging operations) can be used to parse the SVF file to verify the debug (DEBUG) function of the chip;

[0068] Scenario 2: In the chip wafer (generally referring to the wafer) test stage, the serial data of the SVF file can be directly input into the chip through the JTAG interface to implement the test function;

[0069] Scenario 3: When there are a large number of debug (DEBUG) modules inside the chip, the above method can automatically add or delete the target test access port (TAP) according to the configuration of the test access port (TAP), avoiding the impact on chip verification caused by the change of the position of the test access port (TAP), and can be used for large-scale debugging (DEBUG).

[0070] The method of the present invention for implementing an SVF file for verifying the chip debug function based on python, compared with the prior art, can be flexibly applied to different test and debugging scenarios by modifying the configuration file, and is convenient to modify and use, saving the script development cost and test time.

[0071] Those of ordinary skill in the art can understand that the drawings are only schematic diagrams of an embodiment, and the modules or processes in the drawings are not necessarily essential for implementing the present invention.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing an SVF file for verifying the chip debugging function based on Python, which is used to verify the chip debugging function. Characterized in that: It includes the following steps: Step S1: According to the description of the debugging-related test registers in the chip manual, complete the initialization of the test register content and store it in a dictionary. Among them, each chip to be verified contains multiple devices with JTAG test access interfaces inside; Step S2: According to the information in the chip manual, determine the number of test access interfaces and the data width of each test access interface; Step S3: Integrate the results obtained in Step S1 and Step S2 to form a complete main data chain required for the SVF file of the chip to be verified, as the default initial value of the SVF file. Among them, the SVF file contains all the information of all devices with JTAG test access interfaces on the chip to be verified; Step S4: According to the requirements of the debugging operation, complete the configuration file of the target device. Among them, the configuration file includes the test access interface information of the target device and the read / write operation information of the test register; Step S5: Apply the configuration file generated in Step S4 to the content of Step S1, replace the corresponding data in the dictionary according to the configuration file, and convert the debugging operation of the target device into an operation on the corresponding register; Step S6: According to the position of the test access interface of the target device on the data chain, replace the corresponding content of the data chain in Step S3, and update the main data chain of the SVF file; Step S7: Add the commands defined by SVF to the result of Step S6 to complete the SVF file of the required use case.

2. The method for implementing an SVF file for verifying the chip debugging function based on Python according to claim 1, Characterized in that: Step S1 is specifically: For each device with a JTAG test access interface, debugging information is defined in the chip manual. The debugging information includes the specific description of the internal test register of the corresponding device, specifically including: test register address, data width, the meaning of each data bit, and the read / write attribute of each data bit; Store the debugging information of each device in a dictionary defined by the Python scripting language, and map each device to the dictionary according to its built-in ID one by one.

3. The method for implementing an SVF file for verifying the chip debugging function based on Python according to claim 1, Characterized in that: Step S2 is specifically: Determine the number of JTAG test access interfaces according to the information of the JTAG device and the JTAG device chain in the chip manual; Determine the data width of the corresponding JTAG test access interface according to the instruction register and data register inside each JTAG test access interface.

4. The method for implementing an SVF file for verifying the chip debugging function based on Python according to claim 1, Characterized in that: The complete main data chain in Step S3 is formed by linking the JTAG test access interfaces of multiple devices inside the chip to be verified through the JTAG device chain.

5. The method for implementing an SVF file for verifying chip debugging functions based on Python according to claim 4, characterized in that, step S3 further includes a determination process of a debugging command, which is implemented by a shift operation to ensure data integrity, specifically: The JTAG test access interface sends the debugging command in a serial data manner to the corresponding data chain through the data line at the JTAG interface data input end; According to the position of the test access interface of the device to be debugged on the entire data chain, the device to be debugged is selected by shifting the corresponding data width.

6. The method for implementing an SVF file for verifying chip debugging functions based on Python according to claim 1, characterized in that, step S4 is specifically: According to the test cases required for chip verification or the test cases required for the test process, modify the content of the corresponding registers and the corresponding read / write operation attributes in the dictionary of the target device in step S1 to generate a configuration file for the target device.

7. The method for implementing an SVF file for verifying chip debugging functions based on Python according to claim 1, characterized in that, step S7 is specifically: Add commands according to the SVF specification to obtain the SVF file of the required test cases, where the added commands include: DELAY: A command used to delay the start of the test and wait for the start process of the device under test to complete; ENDIR IRPAUSE: A command to configure the default end state of the instruction register scan operation; ENDDR DRPAUSE: A command to configure the default end state of the data register scan operation; and STATE IDLE: A command to configure to stay in the idle state after the test is completed.

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