A heterogeneous multi-core scheduling method and device for unmanned maritime equipment

Abstract

This application proposes a heterogeneous multi-core scheduling method and apparatus for maritime unmanned equipment, relating to the field of edge computing heterogeneous multi-core task scheduling. The method includes: acquiring processing tasks and describing their constraints using a directed acyclic graph (DAG); executing the processing tasks using processing cores; ensuring that the processing time and total energy consumption of the processing cores satisfy preset constraints; acquiring a scheduling scheme that satisfies the constraints, and obtaining a first processing time and a first total energy consumption under the scheduling scheme; generating corresponding Gantt charts and energy consumption charts based on the first processing time and first total energy consumption; and adjusting the adaptive dynamic voltage-frequency adjustment (DVFS) technique of the scheduling scheme based on the constraints of the processing tasks, the Gantt chart, and the energy consumption chart. By monitoring task processing time and energy consumption, and leveraging the idle status of processing cores and the constraints of local tasks, the DVFS level is adjusted to compress idle time and reduce energy consumption.

Description

Technical Field

[0001] This application relates to the field of heterogeneous multi-core task scheduling in edge computing, and in particular to a heterogeneous multi-core scheduling method and apparatus for unmanned maritime equipment. Background Technology

[0002] Currently, existing heterogeneous multi-core task scheduling methods are generally designed for large computing devices such as data centers and servers, and cannot be adapted to the application scenarios of unmanned marine equipment. Furthermore, existing scheduling methods cannot meet the dual-level optimization of scheduling duration and energy consumption.

[0003] Dynamic Voltage and Frequency Scaling (DVFS): This technology dynamically adjusts the chip's operating frequency and voltage according to the different computing power requirements of the applications running on the chip, thereby achieving energy saving.

[0004] A Directed Acyclic Graph (DAG) is a graph that cannot be returned to a given vertex by following a number of edges. Summary of the Invention

[0005] This application aims to at least partially address one of the technical problems in the related art.

[0006] To address the significant problems of traditional heterogeneous multi-core task scheduling methods being unable to adapt to the application scenarios of unmanned maritime equipment and lacking sufficient collaborative optimization of time and energy consumption, this invention proposes a heterogeneous multi-core scheduling method and device for unmanned maritime equipment.

[0007] To achieve the above, the first aspect of this application proposes a heterogeneous multi-core scheduling method for unmanned maritime equipment, comprising:

[0008] Obtain the processing task and describe the constraint relationship of the processing task according to the directed acyclic graph, and execute the processing task through the processing kernel;

[0009] According to preset constraints, the processing time and total energy consumption of the processing core in executing the processing task meet the constraints.

[0010] Obtain a scheduling scheme that satisfies the constraints, and obtain the first processing time and the first total energy consumption under the scheduling scheme. Generate a corresponding Gantt chart and energy consumption chart based on the first processing time and the first total energy consumption.

[0011] Based on the constraints of the processing tasks, the Gantt chart, and the energy consumption chart, the adaptive dynamic voltage and frequency adjustment (DVFS) technique of the scheduling scheme is adjusted.

[0012] Further, the processing task comprises any one or more of a raw marine data acquisition task, a marine target detection task, a marine sensor data processing task, a marine object recognition task, a bearing information processing task, a perception information calculation task, a navigation task processing task, and a processing result saving task.

[0013] Further, the processing time comprises:

[0014] a computation overhead, the computation overhead represents a processing core at a DVFS level executing a processing task a required time, specifically represented as:

[0015]

[0016] wherein represents a number of clock cycles required for a processing core executing a processing task , and represents a frequency of a processing core at a DVFS level

[0017] a communication overhead, wherein the communication overhead is a time spent for data transmission from to , specifically represented as:

[0018]

[0019]

[0020] wherein represents a communication amount between a processing task and

[0021] Further, the total energy consumption comprises:

[0022] an energy consumed by an idle state of the processing core , wherein the is specifically represented as:

[0023] ,

[0024] wherein represents an idle power of a processing core , and represents an idle time of a processing core .​​

[0025] The processing core activity state consumes energy , wherein the Specifically represented as:

[0026]

[0027]

[0028] , wherein The capacitance of the circuit, The processing core The power supply voltage at the DVFS level .

[0029] The energy consumed by data transmission , wherein the Specifically represented as:

[0030]

[0031] , wherein The Manhattan distance between the processing core And The energy consumed by routing per unit of data transmission, The energy consumption per unit of data transmission according to the unit Manhattan distance.

[0032] Further, the preset constraint condition includes:

[0033] The processing time and total energy consumption of the processing task are minimized, and the formula is as follows:

[0034] ,

[0035] ,

[0036] , wherein The processing time of the processing core The processing time of the processing core.

[0037] Further, the adaptive dynamic voltage and frequency adjustment technology DVFS of the scheduling scheme is adjusted according to the constraint relationship, Gantt chart and energy consumption chart of the processing task, including:

[0038] According to the Gantt chart and energy consumption chart, the first processing time and first total energy consumption are monitored to ensure that the first processing time and first total energy consumption always meet the first preset condition in the DVFS adjustment process;

[0039] ​Randomly select a processing core and obtain the processing tasks assigned to the processing core. Check whether there is an idle state after the processing task is completed, except for the last task in the directed acyclic graph.

[0040] If there is an idle state, obtain all subsequent tasks of the current task based on the directed acyclic graph, and calculate the end time FTcur of the current task and the earliest start time of data transmission among all subsequent tasks STear.

[0041] Determine the end time FTcur of the current task and the earliest start time STear among all subsequent tasks for data transmission;

[0042] If FTcur < STear, the DVFS level of the current kernel processing the processing task is adjusted according to the second preset condition.

[0043] Furthermore, if there is no idle state after the processing task is completed, the DVFS level adjustment ends.

[0044] Furthermore, if FTcur > STear, the DVFS level adjustment ends.

[0045] The second aspect of this application proposes a heterogeneous multi-core scheduling device for unmanned maritime equipment, comprising:

[0046] The task acquisition module acquires processing tasks and describes the constraint relationships of the processing tasks according to a directed acyclic graph, and executes the processing tasks through the processing kernel;

[0047] The constraint module, based on preset constraint conditions, ensures that the processing time and total energy consumption of the processing core in executing the processing task meet the constraint conditions.

[0048] The graph generation module obtains a scheduling scheme that satisfies the constraints, and obtains the first processing time and the first total energy consumption under the first scheduling scheme. Based on the first processing time and the first total energy consumption, it generates a corresponding Gantt chart and energy consumption chart.

[0049] The DVFS adjustment module adjusts the adaptive dynamic voltage and frequency adjustment technology (DVFS) of the scheduling scheme according to the constraints of the processing tasks, the Gantt chart, and the energy consumption chart.

[0050] A third aspect of this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the method described in any one of the first aspects above.

[0051] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0052] By monitoring task processing time and energy consumption, and leveraging the idle status of processing cores and the constraints of local tasks, the DVFS level is adaptively adjusted to generate a highly energy-efficient scheduling method. This reduces idle time, improves resource utilization, and further saves processing energy consumption without affecting the overall processing time.

[0053] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0054] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0055] Figure 1 This is a flowchart illustrating a heterogeneous multi-core scheduling method for unmanned maritime equipment according to an exemplary embodiment;

[0056] Figure 2 This is a DAG diagram containing eight tasks, illustrated according to an exemplary embodiment;

[0057] Figure 3 This is a Gantt chart illustrating a scheduling scheme according to an exemplary embodiment;

[0058] Figure 4 This is an energy consumption diagram of a scheduling scheme according to an exemplary embodiment;

[0059] Figure 5 This is a Gantt chart of an adaptive DVFS-adjusted scheduling scheme illustrated according to an exemplary embodiment;

[0060] Figure 6 This is an energy consumption diagram of an adaptive DVFS-adjusted scheduling scheme according to an exemplary embodiment;

[0061] Figure 7 This is a block diagram illustrating a heterogeneous multi-core scheduling device for unmanned maritime equipment according to an exemplary embodiment;

[0062] Figure 8 It is a schematic block diagram of an electronic device. Detailed Implementation

[0063] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0064] The following description, with reference to the accompanying drawings, illustrates a heterogeneous multi-core scheduling method and apparatus for unmanned maritime equipment, according to an embodiment of this application.

[0065] use Represent a directed acyclic graph, where Represents a task set. It is a set of directed edges, representing the amount of data to be transferred between tasks and the direction of transmission. If the edges... Then the task Depends on , It is a task The prerequisite task, and the task It is a task The subsequent tasks, tasks Only in the mission It can only be executed after it has been executed.

[0066] For computing resources, use Indicates by A computing device consists of heterogeneous processing cores, and it is assumed that each processing core can only execute one task at a time. If two dependent tasks... Scheduled separately in the processing core and If so, then the transmission process will incur communication costs, denoted as . , It depends not only on the size of the data to be transmitted, but also on the two processing cores. and bandwidth between related.

[0067] Figure 1 This is an exemplary embodiment illustrating a heterogeneous multi-core scheduling method for unmanned maritime equipment, comprising:

[0068] Step 101: Obtain the processing task and describe the constraint relationship of the processing task according to the directed acyclic graph, and execute the processing task through the processing kernel.

[0069] The processing tasks include any one or more of the following: acquiring raw maritime data, detecting maritime targets, processing underwater sensor data, identifying maritime objects, processing azimuth information, calculating sensory information, processing navigation data, and saving processing results.

[0070] In this embodiment of the application, a directed acyclic graph is used to describe the descriptive relationships between processing tasks.

[0071] In one possible embodiment, eight processing tasks are set: 1-acquiring raw marine data, 2-maritime target detection, 3-undersea sensor data processing, 4-maritime object recognition, 5-position information processing, 6-sensory information calculation, 7-navigation task processing, 8-saving processing results, and the task sequence is: {1,2,3,4,5,6,7,8}.

[0072] In one possible embodiment, there are a total of four heterogeneous processing cores: 1-CPU, 2-GPU, 3-FPGA, and 4-DSP, each processing core having the same number of DVFS levels, i.e. Furthermore, the DVFS level can be adjusted for each processing core when performing specific tasks.

[0073] Step 102: According to the preset constraints, ensure that the processing time and total energy consumption of the processing core in executing the processing task meet the constraints.

[0074] Among them, processing time It can be defined as the time to execute all tasks assigned to it, and the total processing time is equal to the completion time of the last task, specifically expressed as:

[0075] .

[0076] Optionally, processing time includes:

[0077] Calculation cost, calculation cost Indicates processing kernel At the DVFS level Execute the processing task The required time is specifically expressed as follows:

[0078]

[0079] in Indicating the processing of the kernel Execute processing tasks Number of clock cycles required Indicates processing kernel At the DVFS level frequency of time

[0080] Communication overhead, of which, communication overhead For data from Transmit to The time spent is specifically expressed as follows:

[0081]

[0082]

[0083] in Indicates task processing and The amount of communication between them.

[0084] The total energy consumption (TEC) required to process the task is derived from the energy consumed by processing the idle state of the core. Energy consumed in processing nuclear activity Energy consumed by data transmission composition.

[0085] Energy consumed in processing nuclear idle states Specifically, it is expressed as follows:

[0086] ,

[0087] in, Indicates processing kernel idle power, Indicates processing kernel Free time;

[0088] If processing the kernel At the DVFS level Execute task at time Energy consumed ,in, Specifically, it is expressed as follows:

[0089]

[0090]

[0091] in, The capacitor represents the circuit. It is to process the kernel At the DVFS level The power supply voltage at that time.

[0092] Energy consumed by data transmission Specifically, it is expressed as follows:

[0093]

[0094] in, Indicates processing kernel and Manhattan distance between them This represents the routing energy consumed per unit of data transmission. This represents the energy consumption per unit of data transmission based on the Manhattan distance.

[0095] Optional, preset constraints include:

[0096] The formula for minimizing task processing time and total energy consumption is as follows:

[0097] ,

[0098] ,

[0099] in, for This refers to the processing time for the kernel.

[0100] Step 103: Obtain the scheduling scheme that meets the constraints, and obtain the first processing time and the first total energy consumption under the scheduling scheme. Generate the corresponding Gantt chart and energy consumption chart based on the first processing time and the first total energy consumption.

[0101] In one possible embodiment, the settings are as follows: Figure 2 The processing tasks shown include: 1-acquiring raw marine data, 2-marine target detection, 3-undersea sensor data processing, 4-marine object recognition, 5-position information processing, 6-sensory information calculation, 7-navigation task processing, and 8-saving processing results; four heterogeneous processing cores are set, including: 1-CPU, 2-GPU, 3-FPGA and 4-DSP; and four adjustable DVFS levels are set.

[0102] In one possible embodiment, the scheduling scheme that satisfies the constraints is:

[0103] The task execution sequence is {1, 4, 3, 2, 5, 7, 6, 8};

[0104] The processing core allocation is {3, 2, 1, 1, 4, 3, 2, 4};

[0105] The DVFS level is set to {3, 4, 2, 2, 2, 2, 2, 3}.

[0106] The time and duration required to process the task are shown in Table 1, and the performance information of the processing cores is shown in Table 2. The data in this table represents the frequency and power of the processing cores at different DVFS levels. The bandwidth and Manhattan distance between processing cores are shown in Table 3, and the settings are as follows: , It is a fixed value.

[0107] Table 1 Clock cycles required for the task

[0108]

[0109] Table 2 Processing Core Frequency and Power

[0110]

[0111] Table 3. Inter-core bandwidth and Manhattan distance

[0112]

[0113] Based on Tables 1, 2 and 3, the first processing time Cmax = 24.8 and the first total energy consumption TEC = 61.57 can be calculated.

[0114] The Gantt chart and energy consumption chart corresponding to the first processing time and the first total energy consumption are as follows: Figure 3 and Figure 4 As shown.

[0115] Step 104: Adjust the adaptive dynamic voltage and frequency adjustment technology (DVFS) of the scheduling scheme according to the constraints of the processing tasks, the Gantt chart, and the energy consumption chart.

[0116] In this embodiment, the first processing time and the first total energy consumption are monitored according to the Gantt chart and the energy consumption chart to ensure that the first processing time and the first total energy consumption always meet the first preset condition during the DVFS adjustment process.

[0117] The first preset condition is: satisfying Cmax1 = Cmax, such that TEC1 < TEC.

[0118] Optionally, a processing core is randomly selected and the processing tasks assigned to the processing core are obtained. It is then checked whether there is an idle state after the processing tasks are completed, except for the last task in the directed acyclic graph.

[0119] by Figure 3 Taking core "2" as an example, there is a period of idle time after completing task "T4".

[0120] If an idle state exists, obtain all subsequent tasks of the current task based on the directed acyclic graph, and calculate the end time FTcur of the current task and the earliest start time STear of all subsequent tasks for data transmission; if no idle state exists after the task is completed, end DVFS level adjustment.

[0121] by Figure 3 Taking core "2" as an example, after completing task "T4", there is an idle period. Based on the Directed Acyclic Graph (DAG), all subsequent tasks of the current task T4 are obtained, and the end time FTcur of the current task T4 and the earliest start time STear among all subsequent tasks for data transmission are calculated. Figure 3 It can be seen that the follow-up mission to T4 is T6, which is... Figure 5 We know that FTcur = 7.9 and STear = 13.5;

[0122] Determine the end time FTcur of the current task and the earliest start time STear among all subsequent tasks for data transmission;

[0123] If FTcur < STear, adjust the DVFS level of the current kernel processing task according to the second preset condition.

[0124] If FTcur > STear, end DVFS level adjustment.

[0125] The second preset condition is: under the premise of satisfying the first preset condition, make the DVFS as small as possible, that is, after adjustment, FTcur≤STear is satisfied.

[0126] by Figure 3 Taking core "2" as an example, after processing task "T4", FTcur=7.9 and STear=13.5 have been calculated. Therefore, FTcur<STear. According to Table 2, the DVFS level of core "2" for processing T4 can be adjusted from 4 to 1. At this time, FTcur=13.5, which satisfies FTcur≤STear.

[0127] After DVFS level adjustment, the first processing time Cmax1 = 24.8, and the first total energy consumption TEC1 = 54.98. The Gantt chart and energy consumption chart corresponding to the adjusted first processing time and first total energy consumption are as follows: Figure 5 and Figure 6 As shown

[0128] Figure 7 This is a block diagram illustrating a heterogeneous multi-core scheduling device for unmanned maritime equipment according to an exemplary embodiment; see reference. Figure 7 The device includes: a task acquisition module 710, a constraint module 720, a graphics generation module 730, and a DVFS adjustment module 740.

[0129] The task acquisition module 710 acquires processing tasks and describes the constraint relationships of the processing tasks according to the directed acyclic graph, and executes the processing tasks through the processing kernel;

[0130] The constraint module 720 ensures that the processing time and total energy consumption of the processing core meet the preset constraints.

[0131] The graph generation module 730 obtains a scheduling scheme that meets the constraints, and obtains the first processing time and the first total energy consumption under the first scheduling scheme, and generates a corresponding Gantt chart and energy consumption chart based on the first processing time and the first total energy consumption.

[0132] The DVFS adjustment module 740 adjusts the adaptive dynamic voltage and frequency adjustment technology (DVFS) of the scheduling scheme based on the constraints of the processing tasks, the Gantt chart, and the energy consumption chart.

[0133] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0134] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0135] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0136] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0137] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the voice command response method. For example, in some embodiments, the voice command response method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the voice command response method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the voice command response method by any other suitable means (e.g., by means of firmware).

[0138] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0139] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0140] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0141] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0142] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, and blockchain networks.

[0143] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0144] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0145] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A heterogeneous multi-core scheduling method for maritime unmanned equipment, characterized in that, The method comprises the following steps: obtaining a processing task and a constraint relationship of the processing task described by a directed acyclic graph, and executing the processing task by a processing core; making the processing time Cmax and the total energy consumption TEC of the processing core executing the processing task satisfy a preset constraint condition; obtaining a scheduling scheme satisfying the constraint condition, and obtaining a first processing time Cmax1 and a first total energy consumption TEC1 under the scheduling scheme, and generating a corresponding Gantt chart and an energy consumption chart according to the first processing time Cmax1 and the first total energy consumption TEC1; adjusting an adaptive dynamic voltage and frequency scaling (DVFS) technology of the scheduling scheme according to the constraint relationship of the processing task, the Gantt chart and the energy consumption chart, which comprises the following steps: monitoring the first processing time Cmax1 and the first total energy consumption TEC1 according to the Gantt chart and the energy consumption chart, and ensuring that the first processing time Cmax1 and the first total energy consumption TEC1 always satisfy a first preset condition in a DVFS adjustment process, the first preset condition being that Cmax1 = Cmax is satisfied, so that TEC1 < TEC; randomly selecting a processing core and obtaining a processing task allocated to the processing core, checking whether there is an idle state after the processing task is completed, except for the last task in the directed acyclic graph; if there is an idle state, obtaining all subsequent tasks of the current processing task according to the directed acyclic graph, and calculating an end time FTcur of the current task and a time STear of earliest data transmission of all subsequent tasks; judging the size of the end time FTcur of the current task and the time STear of earliest data transmission of all subsequent tasks; if FTcur < STear, adjusting the DVFS level of the processing core processing the processing task according to a second preset condition, the second preset condition being that the DVFS is as small as possible on the premise of satisfying the first preset condition, and the DVFS satisfies FTcur ≤ STear after adjustment.

2. The method of claim 1, wherein, The processing task comprises any one or more of an original marine data task, a marine target detection task, an underwater sensor data processing task, a marine object recognition task, a bearing information processing task, a perception information calculation task, a navigation task processing task and a processing result saving task.

3. The method of claim 1, wherein, The processing time comprises: a computation overhead a processing core at a DVFS level a processing task a required time, specifically represented as: wherein represents the number of clock cycles required to perform a processing task on a processing core represents the number of clock cycles required to perform a processing task on a processing core represents the number of clock cycles required to perform a processing task on a processing core represents the number of clock cycles required to perform a processing task on a processing core represents the number of clock cycles required to perform a processing task on a processing core represents the number of clock cycles required to perform a processing task communication overhead, wherein the communication overhead is the time taken for data to be transmitted from a source to a destination and is expressed as: wherein represents a processing task and the amount of communication between 4. The method of claim 3, wherein, The total energy consumption comprises: The processing core idle state consumes energy wherein the Specifically represented as: ， wherein, represents the idle power of the processing core , represents the idle time of the processing core . Energy consumed by the processing core activity state wherein the is specifically represented as: wherein, a capacitance representing a circuit, is a processing core a power supply voltage at a DVFS level when Energy consumed by data transmission wherein the is specifically represented as: wherein, denotes the Manhattan distance between processing cores and , denotes the routing energy consumed per unit of data transfer, denotes the energy consumption resulting from a unit of data transfer per unit of Manhattan distance.

5. The method of claim 4, wherein, The preset constraint condition comprises: The processing time and the total energy consumption of the processing task are minimum, and a formula is as follows: , , wherein, the time at which all task processing is complete, the processing core C k the time at which the last task is processed.

6. The method of claim 1, wherein, The method further comprises the following steps: if there is no idle state after the processing task is completed, ending the DVFS level adjustment.

7. The method of claim 1, wherein, The method further comprises the following steps: if FTcur > STear, ending the DVFS level adjustment.

8. A heterogeneous multi-core scheduling apparatus for maritime unmanned devices, characterized by, The method comprises the following steps: obtaining a processing task and a constraint relationship of the processing task described by a directed acyclic graph, and executing the processing task by a processing core; making the processing time Cmax and the total energy consumption TEC of the processing core executing the processing task satisfy a preset constraint condition; a graph generation module, configured to obtain a scheduling scheme meeting the constraint condition, and obtain a first processing time Cmax1 and a first total energy consumption TEC1 under the first scheduling scheme, and generate a Gantt chart and an energy consumption chart corresponding to the first processing time Cmax1 and the first total energy consumption TEC1 according to the first processing time Cmax1 and the first total energy consumption TEC1; a DVFS adjustment module, configured to adjust a dynamic voltage and frequency scaling (DVFS) of the scheduling scheme according to the constraint relationship of the processing task, the Gantt chart and the energy consumption chart, including: monitoring the first processing time Cmax1 and the first total energy consumption TEC1 according to the Gantt chart and the energy consumption chart, and ensuring that the first processing time Cmax1 and the first total energy consumption TEC1 always meet a first preset condition in the DVFS adjustment process, the first preset condition being: meeting Cmax1=Cmax, so that TEC1<TEC; randomly selecting a processing core and obtaining a processing task allocated to the processing core, checking whether there is an idle state after the processing task is completed, except for the last task in the directed acyclic graph; if there is an idle state, obtaining all subsequent tasks of the current processing task according to the directed acyclic graph, and calculating an end time FTcur of the current task and a time STear of earliest data transmission of all subsequent tasks; judging the size of the end time FTcur of the current task and the time STear of earliest data transmission of all subsequent tasks; if FTcur<STear, adjusting a DVFS level of the processing task of the current core according to a second preset condition, the second preset condition being: making the DVFS as small as possible on the premise of meeting the first preset condition, and meeting FTcur≤STear after the DVFS adjustment.

9. A computer device, comprising: A computer program product, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1-7 when executing the computer program.

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