Serial port multiplexing circuit

Abstract

A serial port multiplexing circuit, comprising a first communication interface chip, a second communication interface chip, the first communication interface chip and the second communication interface chip being electrically connected to a processor, further comprising: an interface for accessing an external device; a comparison unit electrically connected to the interface, for comparing an access voltage of the external device with a reference voltage and outputting a comparison signal; a control unit electrically connected to the comparison unit, for outputting a control signal according to the comparison signal; a switch unit electrically connected between the interface and the first communication interface chip and the second communication interface chip, for selecting to connect the first communication interface chip or the second communication interface chip according to the control signal, so as to realize interface multiplexing and reduce the volume of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication interface, in particular to a serial port multiplexing circuit. BACKGROUND

[0002] Industrial products use various serial port devices in daily data collection and processing, which requires the product to support various serial port protocols and require various serial interfaces. Usually only one serial interface is needed in an industrial environment, but in order to meet the needs of various serial interfaces, the product integrates multiple serial interfaces, resulting in an increase in product size and space occupation. SUMMARY

[0003] Therefore, it is necessary to provide a serial port multiplexing circuit device that can realize port multiplexing and reduce the size of the product.

[0004] The serial port multiplexing circuit provided by an embodiment of the present application comprises a first communication interface chip and a second communication interface chip, the first communication interface chip and the second communication interface chip are electrically connected to a processor, and further comprises:

[0005] an interface configured to access an external device;

[0006] a comparison unit electrically connected to the interface and configured to compare an access voltage of the external device with a reference voltage and output a comparison signal;

[0007] a control unit electrically connected to the comparison unit and configured to output a control signal according to the comparison signal;

[0008] a switch unit electrically connected between the interface and the first communication interface chip and the second communication interface chip and configured to select the first communication interface chip or the second communication interface chip to be connected according to the control signal.

[0009] Preferably, when the external device is a first type of device, the comparison unit outputs a first comparison signal, and the control unit outputs a first control signal to control the switch unit to connect the interface and the first communication interface chip according to the first comparison signal.

[0010] When the external device is a second type of device, the comparison unit outputs a second comparison signal, and the control unit outputs a second control signal to control the switch unit to connect the interface and the second communication interface chip according to the second comparison signal.

[0011] Preferably, the control unit comprises:

[0012] a first electronic switch comprising a first end, a second end and an enable end, the first end of the first electronic switch being electrically connected to an output end of the comparison unit;

[0013] The first resistor has one end electrically connected to the enable terminal of the first electronic switch and the other end electrically connected to the power supply.

[0014] The second electronic switch includes a first terminal, a second terminal, and an enable terminal. The second terminal of the second electronic switch is grounded, and the first terminal of the second electronic switch is electrically connected to the enable terminal of the first electronic switch.

[0015] The control subunit is electrically connected between the output terminal of the comparison unit and the enable terminal of the second electronic switch;

[0016] The trigger has its input terminal electrically connected to the first terminal of the first electronic switch and its output terminal electrically connected to the switch unit.

[0017] Preferably, when the first type of device or the second type of device is transmitting data, the control subunit maintains a high level to enable the second electronic switch, and the second electronic switch is grounded.

[0018] When the second electronic switch is grounded, the enable terminal of the first electronic switch is grounded, the first electronic switch is turned off, and the trigger maintains its current output state.

[0019] Preferably, the control subunit includes:

[0020] The first capacitor has one end electrically connected to the output terminal of the comparison unit;

[0021] The first logic NOT gate has its input terminal electrically connected to the other end of the first capacitor;

[0022] The second NOT gate has its input terminal electrically connected to the other end of the first NOT gate;

[0023] The diode has its anode connected to the output of the second NOT gate.

[0024] The second capacitor has one end electrically connected to the cathode of the diode and the other end grounded.

[0025] The second resistor has one end electrically connected to the cathode of the diode and the other end grounded.

[0026] Preferably, when the first type of device or the second type of device is transmitting data, the comparison unit outputs a high-low level signal, the first capacitor discharges to enable the second electronic switch, and the second electronic switch is grounded.

[0027] When the second electronic switch is grounded, the enable terminal of the first electronic switch is grounded, the first electronic switch is turned off, and the trigger maintains its current output state.

[0028] Preferably, the switching unit includes:

[0029] The first switch group includes a third electronic switch and a fourth electronic switch. The third electronic switch and the fourth electronic switch each include a first terminal, a second terminal and an enable terminal. The first terminal of the third electronic switch and the fourth electronic switch are electrically connected to the first communication interface chip, the second terminal is electrically connected to the interface, and the enable terminal is electrically connected to the output terminal of the trigger.

[0030] The second switch group includes a fifth electronic switch and a sixth electronic switch. The fifth electronic switch and the sixth electronic switch each include a first terminal, a second terminal and an enable terminal. The first terminal of the fifth electronic switch and the sixth electronic switch are electrically connected to the second communication interface chip, the second terminal is electrically connected to the interface, and the enable terminal is electrically connected to the output terminal of the flip-flop through a third logic NOT gate.

[0031] Preferably, when the trigger outputs a high level, the third and fourth electronic switches are turned on, the fifth and sixth electronic switches are turned off, and the first communication interface chip connects to the interface.

[0032] When the trigger outputs a low level, the fifth and sixth electronic switches are turned on, the third and fourth electronic switches are turned off, and the second communication interface chip connects the interface.

[0033] Preferably, the processor is electrically connected to the input terminal of the trigger and is used to control the output of the trigger.

[0034] Compared to existing technologies, the serial port multiplexing circuit provided in this invention compares the access voltage of the external device with the reference voltage through a comparison unit, outputs a comparison signal, and then the control unit outputs a control signal according to the comparison signal. Finally, the switching unit selects to connect to the first communication interface chip or the second communication interface chip according to the control signal, thereby realizing port multiplexing and reducing the size of the product. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a module of one embodiment of the serial port multiplexing circuit of the present invention.

[0036] Figure 2 This is a flowchart illustrating another embodiment of the serial port multiplexing circuit of the present invention.

[0037] Explanation of main component symbols

[0038] Serial port multiplexing circuit 10

[0039] Interface 100

[0040] Comparison Unit 101

[0041] Control Unit 102

[0042] Switch 103

[0043] First switch group 1031

[0044] Second switch group 1032

[0045] First electronic switch ~ Sixth electronic switch K1 ~ K6

[0046] Control subunit 1011

[0047] First NOT gate ~ Third NOT gate NOT1 ~ NOT3

[0048] First resistor ~ Second resistor R1 ~ R2

[0049] First capacitor ~ Second capacitor C1 ~ C2

[0050] Diode D1

[0051] First communication interface chip ~ Second communication interface chip U1 ~ U2

[0052] Processor U3

[0053] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0054] See Figure 1 As shown, Figure 1 This is a schematic diagram of one embodiment of the serial port multiplexing circuit 10 of the present invention. In this embodiment, the serial port multiplexing circuit device 10 contains different communication serial port chips, which can connect to different types of external devices, such as RS485 serial port devices or RS232 serial port devices. According to the different types of external devices, the corresponding communication serial port chip is selected to realize data transmission.

[0055] In this embodiment, the serial port multiplexing circuit device 10 includes an interface 100, a comparison unit 101, a control unit 102, a switching unit 103, a first communication interface chip U1, a second communication interface chip U2, and a processor U3. The interface 100 is used to connect to external devices. In this embodiment, RS485 and RS232 serial port devices are used as examples of external devices, but this is not a limitation. The comparison unit 101 is electrically connected to the interface 100 and is used to compare the access voltage of the external device with a reference voltage, outputting a comparison signal. The control unit 102 is electrically connected to the comparison unit 101 and is used to output a control signal based on the comparison signal. The switching unit 103 is electrically connected between the interface 100 and the first communication interface chip U1 and the second communication interface chip U2, and is used to select between connecting to the first communication interface chip U1 or the second communication interface chip U2 based on the control signal. Specifically, when the external device is a first type of device, the comparison unit 101 outputs a first comparison signal, and the control unit 102 outputs a first control signal based on the first comparison signal to control the switch unit 103 to connect the interface 100 and the first communication interface chip U1. When the external device is a second type of device, the comparison unit 101 outputs a second comparison signal, and the control unit 102 outputs a second control signal based on the second comparison signal to control the switch unit 103 to connect the interface and the second communication interface chip, thereby enabling a single interface to meet the data transmission needs of different types of devices.

[0056] See Figure 2 As shown, Figure 2 This is a schematic diagram of a specific embodiment of the serial port multiplexing circuit 10 of the present invention. In this embodiment, the serial port multiplexing circuit device 10 includes an interface 100, a comparison unit 101, a control unit 102, a switching unit 103, a first communication interface chip U1, a second communication interface chip U2, and a processor U3. Its working principle has been explained in the above embodiments and will not be repeated here.

[0057] In this embodiment, interface 100 includes a receive pin Rx, a transmit pin Tx, and a ground terminal. The non-inverting input terminal of the comparator unit 101 is electrically connected to the transmit pin Tx of interface 100, and the inverting input terminal is electrically connected to the reference voltage Vref. The value of the reference voltage Vref is determined by the type of device and the type of device. Taking RS485 serial port devices and RS232 serial port devices as examples, the input voltage of RS485 serial port devices is about 3.3V, while that of RS232 serial port devices is about 5V, and the value of the reference voltage Vref is between 3.3V and 5V. The control unit 102 includes a first electronic switch K1, which includes a first terminal, a second terminal, and an enable terminal. The first terminal of the first electronic switch K1 is electrically connected to the output terminal of the comparator unit 101. A first resistor R1 has one end electrically connected to the enable terminal of the first electronic switch K1 and the other end electrically connected to the power supply VDD. A second electronic switch K2 includes a first terminal, a second terminal, and an enable terminal. The second terminal of the second electronic switch K2 is grounded, and the first terminal of the second electronic switch K2 is electrically connected to the enable terminal of the first electronic switch K1. A control subunit 1021 is electrically connected between the output terminal of the comparator unit 101 and the enable terminal of the second electronic switch K2. A trigger J1 has its input terminal electrically connected to the first terminal of the first electronic switch K1 and its output terminal electrically connected to the switch unit 103.

[0058] In this embodiment, by default, the first electronic switch K1 is in the ON state. When the external device is a first type of device, i.e., an RS485 device, the comparison unit 101 outputs a high-level signal, the first electronic switch K1 outputs a high-level signal to the input terminal of the trigger J1, and the trigger outputs a high-level signal to the switch unit 103 to connect the interface 100 with the first communication interface chip U1. When the external device is a second type of device, i.e., an RS232 device, the comparison unit 101 outputs a low-level signal, the first electronic switch K1 outputs a low-level signal to the input terminal of the trigger J1, and the trigger outputs a low-level signal to the switch unit 103 to connect the interface 100 with the second communication interface chip U2.

[0059] In this embodiment, when the first type of device or the second type of device is transmitting data, the control subunit 1021 maintains a high level, enabling the second electronic switch K2, which is then grounded. When the second electronic switch K2 is grounded, the enable terminal of the first electronic switch K1 is grounded, and the first electronic switch K1 is open, causing the trigger J1 to maintain its current output state. Specifically, the control subunit 1021 includes: a first capacitor C1, one end of which is electrically connected to the output terminal of the comparator unit 101; a first NOT gate NOT1, the input terminal of which is electrically connected to the other end of the first capacitor C1; a second NOT gate NOT2, the input terminal of which is electrically connected to the other end of the first NOT gate NOT1; a diode D1, the anode of which is electrically connected to the output terminal of the second NOT gate NOT2; a second capacitor C2, one end of which is electrically connected to the cathode of the diode D1, and the other end is grounded; and a second resistor R2, one end of which is electrically connected to the cathode of the diode D1, and the other end is grounded. When the first type of device or the second type of device is transmitting data, the comparison unit outputs a high-low level signal, the first capacitor C1 discharges to enable the second electronic switch K2, and the second electronic switch K2 is grounded; when the second electronic switch K2 is grounded, the enable terminal of the first electronic switch K1 is grounded, the first electronic switch K1 is open, so that the trigger J1 maintains the current output state, that is, the trigger J1 maintains the current level state.

[0060] In this embodiment, the switch unit 103 includes a first switch group 1031, which includes a third electronic switch K3 and a fourth electronic switch K4. Both the third and fourth electronic switches K3 and K4 include a first terminal, a second terminal, and an enable terminal. The first terminal of each switch is electrically connected to the first communication interface chip U1, the second terminal is electrically connected to the interface 100, and the enable terminal is electrically connected to the output terminal of the flip-flop J1. Specifically, the first terminal of the third electronic switch K3 is electrically connected to the receive pin Rx of the interface 100, and the first terminal of the third electronic switch K4 is electrically connected to the transmit pin Tx of the interface 100. The second switch group 1032 includes a fifth electronic switch K5 and a sixth electronic switch K6. Both the fifth and sixth electronic switches K5 and K6 include a first terminal, a second terminal, and an enable terminal. The first terminal of each switch is electrically connected to the second communication interface chip U2, the second terminal is electrically connected to the interface 100, and the enable terminal is electrically connected to the output terminal of the flip-flop J1 through a third NOT gate NOT3. Specifically, the first terminal of the fifth electronic switch K5 is electrically connected to the receive pin Rx of interface 100, and the first terminal of the sixth electronic switch K6 is electrically connected to the transmit pin Tx of interface 100. When the trigger J1 outputs a high level, the third electronic switch K3 and the fourth electronic switch K4 are turned on, the fifth electronic switch K5 and the sixth electronic switch K6 are turned off, and the first communication interface chip U1 connects to interface 100; when the trigger J1 outputs a low level, the fifth electronic switch K5 and the sixth electronic switch K6 are turned on, the third electronic switch K3 and the fourth electronic switch K4 are turned off, and the second communication interface chip U2 connects to interface 100.

[0061] In this embodiment, the processor U3 is also electrically connected to the input terminal of the flip-flop J1 to control the output of the flip-flop. That is, the user can control the output of the flip-flop D1 through the processor U3, thereby controlling the on / off state of the switching unit 103.

[0062] Those skilled in the art should recognize that the above embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Any appropriate changes and modifications made to the above embodiments within the essential spirit and scope of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A serial port multiplexing circuit, comprising a first communication interface chip and a second communication interface chip, wherein the first communication interface chip and the second communication interface chip are electrically connected to a processor, characterized in that, Also includes: An interface for connecting to external devices; A comparison unit, electrically connected to the interface, is used to compare the input voltage of the external device with the reference voltage and output a comparison signal. A control unit, electrically connected to the comparison unit, is used to output a control signal based on the comparison signal; A switching unit is electrically connected between the interface and the first communication interface chip and the second communication interface chip, and is used to select the first communication interface chip or the second communication interface chip according to the control signal; The control unit includes: A first electronic switch includes a first terminal, a second terminal, and an enable terminal, wherein the first terminal of the first electronic switch is electrically connected to the output terminal of the comparison unit. The first resistor has one end electrically connected to the enable terminal of the first electronic switch and the other end electrically connected to the power supply. The second electronic switch includes a first terminal, a second terminal, and an enable terminal. The second terminal of the second electronic switch is grounded, and the first terminal of the second electronic switch is electrically connected to the enable terminal of the first electronic switch. The control subunit is electrically connected between the output terminal of the comparison unit and the enable terminal of the second electronic switch; The trigger has its input terminal electrically connected to the first terminal of the first electronic switch and its output terminal electrically connected to the switch unit.

2. The serial port multiplexing circuit as described in claim 1, characterized in that: When the external device is a first type of device, the comparison unit outputs a first comparison signal, and the control unit outputs a first control signal according to the first comparison signal to control the switching unit to connect the interface with the first communication interface chip; When the external device is a second type of device, the comparison unit outputs a second comparison signal, and the control unit outputs a second control signal according to the second comparison signal to control the switching unit to connect the interface and the second communication interface chip.

3. The serial port multiplexing circuit as described in claim 1, characterized in that: When the first type of device or the second type of device is transmitting data, the control subunit maintains a high level, enabling the second electronic switch, which is then grounded. When the second electronic switch is grounded, the enable terminal of the first electronic switch is grounded, the first electronic switch is turned off, and the trigger maintains its current output state.

4. The serial port multiplexing circuit as described in claim 3, characterized in that, The control subunit includes: The first capacitor has one end electrically connected to the output terminal of the comparison unit; The first logic NOT gate has its input terminal electrically connected to the other end of the first capacitor; The second NOT gate has its input terminal electrically connected to the other end of the first NOT gate; The diode has its anode connected to the output of the second NOT gate. The second capacitor has one end electrically connected to the cathode of the diode and the other end grounded. The second resistor has one end electrically connected to the cathode of the diode and the other end grounded.

5. The serial port multiplexing circuit as described in claim 4, characterized in that: When the first type of device or the second type of device is transmitting data, the comparison unit outputs a high-low level signal, the first capacitor discharges to enable the second electronic switch, and the second electronic switch is grounded. When the second electronic switch is grounded, the enable terminal of the first electronic switch is grounded, the first electronic switch is turned off, and the trigger maintains its current output state.

6. The serial port multiplexing circuit as described in claim 1, characterized in that, The switching unit includes: The first switch group includes a third electronic switch and a fourth electronic switch. The third electronic switch and the fourth electronic switch each include a first terminal, a second terminal and an enable terminal. The first terminal of the third electronic switch and the fourth electronic switch are electrically connected to the first communication interface chip, the second terminal is electrically connected to the interface, and the enable terminal is electrically connected to the output terminal of the trigger. The second switch group includes a fifth electronic switch and a sixth electronic switch. The fifth electronic switch and the sixth electronic switch each include a first terminal, a second terminal and an enable terminal. The first terminal of the fifth electronic switch and the sixth electronic switch are electrically connected to the second communication interface chip, the second terminal is electrically connected to the interface, and the enable terminal is electrically connected to the output terminal of the flip-flop through a third logic NOT gate.

7. The serial port multiplexing circuit as described in claim 6, characterized in that: When the trigger outputs a high level, the third and fourth electronic switches are turned on, the fifth and sixth electronic switches are turned off, and the first communication interface chip connects to the interface. When the trigger outputs a low level, the fifth and sixth electronic switches are turned on, the third and fourth electronic switches are turned off, and the second communication interface chip connects the interface.

8. The serial port multiplexing circuit as described in claim 1, characterized in that, The processor is electrically connected to the input terminal of the trigger and is used to control the output of the trigger.

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