Method and apparatus for stream data management of reconfigurable processor multi-port cache

Abstract

This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache, relating to the field of large-scale integrated circuit technology. The method includes: when processing a cell array accessing the cache, if a cache miss occurs, evicting a cache line with a target bit set to a first preset value using a polling arbitration method, and setting the target bit of subsequent cache lines entering the cache to the first preset value; when processing a cell array accessing the cache, if a cache hit occurs, setting the target bit of the currently hit cache line to a second preset value based on the interval between the previously hit cache line and the currently hit cache line. This invention can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, increasing the memory access bandwidth of the PEA, mitigating potential conflicts and misses caused by set-associations, and reducing the miss rate for streaming data.

Description

Technical Field

[0001] This invention relates to the field of large-scale integrated circuit technology, and in particular to a streaming data management method and apparatus for a reconfigurable processor multi-port cache. Background Technology

[0002] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] Computers and microprocessors based on the von Neumann architecture have achieved tremendous success in the past because processors characterized by instruction-driven execution typically offer high flexibility. Currently, instruction-driven processors generally include general-purpose processors (GPPs) and embedded processors. However, precisely because of this instruction-driven execution method, and limited computing units and memory bandwidth, the performance and power consumption of such processors are far from ideal, failing to meet the ever-increasing demands of application computing. For example, in a classic MIPS architecture general-purpose processor, executing a single instruction involves five steps: instruction fetch, decode, register access, execution, and data write-back; of these, only the "execution" step is actually the required operation. Application-Specific Integrated Circuits (ASICs), which emerged in the 1990s, employ a data-driven computing architecture. They do not require an instruction set and can be designed with optimal data paths for different applications, achieving excellent performance and low power consumption. However, ASICs also have fatal flaws because their flexibility and scalability are extremely poor, making them unsuitable for ever-evolving application scenarios and functions. As manufacturing processes advance towards 7nm and even 5nm, the cost of manufacturing application-specific integrated circuits (ASICs) has become extremely high, and their long design cycles have also constrained their further development.

[0004] Against this backdrop, processors with coarse-grained reconfigurable architectures (CGRA) are showing broad application prospects due to their coarser computational granularity (referring to the data bit width of the arithmetic units in the data path of the reconfigurable processor; generally, granularity greater than or equal to 4 bits is considered coarse-grained). Although their flexibility is somewhat reduced, they require less configuration information and reconfigure the data path faster. Similar to many traditional spatially parallel computing architectures, CGRA's memory access behavior also exhibits a distinct streaming characteristic; that is, CGRA typically accesses a contiguous address space. Furthermore, CGRA has multiple Processing Element Arrays (PEAs), each with varying degrees of streaming memory access behavior. How to manage this streaming data becomes a key focus of CGRA on-chip cache optimization. Summary of the Invention

[0005] This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache, which can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, improving the memory access bandwidth of PEA, mitigating the conflict and missing data caused by set-associations, and reducing the missing rate for streaming data.

[0006] In a first aspect, embodiments of the present invention provide a streaming data management method for a reconfigurable processor multi-port cache, the method comprising:

[0007] When processing the cell array access cache, if a cache miss occurs, the cache line with the target bit set to the first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value.

[0008] When processing the cell array access cache, if a cache hit occurs, the target bit of the cache line that was hit in the previous hit is set to the second preset value based on the interval between the cache line that was hit in the previous hit and the cache line that was hit in the current hit.

[0009] In a second aspect, embodiments of the present invention also provide a streaming data management device for a reconfigurable processor multi-port cache, the device comprising:

[0010] The eviction and insertion module is used to evict cache lines with a target bit of a first preset value by polling arbitration when a cache miss occurs during the processing of cell array access cache, and set the target bit of subsequent cache lines entering the cache to the first preset value.

[0011] The boosting module is used to, when processing the cell array access cache, if a cache hit occurs, set the target bit of the cache line hit in the current hit to a second preset value based on the interval between the cache line hit in the previous hit and the cache line hit in the current hit.

[0012] Thirdly, embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described streaming data management method for reconfigurable processor multi-port cache.

[0013] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that performs the above-described streaming data management method for a reconfigurable processor multi-port cache.

[0014] The embodiments of the present invention bring the following beneficial effects: The embodiments of the present invention provide a streaming data management method and apparatus for a reconfigurable processor multi-port cache. The method includes: when processing a unit array accessing the cache, if a cache miss occurs, a cache line with a target bit of a first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value; when processing a unit array accessing the cache, if a cache hit occurs, the target bit of the cache line that is hit this time is set to a second preset value based on the interval between the previously hit cache line and the currently hit cache line. The embodiments of the present invention set the target bit of the newly entered cache line to the first preset value, and then, when a memory access miss occurs, evicts the cache line with the target bit of the first preset value by polling arbitration. This can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory and improving the memory access bandwidth of the PEA. In addition, the embodiments of the present invention can also modify the target bit of the hit cache line based on the relationship between the previously hit cache line and the currently hit cache line, setting the target bit to the second preset value, mitigating the collision misses that may be caused by set-associative, and reducing the miss rate for streaming data.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A flowchart of a streaming data management method for a reconfigurable processor multi-port cache provided in an embodiment of the present invention;

[0019] Figure 2 A structural block diagram of a streaming data management device with a reconfigurable processor multi-port cache provided in an embodiment of the present invention;

[0020] Figure 3 A block diagram of another reconfigurable processor multi-port cache streaming data management device provided in an embodiment of the present invention;

[0021] Figure 4 A block diagram of another reconfigurable processor multi-port cache streaming data management device provided in an embodiment of the present invention;

[0022] Figure 5 This is a block diagram of the partitioning module structure provided in an embodiment of the present invention;

[0023] Figure 6 Another block diagram of the module structure provided in this embodiment of the invention;

[0024] Figure 7 A schematic diagram of the system composition structure of an electronic device provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the PEA structure provided in an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of the overall structure of the multi-port cache provided in an embodiment of the present invention;

[0027] Figure 10 A flowchart illustrating the implementation of the streaming data management method for a reconfigurable processor multi-port cache provided in this embodiment of the invention;

[0028] Figure 11 This is a schematic diagram of the prefetch controller structure provided in an embodiment of the present invention;

[0029] Figure 12 This is a schematic diagram of the initial division provided in an embodiment of the present invention;

[0030] Figure 13 This is a schematic diagram of the partitioning after the missing parts are provided in an embodiment of the present invention;

[0031] Figure 14 This is a schematic diagram of the merged cache space provided in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] The reconfigurable architecture processor has a hierarchical structure containing multiple processing elements (PEs) and multiple processing element arrays (PEAs); its on-chip cache structure has a multi-port structure to support simultaneous memory access by multiple PEAs.

[0034] Based on the characteristics of CGRA on-chip cache, this invention provides a streaming data management method and apparatus for reconfigurable processor multi-port cache. It designs an efficient data management scheme for the on-chip cache, including how to evict useless data, move data that may be needed in the future, and rationally allocate cache space for each array to avoid capacity shortages. These three points correspond to replacement policy, prefetching, and cache partitioning, respectively.

[0035] To facilitate understanding of this embodiment, a streaming data management method for a reconfigurable processor multi-port cache disclosed in this embodiment of the invention will first be described in detail.

[0036] First, the PEA structure will be explained. The core unit involved in computation in CGRA is the processing unit array (PEA), whose structure is as follows: Figure 8 As shown.

[0037] exist Figure 8The PEA module integrates an 8×8 processing unit array, a global register for the processing unit, a coprocessor interface, a data controller, shared memory, a PEA controller, and a context controller. Some registers in the global register control memory access behavior; specifically, registers 33, 34, 35, and 36 store the starting address and length for retrieving configuration information, and the starting address and length for retrieving data, respectively.

[0038] See Figure 9 The diagram shows the overall structure of the multi-port cache. The processing unit array interface receives memory access requests from 8 PEAs and temporarily stores them in First In First Out (FIFO) memory. The memory access controller receives the request and accesses either the cache space or the buffer space according to the configuration. If the buffer is accessed, the data banks are accessed directly. If the cache is accessed, an additional process of accessing the flag banks is added. The prefetch controller initiates a prefetch request for off-chip data based on the PEA request and cache hit or miss information. The write buffer temporarily stores write data that does not fall into the buffer space. The master interface arbitrates the requests from the write buffer and the prefetch controller and accesses the off-chip main memory DRAM. The slave interface moves the off-chip data to the buffer space. The partition controller allocates cache space for each PEA. The replacement controller determines which path of data to replace when a miss occurs. The memory interface arbitrates all the above requests for accessing on-chip memory and sends these requests to the corresponding memory banks. This patent mainly introduces a streaming data management scheme for multi-port caching, specifically involving the implementation of three strategies: replacement strategy, prefetch strategy, and partitioning strategy. The corresponding hardware modules are the replacement controller, prefetch controller, and partitioning controller (the part with the bold border).

[0039] Data Banks are used to store cache line data. Flag Banks store information that marks a cache line (including the cache line's address tag and the cache line's validity bit). The cache can access the entire 32-bit address space because these flags are stored in the Flag Banks.

[0040] This invention provides a streaming data management method for a reconfigurable processor multi-port cache, which is based on the above-mentioned PEA structure and the overall structure of the multi-port cache.

[0041] See Figure 1 The flowchart shown illustrates a streaming data management method for a reconfigurable processor multi-port cache, which includes the following steps:

[0042] In step S102, when processing the cell array access cache, if a cache miss occurs, the cache line with the target bit set to the first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value.

[0043] In this embodiment of the invention, when processing streaming data accessed by the cell array cache, in the event of a cache miss, cache lines are evicted through a round-robin arbitration method, with the cache line whose target bit is a first preset value being selected as the cache line to be evicted. The first preset value is used to determine that a cache line is invalid; that is, if a cache line will no longer be used subsequently, its target bit can be set to the first preset value. Cache lines entering the cache subsequently refer to newly entered cache lines.

[0044] It should be noted that, in this embodiment of the invention, the target bit can be the Most Recently Used (MRU) bit. The first preset value can be 0.

[0045] Based on the streaming characteristics of CGRA memory access, this method can optimize the replacement strategy of multi-port caches, namely, a pseudo-least recently used insertion policy based on MRU bits (PLIPM). See also Figure 10The flowchart shown illustrates the implementation of a streaming data management method for a reconfigurable processor multi-port cache. This replacement policy modifies the insertion strategy of the MRU replacement policy, setting the MRU bit of newly entering cache lines to 0 instead of 1. This means the eviction policy cannot simply evict cache lines with an MRU bit of 0, because if a newly entering cache line with an MRU bit of 0 is immediately evicted, it would cause cache thrashing. Therefore, the eviction policy uses a round-robin arbitration method to evict cache lines with an MRU bit of 0, thus avoiding this situation.

[0046] It should be noted that in practical implementation, for example, if four cache lines numbered 3, 2, 1, and 0 all have an MRU of 0, then one line should be arbitrated and evicted. Arbitration in the order of 3→2→1→0→3→2→1→0… is called round-robin arbitration. Round-robin arbitration avoids evicting the same cache line every time.

[0047] In step S104, when processing the cell array access cache, if a hit occurs, the target bit of the cache line that was hit in the current hit is set to the second preset value based on the interval between the cache line that was hit in the previous hit and the cache line that was hit in the current hit.

[0048] In this embodiment of the invention, when processing streaming data accessed by the cell array cache, if a cache hit is successful, and there is an interval between the previously hit cache line and the currently hit cache line, the target bit of the currently hit cache line is set to a second preset value. The second preset value is used to determine that the cache line is valid; that is, if one wants to continue using a certain cache line later, the target bit of that cache line can be set to the second preset value.

[0049] It should be noted that, in this embodiment of the invention, the second preset value can be 1.

[0050] In a reconfigurable processor, the cache line size is 32B×8, meaning each cache line contains eight 32B data items. Under these conditions, discussing replacement policy selection using a simple fully associative cache is inappropriate: firstly, set-associativity introduces potential conflict-based missing data; secondly, increasing the cache line size can cause the replacement policy to incorrectly promote certain cache lines under streaming access. Therefore, in addition to modifying the insertion and eviction policies, the promotion policy of the PLIPM algorithm was also modified, so that the MRU bit is only set to 1 after a certain number of cache line accesses.

[0051] This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache. The method includes: when the processing unit array accesses the cache, if a cache miss occurs, a cache line with a target bit of a first preset value is evicted through a round-robin arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value; when the processing unit array accesses the cache, if a cache hit occurs, the target bit of the currently hit cache line is set to a second preset value based on the interval between the previously hit cache line and the currently hit cache line. This invention sets the target bit of newly entering cache lines to the first preset value, and then, when a memory access miss occurs, evicts cache lines with a target bit of the first preset value through a round-robin arbitration. This effectively reduces the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory and improving the memory access bandwidth of the PEA. Furthermore, this invention can also modify the target bit of the hit cache line based on the relationship between the previously hit cache line and the currently hit cache line, setting the target bit to the second preset value, mitigating potential conflicts and misses caused by set-associative caches, and reducing the miss rate for streaming data.

[0052] In one embodiment, based on the interval between the previously hit cache line and the currently hit cache line, the target bit of the currently hit cache line is set to a second preset value, which can be performed according to the following steps:

[0053] Determine whether the cache line hit in the previous hit is the same as the cache line hit in the current hit; if not, set the target bit of the cache line hit in the current hit to the second preset value; if yes, keep the target bit value of the cache line hit in the current hit unchanged.

[0054] In an embodiment of the present invention, see Figure 10 The flowchart shown illustrates the implementation of a streaming data management method for a reconfigurable processor multi-port cache. By determining whether the cache line hit in the previous instance is the same as the cache line hit in the current instance, the method can determine whether there is a gap between the cache line hit in the previous instance and the cache line hit in the current instance.

[0055] In one embodiment, before setting the target bit of subsequent cache lines to the first preset value, the following steps may also be performed:

[0056] Obtain missing address information and pre-stored information of the processing unit array; the pre-stored information of the processing unit array includes the starting address information and length information of the access sequence to be initiated by the processing unit array; if the missing address information is consistent with the starting address information, the state machine is used to obtain off-chip data based on the length information; the streaming data to be subsequently entered into the cache is determined based on the off-chip data.

[0057] In this embodiment of the invention, when processing the cell array access cache, missing address information is obtained in the case of a miss. In the CGRA, some special registers store the starting address and length of the access sequence that the PEA will initiate, which greatly facilitates data prefetching: we do not need a special mechanism to detect streaming access behavior; we only need to make good use of the values ​​of these special registers for data prefetching. See also Figure 8 In the diagram, registers 33, 34, 35, and 36 store the starting address and length for PEA configuration information retrieval, and the starting address and length for data retrieval, respectively. Since configuration retrieval and data retrieval do not occur simultaneously, their register information is merged, and the starting address and length information are connected to the top layer of the PEA as input signals to the prefetch unit in the on-chip cache. The prefetch unit receives these two signals and stores them in the corresponding registers. The memory access controller notifies the prefetch unit which address is missing. If the missing address matches the starting address in the register, prefetching begins. The prefetch length is the length value stored in the corresponding register. If multiple addresses match, a polling arbitrator selects one for prefetching. Figure 11 The block diagram of the prefetch unit is given, where Base represents the starting address, Len represents the sequence length, and State represents the state machine state.

[0058] In one embodiment, using a state machine to obtain off-chip data based on length information can be performed according to the following steps:

[0059] The state of the control state machine includes one or more of the following states: idle state, start prefetch state, flag access state, replacement cell access state, write operation state, data fetch state, wait state, or flag modification state; external data is obtained based on the state and length information of the state machine.

[0060] In this embodiment of the invention, the state machine of the prefetch unit controls the entire prefetch process: Specifically, IDLE can be used to represent the idle state; START represents the start prefetch state, in which a request is initiated to the partitioning unit to obtain information about which paths the corresponding cache resources are; FLAG READ represents the flag access state, in which an access to the flag memory is initiated to obtain the valid information of the cache line; REPL represents the replacement unit access state, in which an access to the replacement unit is initiated to know which path to replace; FLAG INVALID represents the write operation state, in which a write operation is initiated to the flag memory, writing the valid value of the cache line to be replaced to 0, making this cache line invalid and avoiding errors in reading data during the process; FETCH represents the data fetch state, in which an access to the off-chip DDR is initiated to retrieve the desired data; WAIT represents the wait state, in which the state of waiting for data to be moved from off-chip to on-chip; FLAG VALID represents the flag modification state, in which the valid value of the cache line is set to 1, making this cache line valid. If the number of prefetched cache lines equals the value of the length register, return to the IDLE state; otherwise, return to the FLAG READ state and proceed to the next cache line.

[0061] In one embodiment, the following steps may also be performed:

[0062] The number of memory access misses in the target processing unit array is counted using a counter; based on the number of memory access misses and the number of memory blocks in the target processing unit array, additional memory blocks are allocated to the target processing unit.

[0063] In this embodiment of the invention, a greedy algorithm can be used when allocating cache space for PEAs: each PEA in the cache has a miss counter, and the corresponding counter is incremented by 1 when a memory access miss occurs in a PEA. Each processing unit array includes multiple memory banks, and additional memory banks are allocated to the target processing unit by analyzing the quantitative relationship between the number of memory access misses and the number of memory banks in the target processing unit array.

[0064] It should be noted that the processing unit array that is currently performing storage quantity analysis or allocation is considered the target processing unit array.

[0065] It should also be noted that the storage in the embodiments of the present invention may include a data storage and an access flag storage.

[0066] In one embodiment, allocating additional memory to the target processing unit based on the number of memory access misses and the number of memory blocks in the target processing unit array can be performed according to the following steps:

[0067] When the number of memory access misses accumulates to a target multiple of the number of memory blocks, a memory block is allocated to the target processing unit.

[0068] In this embodiment of the invention, when the value of the missing counter accumulates to a value equal to four times the number of memory blocks in the region, if there are any remaining unallocated memory blocks, then one memory block is allocated to it, and the missing counter is reset to zero. The target multiple can be set according to actual needs, and this embodiment of the invention does not impose specific limitations on it.

[0069] In practical implementation, the example is a cache of 16 memory banks accessed by 4 PEAs.

[0070] See Figure 12 The diagram shown illustrates the initial partitioning. After the initial partitioning, each of the four PEAs has its own cache space. In addition, four banks are reserved and not allocated to any PEA.

[0071] See Figure 13 The diagram illustrates the partitioning process after a missing cache entry. After a certain period of operation, if the number of missing or conflicting cache entries in PEA1 exceeds four times the number of banks allocated to it, then one reserved cache channel will be allocated to PEA1, and the missing counter for PEA1 will be reset to zero. The cache allocation scheme for other PEAs follows the same principle. Following this partitioning strategy, PEA3 through PEA0 will have 4, 4, 5, and 3 banks respectively.

[0072] In one embodiment, the following steps may also be performed:

[0073] If the starting address information of the first processing unit array and the second processing unit array is the same, the cache space of the first processing unit array and the cache space of the second processing unit array are merged; the access flag memory of the first processing unit array and the second processing unit array is controlled based on the preset priority information.

[0074] In this embodiment of the invention, in order to support the multi-port feature of on-chip cache while reducing hardware storage overhead, PEAs can only partially share the cache and not share the entire cache space. Partial sharing occurs when the prefetch unit detects that the starting addresses of two adjacent PEAs are the same. Priority information can be preset, and this embodiment of the invention does not impose specific limitations on it.

[0075] In practical implementation, this is illustrated using a cache with 4 PEAs accessing 16 memory banks. See [link / reference] Figure 14The diagram illustrates the merged cache space. The partitioning controller detects data sharing between PEA 3 and PEA 2 and merges their cache spaces. This sharing information is transmitted from the prefetch module: adjacent PEAs are considered to share data if their prefetch start addresses are the same. When PEA 3 and PEA 2 share the same cache space, since the flag memory is not copied, one of the PEAs must delay accessing the flag memory by one clock cycle. The priority for accessing the flag memory is higher for PEAs with larger sequence numbers, e.g., PEA3 > PEA 2.

[0076] This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache. The method primarily designs a replacement strategy, a prefetch strategy, and a cache partitioning strategy for multi-port on-chip caches. The replacement strategy is triggered each time the cache is accessed; the prefetch strategy is triggered when a cache miss occurs; and the partitioning strategy is triggered when the number of misses reaches a certain value. This method, based on a pseudo-least recently used insertion strategy using the most recently used bit, can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory and improving the memory access bandwidth of the PEA (Peak Cache Area). Prefetching using the value of the CGRA (Current Cache Retrieval Register) special register allows for the early retrieval of valid data that will be needed soon. The partitioning strategy based on a greedy algorithm can effectively partition the cache space and reduce the miss rate.

[0077] This invention also provides a streaming data management device for a reconfigurable processor multi-port cache, as described in the following embodiments. Since the principle by which this device solves the problem is similar to the streaming data management method for a reconfigurable processor multi-port cache, its implementation can be found in the implementation of the streaming data management method for a reconfigurable processor multi-port cache; repeated details will not be elaborated further. See also... Figure 2 The diagram shown illustrates a streaming data management device for a reconfigurable processor multi-port cache. The device includes:

[0078] The eviction and insertion module 21 is used to eviction the cache line with the target bit set to the first preset value by polling arbitration when a cache miss occurs during the processing of the cell array access cache, and to set the target bit of the cache line that enters the cache afterward to the first preset value; the promotion module 22 is used to set the target bit of the cache line that is hit during the processing of the cell array access cache if a cache hit occurs, based on the interval between the cache line that was hit last time and the cache line that was hit this time.

[0079] In one embodiment, the lifting module is specifically used for:

[0080] Determine whether the cache line hit in the previous hit is the same as the cache line hit in the current hit; if not, set the target bit of the cache line hit in the current hit to the second preset value; if yes, keep the target bit value of the cache line hit in the current hit unchanged.

[0081] See Figure 3 The diagram shows another reconfigurable processor multi-port cache streaming data management device, which also includes a prefetch module 23 for:

[0082] Obtain missing address information and pre-stored information of the processing unit array; the pre-stored information of the processing unit array includes the starting address information and length information of the access sequence to be initiated by the processing unit array; if the missing address information is consistent with the starting address information, the state machine is used to obtain off-chip data based on the length information; the streaming data to be subsequently entered into the cache is determined based on the off-chip data.

[0083] In one embodiment, the prefetch module is specifically used for:

[0084] The state of the control state machine includes one or more of the following states: idle state, start prefetch state, flag access state, replacement cell access state, write operation state, data fetch state, wait state, or flag modification state; external data is obtained based on the state and length information of the state machine.

[0085] In one embodiment, see Figure 4 The diagram shows another reconfigurable processor multi-port cache streaming data management device, which also includes a partitioning module 24. (See attached diagram.) Figure 5 The partitioning module shown in the diagram includes: a counting unit 51, used to count the number of memory access misses in the target processing unit array using a counter; and an allocation unit 52, used to allocate new memory to the target processing unit based on the number of memory access misses and the number of memory blocks in the target processing unit array.

[0086] In one embodiment, the allocation unit is specifically used for:

[0087] When the number of memory access misses accumulates to a target multiple of the number of memory blocks, a memory block is allocated to the target processing unit.

[0088] In one embodiment, see Figure 6 Another block diagram of the partitioning module structure shown includes a shared unit 53, used for:

[0089] If the starting address information of the first processing unit array and the second processing unit array is the same, the cache space of the first processing unit array and the cache space of the second processing unit array are merged; the access flag memory of the first processing unit array and the second processing unit array is controlled based on the preset priority information.

[0090] Based on the same inventive concept, this invention also provides an electronic device embodiment for implementing all or part of the above-described streaming data management method for reconfigurable processor multi-port cache. This electronic device specifically includes the following:

[0091] The device comprises a processor, memory, a communications interface, and a bus; wherein the processor, memory, and communications interface communicate with each other via the bus; the communications interface is used to realize information transmission between related devices; the electronic device can be a desktop computer, tablet computer, or mobile terminal, etc., and this embodiment is not limited to these. In this embodiment, the electronic device can be implemented with reference to the embodiments for implementing the above-mentioned streaming data management method for reconfigurable processor multi-port cache and the embodiments for implementing the above-mentioned streaming data management device for reconfigurable processor multi-port cache, the contents of which are incorporated herein by reference, and repeated details will not be described again.

[0092] Figure 7 This is a schematic diagram of the system composition structure of an electronic device provided in an embodiment of the present invention. Figure 7 As shown, the electronic device 70 may include a processor 701 and a memory 702; the memory 702 is coupled to the processor 701. It is worth noting that... Figure 7 This is an example; other types of structures can also be used to supplement or replace this structure to achieve telecommunications functions or other functions.

[0093] In one embodiment, the functionality of the streaming data management method for the reconfigurable processor multi-port cache can be integrated into the processor 701. The processor 701 can be configured to perform the following controls:

[0094] When processing the cell array access cache, if a cache miss occurs, the cache line with the target bit set to the first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value; when processing the cell array access cache, if a cache hit occurs, the target bit of the cache line that is hit this time is set to the second preset value based on the interval between the previously hit cache line and the currently hit cache line.

[0095] As can be seen from the above, the electronic device provided in the embodiments of the present invention can effectively reduce the probability of cache jitter under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, improving the memory access bandwidth of PEA, alleviating the conflict and missing data caused by set-association, and reducing the missing rate for streaming data.

[0096] In another embodiment, the streaming data management device for the reconfigurable processor multi-port cache can be configured separately from the processor 701. For example, the streaming data management device for the reconfigurable processor multi-port cache can be configured as a chip connected to the processor 701, and the function of the streaming data management method for the reconfigurable processor multi-port cache can be realized through the control of the processor.

[0097] like Figure 7 As shown, the electronic device 70 may further include: a communication module 703, an input unit 704, an audio processing unit 705, a display 706, and a power supply 707. It is worth noting that the electronic device 70 does not necessarily need to include these components. Figure 7 All components shown; in addition, the electronic device 70 may also include Figure 7 For components not shown, please refer to existing technologies.

[0098] like Figure 7 As shown, processor 701, sometimes also referred to as controller or operation control, may include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of various components of electronic device 70.

[0099] The memory 702 may be, for example, one or more of a cache, flash memory, hard drive, removable media, volatile memory, non-volatile memory, or other suitable device. It may store the aforementioned failure-related information, and also store a program for executing that information. The processor 701 may execute the program stored in the memory 702 to perform information storage or processing, etc.

[0100] Input unit 704 provides input to processor 701. Input unit 704 may be, for example, a keypad or touch input device. Power supply 707 provides power to electronic device 70. Display 706 displays images and text. Display may be, for example, an LCD display, but is not limited to this.

[0101] The memory 702 can be a solid-state memory, such as a read-only memory (ROM), random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and contains more data; examples of this type of memory are sometimes referred to as EPROMs. The memory 702 can also be some other type of device. The memory 702 includes a buffer memory 7021 (sometimes called a buffer). The memory 702 may include an application / function storage unit 7022 for storing application programs and function programs or processes for executing the operation of the electronic device 70 via the processor 701.

[0102] The memory 702 may also include a data storage unit 7023 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 7024 of the memory 702 may include various drivers for the electronic device's communication functions and / or for performing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0103] The communication module 703 is a transmitter / receiver that transmits and receives signals via the antenna 708. The communication module (transmitter / receiver) 703 is coupled to the processor 701 to provide input signals and receive output signals, which is the same as in a conventional mobile communication terminal.

[0104] Based on different communication technologies, multiple communication modules 703 can be configured in the same electronic device, such as cellular network modules, Bluetooth modules, and / or wireless LAN modules. The communication module (transmitter / receiver) 703 is also coupled to a speaker 709 and a microphone 710 via an audio processing unit 705 to provide audio output via the speaker 709 and receive audio input from the microphone 710, thereby realizing typical telecommunications functions. The audio processing unit 705 may include any suitable buffer, decoder, amplifier, etc. Additionally, the audio processing unit 705 is also coupled to a processor 701, enabling on-device recording via the microphone 710 and on-device playback of stored audio via the speaker 709.

[0105] In embodiments of the present invention, a computer-readable storage medium is also provided for implementing all steps of the streaming data management method for the reconfigurable processor multi-port cache in the above embodiments. The computer-readable storage medium stores a computer program that, when executed by a processor, implements all steps of the streaming data management method for the reconfigurable processor multi-port cache in the above embodiments. For example, when the processor executes the computer program, it implements the following steps:

[0106] When processing the cell array access cache, if a cache miss occurs, the cache line with the target bit set to the first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value; when processing the cell array access cache, if a cache hit occurs, the target bit of the cache line that is hit this time is set to the second preset value based on the interval between the previously hit cache line and the currently hit cache line.

[0107] As can be seen from the above, the computer-readable storage medium provided in the embodiments of the present invention can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, improving the memory access bandwidth of PEA, alleviating the conflict and missing due to set-association, and reducing the missing rate for streaming data.

[0108] While this invention provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual device or client product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0109] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0111] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0112] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0113] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0114] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0115] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0116] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention is not limited to any single aspect, nor to any single embodiment, nor to any combination and / or substitution of these aspects and / or embodiments. Each aspect and / or embodiment of the present invention can be used alone, or in combination with one or more other aspects and / or other embodiments.

[0117] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A streaming data management method for a reconfigurable processor multi-port cache, characterized in that, include: When processing the cell array access cache, if a cache miss occurs, the cache line with the target bit set to the first preset value is evicted by polling arbitration, and the target bit of the subsequent cache line entering the cache is set to the first preset value; the first preset value is used to determine that the cache line is invalid. When processing the cell array access cache, if a cache hit occurs, it is determined whether the cache line hit in the previous hit is the same as the cache line hit in the current hit. If not, the target bit of the cache line hit in the current hit is set to the second preset value. If so, the target bit value of the cache line hit in the current hit remains unchanged. The second preset value is used to determine if a cache line is valid; A counter is used to count the number of memory access misses in the target processing unit array; based on the number of memory access misses and the number of memory blocks in the target processing unit array, new memory blocks are allocated to the target processing unit; wherein, when the number of memory access misses accumulates to a target multiple of the number of memory blocks, a memory block is allocated to the target processing unit and the counter is reset to zero.

2. The method according to claim 1, characterized in that, Before setting the target bit of subsequent cache lines entering the cache to the first preset value, the method further includes: Obtain missing address information and pre-stored information of the processing unit array; the pre-stored information of the processing unit array includes the starting address information and length information of the access sequence to be initiated by the processing unit array; If the missing address information is consistent with the starting address information, then the state machine is used to obtain off-chip data based on the length information; The streaming data that will subsequently enter the cache is determined based on the off-chip data.

3. The method according to claim 2, characterized in that, Using a state machine to obtain off-chip data based on the length information includes: The states of the control state machine include one or more of the following states: idle state, start prefetch state, flag access state, replacement cell access state, write operation state, data fetch state, wait state, or flag modification state. External data is obtained based on the state of the state machine and the length information.

4. The method according to claim 1, characterized in that, Also includes: If the starting address information of the first processing unit array and the second processing unit array is the same, then the cache space of the first processing unit array and the cache space of the second processing unit array are merged. Based on preset priority information, the first processing unit array and the second processing unit array are controlled to access the flag memory.

5. A streaming data management device for a reconfigurable processor multi-port cache, characterized in that, include: The eviction and insertion module is used to evict cache lines with a target bit of a first preset value by polling arbitration when a cache miss occurs during the processing of cell array access cache, and to set the target bit of subsequent cache lines entering the cache to the first preset value; the first preset value is used to determine that the cache line is invalid; The boosting module is used to determine whether the cache line hit in the previous hit and the cache line hit in the current hit are the same cache line when processing the access cache of the cell array. If not, the target bit of the cache line hit in the current hit is set to the second preset value. If so, then keep the target bit value of the cache line hit unchanged; The second preset value is used to determine if a cache line is valid; The modules are divided into: The counting unit is used to count the number of memory access misses in the target processing unit array using a counter; An allocation unit is configured to allocate additional memory to the target processing unit based on the number of memory access misses and the number of memory blocks in the target processing unit array; wherein, when the number of memory access misses accumulates to a target multiple of the number of memory blocks, a memory block is allocated to the target processing unit and the counter is reset to zero.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the streaming data management method of the reconfigurable processor multi-port cache according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that performs the streaming data management method of the reconfigurable processor multi-port cache according to any one of claims 1 to 4.

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