Chip layout method, device, equipment and storage medium

Abstract

Embodiments of the present application disclose a chip layout method, device, equipment and storage medium, wherein the chip layout method comprises: obtaining at least two components in a chip to be laid out; obtaining position information of components already placed on a chip board in an n-1th round and evaluation information of the n-1th round, wherein the evaluation information comprises information obtained by performing performance evaluation on a layout diagram corresponding to the components already placed on the chip board; n is an integer greater than 1; adjusting a distance between two components placed adjacently on the chip board in an n th round based on the position information of the components already placed on the chip board in the n-1th round and the evaluation information of the n-1th round until the evaluation information of the n th round indicates that a layout diagram on the chip board meets a preset layout index; and determining the layout diagram on the chip board corresponding to the preset layout index as a target layout diagram of the chip to be laid out.

Description

Technical Field

[0001] This application relates to the field of chip layout, and more particularly to a chip layout method, apparatus, device, and storage medium. Background Technology

[0002] In related technologies, traditional chip layout design relies on experienced designers using electronic design automation (EDA) tools to perform multiple iterations to find a layout that minimizes power, performance, and area while adhering to constraints such as layout density and routing congestion. This process typically requires massive amounts of computing resources, hindering its widespread adoption. Summary of the Invention

[0003] This application provides a chip layout technology solution.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a chip layout method, the method comprising: acquiring at least two components in a chip to be laid out; acquiring position information of components already placed on the chip board in the (n-1)th round and evaluation information of the (n-1)th round, the evaluation information including information obtained by performance evaluation of the layout diagram corresponding to the already placed components on the chip board; where n is an integer greater than 1; based on the position information of components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, adjusting the distance between two adjacent components placed on the chip board in the nth round until the evaluation information of the nth round indicates that the layout diagram on the chip board meets a preset layout index; and determining the layout diagram on the chip board that meets the preset layout index as the target layout diagram of the chip to be laid out.

[0006] This application provides a chip placement apparatus, comprising: a first acquisition module for acquiring at least two components in a chip to be placed; a second acquisition module for acquiring position information of components already placed on the chip board in the (n-1)th round and evaluation information of the (n-1)th round, the evaluation information including information obtained by performance evaluation of the layout diagram corresponding to the already placed components on the chip board; where n is an integer greater than 1; an adjustment module for adjusting the distance between two adjacent components placed on the chip board in the nth round based on the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, until the evaluation information of the nth round indicates that the layout diagram on the chip board meets a preset layout index; and a determination module for determining the layout diagram on the chip board that meets the preset layout index as the target layout diagram of the chip to be placed.

[0007] This application provides a computer device, which includes a memory and a processor. The memory stores computer-executable instructions, and the processor can implement the chip layout method described above when it executes the computer-executable instructions in the memory.

[0008] This application provides a computer storage medium storing computer-executable instructions, which, when executed, can implement the chip layout method described above.

[0009] This application provides a chip layout method, apparatus, device, and storage medium. The chip layout method includes: first, acquiring at least two components from a chip to be laid out; this identifies at least two components in the chip requiring layout routing, providing a basis for subsequent multi-round layouts; second, acquiring the position information of components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the evaluation information including information obtained from a performance evaluation of the layout diagram corresponding to the already placed components on the chip board; where n is an integer greater than 1; this allows the position information of components already placed in the previous round and the layout feedback information obtained after the previous round to be used as a reference for component placement in the next round; then, based on the position information of components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, adjusting the distance between two adjacent components placed on the chip board in the nth round until the evaluation information of the nth round indicates that the layout diagram on the chip board meets a preset layout index; this allows the position information of components already placed in the previous round and the evaluation information obtained after the previous round to be used as a reference for component placement in the next round. The layout feedback information is used to adjust the placement distance (relative positional relationship) between two adjacent components in the current round, making the current round's placement on the chip board more reasonable, and ensuring that the distance between adjacent components on the chip board is more compact compared to the previous round. This process is iterated until the components on the subsequent chip board are placed more compactly, and the corresponding layout meets the preset layout indicators. Finally, the layout diagram on the chip board that meets the preset layout indicators is determined as the target layout diagram for the chip to be placed. In this way, through multiple rounds of iterative placement, the position information of the components placed in the previous round and the corresponding layout feedback information after the final placement of the previous round are used to adjust the placement position of the components in the current round, that is, to adjust the distance between two adjacent components on the chip board in the current round, so that the components to be placed on the chip board in the current round tend to be closer to the already placed components. In this way, the iteration speed of chip layout design can be accelerated to achieve a better chip layout, such as a more reasonable arrangement between components, while reducing the computing power relied upon for chip layout design.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0012] Figure 1 A flowchart illustrating the first chip layout method provided in this application embodiment;

[0013] Figure 2 A flowchart illustrating the second chip layout method provided in this application embodiment;

[0014] Figure 3 A flowchart illustrating the third chip layout method provided in this application embodiment;

[0015] Figure 4A A schematic diagram of the probability distribution of components placed on a chip board provided in an embodiment of this application;

[0016] Figure 4B A schematic diagram of the probability distribution corresponding to placing a component on a chip board as provided in an embodiment of this application;

[0017] Figure 4C A schematic diagram illustrating the placement probability of placing a second component on a chip board, as provided in an embodiment of this application.

[0018] Figure 5A This is a schematic diagram illustrating the first round of component placement for the chip to be laid out, provided in an embodiment of this application.

[0019] Figure 5B This is a schematic diagram illustrating the second round of component placement for the chip to be laid out, provided in an embodiment of this application.

[0020] Figure 6 This is a schematic diagram of the composition structure of a chip layout device provided in an embodiment of this application;

[0021] Figure 7 This is a schematic diagram of the composition of a computer device provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate the embodiments of this application, but are not intended to limit the scope of the embodiments of this application.

[0023] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of embodiments of this application.

[0026] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0027] 1) Chip placement: This is one of the most critical and time-consuming steps in the chip design process. The placement task requires placing various components in the netlist, including macro elements such as flip-flops and arithmetic logic units, and standard cells (logic gates), into their corresponding positions on the chip board.

[0028] 2) Reinforcement Learning: Also known as reward learning, evaluation learning, or reinforcement learning, it is a paradigm and methodology in machine learning used to describe and solve problems where an agent learns strategies to maximize rewards or achieve specific goals during interactions with the environment. In reinforcement learning, the reinforcement signals provided by the environment evaluate the quality of actions rather than instructing the system on how to produce the correct action. Because the external environment provides limited information, reinforcement learning systems must learn from their own experiences. In this way, reinforcement learning systems acquire knowledge in the action-evaluation environment and improve subsequent actions to adapt to the environment.

[0029] 3) Iteration: Iteration is an activity that involves repeating a feedback process, usually with the aim of approximating a desired goal or result. Each repetition of the process is called an "iteration," and the result of each iteration serves as the initial value for the next iteration.

[0030] The following describes exemplary applications of the chip layout device provided in the embodiments of this application. The device provided in the embodiments of this application can be implemented as various types of user terminals such as laptops, tablets, desktop computers, cameras, and mobile devices (e.g., personal digital assistants, dedicated messaging devices, portable gaming devices), or as a server. Exemplary applications when the device is implemented as a terminal or server will be described below.

[0031] This method can be applied to computer devices. The functions implemented by this method can be achieved by the processor in the computer device calling program code. Of course, the program code can be stored in the computer storage medium. It can be seen that the computer device includes at least a processor and a storage medium.

[0032] This application provides a chip layout method, such as... Figure 1 The diagram shown is a flowchart illustrating the first chip layout method provided in this application embodiment; combined with Figure 1 The steps shown are explained below:

[0033] Step S101: Obtain at least two components from the chip to be laid out.

[0034] In some embodiments, the chip to be laid out can refer to a microcircuit, microchip, or wafer, which is a circuit to be fabricated on the surface of a semiconductor wafer; the chip to be laid out can be an analog integrated circuit or a digital integrated circuit, or a mixed-signal integrated circuit, i.e., analog and digital are integrated on one chip.

[0035] In some embodiments, obtaining at least two components in the chip to be laid out can be achieved by the chip placement device in response to a circuit diagram input from the outside, or by parsing the circuit diagram corresponding to the chip to be laid out; wherein, the at least two components may include macro elements and standard elements in the chip to be laid out, or may refer only to macro elements in the chip to be laid out.

[0036] Here, macro components and standard components in the chip to be laid out can be distinguished based on their area parameters. That is, components in the chip to be laid out can be categorized according to their area parameters. Components with area parameters greater than a preset area threshold are identified as macro components, while components with area parameters less than or equal to the preset area threshold are identified as standard components. The preset area threshold can be determined by EDA tools or based on the properties of the chip to be laid out. For example, components with smaller areas, such as resistors or capacitors, can be identified as standard components, while components with larger areas, such as flip-flops or memory, can be identified as macro components. Static Random-Access Memory (SRAM) can also be identified as macro components, while NOR gates can be identified as standard components.

[0037] In some embodiments, the processing signal corresponding to the chip to be laid out can be an analog signal or a digital signal, and the chip to be laid out can be divided based on its function and application scenario.

[0038] Here, because a single chip contains millions or billions of components, it is difficult to individually locate and connect each component within the chip; moreover, in practical applications, chips are too small to be easily soldered and connected. Therefore, designers use specialized programming languages ​​to create small circuit elements and combine them, thereby gradually increasing the size and density of components on the chip to meet application requirements—this is known as chip layout.

[0039] In some embodiments, at least two components in the chip to be laid out may include transistors, resistors, capacitors, or triggers, etc.

[0040] Step S102: Obtain the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round.

[0041] In some embodiments, the evaluation information includes information obtained by performing a performance evaluation on the layout diagram corresponding to the placed components on the chip board; where n is an integer greater than 1.

[0042] In some embodiments, at least two components of the chip to be laid out can be placed on the chip board in multiple rounds; wherein, each round of placement is to place at least two components on the chip board according to a preset placement order; here, the size of the chip board can be determined according to actual needs, or the size of the chip board can be determined based on the attributes of the chip to be laid out; at the same time, the attributes of the chip to be laid out can refer to the functional parameters of the chip to be laid out, etc.

[0043] Here, when placing at least two components on the chip board, the number of components placed on the chip board in different rounds can be the same or different; for example, the components placed on the chip board in the first round include three of the at least two components, and the components placed on the chip board in the second round include four of the at least two components; wherein, the four components placed on the chip board in the second round include three of the components placed on the chip board in the first round.

[0044] In some embodiments, at least two components are placed on the chip board in multiple rounds, that is, the number of components placed in the current round is greater than or equal to the number of components placed in the previous round, and the placement is carried out in multiple rounds until all components corresponding to at least two components of the chip to be laid out are placed on the chip board, and the corresponding placement layout must meet the preset layout indicators.

[0045] In some embodiments, during the iterative placement of at least two components in the chip to be laid out in multiple rounds, the position information of the components already placed on the chip board in any round, i.e., the (n-1)th round, and the evaluation information of the (n-1)th round are obtained. The position information of the components already placed on the chip board in the (n-1)th round includes the position information of each component already placed on the chip board in the (n-1)th round. At the same time, the evaluation information of the (n-1)th round is the information obtained by performing a performance evaluation on the layout diagram corresponding to the components already placed on the chip board in the (n-1)th round. Here, the layout diagram corresponding to the components already placed on the chip board in the (n-1)th round is the layout diagram obtained by routing the components already placed on the chip board in the (n-1)th round.

[0046] In some embodiments, the performance of a relevant layout diagram is evaluated to obtain information, which may be done by evaluating the performance of the relevant layout diagram using preset layout metrics; here, evaluation may refer to evaluation in one or more aspects such as performance, power consumption, and area.

[0047] In some embodiments, the evaluation information may be represented by numbers, such as 0.9, 0.3, or 0.2, or by words, such as "pass" or "fail".

[0048] Step S103: Based on the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, adjust the distance between two adjacent components placed on the chip board in the nth round until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index.

[0049] In some embodiments, the position information of the components already placed on the chip board in the (n-1)th round, and the evaluation information of the (n-1)th round, can be used as feedback information for the distance between two adjacent components placed on the chip board in the next round, i.e., the nth round.

[0050] Here, based on the position information of the components placed in the (n-1)th round and the evaluation information corresponding to the layout obtained after the (n-1)th round, the distance between two adjacent components placed in the nth round can be adjusted; that is, the distance between two adjacent components placed in the nth round can be reduced or increased, and the reduction or increase can be relative to the distance between two adjacent components placed in the (n-1)th round.

[0051] In some embodiments, based on the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information in the (n-1)th round, the distance between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information obtained in the nth round indicates that the layout diagram on the chip board meets the preset layout index; that is, through multiple rounds of iterative adjustment, until the evaluation information obtained meets the preset layout index, that is, the performance of the layout diagram corresponding to the components already placed on the chip board meets the preset layout index.

[0052] In some embodiments, the placement distance between the j-th component and the k-th component on the chip board in the n-1th round can be reduced based on the position information of the components already placed on the chip board in the (n-1th)th round and the evaluation information of the (n-1th)th round. Here, when reducing the placement distance between the j-th component and the k-th component on the chip board in the n-th round, the electromagnetic interference between the j-th component and the k-th component needs to be considered. Here, the j-th component is the j-th component already placed on the chip board in the (n-1th)th round; j is an integer greater than 1, and k is a positive integer less than j.

[0053] Step S104: The layout diagram on the chip board that satisfies the preset layout index is determined as the target layout diagram of the chip to be laid out.

[0054] In some embodiments, the layout diagram on the chip board that satisfies the preset layout index can be determined as the target layout diagram. Here, through multiple rounds of iterative adjustments in the above steps, a layout diagram is obtained that minimizes various indicators such as power, performance, and area without violating constraints such as layout density and wiring congestion. The layout diagram on the chip board that satisfies the preset layout index is the layout diagram obtained by routing each placed component on the corresponding chip board. The placed components on the chip board include at least two components in the chip to be laid out.

[0055] In some embodiments, when the chip to be laid out is a logic circuit, during the process of mapping the logic circuit to the physical circuit, i.e., when performing chip layout design, the components included in the logic circuit can be determined first, i.e., multiple components included in the logic circuit can be obtained for subsequent routing and layout. Secondly, in the process of placing these multiple components on the chip board in multiple rounds to achieve subsequent component layout, the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round can be obtained. The evaluation information includes information obtained from the performance evaluation of the layout diagram corresponding to the components already placed on the chip board; n is an integer greater than 1. This allows the position information of the successfully placed components in the previous round and the layout feedback information obtained after the previous round to be used as a reference for the component placement in the next round. Then, based on the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the distance between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information of the nth round indicates that the layout diagram on the chip board meets the preset layout indicators. Thus, based on the position information of the components already placed in the previous round... The system uses information from previous placement rounds and layout feedback to adjust the placement distance in the current round. This makes the current round's placement on the chip board more reasonable, resulting in a more compact arrangement of components compared to the previous round. This process iterates until the distance between components on the chip board becomes even more compact, and the corresponding layout meets preset layout criteria. Finally, the layout diagram on the chip board that meets the preset layout criteria is determined as the target layout diagram for the chip to be placed. Through multiple rounds of iterative placement, using the position information of components placed in the previous round and the layout feedback information after the final placement in the previous round, the system adjusts the placement position of components in the current round. This adjusts the distance between two adjacent components on the chip board in the current round, making the components placed in the current round tend to be closer to the already placed components. This accelerates the iteration speed of chip layout design, achieves a better chip layout (such as a more compact and reasonable arrangement of components), and reduces the computing power required for chip layout design.

[0056] The chip layout method provided in this application firstly acquires at least two components from the chip to be laid out. This identifies at least two components in the chip that require layout routing, providing a basis for subsequent multi-round layouts. Secondly, it acquires the position information of components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round. The evaluation information includes information obtained by evaluating the layout diagram corresponding to the already placed components on the chip board; where n is an integer greater than 1. This allows the position information of components already placed in the previous round and the layout feedback information obtained after the previous round to be used as a reference for component placement in the next round. Then, based on the position information of components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the distance between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information of the nth round indicates that the layout diagram on the chip board meets a preset layout index. Thus, based on the position information of components already placed in the previous round and the layout feedback information obtained after the previous round, the distance between two adjacent components placed in the current round is adjusted. The placement distance between components, i.e., their relative positional relationships, is adjusted to make the current round of placement on the chip board more reasonable. This means that, compared to the previous round, the distance between adjacent components on the chip board is more compact, meaning they are closer to existing placements. This process is iterated until the components on the subsequent chip board are more compact, and the corresponding layout meets preset layout criteria, i.e., the iteration converges. Finally, the layout diagram on the chip board that meets the preset layout criteria is determined as the target layout diagram for the chip to be placed. In this way, through multiple rounds of iterative placement, using the position information of components placed in the previous round and the layout feedback information after the final placement of the previous round, the placement position of the components in the current round is adjusted. This means adjusting the distance between two adjacent components on the chip board in the current round, so that the component to be placed on the chip board in the current round tends to be closer to existing components. This accelerates the iteration speed of chip layout design, achieves a better chip layout, such as a more compact and reasonable arrangement of components, and reduces the computing power required for chip layout design.

[0057] In some embodiments, firstly, a circuit diagram corresponding to the chip to be laid out is obtained, that is, a circuit diagram including multiple components and the connection relationships between multiple components is obtained, providing a basis for subsequently obtaining at least two components; then, the original component set corresponding to the circuit diagram is determined, that is, the original components included in the circuit diagram are extracted, and at least two components whose attribute information satisfies preset attributes are determined in the original component set; here, that is, the components in the chip to be laid out are filtered to obtain the components that are given priority for routing layout, such as the macro elements of the chip to be laid out; wherein, since the macro elements in the chip to be laid out are relatively large in size and few in number compared with other components, they can be laid out first; in this way, the speed and accuracy of the overall layout of the chip to be laid out can be improved, that is, the above step S101 can be described by the following steps S201 to S203, such as Figure 2 The diagram shown is a flowchart illustrating the second chip layout method provided in this application embodiment. Figure 1 and Figure 2 The steps shown are explained below:

[0058] Step S201: Obtain the circuit diagram corresponding to the chip to be laid out.

[0059] In some embodiments, a circuit diagram corresponding to the chip to be laid out can be obtained in response to external input information; here, the circuit diagram contains multiple components corresponding to the chip to be laid out, as well as the connection relationships between the multiple components.

[0060] Step S202: Determine the original set of components in the circuit diagram.

[0061] In some embodiments, an original set of components in the circuit diagram is determined, wherein the original set of components includes, but is not limited to: resistors, capacitors, potentiometers, electron tubes, electromechanical components, connectors, etc.; wherein the number and type of original components in the original set of components can be determined according to the function of the chip to be laid out.

[0062] Step S203: In the original component set, determine at least two components whose attribute information satisfies the preset attributes.

[0063] In some embodiments, in the original component set, at least two components whose attribute information satisfies the preset attribute are determined, that is, components whose attribute information satisfies the preset attribute are selected from the original component set. This may be to select macro elements from the original component set.

[0064] In some embodiments, in the original component set, attribute information can refer to the area information of the components. For example, at least two components with an area greater than a preset area can be selected from the original component set. It should be noted that in practical applications, for the chip to be laid out, components with larger areas (e.g., at least two components with an area greater than a preset area) account for a smaller number in the original component set, while components with smaller areas (e.g., an area less than or equal to a preset area) account for a larger number. For example, the storage components involved in the chip to be laid out are typically few in number and large in area, while the related resistors or capacitors are numerous and small in area.

[0065] In some embodiments, in the original component set, attribute information can refer to the aspect ratio corresponding to the component size. For example, in the original component set, it can be determined that the aspect ratio corresponding to the component size satisfies a preset aspect ratio, such as at least two components that are greater than the preset aspect ratio value.

[0066] In some embodiments, at least two components in the original component set can be identified whose aspect ratios are greater than a preset aspect ratio and whose areas are greater than a preset area threshold. Here, this attribute information includes both the component's aspect ratio and its area.

[0067] In some embodiments, firstly, the position information of the components already placed on the chip board in the (n-1)th round can be evaluated to obtain a placement score for each component already placed on the chip board in the (n-1)th round. This allows for the evaluation of the placement position of each component already placed on the chip board in the (n-1)th round; that is, the placement score of each component already placed on the chip board in the (n-1)th round can be used to characterize the rationality of the placement of each component already placed on the chip board in the (n-1)th round. Then, the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round are used as reference information in the process of component placement in the next round, i.e., the nth round. The placement score of each component already placed on the chip board in round 1 and the evaluation information of round n-1 are fed back into the component placement process on the chip board in round n. This allows for the corresponding adjustment of the relative positional relationship between two adjacent components placed in round n. For example, the area corresponding to the target component on the chip board in round n can be made smaller than the area corresponding to the components already placed on the chip board in round n-1. The target component is the same component as the component already placed on the chip board in round n-1. This process is repeated multiple times until a layout diagram on the chip board that satisfies the preset layout indicators is obtained. That is, step S103 provided in the above embodiment can be implemented through steps S301 and S302, such as... Figure 3 The diagram shown is a flowchart illustrating the third chip layout provided in this application embodiment. Figure 1 and Figure 3 The steps shown are explained below:

[0068] Step S301: Evaluate the position information of the components already placed on the chip board in the (n-1)th round to obtain the placement score of each component already placed on the chip board in the (n-1)th round.

[0069] In some embodiments, the position information of the components already placed on the chip board in the (n-1)th round can be evaluated to obtain the placement score of each component already placed on the chip board in the (n-1)th round. The placement score can be used to characterize the rationality of the placement of each component already placed on the chip board in the (n-1)th round.

[0070] In some embodiments, the placement score of each component placed on the chip board in the (n-1)th round can be represented by a number, for example: 0.9 indicates that the placement is relatively reasonable, 0.1 indicates that the placement is not very reasonable, etc.

[0071] In some embodiments, the placement order of at least two components can be used to analyze the position information of each component placed on the chip board in the (n-1)th round, thereby obtaining the starting and ending placement areas corresponding to each component placed on the chip board in the (n-1)th round. For example, according to the placement order, the corresponding areas before and after each component is placed on the chip board can be analyzed, and based on these areas, the starting and ending placement areas corresponding to each component placed on the chip board in the (n-1)th round can be obtained. Then, based on the ending and starting placement areas, the position information of each component placed on the chip board in the (n-1)th round can be evaluated to obtain the placement score of each component placed on the chip board in the (n-1)th round. In this way, by evaluating the placement information based on the starting placement area before placement and the ending placement area after placement, the corresponding placement score can be obtained, which can conveniently and accurately determine the placement rationality of each component in the (n-1)th round. That is, the above step S301 can be implemented by the following steps S3011 and S3012 (not shown in the figure):

[0072] Step S3011: Using the placement order of the at least two components, analyze the position information of each component placed on the chip board in the (n-1)th round to obtain the starting placement area and ending placement area corresponding to each component placed on the chip board in the (n-1)th round.

[0073] In some embodiments, the placement order can be predetermined or determined based on the connection relationship between at least two components. For example, the placement sequence of each component can be determined based on the function of each of the at least two components in the chip to be laid out; for example, firstly, the component corresponding to the power supply function can be placed; secondly, the component corresponding to the timing function can be placed; then, the component corresponding to the storage function can be placed, and so on.

[0074] In some embodiments, the placement order of at least two components is used to analyze the position information of each component placed on the chip board in the (n-1)th round. That is, based on the placement order, the area reserved on the chip board for placing components before each component is placed in the (n-1)th round is obtained, namely the starting placement area, and the area reserved on the chip board for placing components after each component is placed is obtained, namely the ending placement area.

[0075] In some embodiments, the area of ​​the ending placement area is smaller than the area of ​​the starting placement area.

[0076] In some embodiments, the placement order can be used to analyze the position information of each component placed on the chip board in the (n-1)th round, obtaining the first placed area corresponding to the i-th component before placement and the second placed area corresponding to the i-th component after placement in the (n-1)th round. Determining the first placed area before placement and the second placed area corresponding to the i-th component after placement provides a basis for subsequent placement of the i-th component, and also allows for a more accurate determination of the starting and ending placement areas for the i-th component. Then, using the size of the i-th component, the first placed area is adjusted to obtain the starting placement area of ​​the i-th component on the chip board in the (n-1)th round, and using the size of the (i+1)-th component, the second placed area is adjusted to obtain the ending placement area of ​​the i-th component on the chip board in the (n-1)th round. This avoids overlapping placement positions of adjacent components on the chip board, thus improving the placement efficiency and accuracy of each component in the (n-1)th round. Therefore, step S3011 can be implemented through the following process:

[0077] The first step is to analyze the position information of each component placed on the chip board in the (n-1)th round using the placement order, and obtain the first placed area corresponding to the i-th component on the chip board before placement and the second placed area corresponding to the i-th component after placement in the (n-1)th round.

[0078] In some embodiments, the i-th component is the i-th component placed among the placed components; where i is an integer greater than or equal to 1.

[0079] In some embodiments, the placement order is used to analyze the position information of each component placed on the chip board in the (n-1)th round, so as to obtain the first placed area corresponding to the i-th component on the chip board before placement and the second placed area corresponding to the i-th component after placement in the (n-1)th round.

[0080] Here, both the first and second placed areas are areas on the chip board where components have been placed, with the second placed area being larger than the first placed area.

[0081] In some embodiments, when i is 1, the first placed area can refer to all areas on the chip board.

[0082] The second step is to adjust the first placed area using the size of the i-th component to obtain the starting placement area of ​​the i-th component on the chip board in the (n-1)-th round.

[0083] In some embodiments, the size of the first placed area can be adjusted based on the size of the i-th component to obtain the initial placement area of ​​the i-th component on the chip board in the (n-1)-th round.

[0084] The third step is to adjust the second placed area based on the size of the (i+1)th component to obtain the final placement area of ​​the i-th component on the chip board in the (n-1)th round.

[0085] In some embodiments, the size of the second placed area can be adjusted based on the size of the (i+1)th component to obtain the final placement area of ​​the i-th component on the chip board in the (n-1)th round.

[0086] In some embodiments, firstly, the size of the i-th component in the (n-1)th round is used to expand the first placed area outward to obtain a first intermediate area; then, the area on the chip board excluding the first intermediate area is determined as the starting placement area of ​​the i-th component in the (n-1)th round on the chip board. In this way, expanding the first placed area outward based on the size of the i-th component avoids overlap with already placed components during the placement of the i-th component, thus achieving a preset placement area where the starting placement area is the center of the i-th component; thereby improving the placement efficiency and accuracy of the i-th component in the (n-1)th round. That is, the step described above, "adjusting the first placed area based on the size of the i-th component to obtain the starting placement area of ​​the i-th component in the (n-1)th round on the chip board," can be achieved through the following process:

[0087] Using the size of the i-th component in the (n-1)th round, the first placed area is expanded outward to obtain a first intermediate area, and the area on the chip board other than the first intermediate area is determined as the starting placement area of ​​the i-th component in the (n-1)th round on the chip board.

[0088] In some embodiments, the area surrounding the first placed area can be expanded outwards by a size equal to the size of the i-th component in the (n-1)th round, thereby obtaining a first intermediate area. Here, the first intermediate area can surround the first placed area, and the relative distance between the first placed area and the first intermediate area is the size of the i-th component.

[0089] In some embodiments, the area on the chip board other than the first intermediate area is defined as the starting placement area of ​​the i-th component in the (n-1)th round on the chip board; in this way, the center of the i-th component in the (n-1)th round can be placed at any position in the starting placement area, thereby avoiding the overlap between the i-th component and the already placed components.

[0090] And / or, using the size of the (n-1)th component (i+1), the second placed area is expanded outward to obtain a second intermediate area; then, the area on the chip board excluding the second intermediate area is determined as the final placement area of ​​the i-th component on the chip board in the (n-1)th round. In this way, expanding the second placed area based on the size of the (i+1)th component avoids overlap with already placed components, such as the i-th component, during the placement of the (i+1)th component. This achieves the goal of determining the final placement area as the preset placement area of ​​the center of the (i+1)th component; thus, it improves the placement efficiency and accuracy of each component in the (n-1)th round. That is, the step described above, "adjusting the second placed area based on the size of the (i+1)th component to obtain the final placement area of ​​the i-th component on the chip board in the (n-1)th round," can be achieved through the following process:

[0091] Using the size of the (n-1)th round (i+1)th component, the second already placed area is expanded outward to obtain a second intermediate area, and the area on the chip board other than the second intermediate area is determined as the final placement area of ​​the (n-1)th round (i)th component on the chip board.

[0092] In some embodiments, the size of the (n-1)th component (i+1)th component can be used to expand the second placed area to obtain a second intermediate area. This expansion is the same as the above-described method of using the size of the (n-1)th component (i)th component to expand the first placed area to obtain a first intermediate area, and will not be repeated here.

[0093] In some embodiments, the area on the chip board other than the second intermediate area is defined as the final placement area of ​​the i-th component on the chip board in the (n-1)th round; in this way, the overlapping phenomenon between the i-th component and the subsequent placement components can be avoided.

[0094] Step S3012: Based on the ending placement area and the starting placement area, evaluate the position information of each placed component on the chip board in the (n-1)th round to obtain the placement score of each placed component on the chip board in the (n-1)th round.

[0095] In some embodiments, the ending placement area and the starting placement area can be compared to obtain a region comparison score, and then the region comparison score can be determined as the placement score of each placed component on the chip board.

[0096] In some embodiments, the area of ​​the ending placement area can first be compared with the area of ​​the starting placement area to obtain a score, namely the area comparison score. This area comparison score can then be determined as the placement score of each placed component on the chip board in the (n-1)th round. In this way, by comparing the areas of the two regions before and after placement, more direct evaluation information representing the rationality of component placement can be obtained. For example, if the area comparison score obtained by comparing the ending and starting placement areas is low, it indicates that the ending placement area is much smaller than the starting placement area, meaning that the i-th component in the (n-1)th round occupies a large amount of space, which may result in a smaller area available for subsequent placements. This indicates that the placement of the i-th component in the (n-1)th round is poor and unreasonable. Similarly, if the area comparison score obtained by comparing the ending and starting placement areas is high, it indicates that the area of ​​the ending placement area is relatively close to the starting placement area, meaning that the i-th component in the (n-1)th round occupies less space, which may result in a larger area available for subsequent placements. This indicates that the placement of the i-th component in the (n-1)th round is more reasonable. Therefore, step S3012 can be implemented through the following steps:

[0097] First, the area of ​​the ending placement area is compared with the area of ​​the starting placement area to obtain an area comparison score.

[0098] In some embodiments, the areas of the ending placement area and the starting placement area can be directly compared to obtain a region comparison score.

[0099] Secondly, the area comparison score is determined as the placement score of each placed component on the chip board in the (n-1)th round.

[0100] In some embodiments, the area comparison score is directly determined as the placement score of each placed component on the chip board in the (n-1)th round.

[0101] In some embodiments, when the score range corresponding to the placement score is between (0, 1), if the placement score of a component on the chip board in the (n-1)th round is close to 1, it indicates that the placement of the component on the chip board in the (n-1)th round is relatively reasonable; if the placement score of a component on the chip board in the (n-1)th round is close to 0, it indicates that the placement of the component on the chip board in the (n-1)th round is unreasonable.

[0102] Step S302: Based on the placement score of each component placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, adjust the relative positional relationship between two adjacent components placed on the chip board in the nth round until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index.

[0103] In some embodiments, the placement area of ​​the target component on the chip board in the nth round is smaller than the placement area of ​​the components already placed on the chip board in the (n-1)th round; the target component is the same component as the component already placed on the chip board in the (n-1)th round among the components already placed on the chip board in the nth round.

[0104] In some embodiments, the relative positional relationship between two adjacent components placed on the chip board in the (n-1)th round is adjusted based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round. This step is repeated until the evaluation information obtained in the nth round indicates that the layout on the chip board meets the preset layout index.

[0105] In practical applications, during the initial chip placement phase, the distance between components is typically maximized to reduce electromagnetic interference and facilitate subsequent routing. However, this approach may increase the probability of increased area, performance, and power consumption in later placements. To address this, multiple rounds of component placement can be performed. This involves using the placement score of each component placed on the chip board in round n-1 and the evaluation information from round n-1 as adjustment parameters to reduce the distance between adjacent components in round n. This process continues until the evaluation information from round n indicates the desired layout on the chip board. By comprehensively considering area, performance, and power consumption, the goal is to achieve a layout that minimizes all performance metrics.

[0106] In some embodiments, based on the position information of the components placed in the (n-1)th round and the layout feedback information obtained after the (n-1)th round of placement, the placement distance between the j-th component and the k-th component on the chip board in the nth round is reduced. This step is repeated until the obtained evaluation information meets the preset layout index; the j-th component is the j-th component placed on the chip board in the (n-1)th round; j is an integer greater than 1, and k is a positive integer less than j; in this way, the placement on the chip board in the nth round is more reasonable, that is, the distance between the components placed on the chip board in the nth round is more compact than that in the (n-1)th round; thus, through multiple rounds of placement, a better chip layout can be achieved while accelerating the iteration speed of chip layout design, such as a more compact and reasonable arrangement between components, and at the same time, the computing power relied upon in chip layout design can be reduced; that is, the above step S302 can be implemented through the following steps:

[0107] Based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the placement distance between the j-th component and the k-th component on the chip board in the nth round is reduced. The above steps are repeated until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index.

[0108] Wherein, the j-th component is the j-th component placed on the chip board in the (n-1)-th round; j is an integer greater than 1, and k is a positive integer less than j.

[0109] In some embodiments, based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the placement distance between the j-th component and the k-th component on the chip board in the nth round is reduced. This step is repeated until the obtained evaluation information meets the preset layout index. Here, reducing the placement distance between the j-th component and the k-th component on the chip board in the nth round is relative to the placement distance between the j-th component and the k-th component on the chip board in the (n-1)th round; at the same time, when reducing the placement distance between the j-th component and the k-th component on the chip board in the nth round, the electromagnetic interference phenomenon caused by the distance relationship between the j-th component and the k-th component must be taken into account.

[0110] In some embodiments, for example, when the j-th component is the third component placed on the chip board in the (n-1)-th round, and the k-th component is the first and second components placed on the chip board in the (n-1)-th round; here, the distance between the second and first components placed on the chip board in the n-th round can be reduced based on the placement score of each component placed on the chip board in the (n-1)-th round and the evaluation score of the (n-1)-th round, i.e., based on the placement score of the first, second, and third components placed on the chip board in the (n-1)-th round and the evaluation score of the (n-1)-th round. Here, it can refer to reducing the placement distance between the third component and the second component on the chip board in the nth round, or it can refer to reducing the placement distance between the third component and the first component on the chip board in the nth round; it can also refer to simultaneously reducing the placement distance between the third component and the first component, and the placement distance between the third component and the second component on the chip board in the nth round.

[0111] In some embodiments, connection information between at least two components can first be obtained. Then, based on this connection information and the position information of the components already placed on the chip board, layout routing is performed on the chip board to obtain the layout diagram for the (n-1)th round. This yields the layout diagram corresponding to the component placement after the (n-1)th round. Finally, a preset layout metric is used to evaluate the performance of the layout diagram for the (n-1)th round, obtaining the evaluation information for the (n-1)th round. This allows for relatively convenient acquisition of the evaluation information for the (n-1)th round. Specifically, the evaluation information for the (n-1)th round can be obtained through the following methods:

[0112] The first step is to obtain the connection information between the at least two components.

[0113] In some embodiments, connection information between at least two components is obtained, and this connection information may be determined based on the circuit diagram corresponding to the chip to be laid out; for example, the input of component 1 is used as the output of component 4, and the outputs of component 2 and component 3 are used as the input of component 4.

[0114] The second step involves laying out the wiring on the chip board based on the connection information and the position information of the components already placed on the chip board, to obtain the layout diagram of the (n-1)th round.

[0115] In some embodiments, when at least two components are macro elements, the standard components can be filled onto the chip board according to a preset strategy after the macro elements are laid out. Then, based on the connection information and the position information of the components already placed on the chip board, the layout and routing are performed on the chip, that is, the layout and routing of the placed components are performed according to the connection information to obtain the layout diagram of the (n-1)th round.

[0116] The third step is to use the preset layout index to evaluate the performance of the layout diagram in the (n-1)th round, and obtain the evaluation information for the (n-1)th round.

[0117] In some embodiments, a preset layout index can be used to evaluate the performance of the layout diagram in the (n-1)th round to obtain the evaluation information for the (n-1)th round. This evaluation information can be characterized by: qualified, unqualified; passed, failed, etc., or it can be represented by numbers, such as 0.9, 0.5, etc.

[0118] In some embodiments, the area, performance, and power consumption parameters of the layout diagram in the (n-1)th round can be evaluated sequentially based on the area, performance, and power consumption parameters carried in the preset layout indicators to obtain the corresponding evaluation parameters. Then, the three evaluation parameters are comprehensively analyzed to obtain the evaluation information for the (n-1)th round. That is, the step of "using the preset layout indicators to evaluate the performance of the layout diagram in the (n-1)th round and obtaining the evaluation information for the (n-1)th round" can be achieved through the following steps:

[0119] First, the area index in the preset layout index is used to evaluate the area parameter of the layout diagram in the (n-1)th round to obtain the first evaluation parameter.

[0120] In some embodiments, the area index in the preset layout index is used to evaluate the area parameter of the layout diagram in the (n-1)th round to obtain a first evaluation parameter; the first evaluation parameter can be a number or can be represented by text.

[0121] In some embodiments, the area index in the preset layout index can be compared with the area parameter of the layout diagram in the (n-1)th round; here, if the area index in the preset layout index is a preset area range, the corresponding first evaluation parameter can also be obtained based on whether the area parameter of the layout diagram in the (n-1)th round falls within the preset area range.

[0122] Secondly, the performance parameters of the layout diagram in the (n-1)th round are evaluated using the performance indicators in the preset layout indicators to obtain the second evaluation parameters.

[0123] In some embodiments, the process of evaluating the performance parameters of the layout diagram in the (n-1)th round using the performance indicators in the preset layout indicators is similar to the evaluation of the area parameters described above, and will not be repeated here.

[0124] Then, the power consumption parameters of the layout diagram in the (n-1)th round are evaluated using the power consumption index in the preset layout index to obtain the third evaluation parameter.

[0125] In some embodiments, the process of evaluating the power consumption parameters of the layout diagram in the (n-1)th round using the power consumption index in the preset layout index is similar to the evaluation of the area parameters described above, and can be referred to the evaluation of the area parameters described above, and will not be repeated here.

[0126] Finally, the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter are analyzed to obtain the evaluation information for the (n-1)th round.

[0127] In some embodiments, the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter are analyzed to obtain the evaluation information for the (n-1)th round. For example, the three parameters can be summarized, and if any one of them is not met, the evaluation information for the (n-1)th round is considered to be unsuccessful. If all three are met, the evaluation information for the (n-1)th round is considered to be successful. Alternatively, the evaluation parameters corresponding to the three parameters can be superimposed based on relevant weights to obtain the corresponding numerical value, and then this numerical value is determined as the evaluation information for the (n-1)th round.

[0128] In some embodiments, when at least two components are components whose attribute information satisfies preset attributes in the original component set corresponding to the chip to be laid out, based on the chip layout method provided in this application embodiment, after laying out at least two components in the chip to be laid out to obtain the target layout diagram of the chip to be laid out, components whose attribute information does not satisfy preset attributes, such as at least one standard element, can continue to be placed on the chip board in the original component set corresponding to the chip to be laid out, so as to realize the layout of all components in the chip to be laid out. That is, based on the target layout diagram, at least one standard element is placed on the chip board, and the connection relationship between at least one standard element and at least two components is continued to be laid out and traced, so as to adjust the target layout diagram and obtain the adjusted target layout diagram. That is, the chip layout method provided in this application embodiment can also perform the following steps:

[0129] The first step is to identify at least one standard component in the original component set whose attribute information does not satisfy the preset attribute.

[0130] In some embodiments, at least one standard element in the original component set corresponding to the chip to be laid out can be selected whose attribute information does not meet the preset attributes; here, the description of the attribute information can be referred to in step S203 above, and will not be repeated here.

[0131] The second step is to determine the connection relationship between the at least one standard element and the at least two components.

[0132] In some embodiments, the connection relationship between at least one standard element and at least two components can be determined based on the circuit diagram corresponding to the chip to be laid out. For example, component 1 is connected to standard element 1 and standard element 2, while component 2 is connected to standard element 2, standard element 3 and standard element 4, etc.

[0133] The third step involves placing the at least one standard component on the chip board based on the connection relationship and the target layout diagram, thereby obtaining the placement information of the at least one standard component on the chip board.

[0134] In some embodiments, at least one standard component can be placed based on the connection relationship and the target layout diagram. For example, when the standard component 1 is connected to the component 1, the standard component 1 can be placed on the chip board in the surrounding target area that surrounds the component 1 based on the placement position of the component 1 in the target layout diagram, wherein no component or standard component is placed in the surrounding target area.

[0135] Fourth step: Based on the placement information and the connection relationship, adjust the target layout diagram to obtain the adjusted target layout diagram.

[0136] In some embodiments, it is necessary to perform layout routing on at least one standard component and at least two components already placed on the chip board based on the connection relationship between at least one standard component and at least two components. Here, the layout routing of at least one standard component and at least two components placed on the chip board can be performed based on the connection relationship, the placement information of at least one standard component on the chip board and the target layout diagram (wherein the placement information of at least two components on the chip board and the layout routing between at least two components can be obtained from the target layout diagram), that is, the layout routing of the target layout diagram is adjusted and supplemented to obtain the adjusted target layout diagram.

[0137] In some embodiments, in practical applications, the number of standard components to be laid out in the chip is greater than the number of components, and the area of ​​the standard components is usually smaller than the area of ​​the components. Therefore, in the process of placing the standard components, multiple standard components associated with a component (i.e., there is a connection between the component and multiple standard components) can be placed in the surrounding target area corresponding to the placement area of ​​the component on the chip board. In this surrounding target area, there are no components or standard components. The placement of multiple standard components can also refer to the chip layout method provided in the embodiments of this application, that is, multiple rounds of iterative placement of multiple standard components. The position information of the standard components placed in the previous round and the feedback information of the standard components after the final placement of the previous round are used to adjust the placement position of the standard components in the current round. That is, the distance between two adjacent standard components placed on the chip board in the current round is adjusted, so that the standard components to be placed in the surrounding target area in the current round tend to be closer to the standard components that have already been placed.

[0138] It should be noted that in practical applications, the number of standard components to be laid out in a chip is greater than the number of components, but the area of ​​standard components is usually smaller than that of components. Therefore, in the chip layout process, it is usually necessary to place the fewer components with larger areas, such as macro components, to obtain the target layout diagram, and then place the more numerous standard components with smaller areas. In this way, the iteration speed of chip layout design can be accelerated, and by placing macro components and standard components in sequence, the arrangement of components in the obtained chip layout is more compact and reasonable.

[0139] Here, the chip layout method provided in this application embodiment involves layout routing, including layout routing of at least two components placed on the chip board, and layout routing between at least two components and at least one element placed on the chip board. It is necessary to satisfy that the total routing corresponding to the chip to be laid out is as short as possible, and when comprehensively considering factors such as crosstalk between lines and electrical spacing (electrical clearance and creepage distance), multi-layer board routing can be performed.

[0140] Here, the chip layout method provided in the embodiments of this application can be applied to various types of chips, such as computing chips (e.g., central processing unit (CPU), graphics processing unit (GPU)), storage chips (e.g., random access memory (RAM), flash memory (Flash EEPROM Memory, FLASH)), and power chips (e.g., low dropout regulator (LDO)). Simultaneously, the chip layout method provided in the embodiments of this application can be applied to the chip layout stage of computing cluster chips and edge chips, so that the subsequently obtained chips have image processing functions, information acquisition functions, audio / video control functions, etc., which involve, but are not limited to, the fields of image processing and computer vision.

[0141] The chip layout method described above will be explained below with reference to a specific embodiment. However, it is worth noting that this specific embodiment is only for better illustrating the embodiments of this application and does not constitute an improper limitation on the embodiments of this application.

[0142] In related technologies, chip placement design is a crucial step in transforming a chip from logic circuits to physical circuits. The rationality of the placement affects chip performance metrics such as area and power consumption; an improper placement can even lead to tape-out failure, causing significant losses. Traditional chip placement design relies heavily on experienced designers using EDA tools for multiple iterations, a process that can take months. Reinforcement learning is often used to optimize this process, bringing the algorithm's placement performance close to that of experienced designers. However, when applied to large-scale chip placement design, finding a compliant placement requires massive computational resources, hindering its widespread adoption. The root cause of this problem lies in the sparsity of the monitoring signal; feedback is only received after the last component is placed, with no feedback provided in other iterations during the placement process.

[0143] Based on this, embodiments of this application provide a chip placement method, which mainly addresses the problem of algorithm convergence difficulties and the high computational resource consumption required when using reinforcement learning to design chip placement. In the case of a chip to be placed comprising multiple components, the chip placement method provided in this application uses an expected compliant layout determined in the previous round of component placement as feedback for the current round of component placement during the multi-round iterative placement process.

[0144] Among them, reinforcement learning algorithms based on policy gradients can be used, where the policy network predicts the probability distribution of the component's placement in the next round based on the encoding of the current placement. For example... Figure 4A The diagram shown is a probability distribution diagram of components placed on a chip board according to an embodiment of this application; wherein, different colors represent the probability of a component being placed at that position on the chip board, with darker colors indicating lower probabilities and vice versa.

[0145] At the same time, such as Figure 4B The diagram shown is a probability distribution diagram corresponding to the placement of a component on a chip board according to an embodiment of this application. After a component 401 is placed on the chip board, the area it occupies is an area that cannot be placed, and its color is darker than other areas, so that subsequent components cannot overlap with the current position of component 401.

[0146] And such as Figure 4C The diagram shown illustrates the placement probability when placing a second component on a chip board according to an embodiment of this application; wherein, when placing the next component, i.e., the second component, Figure 4B The probability of placing components in the area corresponding to the placement component 401 shown is set to zero.

[0147] Therefore, in each round of component placement for the chip, after placing a component on the chip board in each round, a current feedback information is obtained, which can be a comparison between the area of ​​the feasible area after the current placement and the area of ​​the feasible area after the previous placement. This feedback information can make the component tend to be closer to the existing placement in the next round of placement.

[0148] When the chip to be laid out includes three components: component 501, component 502, and component 503, such as Figure 5A The diagram illustrates the first round of component placement for the chip to be laid out according to an embodiment of this application. Specifically, components 501, 502, and 503 need to be placed onto a preset chip board. Firstly, after placing component 501 on the chip board, the dimensions of the next component 502 to be placed are obtained. The dimensions of component 502, i.e., its side length, are then enclosed within the area corresponding to the component 501 placed on the chip board, resulting in area 504. This avoids the probability of overlap between the next component 502 placed on the chip board and the already placed component 501. Figure 5A As shown, after the first round of component placement 501, the chip board can be divided into three areas, as follows: Figure 5AThree different filling methods are used to represent this: the placement area corresponding to component 501, the area 504 where the placement probability of component 502 needs to be set to 0, and the area 505 where the center of component 502 can be placed. Then, the second step of the first round of placement is performed, that is, component 502 is placed. After placing component 502, the size of the next component 503 to be placed is obtained, and the size of component 503, that is, the side length of component 503, is enclosed in the area corresponding to component 502 placed on the chip board to obtain area 506. Similarly, after the first round of placement of component 502, the chip board can be divided into five areas: the placement area corresponding to component 501, the area 504 where the placement probability of component 502 needs to be set to 0, the placement area corresponding to component 502, the area 506 where the placement probability of component 503 needs to be set to 0, and the area 507 where the center of component 503 can be placed. It can be found that if component 503 is placed at any position in area 507, it will be impossible to place component 503 completely on the chip board, and thus the first round of placement will fail.

[0149] At this point, refer to the positional information of components 501 and 502 on the chip board during the first round of component placement, as well as the layout feedback from the first round (i.e., placement failure), and make corresponding adjustments to the component placement in the second round, such as... Figure 5B The diagram illustrates the second round of component placement for the chip to be laid out, as provided in this embodiment. The first step of placing component 501 is identical to the first round. After placing component 501 on the chip board, the board can be divided into three areas: the placement area corresponding to component 501, the area 504 where the placement probability of the center of component 502 needs to be set to 0, and the area 505 where the center of component 502 may be placed. When performing the second step of the second round, i.e., placing component 502 on the chip board, the information from the first round of placement is referenced. Figure 5A After placing component 502 in the second step, five regions are obtained on the chip board: the placement area corresponding to component 501, region 504 where the placement probability of component 502 needs to be set to 0, the placement area corresponding to component 502, region 506 where the placement probability of component 503 needs to be set to 0, and region 507 where the center of component 503 can be placed. Since region 507 may contain areas where component 503 cannot be placed, the placement distance between component 502 and component 501 can be reduced compared to the distance between component 501 and component 502 in the first round. Figure 5BAs shown in the second step of the second round of placement, after placing component 502, the area on the chip board can be divided into: the placement area corresponding to component 501, the area 508 where the placement probability of component 502's center needs to be set to 0, the placement area corresponding to component 502, the area 509 where the placement probability of component 503's center needs to be set to 0, and the area 510 where the center of component 503 might be placed; then, the placement of component 503 continues, as shown in the third step of the third round of placement in Figure 5, where the three components 501, 502, and 503 are placed adjacent to each other. Here, compared to the components placed in the first round, the center of component 502 is closer to the boundary area of ​​area 504, which increases the probability that all parts of component 503 will be properly placed on the chip board during the subsequent placement process, such as... Figure 5B As shown, the center of component 503 can be placed as close as possible to the boundary area of ​​region 509 so that components 501, 502 and 503 can be placed reasonably on the chip board, that is, reasonably arranged.

[0150] The chip placement method provided in this application dynamically adjusts the positions of components in the current round based on the monitoring signals from each placement iteration in the previous round. This makes the adjacent components in the current round more compact compared to their positions in the previous round, meaning they are closer to existing placements. This process is repeated iteratively until a subsequent round of component placement achieves a compact layout that meets the requirements. In this sense, component placement exhibits a certain bias in the next round of placement. This accelerates the iteration speed of chip placement design, achieving a better chip layout, resulting in a more compact and rational arrangement of components, while also reducing the computational power required for chip placement design. Furthermore, this application lowers the barrier to entry for chip placement design, enabling more junior designers to achieve a similar level of placement design as experienced designers, even with limited computing resources.

[0151] Based on the foregoing embodiments, this application also provides a chip layout apparatus, such as... Figure 6 The diagram shown is a schematic representation of the structure of a chip placement apparatus provided in an embodiment of this application. The chip placement apparatus 600 includes:

[0152] The first acquisition module 601 is used to acquire at least two components in the chip to be laid out;

[0153] The second acquisition module 602 is used to acquire the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round. The evaluation information includes information obtained by performing a performance evaluation on the layout diagram corresponding to the components already placed on the chip board; where n is an integer greater than 1.

[0154] The adjustment module 603 is used to adjust the distance between two adjacent components placed on the chip board in the nth round based on the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index.

[0155] The determining module 604 is used to determine the layout diagram on the chip board that meets the preset layout index as the target layout diagram of the chip to be laid out.

[0156] In some embodiments, the first acquisition module 601 is further configured to acquire the circuit diagram corresponding to the chip to be laid out; determine the original component set in the circuit diagram; and determine at least two components in the original component set whose attribute information satisfies preset attributes.

[0157] In some embodiments, the adjustment module 603 is further configured to evaluate the position information of the components already placed on the chip board in the (n-1)th round to obtain a placement score for each component already placed on the chip board in the (n-1)th round; based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, adjust the relative positional relationship between two adjacent components placed on the chip board in the nth round until the evaluation information of the nth round indicates that the layout diagram on the chip board meets the preset layout index; wherein, the placement area corresponding to the target component on the chip board in the nth round is smaller than the placement area corresponding to the components already placed on the chip board in the (n-1)th round; the target component is the same component as the component already placed on the chip board in the (n-1)th round among the components already placed on the chip board in the nth round.

[0158] In some embodiments, the adjustment module 603 is further configured to analyze the position information of each component placed on the chip board in the (n-1)th round using the placement order of the at least two components, to obtain the starting placement area and the ending placement area corresponding to each component placed on the chip board in the (n-1)th round; and to evaluate the position information of each component placed on the chip board in the (n-1)th round based on the ending placement area and the starting placement area, to obtain the placement score of each component placed on the chip board in the (n-1)th round.

[0159] In some embodiments, the adjustment module 603 is further configured to analyze the position information of each component placed on the chip board in the (n-1)th round using the placement order, to obtain a first placed area corresponding to the i-th component before placement and a second placed area corresponding to the i-th component after placement on the chip board in the (n-1)th round; the i-th component is the i-th component placed among the placed components; i is an integer greater than or equal to 1; based on the size of the i-th component, the first placed area is adjusted to obtain the starting placement area of ​​the i-th component on the chip board in the (n-1)th round; based on the size of the (i+1)-th component, the second placed area is adjusted to obtain the ending placement area of ​​the i-th component on the chip board in the (n-1)th round.

[0160] In some embodiments, the adjustment module 603 is further configured to expand the first placed area outward using the size of the i-th component in the (n-1)th round to obtain a first intermediate area, and determine the area on the chip board other than the first intermediate area as the starting placement area of ​​the i-th component in the (n-1)th round on the chip board; and / or, expand the second placed area outward using the size of the (n-1)th (i+1)th component in the (n-1)th round to obtain a second intermediate area, and determine the area on the chip board other than the second intermediate area as the ending placement area of ​​the i-th component in the (n-1)th round on the chip board.

[0161] In some embodiments, the adjustment module 603 is further configured to compare the area of ​​the end placement area with the area of ​​the start placement area to obtain an area comparison score; and to determine the area comparison score as the placement score of each placed component on the chip board in the (n-1)th round.

[0162] In some embodiments, the adjustment module 603 is further configured to, based on the placement score of each component placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, reduce the placement distance between the j-th component and the k-th component on the chip board in the nth round; repeat the steps until the evaluation information of the nth round indicates that the layout diagram on the chip board meets the preset layout index; wherein, the j-th component is the j-th component placed on the chip board in the (n-1)th round; j is an integer greater than 1, and k is a positive integer less than j.

[0163] In some embodiments, the second acquisition module 602 is further configured to acquire connection information between the at least two components; based on the connection information and the position information of the components already placed on the chip board, perform layout routing on the chip board to obtain the layout diagram of the (n-1)th round; and use the preset layout index to perform performance evaluation on the layout diagram of the (n-1)th round to obtain the evaluation information of the (n-1)th round.

[0164] In some embodiments, the second acquisition module 602 is further configured to: evaluate the area parameters of the layout diagram in the (n-1)th round using the area index among the preset layout indicators to obtain a first evaluation parameter; evaluate the performance parameters of the layout diagram in the (n-1)th round using the performance index among the preset layout indicators to obtain a second evaluation parameter; evaluate the power consumption parameters of the layout diagram in the (n-1)th round using the power consumption index among the preset layout indicators to obtain a third evaluation parameter; and analyze the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter to obtain the evaluation information for the (n-1)th round.

[0165] In some embodiments, the first acquisition module 601 is further configured to acquire at least one standard element in the original component set whose attribute information does not satisfy the preset attribute; the adjustment module 603 is further configured to determine the connection relationship between the at least two standard elements and the at least two components; based on the connection relationship and the target layout diagram, place the at least one standard element on the chip board to obtain the placement information of the at least one standard element on the chip board; based on the placement information and the connection relationship, adjust the target layout diagram to obtain the adjusted target layout diagram.

[0166] It should be noted that the descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0167] It should be noted that, in the embodiments of this application, if the above-described chip layout method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a smartphone, tablet computer, etc. with a camera) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a magnetic disk, or an optical disk. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0168] Based on the same technical concept, this application provides a computer device for implementing the chip layout method described in the above method embodiments. Figure 7 This is a schematic diagram of the composition structure of a computer device provided in an embodiment of this application, such as... Figure 7 As shown, the computer device 700 includes: a processor 701, at least one communication bus 704, a communication interface 702, at least one external communication interface, and a memory 703. The communication interface 702 is configured to enable communication between these components. The communication interface 702 may include a display screen, and the external communication interface may include standard wired and wireless interfaces. The processor 701 is configured to execute a program in the memory to implement the chip layout method provided in the above embodiments.

[0169] Correspondingly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the chip layout methods described in the above embodiments.

[0170] Accordingly, in this application embodiment, a chip is also provided, the chip including programmable logic circuits and / or program instructions, which, when the chip is running, are used to implement any of the chip layout methods described in the above embodiments.

[0171] Accordingly, in this application embodiment, a computer program product is also provided, which, when executed by the processor of an electronic device, is used to implement any of the chip layout methods described in the above embodiments.

[0172] The descriptions of the chip layout apparatus, computer equipment, and storage medium embodiments above are similar to the descriptions of the method embodiments above, and have similar technical descriptions and beneficial effects as the corresponding method embodiments. Due to space limitations, the descriptions of the method embodiments above can be followed, and therefore will not be repeated here. For technical details not disclosed in the chip layout apparatus, computer equipment, and storage medium embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0173] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of the present application, the sequence number of the above-described processes does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0174] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0175] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0176] Furthermore, in the embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0177] Alternatively, if the integrated units described above in this application embodiment are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application embodiment, essentially or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application embodiment. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks. The above descriptions are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A chip layout method, characterized in that, The method includes: Obtain at least two components from the chip to be laid out; Obtain the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round. The evaluation information includes information obtained by performing a performance evaluation on the layout diagram corresponding to the components already placed on the chip board; where n is an integer greater than 1. The position information of the components already placed on the chip board in the (n-1)th round is evaluated to obtain the placement score of each component already placed on the chip board in the (n-1)th round; the placement score is determined based on the starting placement area and the ending placement area of ​​the components already placed in the (n-1)th round, the starting placement area is determined by expanding the first placement area based on the size of the i-th component in the (n-1)th round, and the ending placement area is determined by expanding the second placement area based on the size of the (i+1)-th component in the (n-1)th round; Based on the placement score of each component placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the distance between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index. The layout diagram on the chip board that meets the preset layout indicators is determined as the target layout diagram of the chip to be laid out.

2. The method according to claim 1, characterized in that, The process of obtaining at least two components from the chip to be laid out includes: Obtain the circuit diagram corresponding to the chip to be laid out; Determine the original set of components in the circuit diagram; In the original set of components, at least two components whose attribute information satisfies the preset attributes are identified.

3. The method according to claim 1, characterized in that, The step of adjusting the relative positional relationship between two adjacent components placed on the chip board in the nth round, based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index, includes: Based on the placement score of each component placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the relative positional relationship between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index. Wherein, the placement area of ​​the target component on the chip board in the nth round is smaller than the placement area of ​​the components already placed on the chip board in the (n-1)th round; the target component is the same component as the component already placed on the chip board in the (n-1)th round among the components already placed on the chip board in the nth round.

4. The method according to claim 1, characterized in that, The evaluation of the position information of the components already placed on the chip board in the (n-1)th round, to obtain the placement score of each component already placed on the chip board in the (n-1)th round, includes: Using the placement order of the at least two components, the position information of each component placed on the chip board in the (n-1)th round is analyzed to obtain the starting placement area and the ending placement area corresponding to each component placed on the chip board in the (n-1)th round. Based on the ending placement area and the starting placement area, the position information of each placed component on the chip board in the (n-1)th round is evaluated to obtain the placement score of each placed component on the chip board in the (n-1)th round.

5. The method according to claim 4, characterized in that, The method involves analyzing the position information of each component already placed on the chip board in the (n-1)th round using the placement order of the at least two components, to obtain the starting and ending placement areas corresponding to each component already placed on the chip board in the (n-1)th round, including: Using the aforementioned placement order, the position information of each component placed on the chip board in the (n-1)th round is analyzed to obtain the first placed area corresponding to the i-th component before placement and the second placed area corresponding to the i-th component after placement on the chip board in the (n-1)th round; the i-th component is the i-th component placed among the placed components; i is an integer greater than or equal to 1; Based on the size of the i-th component, the first placed area is adjusted to obtain the starting placement area of ​​the i-th component on the chip board in the (n-1)-th round; Based on the size of the (i+1)th component, the second placed area is adjusted to obtain the final placement area of ​​the i-th component on the chip board for the (n-1)th round.

6. The method according to claim 5, characterized in that, The step of adjusting the first placed area based on the size of the i-th component to obtain the initial placement area of ​​the i-th component on the chip board in the (n-1)-th round includes: Using the size of the i-th component in the (n-1)th round, the first placed area is expanded outward to obtain a first intermediate area, and the area on the chip board other than the first intermediate area is determined as the starting placement area of ​​the i-th component in the (n-1)th round on the chip board. And / or, adjusting the second placed area based on the size of the (i+1)th component to obtain the final placement area of ​​the i-th component on the chip board in the (n-1)th round includes: Using the size of the (n-1)th round (i+1)th component, the second already placed area is expanded outward to obtain a second intermediate area, and the area on the chip board other than the second intermediate area is determined as the final placement area of ​​the (n-1)th round (i)th component on the chip board.

7. The method according to any one of claims 4 to 6, characterized in that, The evaluation of the position information of each placed component on the chip board in the (n-1)th round, based on the ending placement area and the starting placement area, yields a placement score for each placed component on the chip board in the (n-1)th round, including: The area of ​​the final placement area is compared with the area of ​​the initial placement area to obtain an area comparison score; The area comparison score is determined as the placement score of each placed component on the chip board in the (n-1)th round.

8. The method according to any one of claims 3 to 6, characterized in that, The step of adjusting the relative positional relationship between two adjacent components placed on the chip board in the nth round, based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index, includes: Based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the placement distance between the j-th component and the k-th component on the chip board in the nth round is reduced. Repeat the above steps until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout index; Wherein, the j-th component is the j-th component that has been placed on the chip board in the (n-1)-th round; j is an integer greater than 1, and k is a positive integer less than j.

9. The method according to any one of claims 1 to 6, characterized in that, The process of obtaining the evaluation information for the (n-1)th round includes: Obtain the connection information between the at least two components; Based on the connection information and the position information of the components already placed on the chip board, layout and routing are performed on the chip board to obtain the layout diagram of the (n-1)th round; The performance of the layout diagram in the (n-1)th round is evaluated using the preset layout index to obtain the evaluation information for the (n-1)th round.

10. The method according to claim 9, characterized in that, The preset layout metrics are used to evaluate the performance of the layout diagram in the (n-1)th round, and the evaluation information for the (n-1)th round is obtained, including: The area parameters of the layout diagram in the (n-1)th round are evaluated using the area index in the preset layout index to obtain the first evaluation parameter; The performance parameters of the layout diagram in the (n-1)th round are evaluated using the performance indicators in the preset layout indicators to obtain the second evaluation parameters; The power consumption parameters of the layout diagram in the (n-1)th round are evaluated using the power consumption index in the preset layout index to obtain the third evaluation parameter; The evaluation information for the (n-1)th round is obtained by analyzing the first evaluation parameter, the second evaluation parameter, and the third evaluation parameter.

11. The method according to claim 2, characterized in that, The method further includes: In the original component set, at least one standard element whose attribute information does not satisfy the preset attribute is identified. Determine the connection relationship between the at least one standard element and the at least two components; Based on the connection relationship and the target layout diagram, at least one standard component is placed on the chip board to obtain the placement information of the at least one standard component on the chip board; Based on the placement information and the connection relationship, the target layout diagram is adjusted to obtain the adjusted target layout diagram.

12. A chip layout apparatus, characterized in that, The device includes: The first acquisition module is used to acquire at least two components in the chip to be laid out; The second acquisition module is used to acquire the position information of the components already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round. The evaluation information includes information obtained by performing a performance evaluation on the layout diagram corresponding to the components already placed on the chip board; where n is an integer greater than 1. An adjustment module is used to evaluate the position information of the components already placed on the chip board in the (n-1)th round, and obtain a placement score for each component already placed on the chip board in the (n-1)th round. The placement score is determined based on the starting and ending placement areas of the components already placed in the (n-1)th round. The starting placement area is determined by expanding the first placement area based on the size of the i-th component in the (n-1)th round, and the ending placement area is determined by expanding the second placement area based on the size of the (i+1)-th component in the (n-1)th round. Based on the placement score of each component already placed on the chip board in the (n-1)th round and the evaluation information of the (n-1)th round, the distance between two adjacent components placed on the chip board in the nth round is adjusted until the evaluation information of the nth round indicates that the layout on the chip board meets the preset layout indicators. The determining module is used to determine the layout diagram on the chip board that meets the preset layout index as the target layout diagram of the chip to be laid out.

13. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing computer-executable instructions, and the processor, when executing the computer-executable instructions in the memory, is able to implement the chip layout method according to any one of claims 1 to 11.

14. A computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which, when executed, enable the chip layout method according to any one of claims 1 to 11.

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