Light-emitting display device and driving method thereof

Abstract

The present invention relates to a light-emitting display device and a driving method thereof. The provided LED device includes: a display panel configured to display an image; and a data driver including a panel driving circuit for driving the display panel and a panel sensing circuit for sensing the display panel, wherein the panel driving circuit includes a first data voltage output circuit configured to output voltages to be applied to a first data line and a first reference line of the display panel to display black on a first sub-pixel included in the display panel.

Description

Technical Field

[0001] The present invention relates to a light-emitting display (LED) device and a driving method thereof. Background Art

[0002] With the development of information technology, the market for display devices as a medium connecting users and information is growing. Accordingly, display devices such as LEDs, quantum dot displays (QDDs), and liquid crystal displays (LCDs) are increasingly used.

[0003] Each of the above display devices includes: a display panel including sub-pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0004] In such a display device, when sub-pixels formed in the display panel are supplied with driving signals (e.g., a scan signal and a data signal), one of the selected sub-pixels can transmit light or can directly emit light, thereby displaying an image. Summary of the Invention

[0005] Accordingly, the present invention relates to an LED device and a driving method thereof that substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art.

[0006] An object of the present invention is to separately change a voltage applied to a pixel to represent higher brightness and to control a reference voltage and data bits in units of bits (the same number of bits) to expand a gradation expression area.

[0007] Other advantages, objects, and features of the present invention will be partly set forth in the description that follows and, in part, will be obvious to those of ordinary skill in the art after examination of the following, or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended written description and claims and drawings.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, an LED device includes a display panel configured to display an image and a data driver including a panel driving circuit for driving the display panel and a panel sensing circuit for sensing the display panel, wherein the panel driving circuit includes a first data voltage output circuit configured to output voltages to be applied to a first data line and a first reference line of the display panel to display black on a first sub-pixel included in the display panel.

[0009] The first data voltage output circuit can be a circuit for driving first sub-pixels included in sub-pixels in a display panel that do not participate in image display, and can output a voltage for displaying black instead of the data voltage required for image display during a data writing period of the display panel.

[0010] The voltage output from the first data voltage output circuit can be shared through a switch included in the data driver and electrically connecting a first data line and a first reference line to each other.

[0011] The data driver can include a switch configured to send the voltage output from the data voltage output circuit included in the panel driving circuit to a sensing channel and a data channel during a data writing period of the display panel.

[0012] The switch can include: a first switch group configured to perform a switching operation to send the voltage output from the data voltage output circuit to the sensing channel; and a second switch group configured to perform a switching operation to output the voltage output from the data voltage output circuit through the data channel.

[0013] The data voltage output circuit can alternately output a first voltage and a second voltage having different levels during a data writing period of the display panel, and at least one switch included in the first switch group can send the first voltage to the data channel and the second voltage to the sensing channel.

[0014] The data driver can further include an output circuit provided at an output terminal of the data voltage output circuit to alternately output a first voltage and a second voltage having different levels during a data writing period of the display panel.

[0015] The output circuit can include an amplifier, a first voltage output switch configured to output a first voltage from a first voltage source, a second voltage output switch configured to output a second voltage from a second voltage source, an output capacitor charged with the voltages output through the first voltage output switch and the second voltage output switch, and a third switch group configured to perform a switching operation to apply the voltage charged in the output capacitor to a non-inverting terminal of the amplifier.

[0016] The voltage for displaying black can vary according to the state of elements included in the display panel.

[0017] In another aspect of the present invention, a driving method of an LED device, the LED device including a display panel for displaying an image and a data driver, the data driver including a panel driving circuit for driving the display panel and a panel sensing circuit for sensing the display panel, the method including the steps of: applying a voltage to a first data line and a first reference line of the display panel to display black on a first sub-pixel included in the display panel, and applying data voltages to second to fourth data lines of the display panel to display an image on second to fourth sub-pixels included in the display panel.

[0018] It should be understood that the foregoing general description and the following detailed description of the present invention are both exemplary and explanatory, and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. In the drawings:

[0020] Figure 1 is a block diagram schematically illustrating the configuration of an LED device, and Figure 2 is Figure 1 a schematic block diagram of the sub-pixel shown;

[0021] Figure 3A and Figure 3B is a diagram illustrating an example of the layout of an in-panel gate (GIP) type scan driver, and Figure 4 and Figure 5 is a block diagram illustrating an example of the configuration of a device associated with the GIP type scan driver;

[0022] Figure 6 and Figure 7 is a diagram of a sub-pixel having a compensation circuit, Figure 8 is Figure 6 or Figure 7 a schematic diagram of the sub-pixel and the data driver of, and Figure 9 is Figure 8 a detailed diagram of the panel sensing circuit shown;

[0023] Figure 10 is a block diagram of an LED device according to a first embodiment of the present invention, and Figures 11 to 14 is a diagram illustrating a part of the sensing operation of the LED device according to the first embodiment of the present invention;

[0024] Figure 15 is a circuit diagram of an LED device according to a second embodiment of the present invention, and Figure 16 and Figure 17FIG. is a diagram showing a part of a data writing period of an LED device according to a second embodiment of the present invention;

[0025] Figure 18 FIG. is a circuit diagram of an LED device according to a third embodiment of the present invention, and Figures 19 to 21 FIG. is a diagram showing a part of a data writing period of an LED device according to a third embodiment of the present invention;

[0026] Figure 22 FIG. is a circuit diagram of an LED device according to a fourth embodiment of the present invention, Figure 23 is Figure 22 a detailed diagram of a part of the circuit shown, and Figure 24 FIG. is a diagram showing a part of a data writing period of an LED device according to a fourth embodiment of the present invention; and

[0027] Figure 25 and Figure 26A and Figure 26B FIG. is a diagram showing the effects of the embodiments of the present invention. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to the preferred embodiments of the present invention, which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0029] The display device according to the present invention can be implemented as a television, a video player, a personal computer (PC), a home theater, an automotive electronic device, or a smart phone, but is not limited thereto. The display device according to the present invention can be implemented by an LED, a QDD, or an LCD. For convenience of description, an LED device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be described below as an example of the display device according to the present invention.

[0030] Figure 1 FIG. is a block diagram schematically showing the configuration of an LED device, and Figure 2 is Figure 1 a schematic block diagram of a sub-pixel shown.

[0031] As Figure 1 and Figure 2 shown, the LED device may include an image provider 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply 180.

[0032] An image provider (set system or host system) 110 may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image provider 110 may supply a data signal and various driving signals to a timing controller 120.

[0033] The timing controller 120 may output a gate timing control signal GDC for controlling an operation timing of a scan driver 130, a data timing control signal DDC for controlling an operation timing of a data driver 140, and various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync). The timing controller 120 may supply the data signal DATA supplied from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0034] The scan driver 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 may supply the scan signal to sub-pixels included in a display panel 150 through gate lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be directly formed on the display panel 150 in a GIP manner, but is not limited thereto.

[0035] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the obtained digital data signal into an analog data voltage based on a gamma reference voltage, and output the converted analog data voltage. The data driver 140 may supply the data voltage to sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0036] A power supply 180 may generate a first power having a high potential and a second power having a low potential based on an external input voltage supplied from the outside, and output the generated first power and second power through a first power line EVDD and a second power line EVSS, respectively. The power supply 180 may generate and output a voltage required to drive the scan driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) or a voltage required to drive the data driver 140 (e.g., a drain voltage including a drain voltage and a half-drain voltage), as well as the first power and the second power.

[0037] The display panel 150 can display an image in response to a driving signal including a scan signal and a data voltage, a first power, and a second power. Sub-pixels of the display panel 150 emit light directly. The display panel 150 can be manufactured based on a rigid or flexible substrate such as glass, silicon, polyimide, etc. The sub-pixels that emit light can include red sub-pixels, green sub-pixels, and blue sub-pixels, or can include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.

[0038] For example, a sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and can include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. The sub-pixel SP used in the LED device emits light directly and thus has a complex circuit configuration. In addition, there are various compensation circuits for compensating not only the deterioration of the organic light-emitting diode that emits light but also the deterioration of the driving transistor that supplies a driving current to the organic light-emitting diode. In this regard, it should be noted that the sub-pixel SP is simply illustrated in a block form only.

[0039] Meanwhile, the timing controller 120, the scan driver 130, the data driver 140, etc. have been described as having separate configurations. However, according to the implementation method of the LED device, one or more of the timing controller 120, the scan driver 130, and the data driver 140 can be integrated into one IC.

[0040] Figure 3A and Figure 3B are diagrams illustrating an example of the layout of the GIP type scan driver, and Figure 4 and Figure 5 are block diagrams illustrating an example of the configuration of a device associated with the GIP type scan driver.

[0041] As Figure 3A and Figure 3B shown, the GIP type scan drivers 130a and 130b are disposed in the non-display area NA of the display panel 150. As Figure 3A shown, the scan drivers 130a and 130b can be disposed in the left and right portions of the non-display area NA of the display panel 150. Alternatively, as Figure 3B shown, the scan drivers 130a and 130b can be disposed in the upper and lower portions of the non-display area NA of the display panel 150.

[0042] Although the scan drivers 130a and 130b have been illustrated and disclosed as examples as being disposed in the non-display areas NA on the left and right sides or the upper and lower sides of the display area AA, they may also be disposed only in the non-display area NA at one of the left, right, upper, and lower sides of the display area AA.

[0043] As Figure 4 shown, the GIP type scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal Clk and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180. The clock signal Clk may be generated in the form of K different phases such as two-phase, four-phase, and eight-phase (where K is an integer greater than or equal to 2).

[0044] The shift register 131 may operate based on the signals Clk and Vst output from the level shifter 135 and output scan signals Scan[1] to Scan[m] that can turn on or off transistors formed in the display panel. The shift register 131 may be formed in a thin film form on the display panel in a GIP manner. Therefore, Figure 3A and Figure 3B the scan drivers 130a and 130b formed in the non-display area NA of the display panel 150 as shown may correspond to the shift register 131.

[0045] As Figure 4 and Figure 5 shown, different from the shift register 131, the level shifter 135 may be independently formed in the form of an IC or may be included in the power supply 180. However, this is merely an example, and the level shifter 135 is not limited thereto.

[0046] Figure 6 and Figure 7 are diagrams of sub-pixels having a compensation circuit, Figure 8 is Figure 6 or Figure 7 a schematic diagram of a sub-pixel and a data driver, and Figure 9 is Figure 8 a detailed diagram of the panel sensing circuit shown.

[0047] As Figure 6 shown, one sub-pixel SP may include a switching transistor TR, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light emitting diode OLED.

[0048] The driving transistor DT may have a gate electrode connected to the first electrode of the capacitor CST, a first electrode connected to the first power line EVDD, and a second electrode connected to the anode electrode of the organic light-emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may have an anode electrode connected to the second electrode of the driving transistor DT and a cathode electrode connected to the second power line EVSS.

[0049] The switching transistor TR may have a gate electrode connected to the 1A gate line GL1a included in the first gate line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The switching transistor TR may be turned on in response to a scan signal transmitted through the 1A gate line GL1a.

[0050] The sensing transistor ST may have a gate electrode connected to the 1B gate line GL1b included in the first gate line GL1, a first electrode connected to the first reference line REF1, and a second electrode connected to the anode electrode of the organic light-emitting diode OLED. The sensing transistor ST may be turned on in response to a sensing signal transmitted through the 1B gate line GL1b.

[0051] The sensing transistor ST is an additional compensation circuit provided for compensating for the deterioration (in terms of threshold voltage, etc.) of the driving transistor DT or the organic light-emitting diode OLED. The sensing transistor ST may implement physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST may operate to obtain a sensing voltage through a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED. The sensing voltage may be obtained during the sensing period of the display panel.

[0052] Meanwhile, although the first gate line GL1 may be divided into the 1A gate line GL1a and the 1B gate line GL1b as an example, the 1A gate line GL1a and the 1B gate line GL1b may be integrated into one as Figure 7 shown. That is, the switching transistor TR and the sensing transistor ST may be commonly connected to the first gate line GL1 and turned on or off simultaneously.

[0053] As Figure 8As shown, the data driver 140 may include a panel driving circuit 141 configured to drive the sub-pixels SP and a panel sensing circuit 145 configured to sense the sub-pixels SP. The panel driving circuit 141 may be connected to the first data line DL1 through the first data channel DCH1, and the panel sensing circuit 145 may be connected to the first reference line REF1 through the first sensing channel SIO1. The panel driving circuit 141 may output a data voltage for driving the sub-pixels SP through the first data channel DCH1. The panel sensing circuit 145 may obtain a sensing voltage from the sub-pixels SP through the first sensing channel SIO1.

[0054] As Figure 9 shown, the panel sensing circuit 145 may include a sampling circuit SAM and an analog-to-digital converter ADC. The sampling circuit SAM and the analog-to-digital converter ADC may operate during the sensing period of the display panel.

[0055] The sampling circuit SAM may perform a sampling operation to obtain a sensing voltage through the first reference line REF1. When the voltage or current reaches a specific condition (sensing condition) after the sensing transistor ST included in the sub-pixel SP is turned on, the sampling circuit SAM may be turned on to obtain the voltage or current by a sampling method. The analog-to-digital converter ADC may convert the analog sensing voltage obtained through the sampling circuit SAM into a digital sensing voltage and output the converted voltage.

[0056] As described above, the panel sensing circuit 145 may obtain a sensing voltage for compensating for the deterioration of the driving transistor DT or the organic light-emitting diode OLED included in the sub-pixel SP through the first reference line REF1, and output the obtained sensing voltage. The sensing voltage output from the panel sensing circuit 145 may be transmitted to the timing controller 120. The timing controller 120 may determine whether the driving transistor DT or the organic light-emitting diode OLED included in the sub-pixel SP has deteriorated based on the sensing voltage and perform a compensation operation for compensating for the deterioration.

[0057] Figure 10 is a block diagram of an LED device according to a first embodiment of the present invention, and Figures 11 to 14 is a diagram illustrating a part of the sensing operation of the LED device according to the first embodiment of the present invention.

[0058] As Figure 10 shown, a plurality of pixels may be provided in the display area AA of the display panel 150. One pixel P may include a red sub-pixel SPR, a white sub-pixel SPW, a green sub-pixel SPG, and a blue sub-pixel SPB.

[0059] The red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB can be separately and individually connected to the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4, respectively. However, the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB can be commonly connected to the first reference line REF1 to share the first reference line REF1. That is to say, the total of four sub-pixels SPR, SPW, SPG, and SPB included in one pixel P can have a structure of being connected to the panel sensing circuit 145 of the data driver 140 through one first reference line REF1.

[0060] The data driver 140 can be connected to the display panel 150. The panel sensing circuit 145 of the data driver 140 can obtain a sensing voltage from a selected sub-pixel among the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB through the first reference line REF1.

[0061] The panel driving circuit of the data driver 140 can include a red data voltage output unit (or circuit) DAC[R], a white data voltage output unit (or circuit) DAC[W], a green data voltage output unit (or circuit) DAC[G], and a blue data voltage output unit (or circuit) DAC[B]. The red data voltage output unit DAC[R], the white data voltage output unit DAC[W], the green data voltage output unit DAC[G], and the blue data voltage output unit DAC[B] can output data voltages during a data writing period of the display panel 150.

[0062] The red data voltage output unit DAC[R] can output a red data voltage through the first data channel DCH1. The red data voltage can be applied to the red sub-pixel SPR connected to the first data line DL1. The white data voltage output unit DAC[W] can output a white data voltage through the second data channel DCH2. The white data voltage can be applied to the white sub-pixel SPW connected to the second data line DL2. The green data voltage output unit DAC[G] can output a green data voltage through the third data channel DCH3. The green data voltage can be applied to the green sub-pixel SPG connected to the third data line DL3. The blue data voltage output unit DAC[B] can output a blue data voltage through the fourth data channel DCH4. The blue data voltage can be applied to the blue sub-pixel SPB connected to the fourth data line DL4.

[0063] The red data voltage output unit DAC[R], white data voltage output unit DAC[W], green data voltage output unit DAC[G], and blue data voltage output unit DAC[B] included in the panel driving circuit of the data driver 140 may output a red data voltage, a white data voltage, a green data voltage, and a blue data voltage, respectively, during a first image implementation period of the display panel 150. The red data voltage, white data voltage, green data voltage, and blue data voltage are voltages for placing red sub-pixels, white sub-pixels, green sub-pixels, and blue sub-pixels in a light-emitting state (or display state) during a display period of the display panel 150.

[0064] In addition, at least one of the data voltage output units, namely the red data voltage output unit DAC[R], white data voltage output unit DAC[W], green data voltage output unit DAC[G], and blue data voltage output unit DAC[B], included in the panel driving circuit of the data driver 140 may output a black voltage during a second image implementation period of the display panel 150, instead of a red data voltage, a white data voltage, a green data voltage, or a blue data voltage. The black voltage is a voltage for placing a specific sub-pixel in a non-light-emitting state (black display state or non-display state) during a display period of the display panel 150.

[0065] The first image implementation period may be defined as a period for implementing an image to be displayed on the display panel 150 in a high dynamic range (HDR), and the second image implementation period may be defined as a period for implementing an image to be displayed on the display panel 150 in a standard dynamic range (SDR).

[0066] As Figures 11 to 14 shown, at least one of the data voltage output units, namely the red data voltage output unit DAC[R], white data voltage output unit DAC[W], green data voltage output unit DAC[G], and blue data voltage output unit DAC[B], included in the panel driving circuit of the data driver 140 may output a black voltage during a data writing period included in the second image implementation period.

[0067] Except for the data voltage output unit that outputs the black voltage, the remaining data voltage output units may output data voltages for placing the sub-pixels in a light-emitting state (or display state).

[0068] As Figure 11 shown, the black voltage may be output from the red data voltage output unit DAC[R] and may be sent through a first data channel DCH1 and a first sensing channel SIO1. As Figure 12As shown, the black voltage can be output from the white data voltage output unit DAC[W] and can be sent through the second data channel DCH2 and the first sensing channel SIO1. As Figure 13 As shown, the black voltage can be output from the green data voltage output unit DAC[G] and can be sent through the third data channel DCH3 and the first sensing channel SIO1. As Figure 14 As shown, the black voltage can be output from the blue data voltage output unit DAC[B] and can be sent through the fourth data channel DCH4 and the first sensing channel SIO1.

[0069] From the above description, it can be seen that the black voltage is not applied from a separate voltage source provided internally or externally, but can be output from one of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] included in the panel driving circuit. Additionally, the black voltage can be applied to different types of lines such that the voltage is shared when the data line and the reference line are electrically connected to each other (such that there are two output lines).

[0070] In this way, when using the data voltage output unit connected to the sub-pixel that is not used during the data writing period included in the second image implementation period of the display panel 150 to apply the black voltage as the reference voltage type, there is an advantage that the internal circuit of the data driver 140 can be simplified. Additionally, since the data voltage output unit capable of changing the voltage is used, there is an advantage that the reference voltage can be controlled for each individual pixel. Additionally, since the previously used separate voltage source can be removed, there is an advantage that the power consumption can be reduced due to the removal / deletion of the configuration using the constant power source.

[0071] Hereinafter, a detailed configuration of using the data voltage output unit connected to the sub-pixel that is not used during the data writing period included in the second image implementation period of the display panel 150 to output the black voltage will be given. However, in the following description, the parts that are particularly illustrated or changed compared to the first embodiment will be mainly described.

[0072] Figure 15 is a circuit diagram of an LED device according to a second embodiment of the present invention, and Figure 16 and Figure 17 is a diagram illustrating a part of the data writing period of the LED device according to the second embodiment of the present invention.

[0073] As Figure 15 shown, the panel driving circuit of the data driver 140 may include data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] and a first switch group SW1 to SW4.

[0074] The first switch group SW1 to SW4 may include a first switch SW1 to a fourth switch SW4. The first switch SW1 to the fourth switch SW4 may be used to send a black voltage output from one of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to a first reference line REF1 connected to a first sensing channel SIO1. Accordingly, one of the first switch SW1 to the fourth switch SW4 may be turned on during a data writing period of the display panel.

[0075] The first switch SW1 may have a first electrode connected to the red data voltage output unit DAC[R], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to a first control line to which a first switch control signal is sent. The second switch SW2 may have a first electrode connected to the white data voltage output unit DAC[W], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to a second control line to which a second switch control signal is sent. The third switch SW3 may have a first electrode connected to the green data voltage output unit DAC[G], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to a third control line to which a third switch control signal is sent. The fourth switch SW4 may have a first electrode connected to the blue data voltage output unit DAC[B], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to a fourth control line to which a fourth switch control signal is sent.

[0076] Hereinafter, an example in which the green data voltage output unit DAC[G] is used as a circuit for outputting a black voltage will be used to illustrate and describe a driving method of the second embodiment and a part of the operation of the device according to the driving method. That is, in this example, it is assumed that the green sub-pixel SPG and the green data voltage output unit DAC[G] are driven to display only a black gradation without participating in the image display of the display panel.

[0077] As Figure 16 and Figure 17 shown, during a data writing period of the display panel, the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] may output 2.3V, 3V, and 2.2V, respectively, as data voltages for representing a specific gray level. The data voltages may be applied to the sub-pixels SPR, SPW, and SPB within one horizontal time 1H in which the first scan signal Scan1 is generated as a logic high H.

[0078] When the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] output data voltages representing specific gray levels, the first switch SW1, the second switch SW2, and the fourth switch SW4 can be turned off. The first switch SW1, the second switch SW2, and the fourth switch SW4 can remain off during the driving time, which includes the time when the first scan signal Scan1 is generated as logic high H while the first switch control signal Sw1, the second switch control signal Sw2, and the fourth switch control signal Sw4 are applied as logic low L.

[0079] During the data writing period of the display panel, the green data voltage output unit DAC[G] can output 1V as the black voltage for representing the black gray level. When the green data voltage output unit DAC[G] outputs the black voltage for representing the black gray level, the third switch SW3 can be turned on. The third switch SW3 can remain on for one horizontal time 1H, during which the first scan signal Scan1 is generated as logic high H while the third switch control signal Sw3 is applied as logic high H.

[0080] Referring to the above operation, the black voltage output from the green data voltage output unit DAC[G] can be sent to the third data line DL3 connected to the green sub-pixel SPG. Since the third data channel DCH3 and the first sensing channel SIO1 are electrically connected to each other through the turned-on third switch SW3, the black voltage output from the green data voltage output unit DAC[G] can be sent to the first reference line REF1.

[0081] In this case, the switching transistor TR and the sensing transistor ST included in the green sub-pixel SPG can be turned on by the first scan signal Scan1. Therefore, the same voltage (Vg = Vs or Vgs = 0) can be applied to the gate electrode (1V) and the source electrode (1V) of the driving transistor DT. As a result, the green sub-pixel SPG can display the black gray level.

[0082] Figure 18 is a circuit diagram of an LED device according to the third embodiment of the present invention, and Figures 19 to 21 is a diagram illustrating a part of the data writing period of the LED device according to the third embodiment of the present invention.

[0083] As Figure 18 shown, the panel driving circuit of the data driver 140 can include data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B], a first inverting switch group / SW1 to / SW4, and a second switch group SW1 to SW4.

[0084] The first inverter switch group / SW1 to / SW4 may include a first inverter switch / SW1 to a fourth inverter switch / SW4. The first inverter switch / SW1 to the fourth inverter switch / SW4 may be used to send the black voltage output from one of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to the first reference line REF1 connected to the first sensing channel SIO1. Accordingly, one of the first inverter switch / SW1 to the fourth inverter switch / SW4 may be turned on during the data writing period of the display panel.

[0085] The first inverter switch / SW1 may have a first electrode connected to the red data voltage output unit DAC[R], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the first control line to which the first switch control signal is sent. The second inverter switch / SW2 may have a first electrode connected to the white data voltage output unit DAC[W], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the second control line to which the second switch control signal is sent. The third inverter switch / SW3 may have a first electrode connected to the green data voltage output unit DAC[G], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the third control line to which the third switch control signal is sent. The fourth inverter switch / SW4 may have a first electrode connected to the blue data voltage output unit DAC[B], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the fourth control line to which the fourth switch control signal is sent.

[0086] The second switch group SW1 to SW4 may include a first switch SW1 to a fourth switch SW4. The first switch SW1 to the fourth switch SW4 may be used to send the data voltage or the black voltage output from the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to the data lines DL1 to DL4 connected to the data channels DCH1 to DCH4, respectively. The first switch SW1 to the fourth switch SW4 may operate contrary to the first inverter switch / SW1 to the fourth inverter switch / SW4. Accordingly, since the first switch SW1 to the fourth switch SW4 operates contrary to the first inverter switch / SW1 to the fourth inverter switch / SW4, all of the first switch SW1 to the fourth switch SW4 except one may be turned on during the data writing period of the display panel.

[0087] The first switch SW1 may have a first electrode connected to the red data voltage output unit DAC[R], a second electrode connected to the first data channel DCH1, and a control electrode connected to the first control line to which the first switch control signal is sent. The second switch SW2 may have a first electrode connected to the white data voltage output unit DAC[W], a second electrode connected to the second data channel DCH2, and a control electrode connected to the second control line to which the second switch control signal is sent. The third switch SW3 may have a first electrode connected to the green data voltage output unit DAC[G], a second electrode connected to the third data channel DCH3, and a control electrode connected to the third control line to which the third switch control signal is sent. The fourth switch SW4 may have a first electrode connected to the blue data voltage output unit DAC[B], a second electrode connected to the fourth data channel DCH4, and a control electrode connected to the fourth control line to which the fourth switch control signal is sent.

[0088] Hereinafter, an example in which the green data voltage output unit DAC[G] is used as a circuit for outputting a black voltage will be used to illustrate and describe a part of the driving method of the third embodiment and the operation of the device according to the driving method. That is, in this example, it is assumed that the green sub-pixel SPG and the green data voltage output unit DAC[G] are driven to display only the black gradation and do not participate in the image display of the display panel.

[0089] As Figures 19 to 21 shown, during the data writing period of the display panel, the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] may output 2.3V, 3V, and 2.2V, respectively, as data voltages for representing a specific gray level. The data voltages may be applied to the sub-pixels SPR, SPW, and SPB within one horizontal time 1H when the first scan signal Scan1 is generated as a logic high H.

[0090] When the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] output data voltages representing a specific gray level, the first inverter switch / SW1, the second inverter switch / SW2, and the fourth inverter switch / SW4 may be turned off. The first inverter switch / SW1, the second inverter switch / SW2, and the fourth inverter switch / SW4 may remain off during the driving time, which includes the time when the first scan signal Scan1 is generated as a logic high H when the first switch control signal Sw1, the second switch control signal Sw2, and the fourth switch control signal Sw4 are applied as a logic high H.

[0091] During the data writing period of the display panel, the green data voltage output unit DAC[G] may alternately output a first voltage (0V) and a second voltage (1V) as a black voltage for representing black grayscale. When the green data voltage output unit DAC[G] changes and outputs a black voltage for representing black grayscale, the third switch SW3 and the third inverter switch / SW3 may alternately turn on / off, such that the switches are in opposite on / off states.

[0092] The third switch SW3 and the third inverter switch / SW3 may alternately turn on / off at least once, such that the switches are in opposite on / off states within one horizontal time 1H, in which the first scan signal Scan1 is generated as logic high H when the third switch control signal Sw3 is alternately applied as logic high H and logic low L. Thus, when the third switch SW3 is turned on as shown in Figure 19 it can turn off the third inverter switch / SW3, and when the third switch SW3 is turned off as shown in Figure 20 it can turn on the third inverter switch / SW3.

[0093] Meanwhile, in order to accurately implement black grayscale, after one horizontal time 1H in which the first scan signal Scan1 is generated as logic high H, the third switch control signal Sw3 may be alternately applied as logic high H and logic low L at least once. However, the present invention is not limited thereto.

[0094] Referring to the above operations, the black voltage of 0V output from the green data voltage output unit DAC[G] may be sent to the third data line DL3 connected to the green sub-pixel SPG through the turned-on third switch SW3, and may not be sent to the first reference line REF1. Additionally, the black voltage of 1V output from the green data voltage output unit DAC[G] may be sent to the first reference line REF1 connected to the first sensing channel SIO1 through the turned-on third inverter switch / SW3, and may not be sent to the third data line DL3.

[0095] In this case, the switching transistor TR and the sensing transistor ST included in the green sub-pixel SPG may be turned on by the first scan signal Scan1. Thus, different voltages (Vg < Vs or Vgs < 0) may be applied to the gate electrode (0V) and the source electrode (1V) of the driving transistor DT. As a result, the voltage applied to the third data line DL3 is lower than the voltage applied to the first reference line REF1. Therefore, when the threshold voltage Vth of the driving transistor DT moves to the negative voltage range due to NBTIS stress, the green sub-pixel SPG may display black grayscale.

[0096] Meanwhile, in the above description, an example is given in which the green sub-pixel SPG connected to the green data voltage output unit DAC[G] displays black grayscale in at least two horizontal times, and thus the waveform for the switching operation of the third switch SW3 is illustrated and described as receiving 0V, 1V, 0V, and 1V. Therefore, it should be noted that when the green sub-pixel SPG connected to the green data voltage output unit DAC[G] displays black grayscale in one horizontal time 1H, the third switch SW3 only performs one conduction and cut-off operation.

[0097] Figure 22 is a circuit diagram of an LED device according to a fourth embodiment of the present invention, Figure 23 is Figure 22 a detailed diagram of a part of the circuit shown, and Figure 24 is a diagram illustrating a part of a data writing period of an LED device according to a fourth embodiment of the present invention.

[0098] As Figure 22 and Figure 23 shown, the panel driving circuit of the data driver 140 may include data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B], a first switch group SW1c to SW4c, a second switch group SW1a to SW4a, and an output circuit unit OUC.

[0099] The first switch group SW1c to SW4c may include a 1C switch SW1c to a 4C switch SW4c. The 1C switch SW1c to the 4C switch SW4c may be used to send a black voltage output from one of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to the first reference line REF1 connected to the first sensing channel SIO1. Therefore, one of the 1C switch SW1c to the 4C switch SW4c may be turned on during the data writing period of the display panel.

[0100] The 1C switch SW1c has a first electrode connected to the red data voltage output unit DAC[R], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the 1C control line to which the 1C switch control signal is sent. The 2C switch SW2c has a first electrode connected to the white data voltage output unit DAC[W], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the 2C control line to which the 2C switch control signal is sent. The 3C switch SW3c has a first electrode connected to the green data voltage output unit DAC[G], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the 3C control line to which the 3C switch control signal is sent. The 4C switch SW4c has a first electrode connected to the blue data voltage output unit DAC[B], a second electrode connected to the first sensing channel SIO1, and a control electrode connected to the 4C control line to which the 4C switch control signal is sent.

[0101] The second switch group SW1a to SW4a may include the 1A switch SW1a to the 4A switch SW4a. The 1A switch SW1a to the 4A switch SW4a may be used to send each of the data voltages and the black voltage output from the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to the output circuit unit OUC.

[0102] The 1A switch SW1a may have a first electrode connected to the red data voltage output unit DAC[R], a second electrode connected to the first electrode of the 1B switch SW1b included in the output circuit unit OUC, and a control electrode connected to the 1A control line to which the 1A switch control signal is sent. The 2A switch SW2a may have a first electrode connected to the white data voltage output unit DAC[W], a second electrode connected to the first electrode of the 2B switch SW2b included in the output circuit unit OUC, and a control electrode connected to the 2A control line to which the 2A switch control signal is sent. The 3A switch SW3a may have a first electrode connected to the green data voltage output unit DAC[G], a second electrode connected to the first electrode of the 3B switch SW3b included in the output circuit unit OUC, and a control electrode connected to the 3A control line to which the 3A switch control signal is sent. The 4A switch SW4a may have a first electrode connected to the blue data voltage output unit DAC[B], a second electrode connected to the first electrode of the 4B switch SW4b included in the output circuit unit OUC, and a control electrode connected to the 4A control line to which the 4A switch control signal is sent.

[0103] The output circuit unit OUC may include amplifiers AMP1 to AMP4, third switch groups SW1b to SW4b, first voltage output switches SW1bb to SW4bb respectively for outputting a first voltage, second voltage output switches SW1aa to SW4aa respectively for outputting a second voltage, and corresponding output capacitors C1 to C4.

[0104] In the output circuit unit OUC, the third switch groups SW1b to SW4b, the first voltage output switches SW1bb to SW4bb respectively for outputting a first voltage, the second voltage output switches SW1aa to SW4aa respectively for outputting a second voltage, and the output capacitors C1 to C4 are circuits provided at the output terminals of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] to alternately output a first voltage and a second voltage having different levels.

[0105] The amplifiers AMP1 to AMP4 may include a first amplifier AMP1 to a fourth amplifier AMP4. The first amplifier AMP1 to the fourth amplifier AMP4 may be used to amplify the data voltage or the black voltage output through the third switch groups SW1b to SW4b, and output the amplified data voltage or black voltage through the first data channel DCH1 to the fourth data channel DCH4 respectively. For reference, Figure 22 The illustrated amplifiers AMP1 to AMP4 may be included in the output terminals of the data voltage output units DAC[W], DAC[R], DAC[G], and DAC[B] in the above first to third embodiments.

[0106] The first voltage output switches SW1bb to SW4bb respectively for outputting a first voltage may each have a first electrode connected to a first voltage source V1, a second electrode connected to one of the output capacitors C1 to C4, and a control electrode connected to a first voltage output control line. The first voltage output switches SW1bb to SW4bb may be turned on or off simultaneously in response to a first B switch control signal to a fourth B switch control signal applied through a 1B control line to a 4B control line. That is, the first voltage output switches SW1bb to SW4bb may be turned on or off simultaneously with the switches included in the third switch groups SW1b to SW4b.

[0107] Second voltage output switches SW1aa to SW4aa respectively for outputting a second voltage may each have a first electrode connected to a second voltage source V2, a second electrode connected to one of output capacitors C1 to C4, and a control electrode connected to a second voltage output control line. Second voltage output switches SW1aa to SW4aa may be turned on or off simultaneously in response to first A switch control signals to fourth A switch control signals applied through first A control lines to fourth A control lines. That is, second voltage output switches SW1aa to SW4aa may be turned on or off simultaneously with switches included in second switch group SW1a to SW4a. At the same time, the level of the second voltage applied to second voltage source V2 may be higher than the level of the first voltage applied to first voltage source V1.

[0108] One end of each of first output capacitor C1 to fourth output capacitor C4 may be connected to each corresponding first voltage output switch among first voltage output switches SW1bb to SW4bb and each corresponding second voltage output switch among second voltage output switches SW1aa to SW4aa, and the other end of each of first output capacitor C1 to fourth output capacitor C4 may be connected to each corresponding first electrode among first electrodes of first B switch SW1b to fourth B switch SW4b included in third switch group SW1b to SW4b. First output capacitor C1 to fourth output capacitor C4 may be charged using the first voltage, the second voltage, or a voltage difference between the first voltage and the second voltage.

[0109] Third switch group SW1b to SW4b may include first B switch SW1b to fourth B switch SW4b. First B switch SW1b to fourth B switch SW4b may be used to apply data voltage or black voltage output from first A switch SW1a to fourth A switch SW4a to non-inverting terminals (+) of first amplifier AMP1 to fourth amplifier AMP4, respectively. Additionally, first B switch SW1b to fourth B switch SW4b may be used to apply the first voltage or the second voltage output from first output capacitor C1 to fourth output capacitor C4 to non-inverting terminals (+) of first amplifier AMP1 to fourth amplifier AMP4, respectively.

[0110] The first B switch SW1b may have a first electrode connected to the second electrode of the first A switch SW1a, a second electrode connected to the non-inverting terminal (+) of the first amplifier AMP1, and a control electrode connected to the 1B control line to which the 1B switch control signal is applied. The second B switch SW2b may have a first electrode connected to the second electrode of the second A switch SW2a, a second electrode connected to the non-inverting terminal (+) of the second amplifier AMP2, and a control electrode connected to the 2B control line to which the 2B switch control signal is applied. The third B switch SW3b may have a first electrode connected to the second electrode of the third A switch SW3a, a second electrode connected to the non-inverting terminal (+) of the third amplifier AMP3, and a control electrode connected to the 3B control line to which the 3B switch control signal is applied. The fourth B switch SW4b may have a first electrode connected to the second electrode of the fourth A switch SW4a, a second electrode connected to the non-inverting terminal (+) of the fourth amplifier AMP4, and a control electrode connected to the 4B control line to which the 4B switch control signal is applied.

[0111] Hereinafter, an example in which the green data voltage output unit DAC[G] is used as a circuit for outputting a black voltage will be used to illustrate and describe a part of the driving method of the fourth embodiment and the operation of the device according to the driving method.

[0112] As Figures 22 to 24 shown, during the data writing period of the display panel, the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] may each output a data voltage for representing a specific gray level. In addition, the green data voltage output unit DAC[G] may output a black voltage for representing the black gray level.

[0113] Meanwhile, Figure 24 is a timing diagram in which, when the red data voltage, the white data voltage, and the blue data voltage are output according to the first scan line (the scan line to which Scan1 is applied) to the second scan line (the scan line to which Scan2 is applied), the black voltage is output from the green data voltage output unit DAC[G], and thereafter, when the red data voltage, the white data voltage, and the blue data voltage are output according to the third scan line (the scan line to which Scan3 is applied), the black voltage is output from the red data voltage output unit DAC[R]. However, as in the previous embodiment, the case where the green sub-pixel SPG and the green data voltage output unit DAC[G] are driven to display only the black gray level and do not participate in the image display of the display panel is described as an embodiment.

[0114] When the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] output data voltages, and the green data voltage output unit DAC[G] outputs a black voltage, the 1C switch SW1c, the 2C switch SW2c, and the 4C switch SW4c can be turned off, and the 3C switch SW3c can be turned on. At the same time, the 3C switch SW3c can be turned on only during one horizontal time 1H when the first scan signal Scan1 is generated as a logic high H. However, it should be noted that Figure 24 It is exemplified that the green data voltage output unit DAC[G] outputs a black voltage within two horizontal times (as an example) [due to driving characteristics, the data voltage output unit can output a black voltage within M horizontal times (M is an integer greater than or equal to 2) instead of one horizontal time 1H, and this similarly applies to data voltages].

[0115] When the data voltage output units DAC[R] to DAC[B] have the above output states, the second switch groups SW1a to SW4a, the second voltage output switches SW1aa to SW4aa, the third switch groups SW1b to SW4b, and the first voltage output switches SW1bb to SW4bb can have the following operating states.

[0116] The second switch groups SW1a to SW4a and the second voltage output switches SW1aa to SW4aa, and the third switch groups SW1b to SW4b and the first voltage output switches SW1bb to SW4bb can be alternately and repeatedly turned on and off. For example, when the second switch groups SW1a to SW4a and the second voltage output switches SW1aa to SW4aa are turned on, the third switch groups SW1b to SW4b and the first voltage output switches SW1bb to SW4bb can be turned off. For example, when the second switch groups SW1a to SW4a and the second voltage output switches SW1aa to SW4aa are turned off, the third switch groups SW1b to SW4b and the first voltage output switches SW1bb to SW4bb can be turned on.

[0117] According to the above operations, data voltages prepared by the sum of the data voltages output from the red data voltage output unit DAC[R], the white data voltage output unit DAC[W], and the blue data voltage output unit DAC[B] and the alpha voltage α output from the output circuit unit OUC can be formed on the first data line DL1, the second data line DL2, and the fourth data line DL4. In addition, a reference voltage Vref prepared as the black voltage output from the green data voltage output unit DAC[G] can be formed on the first reference line REF1.

[0118] The voltages formed on the first data line DL1, the second data line DL2, and the fourth data line DL4 can change the +alpha voltage (+α) or the -alpha voltage (-α) because the voltages charged in the output capacitors C1 to C4 are affected by the first voltage source V1 and the second voltage source V2. On the other hand, the -alpha reference voltage Vref-α can be formed on the third data line DL3 by the alpha voltage α output from the output circuit unit OUC and the reference voltage Vref output from the green data voltage output unit DAC[G].

[0119] As can be seen from the voltage formed on the third data line DL3, in the fourth embodiment, without switching the black voltage output from the data voltage output units DAC[R] to DAC[B], a reference voltage Vref-α lower than the reference voltage Vref formed on the first reference line REF1 can be applied. That is, the advantage of the fourth embodiment is that black gradation can be represented without using a configuration or method for switching the black voltage output from the data voltage output units DAC[R] to DAC[B].

[0120] Figure 25 and Figure 26A and Figure 26B are diagrams illustrating the effects of embodiments of the present invention.

[0121] As Figure 25 shown, according to the present invention including the above-described first to fourth embodiments, since a data voltage output unit capable of changing the voltage is used, the reference voltage Ref of each individual pixel can be changed (controlled). At the same time, although Figure 25 the reference voltage Ref is illustrated as being changed from 0V to 3V as an example, this is only an example for better understanding, and the present invention is not limited thereto because the voltage can be selected according to the state of the elements formed on the display panel (such as the degradation state of the driving transistor).

[0122] As in Figure 26A the conventional example shown, when a fixed reference voltage is used, the gate voltage vg and the source voltage vs are limited to specific conditions, so the gradation representation region can be correspondingly limited.

[0123] However, as Figure 26B shown in the present invention, when a variable reference voltage is used, the source voltage vs can be changed under specific conditions, and thus higher brightness can be represented by separately changing the voltage applied to the pixel. In addition, even when the same number of bits as in the prior art is used, the gradation representation region can be further expanded. Furthermore, when a circuit capable of changing the reference voltage is provided as in the present invention, the data voltage margin required for external compensation can be calculated and applied for each pixel.

[0124] As described above, the present invention has the effect of representing higher brightness by separately changing the voltage applied to the pixels. In addition, the present invention has the effect of expanding the grayscale representation region by controlling not only the data bits but also the reference voltage in units of bits (the same number of bits). In addition, the effect of the present invention is that the data voltage margin required for external compensation can be calculated and applied for each pixel. In addition, since the voltage source existing in the data driver can be removed during external compensation, the present invention has the effect of reducing power consumption due to the removal / deletion of the configuration using a constant power supply.

[0125] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Accordingly, the present invention is intended to cover modifications and variations of the present invention falling within the scope of the appended claims and their equivalents.

[0126] This application claims the benefit of Korean Patent Application No. 10-2021-0056624, filed on Apr. 30, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A light-emitting display LED device, the LED device comprising: A display panel configured to display an image; And A data driver including a panel driving circuit for driving the display panel and a panel sensing circuit for sensing the display panel, Wherein the panel driving circuit includes a first data voltage output circuit configured to output voltages to be applied to a first data line and a first reference line of the display panel to display black on a first sub-pixel included in the display panel, Wherein the first data voltage output circuit is a digital-to-analog converter capable of changing the voltage, and Wherein the first data voltage output circuit is a circuit for driving the first sub-pixel that does not participate in image display among the sub-pixels included in the display panel, and outputs a voltage for displaying black instead of the data voltage required for image display during a data writing period of the display panel.

2. The LED device according to claim 1, wherein The voltage output from the first data voltage output circuit is shared through a switch included in the data driver and electrically connects the first data line and the first reference line to each other.

3. The LED device according to claim 1, wherein, The data driver includes a switch configured to send the voltage output from the first data voltage output circuit included in the panel driving circuit to a sensing channel and a data channel during a data writing period of the display panel.

4. The LED device according to claim 3, wherein, The switch includes: A first switch group configured to perform a switching operation to send the voltage output from the first data voltage output circuit to the sensing channel; and A second switch group configured to perform a switching operation to output the voltage output from the first data voltage output circuit through the data channel.

5. The LED device according to claim 4, wherein The first data voltage output circuit alternately outputs a first voltage and a second voltage having different levels during a data writing period of the display panel; and At least one switch included in the first switch group sends the first voltage to the data channel and sends the second voltage to the sensing channel.

6. The LED device according to claim 3, wherein, The data driver further includes an output circuit provided at an output terminal of the first data voltage output circuit to alternately output a first voltage and a second voltage having different levels during the data writing period of the display panel.

7. The LED device according to claim 6, wherein The output circuit includes: An amplifier; A first voltage output switch configured to output a first voltage from a first voltage source; A second voltage output switch configured to output a second voltage from a second voltage source; An output capacitor charged with the voltages output through the first voltage output switch and the second voltage output switch; and A third switch group configured to perform a switching operation to apply the voltage charged in the output capacitor to a non-inverting terminal of the amplifier.

8. The LED device according to claim 1, wherein, The voltage for displaying black varies according to the states of elements included in the display panel.

9. A driving method of an LED device according to claim 1, the driving method comprising the following steps: Applying the voltage to the first data line and the first reference line of the display panel to display black on the first sub-pixel included in the display panel, and applying data voltages to the second data line to the fourth data line of the display panel to display an image on the second sub-pixel to the fourth sub-pixel included in the display panel.

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