Display panel and display device

Abstract

The present invention discloses a display panel and a display device, wherein the display panel comprises: a first driving circuit, wherein the first driving circuit comprises a cascaded multi-stage first shift register, wherein the first shift register comprises a first signal input terminal; a first control circuit, wherein the first control circuit comprises a plurality of signal control units, wherein the output terminal of the signal control unit is connected to the first signal input terminal of at least one stage of the first shift register; a first signal line, wherein the first signal line is connected to the input terminal of the signal control unit; and a plurality of signal control units are turned on in time division. In the present invention, the plurality of signal control units are turned on in time division, and the loading difference of the first signal line at different positions can be adjusted, thereby reducing the delay difference of the first signal received by the first shift registers at different stages, and making the delay of the first signal received by the first shift registers at different stages tend to be consistent, thereby reducing the transmission power consumption of the first signal line and improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, a driving circuit arranged in a non-display area is an indispensable circuit structure, which is used to realize the display, touch and other functions of the display panel.

[0003] The driving circuit is usually composed of a cascade of multiple shift registers. The driving chip provides a driving signal to each shift register in the driving circuit through a signal line so that the driving circuit can operate normally.

[0004] However, the transmission power consumption of the signal lines in the existing display panel is relatively high, resulting in large differences in signal delays received by the shift registers at different positions in the driving circuit, thus affecting the display effect. Summary of the invention

[0005] The present invention provides a display panel and a display device to solve the problem of large differences in signal delays received by shift registers at different positions in a driving circuit.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising:

[0007] A first driving circuit, the first driving circuit comprising a cascaded multi-stage first shift register, the first shift register comprising a first signal input terminal;

[0008] A first control circuit, the first control circuit comprising a plurality of signal control units, wherein an output end of the signal control unit is connected to a first signal input end of at least one stage of the first shift register;

[0009] A first signal line, wherein the first signal line is connected to an input end of the signal control unit;

[0010] The plurality of signal control units are turned on in different time periods.

[0011] According to another aspect of the present invention, a display device is provided, comprising the display panel as described above.

[0012] In the present invention, the first control circuit is electrically connected to the first drive circuit and the first signal line, the first drive circuit includes a cascaded multi-stage first shift register, the first control circuit includes a plurality of signal control units, the signal control unit is connected between the first signal line and the first shift register, and the signal control unit receives the first signal provided by the first signal line and transmits the first signal to the first shift register when turned on. In the present invention, the plurality of signal control units are turned on in time-sharing, so that the plurality of signal control units transmit the first signal to the first shift registers at different positions in time-sharing, and the loading difference of the first signal line at different positions can be adjusted, so as to reduce the delay difference of the first signal received by the first shift registers at different levels, and make the delay of the first signal received by the first shift registers at different levels tend to be consistent, thereby reducing the influence of the loading of the first signal line on the display, and also reducing the power consumption, and improving the display effect.

[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 7 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 8 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Fig. 9 is a schematic diagram of a pixel unit provided by an embodiment of the present invention;

[0024] Fig.10 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 It is a schematic diagram of another display panel provided by an embodiment of the present invention. This embodiment can be applied to any type of display panel, such as an organic light-emitting display panel, a Micro LED display panel, a quantum dot display panel, etc., but is not limited thereto. As shown in the figure, the display panel includes: a first driving circuit 11, the first driving circuit 11 includes a cascaded multi-stage first shift register 12, and the first shift register 12 includes a first signal input terminal in; a first control circuit 13, the first control circuit 13 includes a plurality of signal control units 14, and the output end of the signal control unit 14 is connected to the first signal input terminal in of at least one stage of the first shift register 12; a first signal line 15, the first signal line 15 is connected to the input end of the signal control unit 14; and the plurality of signal control units 14 are turned on in time division.

[0028] In this embodiment, the display panel includes a display area 16 and a non-display area 17. The display area 16 includes a pixel unit 18. The non-display area 17 includes a circuit structure for driving the pixel unit 18 to display, such as a first drive circuit 11, a first control circuit 13 and a first signal line 15 are all located in the non-display area 17, but the circuit structure of the non-display area 17 is not limited thereto.

[0029] The first driving circuit 11 is used to drive the pixel unit 18 to display. Specifically, the first driving circuit 11 includes a cascade of multiple first shift registers 12, the first shift register 12 includes a first signal output terminal, and a first shift register 12 is electrically connected to one or more rows of pixel units 18 through the first signal output terminal. The first shift register 12 provides a first driving signal to the electrically connected pixel unit 18 through the first signal output terminal. Figure 2 As shown, the first shift register 12 of the first level can be set corresponding to a row of pixel units 18, and the first signal output terminal of the first shift register 12 is electrically connected to the corresponding row of pixel units 18 and provides the first driving signal to the pixel units 18. However, in other embodiments, the first shift register of the first level can be set corresponding to multiple adjacent rows of pixel units, and the first signal output terminal of the first shift register of the first level is electrically connected to the corresponding multiple rows of pixel units. The first driving circuit 11 can be any circuit that drives the pixel unit 18 to display. For example, the first driving circuit 11 can be a gate driving circuit, and the first shift register 12 provides a scanning driving signal to the electrically connected pixel unit 18 through the first signal output terminal. In other embodiments, the first driving circuit can also be selected as a light-emitting control circuit, and the first shift register provides a light-emitting control signal to the pixel unit through the first signal output terminal, etc. The structure or function of the first driving circuit is not limited to this.

[0030] The first shift register 12 also includes a first signal input terminal in, and the first shift register 12 receives an external input signal through the first signal input terminal in. The first driving circuit 11 includes x-stage cascaded first shift registers 12, where x is a positive integer greater than or equal to 2, and the first signal input terminal of the first stage, i.e., the first stage, is marked as in1, the first signal input terminal of the second stage, i.e., the first signal input terminal of the third stage, i.e., the first shift register is marked as in2, and the first signal input terminal of the third stage, i.e., the first shift register of the last stage, i.e., the xth stage, is marked as inx. The first driving circuit 11 shifts and drives the pixel unit 18 in the order of the first shift registers 12 of the first stage to the xth stage.

[0031] The pixel unit 18 needs to be driven by a variety of driving signals, each driving signal needs to be generated by a driving circuit and provided to the pixel unit 18. In this embodiment, the first driving circuit 11 is used to generate a first driving signal to drive the pixel unit 18 to work. Each level of the first shift register 12 in the first driving circuit 11 generates a first driving signal and provides it to the corresponding pixel unit 18. The normal operation of the driving circuit also requires many signals to drive. Specifically, the non-display area 17 includes a driving chip 19, which is used to provide many signals to the first driving circuit 11 so that the first driving circuit 11 can operate normally.

[0032] The non-display area 17 of the display panel includes a first signal line 15, and the driver chip 19 is electrically connected to the first signal line 15. The driver chip 19 provides a first signal to the first signal input terminal in of each stage of the first shift register 12 through the first signal line 15, so that the first shift register 12 works. The optional first signal is a timing signal output by the driver chip 19. The driver chip 19 provides the timing signal to each stage of the first shift register 12 through the first signal line 15, so that the cascaded multi-stage first shift register 12 works and generates a first driving signal to the pixel unit 18. It can be understood that the signal line electrically connected to the driver chip 19 includes but is not limited to the first signal line 15; the first signal provided to the first signal line 15 by the driver chip 19 can also be other types of signals, not limited to timing signals, which will not be described in detail here.

[0033] When the first signal is transmitted on the first signal line 15, there will be a load (loading), and the loading will cause signal delay. The larger the loading, the larger the signal delay, and the smaller the loading, the smaller the signal delay. The first signal line 15 includes a main line 20 and a branch line 21, and the loading of the first signal transmitted on the first signal line 15 can also be divided into two parts, one part is the loading generated by the main line 20 of the first signal line 15, and the other part is the loading generated by the branch line 21 of the first signal line 15. The branch line 21 refers to the wiring connected from the main line 20 to the gate or source and drain of the transistor in the first drive circuit 11. The proportion of the loading of the main line 20 to the total loading of the first signal line 15 is small, and the proportion of the loading of the branch line 21 to the total loading of the first signal line 15 is large.

[0034] Normally, the driver chip 19 is located at the bottom of the display panel. In the direction of the first shift register 12 from the 1st stage to the xth stage in the first driving circuit 11, the distance between the first shift register 12 and the driver chip 19 changes from large to small, that is, the driver chip 19 is close to the last first shift register 12 of the first driving circuit 11, and the driver chip 19 is far away from the first first shift register 12 of the first driving circuit 11. Then, the first shift register 12 close to the driver chip 19 receives relatively small loading of the first signal line 15, and the first shift register 12 far away from the driver chip 19 receives relatively large loading of the first signal line 15. Specifically, the loading of the main line 20 accounts for a small proportion of the total loading of the first signal line 15, so the loading of the main line 20 received by the first shift registers 12 of different stages is not much different. As for the loading of the branch line 21, it accounts for a large proportion of the total loading of the first signal line 15. Therefore, the loading of the branch line 21 on the first shift registers 12 at different levels will be different, especially the first and last level first shift registers 12 will be the most different in the loading of the branch line 21. It can be seen from this that when the driver chip 19 transmits the first signal through the first signal line 15, affected by the loading of the first signal line 15, the first signals received by the first shift registers 12 at different levels will have different delays, wherein the delay of the first signal received by the first shift register 12 close to the driver chip 19 is relatively small, and the delay of the first signal received by the first shift register 12 far from the driver chip 19 is relatively large. The first signals received by the first shift registers 12 at different levels will have different delays, which affects the shift output of the first drive signal of the first shift registers 12 at different levels, and then affects the display of the pixel units 18 in different rows, and finally affects the display effect.

[0035] Based on this, a first control circuit 13 is set in the display panel. The first control circuit 13 is set between the first signal line 15 and the first driving circuit 11. The first control circuit 13 is electrically connected to the first signal line 15 and the first driving circuit 11 respectively. The first control circuit 13 is used to control the transmission of the first signal to each level of the first shift register 12, so as to reduce the delay difference of the first shift registers 12 at different levels receiving the first signal and improve the display effect.

[0036] Specifically, the first control circuit 13 includes a plurality of signal control units 14, the signal control unit 14 includes an input end and an output end, the input end of the signal control unit 14 is electrically connected to the first signal line 15, the output end of the signal control unit 14 is electrically connected to the first signal input end in of at least one first shift register 12, the working state of the signal control unit 14 includes on or off, and the signal control unit 14 is used to receive the first signal provided by the first signal line 15 and transmit the first signal to the first shift register 12 when it is on. Figure 1 As shown, a signal control unit 14 may be optionally provided corresponding to the first shift register 12, and the output end of the signal control unit 14 is electrically connected to the first signal input end in of the first shift register 12. The first shift register 12 is driven by the first signal provided by the signal control unit 14 to generate a first driving signal and provide it to the pixel unit 18.

[0037] In other embodiments, the output end of the signal control unit may be optionally connected to the first signal input ends of at least two stages of cascaded first shift registers. Figure 3 is a schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 3 As shown, there is at least one signal control unit 14 in the first control circuit 13, which is set corresponding to at least two stages of the cascaded first shift registers 12, and the output end of one signal control unit 14 is electrically connected to the first signal input end in of the corresponding multi-stage first shift register 12, and provides the first signal to the first shift register 12. The first stage and the last stage first shift registers 12 with a relatively long position interval receive the largest difference in loading of the first signal line 15, but in fact, the position difference of the cascaded two-stage first shift registers 12 relative to the driving chip 19 is relatively small, so it can be considered that the loading difference of the cascaded two-stage first shift registers 12 received by the first signal line 15 is not large. Based on this, designing a signal control unit 14 corresponding to the connection of at least two stages of the cascaded first shift registers 12 can reduce the number of signal control units 14 in the first control circuit 13, realize a narrow frame, and can also reduce the delay difference of the first signal received by the first shift registers 12 at different positions, improve the display effect, especially can improve the brightness uniformity of the display panel in the longitudinal direction at low gray scale, and reduce the power consumption of the shift register.

[0038] Multiple signal control units 14 are turned on in time. The driving chip 19 is electrically connected to the first control circuit 13, and is used to control the working state of each signal control unit 14 in the first control circuit 13. When the signal control unit 14 is turned on, the first shift register 12 electrically connected thereto receives the first signal provided by the first signal line 15; when the signal control unit 14 is turned off, the first shift register 12 electrically connected thereto does not receive the first signal. Based on this, the driving chip 19 controls multiple signal control units 14 in the first control circuit 13 to be turned on in time, and the loading difference of the first signal line 15 at different positions can be adjusted, so that the first shift registers 12 at different positions receive the first signal at different times, thereby reducing the delay difference of the first shift registers 12 at different levels receiving the first signal, and making the delay of the first shift registers 12 at different levels receiving the first signal tend to be consistent, so that the impact of the loading of the first signal line on the display can be reduced, and power consumption can also be reduced.

[0039] In the present invention, the first control circuit is electrically connected to the first drive circuit and the first signal line, the first drive circuit includes a cascaded multi-stage first shift register, the first control circuit includes a plurality of signal control units, the signal control unit is connected between the first signal line and the first shift register, and the signal control unit receives the first signal provided by the first signal line and transmits the first signal to the first shift register when turned on. In the present invention, the plurality of signal control units are turned on in time-sharing, so that the plurality of signal control units transmit the first signal to the first shift registers at different positions in time-sharing, and the loading difference of the first signal line at different positions can be adjusted, so as to reduce the delay difference of the first signal received by the first shift registers at different levels, and make the delay of the first signal received by the first shift registers at different levels tend to be consistent, thereby reducing the influence of the loading of the first signal line on the display, and also reducing the power consumption, and improving the display effect.

[0040] Optionally, for two-stage first shift registers connected to different signal control units, a start time of the signal control unit connected to the upper stage first shift register is earlier than a start time of the signal control unit connected to the lower stage first shift register.

[0041] refer to Figure 1As shown, the driving chip 19 is located at the bottom of the display panel, that is, the driving chip 19 is close to the last first shift register 12 of the first driving circuit 11, and far away from the first first shift register 12. The first shift register 12 close to the driving chip 19 receives relatively less loading of the first signal line 15, and the first shift register 12 far away from the driving chip 19 receives relatively greater loading of the first signal line 15. The first driving circuit 11 shifts and drives the first shift register 12 in the order from the 1st stage to the xth stage. For any 2-stage first shift register 12, the upper first shift register 12 is relatively far away from the driving chip 19, and the lower first shift register 12 is relatively close to the driving chip 19. Therefore, the upper first shift register 12 is relatively more affected by the loading of the first signal line 15, and the lower first shift register 12 is relatively less affected by the loading of the first signal line 15. Based on this, for any 2-level first shift register 12, the time when the upper-level first shift register 12 receives the first signal provided by the first signal line 15 is earlier than the time when the lower-level first shift register 12 receives the first signal, which can reduce the loading difference between the two and make the delay of different-level first shift registers receiving the first signal tend to be consistent.

[0042] For the two-stage first shift register 12 connected to different signal control units 14, taking the first stage first shift register 12 and the third stage first shift register 12 as examples, the first signal input terminal in1 of the first stage first shift register 12 and the first signal input terminal in3 of the third stage first shift register are connected to different signal control units 14. For the first stage first shift register 12 and the third stage first shift register 12, the start time of the signal control unit 14 connected to the first stage first shift register 12 at the upper stage is earlier than the start time of the signal control unit 14 connected to the third stage first shift register 12 at the lower stage, which can reduce the loading difference between the first stage first shift register 12 and the third stage first shift register 12 at different positions, thereby reducing the delay difference of the first signal received by the first shift registers 12 at different stages, and making the delay of the first signal received by the first shift registers 12 at different stages tend to be consistent, thereby reducing the influence of the loading of the first signal line 15 on the display while reducing power consumption and improving the display effect.

[0043] It is understandable that Figure 3As shown, the positions of the first-stage first shift register 12 and the second-stage first shift register 12 in the display panel are very close, so the loading difference between the two is almost the same. Based on this, the two can be connected to the same signal control unit 14. When the signal control unit 14 is turned on, the first-stage first shift register 12 and the second-stage first shift register 12 receive the first signal at the same time, and the delay of the two receiving the first signal is the same. There is a certain distance between the positions of the first-stage first shift register 12 and the fifth-stage first shift register 12 in the display panel, so there are some differences in the loading between the two. Based on this, the two can be connected to two different signal control units 14, and the two different signal control units 14 are turned on in time division, so that the first-stage first shift register 12 and the fifth-stage first shift register 12 receive the first signal in time division, thereby reducing the delay difference between the two receiving the first signal.

[0044] The optional signal control unit includes a first switch, the first switch is connected between the first signal line and the first signal input terminal of the first shift register. The optional first switch includes a first transistor; or, the first switch includes an inverter and a second transistor. The optional first transistor is NMOS or PMOS; the second transistor is NMOS or PMOS.

[0045] Figure 4 is a schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 4 As shown, the signal control unit 14 includes a first switch connected between the first signal line 15 and the first signal input terminal in of the first shift register 12. The first switch includes a first transistor M1, and the first transistor M1 can be NMOS.

[0046] In this embodiment, the signal control unit 14 includes a first transistor M1, an input end of the first transistor M1 is connected to the first signal line 15, an output end of the first transistor M1 is connected to the first signal input end in of the first shift register 12, and a control end of the first transistor M1 is connected to the signal control end CT. Optionally, the control end of the first transistor M1 of the first signal control unit 14 is connected to the signal control end CT1, the control end of the first transistor M1 of the second signal control unit 14 is connected to the signal control end CT2, the control end of the first transistor M1 of the third signal control unit 14 is connected to the signal control end CT3, and so on. It can be understood that the driver chip 19 drives the first control circuit 13 to control the switching state of each first transistor M1, and in particular, the driver chip 19 can drive the first control circuit 13 to independently control the switching state of each first transistor M1. Specifically, the driving chip 19 drives the first control circuit 13 to provide effective driving signals to different signal control terminals CT1, CT2, CT3, ... in a time-sharing manner, so that the first transistors M1 of different signal control units 14 are turned on in a time-sharing manner, and the loading differences of the first signal line 15 at different positions can be adjusted, so that the first shift registers 12 at different positions receive the first signal at different times.

[0047] The first transistor M1 can be selected as NMOS, and the driver chip 19 drives the first control circuit 13 to provide a high-level signal to the control end of the first transistor M1 to turn on the first transistor M1, and the driver chip 19 drives the first control circuit 13 to provide a low-level signal to the control end of the first transistor M1 to turn off the first transistor M1. In other embodiments, the first transistor can also be selected as PMOS; the driver chip drives the first control circuit to provide a low-level signal to the control end of the first transistor to turn on the first transistor, and the driver chip drives the first control circuit to provide a high-level signal to the control end of the first transistor to turn off the first transistor.

[0048] The driving chip 19 controls the multiple first transistors M1 in the first control circuit 13 to be turned on in time-sharing manner, and the loading difference of the first signal line 15 at different positions can be adjusted, so that the time when the first shift registers 12 at different positions receive the first signal is different. For example, the turning-on time of the first transistor M1 connected to the upper first shift register 12 is earlier than the turning-on time of the first transistor M1 connected to the lower first shift register 12, which can reduce the delay difference of the first shift registers 12 at different positions receiving the first signal, so that the delay of the first shift registers 12 at different levels receiving the first signal tends to be consistent, so that the influence of the loading of the first signal line on the display can be reduced, and the power consumption can also be reduced.

[0049] Figure 5 is a schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 5As shown, the signal control unit 14 includes a first switch connected between the first signal line 15 and the first signal input terminal in of the first shift register 12. The optional first switch includes an inverter 22 and a second transistor M2. The optional second transistor is a PMOS.

[0050] In this embodiment, the signal control unit 14 includes an inverter 22 and a second transistor M2, the input end of the second transistor M2 is connected to the first signal line 15, the output end of the second transistor M2 is connected to the first signal input end in of the first shift register 12, and the control end of the second transistor M2 is connected to the signal control end CT through the inverter 22. The inverter 22 receives the signal provided by the signal control end CT and performs a high-low level flip on it, and then the output signal of the inverter 22 controls the second transistor M2 to turn on or off. The input end of the inverter 22 of the first signal control unit 14 can be connected to the signal control end CT1, the input end of the inverter 22 of the second signal control unit 14 is connected to the signal control end CT2, and the input end of the inverter 22 of the third signal control unit 14 is connected to the signal control end CT3, and so on. It can be understood that the driver chip 19 drives the first control circuit 13 to control the switch state of each signal control unit 14, especially the driver chip 19 can drive the first control circuit 13 to independently control the switch state of each signal control unit 14. Specifically, the driving chip 19 drives the first control circuit 13 to provide effective driving signals to different signal control terminals CT1, CT2, CT3, ... in a time-sharing manner, so that the second transistors M2 of different signal control units 14 are turned on in a time-sharing manner, and the loading difference of the first signal line 15 at different positions can be adjusted, so that the first shift registers 12 at different positions receive the first signal at different times.

[0051] The second transistor M2 can be selected as a PMOS, and the driver chip 19 drives the first control circuit 13 to provide a high-level signal to the input end of the inverter 22 to turn on the second transistor M2, and the driver chip 19 drives the first control circuit 13 to provide a low-level signal to the input end of the inverter 22 to turn off the second transistor M2. In other embodiments, the second transistor can also be selected as an NMOS; the driver chip drives the first control circuit to provide a low-level signal to the input end of the inverter to turn on the second transistor, and the driver chip drives the first control circuit to provide a high-level signal to the input end of the inverter to turn off the second transistor.

[0052] The driving chip 19 controls the multiple signal control units 14 in the first control circuit 13 to start up in time-sharing manner, and thus the loading difference of the first signal line 15 at different positions can be adjusted, so that the first shift registers 12 at different positions receive the first signal at different times. For example, the start time of the signal control unit 14 connected to the upper first shift register 12 is earlier than the start time of the signal control unit 14 connected to the lower first shift register 12, which can reduce the delay difference of the first shift registers 12 at different positions receiving the first signal, and make the delay of the first shift registers 12 at different levels receiving the first signal tend to be consistent, so that the influence of the loading of the first signal line on the display can be reduced, and the power consumption can also be reduced.

[0053] The first shift register may optionally include an energy storage capacitor; the first shift register is used to output under the drive of the first signal line when the signal control unit is turned on, and is also used to output under the drive of the energy storage capacitor when the signal control unit is turned off.

[0054] When the signal control unit is turned on, the transmission path of the first signal line and the first shift register is connected, and the first signal of the first signal line is transmitted to the first shift register through the signal control unit, and the first shift register outputs under the drive of the first signal line. At the same time, the first signal line also charges the energy storage capacitor in the first shift register. When the signal control unit is turned off, the transmission path of the first signal line and the first shift register is disconnected, and the first shift register outputs under the drive of the energy storage capacitor therein. The normal operation of the first shift register is guaranteed. Those skilled in the art can reasonably design the capacity of the energy storage capacitor according to the working requirements of the first shift register, which is not described in detail here.

[0055] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 6 As shown, the optional first control circuit 13 also includes: a second driving circuit 23, the second driving circuit 23 includes a cascaded multi-stage second shift register 24, the second shift register 24 includes a second signal output terminal out; the control end of the signal control unit 14 is connected to the second signal output terminal out of the first-stage second shift register 24, and the second shift register 24 is used to control the signal control unit 14 to turn on or off.

[0056] In this embodiment, the first control circuit 13 further includes a second driving circuit 23, the second driving circuit 23 includes a cascaded multi-stage second shift register 24, the driving chip 19 is electrically connected to the second driving circuit 23, and is used to control the cascaded multi-stage second shift register 24 in the second driving circuit 23 to shift and drive in a cascaded sequence, and the connection relationship between the driving chip 19 and the second driving circuit 23 is not shown here. The second shift register 24 includes a second signal output terminal out, and according to the cascade sequence of the cascaded multi-stage second shift register 24, the second signal output terminal of the first-stage second shift register 24 is marked as out1, the second signal output terminal of the second-stage second shift register 24 is marked as out2, the second signal output terminal of the third-stage second shift register 24 is marked as out3, and so on. The optional driving chip 19 is located at the bottom of the display panel. In the second driving circuit 23, along the direction of the second shift register 24 from the first level to the last level, the distance between the second shift register 24 and the driving chip 19 changes from large to small; and in the first driving circuit 11, along the direction of the first shift register 12 from the first level to the xth level, the distance between the first shift register 12 and the driving chip 19 changes from large to small.

[0057] The control end of the signal control unit 14 is connected to the second signal output end out of the first-stage second shift register 24, that is, the second signal output end out of the second shift register 24 is multiplexed as the signal control end CT, and the second driving signal outputted by the second signal output end out of the second shift register 24 can be used to control the connected signal control unit 14 to turn on or off. The cascaded multi-stage second shift register 24 can control multiple signal control units 14 to turn on in time division.

[0058] refer to Figure 6 As shown, in the optional first control circuit 13, the number of stages of the second shift register 24 is greater than or equal to the number of the signal control units 14. In the optional multi-stage second shift register 24 connected to multiple signal control units 14, the multi-stage second shift register 24 is cascade connected.

[0059] In this embodiment, the number of stages of the second shift register 24 may be greater than the number of the signal control units 14, then a part of the cascaded second shift registers 24 may be selected from the second drive circuit 23, and the part of the cascaded second shift registers 24 may correspond to and be connected to a plurality of signal control units 14, respectively, and the second signal output end out of the selected second shift register 24 is multiplexed as a signal control end CT, which is used to control the corresponding signal control unit 14 to turn on or off. The number of stages of the second shift register 24 may be equal to the number of the signal control units 14, then all the second shift registers 24 in the second drive circuit 23 correspond to and are connected to a plurality of signal control units 14, respectively, and the second signal output end out of each second shift register 24 is multiplexed as a signal control end CT, which is used to control the corresponding signal control unit 14 to turn on or off. For example, the second signal output terminal out1 of the first-stage second shift register 24 is multiplexed as the signal control terminal CT1, the second signal output terminal out2 of the second-stage second shift register 24 is multiplexed as the signal control terminal CT2, the second signal output terminal out3 of the third-stage second shift register 24 is multiplexed as the signal control terminal CT3, and so on.

[0060] Figure 7 is a schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 7 As shown, in the optional first control circuit 13, the number of stages of the second shift register 24 is greater than the number of the signal control units 14. In the multi-stage second shift register 24 optionally connected to the plurality of signal control units 14, there are two adjacent stages of the second shift register 24 that are not cascaded.

[0061] In this embodiment, the number of stages of the second shift register 24 may be greater than the number of the signal control units 14, and a part of the second shift register 24 may be selected from the second driving circuit 23, the number of the part of the second shift register 24 is equal to the number of the signal control units 14 in the first control circuit 13, and the selected part of the second shift register 24 may be all cascade connected, partially cascade connected, or not cascade connected at all. The second signal output terminal out of the selected second shift register 24 is multiplexed as the signal control terminal CT, which is used to control the corresponding signal control unit 14 to turn on or off. For example, the selected part of the second shift register 24 may be partially cascade connected, illustratively, the second signal output terminal out1 of the first-stage second shift register 24 is multiplexed as the signal control terminal CT1, the second signal output terminal out3 of the third-stage second shift register 24 is multiplexed as the signal control terminal CT2, the second signal output terminal out4 of the fourth-stage second shift register 24 is multiplexed as the signal control terminal CT3, and so on.

[0062] Figure 8 is a schematic diagram of another display panel provided by an embodiment of the present invention, combined with Figure 2 and Figure 8 As shown, the optional display panel includes a first area 16 and a second area 17, the first area 16 includes a pixel unit 18; the second driving circuit 23 is arranged in the second area 17, and the second signal output terminal out-b of the second shift register 24 is also connected to a row of pixel units 18; the first shift register 12 includes a first signal output terminal out-a, and the first signal output terminal out-a of the first shift register 12 is connected to a row of pixel units 18.

[0063] In this embodiment, the first area 16 can be selected as a display area, the second area 17 can be selected as a non-display area, the pixel unit 18 is located in the display area 16, and a plurality of circuit structures for driving the pixel unit 18 to work are located in the non-display area 17. The pixel unit 18 needs to be driven by a plurality of driving signals, and each driving signal needs to be generated by a driving circuit and provided to the pixel unit 18.

[0064] As described above, the first driving circuit 11 is a circuit structure for driving the pixel unit 18 to work, and is used to generate a first driving signal for driving the pixel unit 18 to work. Each level of the first shift register 12 in the first driving circuit 11 generates a first driving signal and provides it to the pixel unit 18 of the corresponding row. The first signal output end out-a of the first shift register 12 of the first level can be connected to a row of pixel units 18, and the first driving signal is provided to the corresponding row of pixel units 18; illustratively, the first signal output end out-a1 of the first shift register 12 of the first level is connected to the pixel unit 18 of the first row, the first signal output end out-a2 of the second level of the first shift register 12 is connected to the pixel unit 18 of the second row, and the first signal output end out-a3 of the third level of the first shift register 12 is connected to the pixel unit 18 of the third row. In other embodiments, according to product requirements, the first signal output end of the first shift register of the first level can also be connected to multiple rows of pixel units, which is not specifically exemplified.

[0065] The second driving circuit 23 is another circuit structure for driving the pixel unit 18 to work. Different from the first driving circuit 11, the second driving circuit 23 is used to generate a second driving signal for driving the pixel unit 18 to work. Each level of the second shift register 24 in the second driving circuit 23 generates a second driving signal and provides it to the pixel unit 18 of the corresponding row. The second signal output end out-b of the second shift register 24 of the first level can be connected to a corresponding row of pixel units 18, and the second driving signal is provided to the corresponding row of pixel units 18; illustratively, the second signal output end out-b1 of the second shift register 24 of the first level is connected to the pixel unit 18 of the first row, the second signal output end out-b2 of the second shift register 24 of the second level is connected to the pixel unit 18 of the second row, and the second signal output end out-b3 of the second shift register 24 of the third level is connected to the pixel unit 18 of the third row. In other embodiments, according to product requirements, the second signal output end of the second shift register of the first level can also be connected to multiple rows of pixel units, which is not specifically exemplified.

[0066] The second signal output terminal out of at least part of the second shift registers 24 in the second driving circuit 23 is also multiplexed as the signal control terminal CT, then the second driving signal output by the second signal output terminal out of this type of second shift register 24 is not only transmitted to the pixel unit 18, but also transmitted to the signal control unit 14 to control the signal control unit 14 to turn on or off.

[0067] In this embodiment, the non-display area 17 includes a first driving circuit 11 and a second driving circuit 23 for driving the pixel unit 18. The first shift register 12 in the first driving circuit 11 provides a first driving signal for the pixel unit 18, and the second shift register 24 in the second driving circuit 23 provides a second driving signal for the pixel unit 18. At least part of the second shift register 24 in the second driving circuit 23 is also multiplexed as a controller of the signal control unit 14, and the second driving signal provided by the second shift register 24 also controls the correspondingly connected signal control unit 14 to turn on or off, so there is no need to set an additional controller for the signal control unit 14 in the non-display area 17, thereby achieving a narrow frame.

[0068] The working phase of the optional first shift register includes a first valid pulse phase and a first invalid pulse phase; the working phase of the second shift register includes a second valid pulse phase and a second invalid pulse phase; for the first shift register and the second shift register connected to the signal control unit, the first shift register executes the first valid pulse phase within the second invalid pulse phase.

[0069] Optionally, for the first shift register and the second shift register connected to the signal control unit, in the second invalid pulse phase, the signal control unit is turned on, and the first shift register executes the first valid pulse phase in a cascade sequence.

[0070] The second driving circuit can be optionally a light-emitting control circuit, the second effective pulse stage is a light-emitting stage, and the second invalid pulse stage is a non-light-emitting stage.

[0071] The first driving circuit may be a gate scanning circuit, the first valid pulse phase may be a data writing phase, and the first invalid pulse phase may be a non-writing phase.

[0072] Fig. 9 is a schematic diagram of a pixel unit provided by an embodiment of the present invention. Fig. 9 As shown, the optional pixel unit includes a pixel circuit 31 and a light emitting element 32, and the pixel circuit 31 includes a driving transistor T0, a data writing transistor T1, a first light emitting control transistor T2, a second light emitting control transistor T3, a compensation transistor T4 and an initialization transistor T5. The first end of the driving transistor T0 is connected to the second node N2, the second end of the driving transistor T0 is connected to the third node N3, and the control end of the driving transistor T0 is connected to the first node N1. The first end of the data writing transistor T1 is connected to the data signal end Vdata, the second end of the data writing transistor T1 is connected to the second node N2, and the control end of the data writing transistor T1 is connected to the first scanning signal end S1. The first end of the first light emitting control transistor T2 is connected to the first power supply voltage end PVDD, the second end of the first light emitting control transistor T2 is connected to the second node N2, and the control end of the first light emitting control transistor T2 is connected to the light emitting control end EM. The first end of the second light emitting control transistor T3 is connected to the third node N3, the second end of the second light emitting control transistor T3 is connected to the light emitting element 32, and the control end of the second light emitting control transistor T3 is connected to the light emitting control end EM. The first end of the compensation transistor T4 is connected to the first node N1, the second end of the compensation transistor T4 is connected to the third node N3, and the control end of the compensation transistor T4 is connected to the second scan signal end S2. The first end of the initialization transistor T5 is connected to the initialization signal end Vref, the second end of the initialization transistor T5 is connected to the light emitting element 32, and the control end of the initialization transistor T5 is connected to the third scan signal end S3.

[0073] Understandably, Fig. 9 This is only a circuit diagram of a pixel unit. The pixel unit circuit structure of the display panel in the present invention includes but is not limited to Fig. 9 As shown, in other embodiments, the pixel unit circuit structure of the display panel can be 7T1C or 8T1C, etc., but is not limited thereto. Fig. 9 The pixel unit circuit structure shown is taken as an example for explanation.

[0074] Combination Figure 8 and Fig. 9As shown, the optional first drive circuit 11 is a gate scanning circuit, and the first drive signal provided by the first shift register 12 in the first drive circuit 11 is transmitted to the first scanning signal terminal S1 of the pixel unit 18, that is, the first drive signal controls the data writing transistor T1 of the pixel circuit 31 to turn on or off. If the first drive signal is a valid pulse, the first drive signal can control the data writing transistor T1 of the pixel circuit 31 to turn on, and the pixel circuit 31 performs a data writing operation, and the stage of performing the data writing operation is the data writing stage. If the first drive signal is an invalid pulse, the first drive signal can control the data writing transistor T1 of the pixel circuit 31 to turn off, and the pixel circuit 31 does not perform a data writing operation, and the stage of not performing a data writing operation is the non-writing stage. Therefore, the first valid pulse stage of the first shift register 12 is the data writing stage, and the first invalid pulse stage is the non-writing stage.

[0075] The optional second driving circuit 23 is a light-emitting control circuit, and the second driving signal provided by the second shift register 24 in the second driving circuit 23 is transmitted to the light-emitting control terminal EM of the pixel unit 18, that is, the second driving signal controls the first and second light-emitting control transistors T2 & T3 of the pixel circuit 31 to be turned on or turned off at the same time. If the second driving signal is a valid pulse, the second driving signal can control the first and second light-emitting control transistors T2 & T3 of the pixel circuit 31 to be turned on, and the pixel circuit 31 enters the light-emitting stage. If the second driving signal is an invalid pulse, the second driving signal can control the first and second light-emitting control transistors T2 & T3 of the pixel circuit 31 to be turned off, and the pixel circuit 31 enters the non-light-emitting stage. Therefore, the second valid pulse stage of the second shift register 24 is the light-emitting stage, and the second invalid pulse stage is the non-light-emitting stage.

[0076] Normally, the pixel circuit 31 performs a data write operation during a partial time period of the non-luminous stage. Therefore, for the first shift register 12 and the second shift register 24 connected to the signal control unit 14, during the second invalid pulse stage of the second shift register 24, the first shift register 12 performs a first valid pulse stage, that is, during the non-luminous stage of the pixel circuit 31, a data write operation is performed using a partial time period.

[0077] For the first shift register 12 and the second shift register 24 connected to the signal control unit 14, the first shift register 12 performs the first valid pulse stage in the second invalid pulse stage, so the first shift register 12 needs to output a valid first drive signal in a partial time period of the second invalid pulse stage. Based on this, the signal control unit 14 is turned on, and the first signal provided by the first signal line 15 is transmitted to each first shift register 12 connected to the signal control unit 14, so that each first shift register 12 connected to the signal control unit 14 outputs a valid first drive signal in a cascade sequence, so that the pixel circuit 31 performs a data write operation.

[0078] In other embodiments, the first driving circuit may be another type of circuit that drives the pixel unit. Fig. 9 The first shift register in the first driving circuit shown in the figure can provide a first driving signal to the second scanning signal terminal S2 in the pixel circuit 31. When the first driving signal is a valid pulse, the compensation transistor T4 in the pixel circuit 31 is turned on to perform threshold compensation on the driving transistor T0. Example 2, as shown in Fig. 9 The first shift register in the first driving circuit shown can provide a first driving signal to the third scanning signal terminal S3 in the pixel circuit 31. When the first driving signal is a valid pulse, the initialization transistor T5 in the pixel circuit 31 is turned on to perform an initialization operation.

[0079] As described above, the optional first signal is a normally high signal VGH in the first shift register, and the state of the second drive signal EMIT controls the signal control unit to open and close, thereby reducing the power consumption of the first signal line and improving the longitudinal uniformity. Specifically, in the non-luminous stage of the pixel circuit, the signal control unit is turned on, and the first signal line provides a stable first signal to the first shift register, and the first signal can be a high-level signal. At this time, the first shift register works normally under the drive of the first signal and outputs the first drive signal; at the same time, the energy storage capacitor in the first shift register receives the first signal and stores electrical energy. When the pixel circuit enters the luminous stage, the signal control unit is turned off, and the first signal line is disconnected from the first shift register. At this time, the energy storage capacitor in the first shift register can continue to maintain the normal operation of the first shift register, ensuring that the first shift register outputs the first drive signal. It also reduces the signal delay difference of the first shift registers of different levels.

[0080] It can be understood that the above circuit structure of the non-display area is only an example. When reducing the signal delay difference of the first shift register, the structure of the first control circuit can be flexibly selected according to different processes, devices, sizes, etc.

[0081] Based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising a display panel as described in any of the above embodiments. The display panel may be an organic light emitting display panel or a micro LED display panel, etc., but is not limited thereto. Fig.10 1 is a schematic diagram of a display device provided by an embodiment of the present invention, and the display device can be optionally applied to electronic devices 100 such as smart phones and tablet computers. It can be understood that any of the above embodiments only provide partial examples or local structures of the display panel, and the display panel in actual applications also includes other structures, which will not be described one by one here.

[0082] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A first driving circuit, the first driving circuit comprising a cascaded multi-stage first shift register, the first shift register comprising a first signal input terminal; A first control circuit, the first control circuit comprising a plurality of signal control units, wherein an output end of the signal control unit is connected to a first signal input end of at least one stage of the first shift register; A first signal line, wherein the first signal line is connected to an input end of the signal control unit; The multiple signal control units are turned on in different time periods; The first control circuit further includes: a second driving circuit, the second driving circuit includes a cascaded multi-stage second shift register, and the second shift register includes a second signal output terminal; The control end of the signal control unit is connected to the second signal output end of the second shift register of one stage, and the second shift register is used to control the signal control unit to be turned on or off.

2. The display panel according to claim 1, characterized in that: For two stages of the first shift registers connected to different signal control units, the start time of the signal control unit connected to the upper stage of the first shift register is earlier than the start time of the signal control unit connected to the lower stage of the first shift register.

3. The display panel according to claim 1, characterized in that: The output end of the signal control unit is connected to the first signal input ends of at least two cascaded stages of the first shift registers.

4. The display panel according to claim 1, characterized in that: The signal control unit includes a first switch connected between the first signal line and a first signal input terminal of the first shift register.

5. The display panel according to claim 4, characterized in that: The first switch includes a first transistor; or, the first switch includes an inverter and a second transistor.

6. The display panel according to claim 5, characterized in that: The first transistor is NMOS or PMOS; The second transistor is NMOS or PMOS.

7. The display panel according to claim 1, characterized in that: The first shift register includes an energy storage capacitor; The first shift register is used to output under the drive of the first signal line when the signal control unit is turned on, and is also used to output under the drive of the energy storage capacitor when the signal control unit is turned off.

8. The display panel according to claim 1, characterized in that: In the first control circuit, the number of stages of the second shift register is greater than or equal to the number of the signal control units.

9. The display panel according to claim 1, characterized in that: In the multiple stages of the second shift registers connected to the multiple signal control units, the multiple stages of the second shift registers are cascade-connected.

10. The display panel according to claim 1, characterized in that: Among the plurality of stages of the second shift registers connected to the plurality of signal control units, there are two adjacent stages of the second shift registers that are not cascaded.

11. The display panel according to claim 1, characterized in that: The display panel includes a first area and a second area, the first area includes pixel units; The second driving circuit is arranged in the second area, and the second signal output terminal of the second shift register is also connected to a row of pixel units; The first shift register comprises a first signal output terminal, and the first signal output terminal of the first shift register is connected to a row of pixel units.

12. The display panel according to claim 1, characterized in that: The working phase of the first shift register includes a first valid pulse phase and a first invalid pulse phase; The working phase of the second shift register includes a second valid pulse phase and a second invalid pulse phase; For the first shift register and the second shift register connected to the signal control unit, the first shift register performs the first valid pulse phase within the second invalid pulse phase.

13. The display panel according to claim 12, characterized in that: For the first shift register and the second shift register connected to the signal control unit, in the second invalid pulse phase, the signal control unit is turned on, and the first shift register performs the first valid pulse phase in a cascade sequence.

14. The display panel according to claim 12, characterized in that: The second driving circuit is a light-emitting control circuit, the second effective pulse stage is a light-emitting stage, and the second invalid pulse stage is a non-light-emitting stage.

15. The display panel according to claim 12, characterized in that: The first driving circuit is a gate scanning circuit, the first valid pulse phase is a data writing phase, and the first invalid pulse phase is a non-writing phase.

16. A display device, characterized in that: A display panel comprising any one of claims 1-15.

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