Scan driving circuit and display device

Abstract

The application discloses a scanning driving circuit and a display device. The scanning driving circuit comprises a plurality of shift registers. The shift register comprises a driving control module, an output control module and a scanning output module. The driving control module is used for controlling the potential of the first output end and the second output end of the driving control module according to an input signal; the input end of the output control module is connected with the first output end or the second output end, and the control end of the output control module inputs a frequency switching control signal; and the scanning output module is used for responding to the potential of the output end of the output control module, and controlling the output of a scanning signal to the output end of the shift register. The embodiment of the application can make the display device have a partition frequency display function.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a scanning driving circuit and a display device. BACKGROUND

[0002] With the development of display technology, the application scenarios of display devices are more and more, and the display requirements of users on display devices are more and more diversified. Based on the release of folding mobile phones and folding laptops, the application scenarios of display devices are further expanded. For the user's demand for multiple applications to be displayed simultaneously on terminal products, part of the interface (such as the game interface) in the display screen needs to be displayed at high frequency to ensure the smoothness of the picture, and part of the interface can meet the display requirement by using low frequency. This part is expected to use low frequency display to reduce product power consumption. However, the scanning driving circuit in the prior art cannot meet the user's demand for displaying multiple scenes in one screen on terminal products, and cannot realize the partition frequency display of the display device. SUMMARY

[0003] The present application provides a scanning driving circuit and a display device, so that the display device has the function of partition frequency display.

[0004] In a first aspect, an embodiment of the present application provides a scanning driving circuit, comprising: a plurality of shift registers;

[0005] The shift register comprises:

[0006] a driving control module, the driving control module being configured to control the potential of the first output end and the second output end of the driving control module according to the input signal of the shift register;

[0007] an output control module, an input end of the output control module being connected to the first output end or the second output end, and a control end of the output control module inputting a frequency switching control signal;

[0008] a scanning output module connected to an output end of the output control module, configured to control the output of a scanning signal to the output end of the shift register in response to the potential of the output end of the output control module; wherein the frequency switching control signal controls the frequency of the scanning signal by controlling the potential of the output end of the output control module.

[0009] Optionally, the output control modules in the shift registers at all levels are connected to the same frequency switching control signal.

[0010] The frequency switching control signal maintains the on-potential of the output control module in part of the display frames, and performs potential jump in part of the display frames, so that the frequencies of the scanning signals output by at least two shift registers are different, to realize the partition frequency display of the display device.

[0011] Optionally, the input terminal of the output control module is connected to the first output terminal; the first control terminal of the scan output module is connected to the output terminal of the output control module, and the second control terminal of the scan output module is connected to the second output terminal; the potential of the output terminal of the output control module is used to control whether the scan output module outputs the on-state potential of the scan signal.

[0012] Optionally, the output control module includes: a first transistor; the gate of the first transistor is electrically connected to the control terminal of the output control module, the first electrode of the first transistor is electrically connected to the input terminal of the output control module, and the second electrode of the first transistor is electrically connected to the output terminal of the output control module.

[0013] Optionally, the shift register further includes: a first switch module electrically connected to the output terminal of the output control module, used to respond to a first switch signal, transmit a first potential signal to the output terminal of the output control module, and control the scan output module to stop outputting the on-potential of the scan signal.

[0014] Optionally, the output control module includes: a first transistor; the gate of the first transistor is electrically connected to the control terminal of the output control module, the first electrode of the first transistor is electrically connected to the input terminal of the output control module, and the second electrode of the first transistor is electrically connected to the output terminal of the output control module;

[0015] The first switching module includes: a second transistor; the gate of the second transistor is connected to the first switching signal, the first terminal of the second transistor is connected to the first potential signal, and the second terminal of the second transistor is electrically connected to the output terminal of the output control module;

[0016] Preferably, the first transistor and the second transistor have the same channel type, and the frequency switching control signal and the first switching signal are inverse signals to each other;

[0017] Alternatively, the first transistor and the second transistor may have different channel types, and the frequency switching control signal may be multiplexed as the first switching signal.

[0018] Optionally, the shift register further includes: a second switch module electrically connected to the output terminal of the output control module, used to respond to a second switch signal, transmit a second potential signal to the output terminal of the output control module, and control the scanning output module to output the on-potential of the scanning signal;

[0019] Preferably, the second switching module includes a third transistor; the gate of the third transistor is connected to the second switching signal, the first terminal of the third transistor is connected to the second potential signal, and the second terminal of the third transistor is electrically connected to the output terminal of the output control module.

[0020] Preferably, the input signal connected to this stage shift register is multiplexed into the second switching signal required by this stage shift register.

[0021] Optionally, the shift register further includes: a first protection module; the first protection module is connected between the output terminal of the output control module and the scan output module, and the control terminal of the first protection module is connected to a second potential signal;

[0022] Preferably, the first protection module includes a fourth transistor; the gate of the fourth transistor is connected to a second potential signal, the first terminal of the fourth transistor is electrically connected to the output terminal of the output control module, and the second terminal of the fourth transistor is electrically connected to the scan output module.

[0023] Optionally, the drive control module includes:

[0024] An input unit, electrically connected to the first output terminal, is used to transmit the input signal to the first output terminal in response to a first clock signal;

[0025] A potential control unit, electrically connected to the second output terminal, is used to transmit a second potential signal to the second output terminal in response to the first clock signal;

[0026] The first node control unit is electrically connected to the first output terminal and the second output terminal respectively, and is used to transmit the first clock signal to the second output terminal in response to the potential of the first output terminal.

[0027] The second node control unit is electrically connected to the first output terminal and the second output terminal respectively, and is used to transmit the first potential signal to the first output terminal in response to the second clock signal and the potential of the second output terminal.

[0028] Optionally, the scan output module includes:

[0029] The first output unit is electrically connected to the output terminal of the output control module and is used to respond to the potential conduction of the output terminal of the output control module.

[0030] The second output unit is electrically connected to the second output terminal and is used to respond to the potential conduction of the second output terminal;

[0031] Preferably, the first output unit includes a fifth transistor and a first capacitor; the gate of the fifth transistor is electrically connected to the output terminal of the output control module, the first terminal of the fifth transistor is connected to a second clock signal, and the second terminal of the fifth transistor serves as the output terminal of the scan output module; the first capacitor is connected between the gate and the second terminal of the fifth transistor.

[0032] The second output unit includes a sixth transistor; the gate of the sixth transistor is electrically connected to the second output terminal, the first terminal of the sixth transistor is connected to a first potential signal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor.

[0033] Optionally, the plurality of shift registers are cascaded; the scan signal serves as the input signal for the next-stage shift register.

[0034] Optionally, the plurality of shift registers are cascaded; the shift register further includes: a stage output module, electrically connected to the first output terminal and the second output terminal respectively, for responding to the potential of the first output terminal and the second output terminal and outputting a stage transmission signal; the stage transmission signal serves as the input signal for the next stage shift register;

[0035] Preferably, the first control terminal of the stage transmission module is connected to the first output terminal, and the second control terminal of the stage transmission module is connected to the second output terminal.

[0036] Optionally, the shift register further includes: a second protection module, the first end of which is connected to the first output terminal, and the second end of which is connected to the first control terminal of the stage output module;

[0037] The input terminal of the output control module is connected to either the first or second terminal of the second protection module.

[0038] Optionally, the stage transmission module includes:

[0039] The third output unit is electrically connected to the first output terminal and is used to respond to the potential conduction of the first output terminal;

[0040] The fourth output unit is electrically connected to the second output terminal and is used to respond to the potential conduction of the second output terminal;

[0041] Preferably, the third output unit includes a seventh transistor and a second capacitor; the gate of the seventh transistor is electrically connected to the first output terminal, the first terminal of the seventh transistor is connected to a second clock signal, and the second terminal of the seventh transistor serves as the output terminal of the stage transmission module; the second capacitor is connected between the gate and the second terminal of the seventh transistor.

[0042] The fourth output unit includes an eighth transistor and a third capacitor; the gate of the eighth transistor is electrically connected to the second output terminal, the first terminal of the eighth transistor is connected to a first potential signal, and the second terminal of the eighth transistor is electrically connected to the second terminal of the seventh transistor; the third capacitor is connected between the gate and the first terminal of the eighth transistor.

[0043] Preferably, the capacitance of the second capacitor is greater than the capacitance of the third capacitor.

[0044] Secondly, embodiments of the present invention also provide a display device, including: a pixel circuit and a scanning driving circuit provided in any embodiment of the present invention.

[0045] The scanning drive circuit provided in this embodiment of the invention includes multiple shift registers, each of which includes a drive control module, an output control module, and a scan output module. By adjusting the on / off state of the output control module through a frequency switching control signal, the potential of the first output terminal (or the second output terminal) can be allowed / blocked from being transmitted to the output terminal of the output control module, thereby allowing / blocking the scanning output module to output the scanning signal's conduction potential, thus controlling the operating mode of the shift registers. By controlling the potential transition process of the frequency switching control signal, different combinations of operating modes for each shift register can be controlled, so that the scan signals output by at least two shift registers have different frequencies, thereby achieving segmented frequency display on the display device. In summary, compared to the prior art, this embodiment of the invention enables the display device to support segmented frequency display functionality.

[0046] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0050] Figure 3This is a schematic diagram of the driving timing of a display panel provided in an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the driving timing of a shift register in a first working mode according to an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the driving timing of a shift register in a second working mode according to an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0057] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0058] Figure 11 This is a schematic diagram of the driving timing of another shift register in the second working mode provided by an embodiment of the present invention;

[0059] Figure 12 This is a schematic diagram of the driving timing of another shift register in the second working mode provided by an embodiment of the present invention;

[0060] Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0061] Figure 14 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0062] Figure 15 This is a schematic diagram of the driving timing of another shift register in the first working mode provided by an embodiment of the present invention;

[0063] Figure 16 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0064] Figure 17 This is a schematic diagram of the driving timing of another display panel provided in an embodiment of the present invention;

[0065] Figure 18 This is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0066] Figure 19 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0067] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0068] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0070] This invention provides a scanning driving circuit to enable a display device to support the function of displaying different frequencies in partitions within a screen. Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention. See also... Figure 1 The scan drive circuit includes multiple shift registers 10, and each shift register 10 may have the same structure. Figure 1 The first two stages of shift register 10 are shown as an example. Shift register 10 may include: a drive control module 110, an output control module 130, and a scan output module 140.

[0071] The drive control module 110 controls the potentials of its first output terminal N1 and second output terminal N2 based on the input signal from the shift register 10. The input terminal of the output control module 130 is connected to either the first output terminal N1 or the second output terminal N2. Figure 1The example diagram illustrates an output control module 130 with its input terminal connected to a first output terminal N1, and its control terminal receiving a frequency switching control signal SW0. A scan output module 140 is connected to the output terminal N3 of the output control module 130 and, in response to the potential of the output terminal N3 of the output control module 130, controls the output scan signal to the output terminal of the shift register 10. The frequency switching control signal SW0 controls the frequency of the scan signal by controlling the potential of the output terminal N3 of the output control module 130.

[0072] For example, the scan output module 140 may include a first control terminal, a second control terminal, a turn-on potential input terminal, a cut-off potential input terminal, and an output terminal. The potential of the first control terminal of the scan output module 140 is used to control whether the turn-on potential input terminal is connected to the output terminal, and the potential of the second control terminal is used to control whether the cut-off potential input terminal is connected to the output terminal, thereby enabling the scan output module 140 to control the potential of the scan signal based on the potentials of its first and second control terminals. When the potential of the first control terminal of the scan output module 140 controls its turn-on potential input terminal to be connected to the output terminal, and the turn-on potential input terminal is connected to a turn-on potential, the scan signal is at a turn-on potential. It should be noted that the turn-on potential can be understood as the potential used to control the functional module connected to the scan signal to be turned on, and correspondingly, the cut-off potential can be understood as the potential used to control the functional module connected to the scan signal to be turned off. For example, when the functional module includes a P-type transistor, the turn-on potential is low and the cut-off potential is high.

[0073] The output terminal N3 of the output control module 130 can be connected to the first control terminal of the scan output module 140, so that the output control module 130 controls whether the scan output module 140 outputs a scan signal conduction potential by controlling the potential of the output terminal N3. The two output terminals of the drive control module 110 can be connected to the input terminal of the output control module 130 and the second control terminal of the scan output module 140, respectively. For example, the first output terminal N1 can be connected to the input terminal of the output control module 130, and the second output terminal N2 can be connected to the second control terminal of the scan output module 140.

[0074] For any shift register 10, the frequency switching control signal SW0 controls the on / off state of the output control module 130, thereby controlling the operating mode of the shift register 10. Specifically, the output control module 130 can control the scan output module 140 to operate in the following two modes:

[0075] In the first operating mode, when the first output terminal N1 provides a potential that controls the connection between the on-state potential input terminal and the output terminal of the scan output module 140, the frequency switching control signal SW0 maintains the on-state potential of the output control module 130 (e.g., a low potential), so that the output control module 130 is turned on. Then, the potential of the first output terminal N1 can be reliably transmitted to the output terminal N3 of the output control module 130, controlling the connection between the on-state potential input terminal and the output terminal of the scan output module 140, so that the scan signal of this stage includes the on-state potential (e.g., a low potential).

[0076] In the second operating mode, when the first output terminal N1 provides a potential that can control the connection between the on-state potential input terminal and the output terminal of the scan output module 140, the frequency switching control signal SW0 maintains the off-state potential (e.g., a high potential) of the output control module 130, causing the output control module 130 to turn off. The potential of the first output terminal N1 cannot be transmitted to the output terminal N3 of the output control module 130, so the connection between the on-state potential input terminal and the output terminal of the scan output module 140 cannot be controlled. The scan signal of this stage maintains the off-state potential (e.g., a high potential) from the previous stage.

[0077] When a certain stage shift register 10 is always working in the first working mode, it can shift the conduction pulse in its input signal to the output, so that the frequency of the scan signal is the same as the frequency of the input signal; when a certain stage shift register 10 is in the second working mode for at least part of the time period, the frequency of the scan signal output by the shift register 10 is lower than the frequency of its input signal.

[0078] For example, each level of scan signal is transmitted through each row of scan lines to the functional modules related to the data writing process in each row of pixel circuits. When a certain level of shift register 10 operates in the first operating mode, since the scan signal contains a conduction pulse, it can control the pixel circuit of the corresponding row to refresh the data, making the current frame of that row of pixel circuits a refreshed frame. When a certain level of shift register 10 operates in the second operating mode, since the scan signal does not contain a conduction pulse, the pixel circuit of the corresponding row cannot refresh the data, making the current frame of that row of pixel circuits a held frame. Therefore, the frequency of the scan signal determines the data refresh frequency of the pixel circuit. Based on this, by controlling the potential transition of the frequency switching control signal SW0, the operating mode of each shift register 10 can be controlled in each frame of display, thereby realizing the display of different frequencies in the column direction of the display device.

[0079] The scanning drive circuit provided in this embodiment of the invention includes multiple shift registers 10, each shift register 10 comprising a drive control module 110, an output control module 130, and a scan output module 140. By adjusting the on / off state of the output control module 130 through the frequency switching control signal SW0, the potential of the first output terminal N1 (or the second output terminal N2) can be allowed / blocked from transmitting to the output terminal N3 of the output control module 130, thereby allowing / blocking the conduction potential of the scan output module 140 to output the scan signal, thus controlling the operating mode of the shift registers 10. By controlling the potential transition process of the frequency switching control signal SW0, the operating mode combination of each shift register 10 can be controlled to be different, so that the scan signals output by at least two shift registers 10 have different frequencies, thereby realizing the segmented frequency display of the display device. In summary, compared with the prior art, this embodiment of the invention enables the display device to support segmented frequency display functionality.

[0080] See also Figure 1 Based on the above embodiments, optionally, multiple shift registers 10 can be cascaded. Specifically, the scan signal output by the current shift register 10 can be set as the input signal of the next-stage shift register. For example... Figure 1 As shown, the first-stage shift register 101 receives the first-stage input signal SIN1 and outputs the first-stage scan signal GOUT1 based on the first-stage input signal and the frequency switching control signal SW0. The first-stage scan signal GOUT1 serves as the second-stage input signal SIN2 and is transmitted to the second-stage shift register 102. The second-stage shift register 102 outputs the second-stage scan signal GOUT2 (serving as the third-stage input signal SIN3) based on the second-stage input signal SIN2 and the frequency switching control signal SW0, and so on.

[0081] Based on the above embodiments, optionally, the output control modules 130 in each level of shift register 10 can all be connected to the same frequency switching control signal SW0, so that each level of output control module 130 is simultaneously turned on or off in response to the frequency switching control signal SW0. This configuration simplifies the structure of the scan drive circuit, reduces the number of output ports of the driver chip, lowers the cost, and makes the scan drive circuit easy to implement and apply. By controlling the frequency switching control signal SW0 to maintain the on potential of the output control module 130 in some display frames and to perform potential transitions in some display frames, the frequencies of the scan signals output by at least two shift registers 10 can be different, thereby realizing the segmented frequency display of the display device. Furthermore, by adjusting the potential transition time of the frequency switching control signal SW0 in a frame of display, the boundary position of the shift register 10's working mode switching can be adjusted, thereby realizing the adjustment of the display partition position of the display device. Each level shift register 10 is connected to at least one row of pixel circuits, and the number of shift registers 10 in the first working mode in a frame determines the number of pixel circuit rows refreshed in that frame.

[0082] It should be noted that at any given moment, only one first shift register 10 has its output stage signal transmission at the on-state potential, while the other first shift registers 10 have their output stage signal transmission at the off-state potential. Therefore, the frequency switching control signal SW0 only affects the first shift register 10 that is currently at the on-state potential of its output stage signal transmission, controlling whether its scan output module 140 outputs the scan signal at that moment. For other first shift registers 10, regardless of whether the frequency switching control signal SW0 cuts off the output control module, the scan signals of other stages remain at the off-state potential. Therefore, the simultaneous on / off state of all output control modules 130 does not affect the normal driving of the display panel.

[0083] according to Figure 1The cascading of shift registers 10 in the display panel enables zoned frequency reduction display. Specifically, when the frequency switching control signal SW0 controls the output control module 130 to turn off during the phase when any shift register 10 should output the on-state potential of the scan signal, that shift register 10 cannot output the on-state potential of the scan signal, making the frequency of the scan signal at that level lower than the frequency of the scan signal at the previous level. The shift register 10 at the previous level and the shift register 10 at this level correspond to the frequency reduction display zone positions. Furthermore, in the current frame display, since the shift register 10 at this level cannot output the on-state potential, the input signal of the next-level shift register 10 does not contain a conduction pulse. Therefore, even if the frequency switching control signal SW0 switches back to the on-state potential of the output control module 130 during the phase when the next-level shift register 10 is in operation, since there is no conduction pulse in the input signal of the next-level shift register, the next-level shift register 10 cannot restore the on-state potential of the output scan signal and can only continuously output the off-state potential, thus failing to achieve zoned frequency increase display.

[0084] The above embodiments provide structures for scanning drive circuits capable of achieving zoned frequency reduction display, but are not intended to limit the invention. In other embodiments, by setting the shift registers 10 at each stage to adopt other cascading methods, the scanning drive circuit can support arbitrarily adjustable zoned frequency reduction and increase display functions.

[0085] Figure 2 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 2 In one embodiment, the shift register 10 may optionally include a stage transmission output module 120, which is electrically connected to the first output terminal N1 and the second output terminal N2 respectively, and is used to output a stage transmission signal in response to the potential of the first output terminal N1 and the second output terminal N2; the stage transmission signal is used as the input signal of the next stage shift register 10.

[0086] Specifically, the cascading method between each shift register 10 is as follows: Figure 2 As shown, the first-stage shift register 101 receives the first-stage input signal SIN1 and outputs the first-stage transmission signal Carry1 and the first-stage scan signal GOUT1 based on the first-stage input signal and the frequency switching control signal SW0. The first-stage transmission signal Carry1 serves as the second-stage input signal SIN2 and is transmitted to the second-stage shift register 102. The second-stage shift register 102 outputs the second-stage transmission signal Carry2 (serving as the third-stage input signal SIN3) and the second-stage scan signal GOUT2 based on the second-stage input signal SIN2 and the frequency switching control signal SW0, and so on.

[0087] For example, the stage transmission output module 120 and the scan output module 140 can be output modules with the same structure. The stage transmission output module 120 may also include a first control terminal, a second control terminal, a conduction potential input terminal, a cutoff potential input terminal, and an output terminal. Then, for the stage transmission output module 120, the two output terminals of the drive control module 110 can be respectively connected to the two control terminals of the stage transmission output module 120, so that the drive control module 110 controls the stage transmission output module 120 to output the stage transmission signal by controlling the potentials of the first output terminal N1 and the second output terminal N2. For example, the first output terminal N1 can be connected to the first control terminal of the stage transmission output module 120, and the second output terminal N2 can be connected to the second control terminal of the stage transmission output module 120. Based on the potential control of the first output terminal N1 and the second output terminal N2 by the drive control module 110, the stage transmission output module 120 can realize the shifted output of the input signal conduction pulse. Figure 3 As shown, Figure 3 The example illustrates the output of a 6-stage bit register 10. Since each stage of the shift register 10 is cascaded through a stage output module 120, the stage-by-stage shift output of the conduction pulse of the first-stage input signal SIN1 can be achieved through each stage output module 120. This provides a high-frequency cascaded signal sequence with the same frequency as the first-stage input signal SIN1, allowing each stage of the scan output module 140 to freely select whether to output the conduction pulse based on the control of the output control module 130. The frequency of the first-stage input signal SIN1 can be understood as the pulse frequency of the conduction pulse of the first-stage input signal SIN1.

[0088] Based on the stepped output module 120, the output states of the shift register 10 in different operating modes are as follows:

[0089] For the first working mode, please refer to Figure 3 The output states of shift registers 10 at each level in frames F1 and F3 are displayed, as are the output states of shift registers 10 at levels 1, 2, 5, and 6 in frames F2 and F4. During the stage where the output module 120 of this level outputs a conduction potential (e.g., a low potential), the frequency switching control signal SW0 maintains the conduction potential (e.g., a low potential VL) of the output control module 130, enabling the output control module 130 to conduct. Then, the potential of the first output terminal N1 can be transmitted to the output terminal N3 of the output control module 130, controlling the connection between the conduction potential input and output terminals of the scan output module 140, making the scan signal of this level also a conduction potential.

[0090] For the second working mode, please refer to Figure 3The output states of the third and fourth stage shift registers 10 in frames F2 and F4 are displayed. During the stage when the output module 120 of this stage is on, the frequency switching control signal SW0 maintains the cutoff potential (e.g., high potential VH) of the output control module 130, causing the output control module 130 to turn off. The potential of the first output terminal N1 cannot be transmitted to the output terminal N3 of the output control module 130. Therefore, the connection between the on potential input terminal and the output terminal of the scan output module 140 cannot be controlled, and the scan signal of this stage maintains the cutoff potential (e.g., high potential) from the previous stage.

[0091] When a certain level shift register 10 is always operating in the first operating mode, the frequency of the level transmission signal output by the shift register 10 is the same as the frequency of the scan signal; when a certain level shift register 10 is in the second operating mode for at least part of the time period, the frequency of the scan signal output by the shift register 10 is lower than the frequency of its output level transmission signal.

[0092] based on Figure 2 When the structure of the mid-scan drive circuit controls the display panel to perform zoned and frequency-based display, it uses... Figure 3 Taking a three-screen display as an example, assuming the display panel is divided into a first display area A1, a second display area A2, and a third display area A3 from top to bottom, with refresh rates of f, f / 2, and f respectively, then the frequency division from the first display area A1 to the second display area A2 is equivalent to a frequency division display where the display frequency decreases from high to low, and the frequency division from the second display area A2 to the third display area A3 is equivalent to a frequency division display where the display frequency increases from low to high. The size of each display area is determined by the number of shift registers 10 that provide the corresponding frequency scan signals. Taking two levels of shift registers 10 for each display area as an example, the frequency of the scan signals output by the shift registers 10 corresponding to the first display area A1 and the third display area A3 is f. For example, the first, second, fifth, and sixth level shift registers 10 are set to operate in the first working mode in each display frame. The frequency of the scanning signal output by the shift register 10 corresponding to the second display area A2 is f / 2. For example, the third and fourth level shift registers 10 are set to work in the first working mode in odd frames and in the second working mode in even frames.

[0093] In summary, during the entire display process, by controlling the frequency switching control signal SW0 to maintain the on-state potential of the output control module 130 in some display frames (e.g., display frames F1 and F3) and to perform potential transitions in other display frames (e.g., display frames F2 and F4), the display device can achieve segmented frequency display in the column direction. Furthermore, by adjusting the specific potential transition time of the frequency switching control signal SW0, the display partition positions of the display device can be flexibly adjusted. For example, for... Figure 3The partition position between the first display area A1 and the second display area A2, in each even-numbered display frame, if the rising edge of the control frequency switching control signal SW0 occurs earlier than... Figure 3 When the potential jumps in the middle, the number of shift registers corresponding to the first display area A1 can be reduced, thereby realizing the upward shift of the partition position between the first display area A1 and the second display area A2.

[0094] It is important to note that Figure 3 The fact that the frequency switching control signal SW0 performs two potential transitions in each even-numbered frame is merely illustrative and not intended to limit the scope of the invention. In other embodiments, the frequency switching control signal SW0 can be configured to perform potential transitions in any desired display frame to control the refresh rate of each display area. The frequency switching control signal SW0 can be configured to perform only one potential transition or multiple potential transitions in a single display frame, depending on requirements, to control the number of display zones on the display device. Furthermore, the timing of the potential transitions of the frequency switching control signal SW0 can differ in different display frames to achieve dynamic adjustment of the display zone positions during the display process.

[0095] The scanning drive circuit provided in this embodiment of the invention includes multiple cascaded shift registers 10. Each shift register 10 includes a drive control module 110, a stage transmission output module 120, an output control module 130, and a scan output module 140. Based on the control of the first output terminal N1 and the second output terminal N2 by the drive control module 110, each stage transmission output module 120 can realize the stage-by-stage shift output of the first-stage input signal SIN1, providing a stage transmission signal with the same frequency as the first-stage input signal SIN1. This provides a basis for each stage shift register 10 to freely select the output of a scan signal with the same frequency as or lower than the first-stage input signal SIN1. The on / off state of the output control module 130 is adjusted by the frequency switching control signal SW0 to allow / block the transmission of the potential of the first output terminal N1 to the output terminal N3 of the output control module 130, thereby allowing / blocking the conduction potential of the scan output module 140 to output the scan signal, thus realizing the control of the working mode of the shift register 10. By controlling the potential transition process of the frequency switching control signal SW0, the operating mode combination of each shift register 10 can be controlled to be different, so that the scanning signal output by at least two shift registers 10 has a different frequency, thereby realizing the segmented frequency display of the display device. In summary, compared with the prior art, the embodiments of the present invention enable the display device to support the segmented frequency display function and support arbitrary switching of different zone display frequencies.

[0096] The structure of shift register 10 will be described first by example, and then the specific driving process of driving the display device to perform multi-frequency display based on the scanning driving circuit will be described by example.

[0097] Figure 4 This is a schematic diagram of a shift register provided in an embodiment of the present invention. See also: Figure 4 In one embodiment, optionally, the drive control module 110 controls the potentials of the first output terminal N1 and the second output terminal N2 in response to the first clock signal SCK1, the second clock signal SCK2, the input signal SIN, the first potential signal VGH, and the second potential signal VGL. The stage transmission output module 120 outputs either the first potential signal VGH or the second clock signal SCK2 as the stage transmission signal Carry based on the potentials of the first output terminal N1 and the second output terminal N2. Specifically, the first control terminal 21 of the stage transmission output module 120 is connected to the first output terminal N1, the second control terminal 22 is connected to the second output terminal N2, the on-potential input terminal 23 is connected to the second clock signal SCK2, the off-potential input terminal 24 is connected to the first potential signal VGH, and the output terminal 25 outputs the stage transmission signal Carry. The input terminal of the output control module 130 is connected to the first output terminal N1 of the drive control module 110 and is used to control whether the potential of the first output terminal N1 is transmitted to the output terminal N3 of the output control module 130 according to the frequency switching control signal SW0. The scan output module 140 is used to respond to the potential of the output terminal N3 and the second output terminal N2 of the output control module 130, and outputs the first potential signal VGH or the second clock signal SCK2 as the scan signal GOUT to the pixel circuit. Specifically, the first control terminal 41 of the scan output module 140 is connected to the output terminal N3 of the output control module 130, the second control terminal 42 is connected to the second output terminal N2, the on potential input terminal 43 is connected to the second clock signal SCK2, the off potential input terminal 44 is connected to the first potential signal VGH, and the output terminal 45 outputs the scan signal GOUT.

[0098] For example, the first potential signal VGH and the second potential signal VGL can be DC voltage signals with different potentials, such as the first potential signal VGH being a high potential and the second potential signal VGL being a low potential. The first clock signal SCK1 and the second clock signal SCK2 are both clock signals with alternating high and low potentials.

[0099] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 5Based on the above embodiments, optionally, the drive control module 110 includes: an input unit 111, a potential control unit 112, a first node control unit 113, and a second node control unit 114. The input unit 111 is electrically connected to the first output terminal N1 and is used to transmit the input signal SIN to the first output terminal N1 in response to the first clock signal SCK1. The potential control unit 112 is electrically connected to the second output terminal N2 and is used to transmit the second potential signal VGL to the second output terminal N2 in response to the first clock signal SCK1. The first node control unit 113 is electrically connected to both the first output terminal N1 and the second output terminal N2 and is used to transmit the first clock signal SCK1 to the second output terminal N2 in response to the potential of the first output terminal N1. The second node control unit 114 is electrically connected to both the first output terminal N1 and the second output terminal N2 and is used to transmit the first potential signal VGH to the first output terminal N1 in response to the second clock signal SCK2 and the potential of the second output terminal N2.

[0100] Specifically, input unit 111 includes transistor M11, whose gate is connected to a first clock signal SCK1, whose first terminal is connected to an input signal SIN, and whose second terminal is electrically connected to a first output terminal N1. Potential control unit 112 includes transistor M12, whose gate is connected to the first clock signal SCK1, whose first terminal is connected to a second potential signal VGL, and whose second terminal is electrically connected to a second output terminal N2. First node control unit 113 includes transistor M13, whose gate is electrically connected to a first output terminal N1, whose first terminal is connected to the first clock signal SCK1, and whose second terminal is electrically connected to a second output terminal N2. Second node control unit 114 includes transistors M14 and M15, whose gate is electrically connected to a second output terminal N2, whose first terminal is connected to a first potential signal VGH, whose second terminal is connected to the second terminal of transistor M15, whose gate is connected to a second clock signal SCK2, and whose first terminal is electrically connected to a first output terminal N1.

[0101] See also Figure 5 Based on the above embodiments, optionally, the stage transmission output module 120 includes: a third output unit 121 and a fourth output unit 122, which respectively control the conduction state between the on-potential input terminal and the off-potential input terminal and the output terminal of the stage transmission output module 120. The third output unit 121 is electrically connected to the first output terminal N1 and is used to control the conduction state between the on-potential input terminal and the output terminal of the stage transmission output module 120 in response to the potential of the first output terminal N1. The fourth output unit 122 is electrically connected to the second output terminal N2 and is used to control the conduction state between the off-potential input terminal and the output terminal of the stage transmission output module 120 in response to the potential of the second output terminal N2.

[0102] Specifically, the third output unit 121 includes a seventh transistor M7 and a second capacitor C2; the gate of the seventh transistor M7 is electrically connected to the first output terminal N1, the first terminal of the seventh transistor M7 is connected to the second clock signal SCK2, and the second terminal of the seventh transistor M7 serves as the output terminal of the stage transmission output module 120; the second capacitor C2 is connected between the gate and the second terminal of the seventh transistor M7. The second capacitor C2 is used to maintain the gate potential of the seventh transistor M7 and to control the gate potential of the seventh transistor M7 according to the potential coupling of the stage transmission signal Carry. The fourth output unit 122 includes an eighth transistor M8 and a third capacitor C3; the gate of the eighth transistor M8 is electrically connected to the second output terminal N2, the first terminal of the eighth transistor M8 is connected to the first potential signal VGH, and the second terminal of the eighth transistor M8 is electrically connected to the second terminal of the seventh transistor M7; the third capacitor C3 is connected between the gate and the first terminal of the eighth transistor M8. The second capacitor C2 is used to maintain the gate potential of the eighth transistor M8.

[0103] See also Figure 5 Based on the above embodiments, optionally, the output control module 130 includes a first transistor M1. The gate of the first transistor M1 is electrically connected to the control terminal of the output control module 130, the first electrode of the first transistor M1 is electrically connected to the input terminal of the output control module 130, and the second electrode of the first transistor M1 is electrically connected to the output terminal of the output control module 130. In this embodiment, the output control module 130 is configured with a single transistor, making the structure of the output control module 130 simple and easy to implement.

[0104] See also Figure 5 Based on the above embodiments, optionally, the scan output module 140 includes: a first output unit 141 and a second output unit 142, which respectively control the conduction state between the on-potential input terminal and the off-potential input terminal of the scan output module 140 and the output terminal. The first output unit 141 is electrically connected to the output terminal N3 of the output control module 130 and is used to control the conduction between the on-potential input terminal and the output terminal of the scan output module 140 in response to the potential of the output terminal N3 of the output control module 130. The second output unit 142 is electrically connected to the second output terminal N2 and is used to control the conduction between the off-potential input terminal and the output terminal of the scan output module 140 in response to the potential of the second output terminal N2.

[0105] Specifically, the first output unit 141 includes a fifth transistor M5 and a first capacitor C1. The gate of the fifth transistor M5 is electrically connected to the output terminal N3 of the output control module 130, the first terminal of the fifth transistor M5 is connected to the second clock signal SCK2, and the second terminal of the fifth transistor M5 serves as the output terminal of the scan output module 140. The first capacitor C1 is connected between the gate and the second terminal of the fifth transistor M5. The first capacitor C1 is used to maintain the gate potential of the fifth transistor M5 and to control the gate potential of the fifth transistor M5 according to the potential coupling of the scan signal GOUT. The second output unit 142 includes a sixth transistor M6. The gate of the sixth transistor M6 is electrically connected to the second output terminal N2, the first terminal of the sixth transistor M6 is connected to the first potential signal VGH, and the second terminal of the sixth transistor M6 is electrically connected to the second terminal of the fifth transistor M5. Since the gates of both the sixth transistor M6 and the eighth transistor M8 are connected to the second output terminal N2, the third capacitor C3 can simultaneously maintain the gate potential of the sixth transistor M6. Therefore, it is not necessary to separately set a capacitor between the gate and the first terminal of the sixth transistor M6, thereby reducing the area of ​​the shift register 10.

[0106] The following is based on Figure 5 The structure of shift register 10, taking the example where all transistors in shift register 10 are P-type transistors, combined with... Figure 5-6 The driving process of shift register 10 is explained.

[0107] Figure 6 This is a schematic diagram of the driving timing of a shift register in a first operating mode according to an embodiment of the present invention, combined with... Figure 5 and Figure 6 When shift register 10 operates in the first operating mode, the frequency switching control signal SW0 can maintain a low potential VL during a single display frame, keeping the first transistor M1 on. During this display frame, the potential VN3 of the output terminal N3 of the output control module 130 remains consistent with the potential VN1 of the first output terminal N1, thus ensuring that the operating states of the stage transmission output module 120 and the scan output module 140 are consistent. In the first operating mode, the driving process of shift register 10 includes:

[0108] In the first stage T11, the first clock signal SCK1 and the input signal SIN are at low potentials, while the second clock signal SCK2 is at a high potential. Transistors M11 and M12 are turned on, and transistor M15 is turned off. The low potential of the input signal SIN is transmitted to the first output terminal N1 through transistor M11, causing the potential VN1 of the first output terminal N1 to change to a low potential. The low potential of the first output terminal N1 causes transistor M13 to turn on, and simultaneously causes the seventh transistor M7 to turn on, outputting the high potential of the second clock signal SCK2. The low potential of the first clock signal SCK1 is transmitted to the second output terminal N2 through transistor M13, and the low potential of the first potential signal VGL is transmitted to the second output terminal N2 through transistor M12, causing the eighth transistor M8 to turn on, outputting the high potential of the first potential signal VGH. Therefore, both the seventh transistor M7 and the eighth transistor M8 in the stage transmission output module 120 are turned on, and the stage transmission signal Carry is at a high potential. Correspondingly, the fifth transistor M5 and the sixth transistor M6 in the scan output module 140 are also turned on, making the scan signal GOUT also high.

[0109] In the second stage T12, the second clock signal SCK2 is at a low level, while the first clock signal SCK1 and the input signal SIN are both at a high level. Transistors M11 and M12 are turned off, and transistor M15 is turned on. Due to the storage effect of the second capacitor C2, the first output terminal N1 maintains the low level of the previous stage, causing transistor M13 to turn on and transmit the high level of the first clock signal SCK1 to the second output terminal N2, thereby turning off the eighth transistor M8 and the sixth transistor M6. At the same time, the low level of the first output terminal N1 causes the seventh transistor M7 to turn on, outputting the low level of the second clock signal SCK2. As the stage transmission signal Carry changes from a high level to a low level, based on the coupling effect of the second capacitor C2, the potential of the first output terminal N1 further decreases, stabilizing the low level output of the stage transmission signal Carry. Correspondingly, the fifth transistor M5 turns on, outputting the low level of the second clock signal SCK2 as the scan signal, and the first capacitor C1 plays a similar role to the second capacitor C2, controlling the stable low level output of the scan signal GOUT.

[0110] In the third stage T13, the first clock signal SCK1 is at a low level, while the second clock signal SCK2 and the input signal SIN are both at a high level. Transistors M11 and M12 are turned on, and transistor M15 is turned off. The high level of the input signal SIN is transmitted to the first output terminal N1 through transistor M11, causing the potential VN1 of the first output terminal N1 to jump to a high level. The high potential of the first output terminal N1 controls transistors M13, the seventh transistor M7, and the fifth transistor M5 to all turn off. The low potential of the first potential signal VGL is transmitted to the second output terminal N2 through transistor M12, causing the eighth transistor M8 and the sixth transistor M6 to both turn on, and both output the high potential of the first potential signal VGH. Therefore, in this stage, the stage transfer signal Carry and the scan signal GOUT are both at a high level.

[0111] In the fourth stage T14, the second clock signal SCK2 is at a low level, while the first clock signal SCK1 and the input signal SIN are both at a high level. Transistors M11 and M12 are turned off, and transistor M15 is turned on. Due to the storage effect of the third capacitor C3, the second output terminal N2 maintains the low level of the previous stage, causing transistor M14 to turn on. The high level of the first potential signal VGH is transmitted along transistors M14 and M15 to the first output terminal N1, controlling transistors M13, the seventh transistor M7, and the fifth transistor M5 to turn off. At the same time, the low level of the second output terminal N2 controls the sixth transistor M6 and the eighth transistor M8 to turn on, both outputting the high level of the first potential signal VGH. Therefore, in this stage, the stage transfer signal Carry and the scan signal GOUT are both kept at a high level.

[0112] The subsequent stages repeat the driving process of the third stage T13 and the fourth stage T14. The transmission signal Carry and the scan signal GOUT are both kept at high potential until the next display frame arrives, at which point the input signal SIN jumps to low potential again.

[0113] The above embodiments exemplify that when the shift register 10 is operating in the first operating mode, the frequency switching control signal SW0 remains at a low level VL throughout the entire display frame, but this is not intended to limit the invention. In other embodiments, as long as the frequency switching control signal SW0 is kept at a low level in the second stage T12, so that the first output unit 141 can normally output the low level of the second clock signal SCK2 in the second stage T12, the driving process of the first operating mode can be realized.

[0114] Figure 7 This is a schematic diagram illustrating the driving timing of a shift register in a second operating mode, as provided in an embodiment of the present invention. (Combined with...) Figure 5 and Figure 7When shift register 10 operates in the second operating mode, the operating states of drive control module 110 and stage output module 120, as well as the potential changes of the first output terminal N1 and the second output terminal N2, are all related to... Figure 6 The waveform of the Carry signal is the same as in the previous example. Figure 6 The operation is the same as in the previous section. The difference lies in the fact that the frequency switching control signal SW0 has a potential jump, which causes the output control module 130 to have a period of shutdown, thus making the operation of the scan output module 140 the same as in the previous section. Figure 6 Unlike in the text, the waveform of the scanning signal GOUT is different. Figure 6 The differences are as follows. The following mainly explains the differences in the driving process between the second and first working modes; the similarities will not be repeated.

[0115] Specifically, in the second operating mode, the rising edge of the frequency switching control signal SW0 is set before the potential VN1 of the first output terminal N1 jumps to a low potential, and the falling edge of the frequency switching control signal SW0 is set after the potential VN1 of the first output terminal N1 jumps to a high potential. That is, during the period when the potential VN1 of the first output terminal N1 remains low (including the first stage T11 and the second stage T12), the frequency switching control signal SW0 remains high, causing the output control module 130 to turn off. Therefore, the low potential of the first output terminal N1 cannot be transmitted to the output terminal N3 of the output control module 130, and the potential of the output terminal N3 of the output control module 130 remains high in this display frame. Therefore, in both the first stage T11 and the second stage T12, the fifth transistor M5 will not be turned on. Specifically, in the first stage T11, the sixth transistor M6 is turned on, outputting the first potential signal VGH as the scan signal GOUT; in the second stage T12, the sixth transistor M6 is turned off, and the scan signal GOUT maintains the high potential of the previous stage. Therefore, in the second operating mode, the scan signal GOUT is always kept at a high potential.

[0116] It should be noted that in the second operating mode, the high potential of the frequency switching control signal SW0 only needs to cover the period during which the potential VN1 of the first output terminal N1 remains low. The specific duration for which the high potential of the frequency switching control signal SW0 is maintained within this display frame is not limited. For example, the frequency switching control signal SW0 can remain high throughout this type of display frame.

[0117] Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present invention. See also... Figure 8Based on the above embodiments, the shift register 10 may optionally include a second protection module 150 to improve the output stability of the shift register 10. The first terminal of the second protection module 150 is connected to the first output terminal N1, and the second terminal N4 of the second protection module 150 is connected to the first control terminal of the stage transmission output module 120. Specifically, the second protection module 150 may include a transistor M16, the gate of which is connected to a second potential signal VGL, the first terminal of which is connected to the first output terminal N1, and the second terminal of which is connected to the first control terminal of the stage transmission output module 120.

[0118] As the above analysis shows, in the second stage T12, due to the coupling effect of the second capacitor C2, the gate potential of the seventh transistor M7 will be coupled to an extremely low potential lower than the second potential signal VGL. By setting the second protection module 150, the transmission of this extremely low potential to the first output terminal N1 can be prevented, thus preventing the transistors connected to the first output terminal from being damaged due to excessive voltage stress. Specifically, the conduction condition of transistor M16 is that its gate-source voltage difference is less than its threshold voltage. When the gate of the seventh transistor M7 is coupled to an extremely low potential, if it is transmitted to the first output terminal N1 through transistor M16, the gate-source voltage difference of transistor M16 will be greater than its threshold voltage, failing to meet the conduction condition of transistor M16, causing transistor M16 to turn off. Therefore, the transmission of this extremely low potential to the first output terminal N1 can be blocked.

[0119] Based on the above embodiments, optionally, after adding the second protection module 150, such as Figure 8 As shown, the input terminal of the output control module 130 can still be directly connected to the first output terminal N1. Then, the second protection module 150 can simultaneously protect the first transistor M1, preventing excessive gate-source voltage difference in the first transistor M1 when the gate of the seventh transistor M7 changes to an extremely low potential, especially preventing excessive gate-source voltage difference when the first transistor M1 is turned off, thereby improving the stability of the first transistor M1.

[0120] Or, such as Figure 9 As shown, the input terminal of the output control module 130 can be connected to the second terminal N4 of the second protection module 150, that is, the output control module 130 is connected to the first output terminal N1 through the second protection module 150. Since the control terminal of the second protection module 150 is connected to the second potential signal VGL, the transistor M16 can reliably conduct in the first stage T11, without affecting the normal transmission of the low potential of the input signal SIN. With this configuration, by changing the connection point of the input terminal of the output control module 130, the layout wiring of the scan drive circuit can be simplified, making the wiring method more flexible.

[0121] Figure 10This is a schematic diagram of another shift register provided in an embodiment of the present invention. See also... Figure 10 Based on the above embodiments, optionally, the shift register 10 further includes: a first switch module 160, electrically connected to the output terminal N3 of the output control module 130, used to transmit the first potential signal VGH to the output terminal N3 of the output control module 130 in response to the first switch signal SW1. Specifically, when the shift register 10 is operating in the second operating mode, it provides the gate of the fifth transistor M5 with its cutoff potential in a timely manner when the output control module 130 is turned off, ensuring that the fifth transistor M5 remains in the off state when the output control module 130 is turned off. For example, each level of the first switch module 160 can be connected to the same first switch signal SW1.

[0122] For example, after adding the first switch module 160, when the shift register 10 needs to operate in the second working mode, the frequency switching control signal SW0 can still be set to maintain the cutoff potential of the output control module 130 in both the first stage T11 and the second stage T12. It should be noted that the cutoff potential maintenance period of the frequency switching control signal SW0 must cover the period during which the first switch signal SW1 controls the first switch module 160 to turn on, in order to avoid the output control module 130 and the first switch module 160 being turned on simultaneously, to prevent the high potential of the first potential signal VGH from being transmitted to the first output terminal N1 through the first switch module 160 and the output control module 130, and to prevent the low potential of the input signal SIN from conflicting with the high potential of the first potential signal VGH, thus affecting the normal operation of the shift register 10.

[0123] Figure 11 This is a schematic diagram illustrating the driving timing of another shift register in the second operating mode according to an embodiment of the present invention. See also... Figure 11 In another embodiment, optionally, after adding the first switch module 160, when the shift register 10 needs to work in the second working mode, the time when the frequency switching control signal SW0 jumps to the cutoff potential of the output control module 130 is later than the start time of the first stage T11, and the first switch module 160 is turned on before the start time of the second stage T12, so as to realize the control process of the second working mode.

[0124] Since the potential VN1 of the first output terminal N1 changes to a low potential from the beginning of the first stage, in the first operating mode, the first output unit 141 and the third output unit 121 actually start outputting the second clock signal SCK2 from the first stage T11; however, since the second clock signal SCK2 only changes to a low potential in the second stage T12, the first output unit 141 and the third output unit 121 only start outputting a low potential in the second stage T12. Before the first switch module 160 is set, the output control module 130 can only block the backward transmission of the potential of the first output terminal N1, but cannot provide the cutoff potential (e.g., a high potential) of the first output unit 141 to the control terminal of the first output unit 141. However, the setting of the first switch module 160 is equivalent to providing the source of the cutoff potential of the first output unit 141. Therefore, as long as the output control module 130 is turned off before the start of the second stage T12, the transmission path of the low potential of the first output terminal N1 is cut off, and the first switch module 160 is turned on to transmit the high potential of the first potential signal VGH to the control terminal of the first output unit 141, it can be ensured that the first output unit 141 remains off in the second stage T12, and that the shift register 10 will not output the on potential (e.g., low potential) of the scan signal GOUT when it is working in the second working mode.

[0125] For example, the frequency switching control signal SW0 and the first switching signal SW1 can be as follows: Figure 11 As shown, the potential jump is performed synchronously. Therefore, the time period during which the frequency switching control signal SW0 controls the output control module 130 to turn off corresponds exactly to the time period during which the first switch signal SW1 controls the first switch module 160 to turn on. This time period only needs to cover the second stage T12, and the specific duration of this time period is not limited.

[0126] Or, it can be like Figure 12 As shown, the potential transitions of the frequency switching control signal SW0 and the first switch signal SW1 can be asynchronous. Therefore, it is sufficient to set the time period during which the first switch signal SW1 controls the first switch module 160 to be on to cover the second stage T12, and to set the time period during which the frequency switching control signal SW0 controls the output control module 130 to be off to cover the time period during which the first switch signal SW1 controls the first switch module 160 to be on. For example... Figure 12 As shown, when the frequency switching control signal SW0 transitions to the cutoff potential of the output control module 130 after entering the first stage T11, the low potential of the first output terminal N1 is transmitted to the output terminal N3 of the output control module 130 before the frequency switching control signal SW0 undergoes a potential transition. The low potential of the output terminal N3 of the output control module 130 continues until the first switching module 160 is turned on.

[0127] See alsoFigure 10 Based on the above embodiments, optionally, the first switching module 160 includes: a second transistor M2; the gate of the second transistor M2 is connected to a first switching signal SW1, the first terminal of the second transistor M1 is connected to a first potential signal VGH, and the second terminal of the second transistor M2 is electrically connected to the output terminal N3 of the output control module 130. In this embodiment, the first switching module 160 is composed of a single transistor, making the structure of the first switching module 160 simple and easy to implement.

[0128] Based on the above embodiments, optionally, when the channel types of the first transistor M1 and the second transistor M2 are the same, the frequency switching control signal SW0 and the first switching signal SW1 can be set to be inverse signals with opposite high and low potentials, which can be used to provide, for example Figure 11 The control process is shown.

[0129] Or, such as Figure 13 As shown, when the channel types of the first transistor M1 and the second transistor M2 are different, the frequency switching control signal SW0 can be multiplexed as the first switching signal SW1 to reduce the signal lines required by the scan drive circuit and simplify the wiring of the display panel. For example Figure 13 The first transistor M1 can be configured as a P-type transistor and the second transistor M2 as an N-type transistor. Alternatively, the first transistor M1 can be configured as an N-type transistor and the second transistor M2 as a P-type transistor; the specific configuration is not limited.

[0130] Based on the above embodiments, optionally, the capacitance value of the second capacitor C2 can be set to be larger, for example, greater than the capacitance value of the third capacitor C3, so as to increase the ability of the second capacitor C2 to maintain the potential, thereby reducing the influence of the high potential of the control terminal N3 of the output control module 130 on the potential of the first output terminal N1 when the frequency switching control signal SW0 controls the output control module 130 to be turned on.

[0131] Figure 14 This is a schematic diagram of another shift register provided in an embodiment of the present invention. See also... Figure 14 Based on the above embodiments, the shift register 10 may optionally include a second switch module 170, which is electrically connected to the output terminal N3 of the output control module 130, and is used to transmit the second potential signal VGL to the output terminal N3 of the output control module 130 in response to the second switch signal SW2. Specifically, when the shift register 10 is working in the first working mode, after the start of the first stage T11 and before the start of the second stage T12, it provides the gate of the fifth transistor M5 with the conduction potential (e.g., a low potential) of the fifth transistor M5 in a timely manner.

[0132] Figure 15This is a schematic diagram illustrating the driving timing of another shift register in the first operating mode according to an embodiment of the present invention. (Combined with...) Figure 14 and Figure 15 For example, the second switching signal SW2 can be converted to the conduction potential (e.g., low potential) of the second switching module 170 before the frequency switching control signal SW0 controls the first transistor M1 to turn on, controlling the second switching module 170 to turn on, and pre-providing the gate of the fifth transistor M5 with the low potential of the second potential signal VGL. This causes the output terminal N3 of the output control module 130 to change to a low potential before the output control module 130 turns on, thus avoiding the delay increase caused by the first output terminal N1 changing to a low potential when the output control module 130 is still at a high potential. It should be noted that the falling edge of the second switching signal SW2 should not be earlier than the start time of the first stage T11 to avoid the fifth transistor M5 outputting the low potential of the second clock signal SCK2 prematurely; and the falling edge of the second switching signal SW2 should be earlier than the start time of the second stage T12 to ensure that the fifth transistor M5 is reliably turned on in the second stage T12.

[0133] Alternatively, the second switching signal SW2 can also be changed to a low potential after the frequency switching control signal SW0 changes to a low potential, which can still ensure that the fifth transistor M5 is turned on.

[0134] It should be noted that the first switch signal SW1 should control the first switch module 160 to turn off before the second switch signal SW2 controls the second switch module 170 to turn on, so as to avoid the situation where the first potential signal VGH and the second potential signal VGL are simultaneously transmitted to the output terminal N3 of the output control module 130, and to ensure the reliability of the shift register 10.

[0135] Based on the above embodiments, the input signal SIN connected to the shift register 10 can be multiplexed into the second switch signal SW2 required by the shift register 10 to reduce the number of signal lines and simplify the display panel wiring.

[0136] See also Figure 14 Based on the above embodiments, optionally, the second switch module 170 includes a third transistor M3; the gate of the third transistor M3 is connected to the second switch signal SW2, the first terminal of the third transistor M3 is connected to the second potential signal VGL, and the second terminal of the third transistor M3 is electrically connected to the output terminal N3 of the output control module 130. This embodiment sets the second switch module 170 to include one transistor, making the structure of the second switch module 170 simple and easy to implement.

[0137] See also Figure 14Optionally, based on the above embodiments, the shift register 10 may further include a first protection module 180 to improve the output stability of the shift register 10. The first protection module 180 is connected between the output terminal N3 of the output control module 130 and the first control terminal of the scan output module 140, and is connected to a second potential signal VGL. Specifically, the first protection module 180 may include a fourth transistor M4; the gate of the fourth transistor M4 is connected to the second potential signal VGL, the first terminal of the fourth transistor M4 is electrically connected to the output terminal N3 of the output control module 130, and the second terminal of the fourth transistor M4 is electrically connected to the first control terminal of the scan output module 140. The first protection module 180 can prevent the extremely low potential of the gate of the fifth transistor M5 from being transmitted to the output terminal N3 of the output control module 13. Its protection principle can be found in the explanation of the second protection module 150, and will not be repeated here.

[0138] Figure 16 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 16 and Figure 14 The difference is: Figure 14 The first terminal of the first transistor M1 is connected to the first output terminal N1, and Figure 16 The first terminal of the first transistor M1 is connected to the first output terminal N1 via transistor M16. The connection position of the first terminal of the first transistor M1 can be set according to actual needs and is not limited here.

[0139] The above embodiments exemplarily illustrate the specific structure of the shift register 10. The driving process of the display device will now be described. Exemplarily, the output control modules 130 in all shift registers 10 are connected to the same frequency switching control signal SW0, and correspondingly, the first switching modules 150 in all shift registers 10 are connected to the same first switching signal SW1. Furthermore, the input signal SIN at each stage serves as the second switching signal SW2 for that stage.

[0140] The following is combined Figure 17 The display device still includes three display areas, and performs operations such as... Figure 2 The driving process shown is taken as an example, and the frequency switching control signal SW0 and the first switch signal SW1 are inverted signals for explanation. In the attached figure, the shading indicates that the pixel circuits of each row of the display area are refreshing data, and the blanking indicates that the pixel circuits of each row of the display area are holding data. Also, the i-th stage shift register is labeled 10i, the i-th stage pass signal is labeled Carryi, and the i-th stage scan signal is labeled GOUTi, where i is a positive integer.

[0141] See Figure 17In display frame F1, the frequency switching control signal SW0 remains at a low level, and the first switch signal SW1 remains at a high level V1. Each output control module 130 is always on in this display frame, and each first switch module 160 is always off. Each level of scan signal is consistent with the corresponding level transmission signal, and the scan drive circuit can realize the step-by-step transmission of the scan signal conduction potential, enabling data refresh of the pixel circuits in all display areas. This type of display frame can be called a full refresh frame.

[0142] In display frame F2, a portion of the row pixel circuitry is refreshed; this type of display frame can be called a partially refreshed frame. Specifically, in display frame F2:

[0143] During the scanning phase TA1 of the first display area A1, the frequency switching control signal SW0 is kept at a low potential, and the first switch signal SW1 is kept at a high potential, so that the scanning signals output by each level of the shift register corresponding to the first display area A1 are consistent with the corresponding level transmission signals, including the conduction pulse, so that each row of pixel circuits in the first display area A1 is refreshed.

[0144] During the scanning phase TA2 of the second display area A2, the frequency switching control signal SW0 is at a high potential and the first switch signal SW1 is at a low potential, so that the scanning signals output by each level of the shift register corresponding to the second display area A2 are different from the corresponding level transmission signals and do not contain conduction pulses, so that the pixel circuit in the second display area A2 does not perform data refresh.

[0145] During the scanning phase TA3 of the third display area A3, the frequency switching control signal SW0 is at a low potential and the first switching signal SW1 is at a high potential, so that the scanning signals output by each level of the shift register corresponding to the third display area A3 are consistent with the corresponding level transmission signals, including the conduction pulse, so that the pixel circuits in the third display area A3 are refreshed.

[0146] In different refresh frames, the timing and number of potential transitions of the frequency switching control signal SW0 and the first switch signal SW1 can differ. As long as the high-potential period of the frequency switching control signal SW0 in the hold frame of the low-frequency display area corresponds to the scan time of each row of pixel circuits requiring data hold, the specific process will not be elaborated further. In this embodiment, whether the scan signal GOUT of each shift register 10 outputs a conduction potential is controlled by the output control module 130 of that stage and is independent of the output state of the scan signals GOUT of other stages. Therefore, the refresh frequency corresponding to each display area is only related to the output state of the shift register 10 corresponding to that display area and has no correlation with the refresh frequency of other display areas. This embodiment of the invention allows for arbitrary switching of the refresh frequency of different display areas.

[0147] In practical applications, by adjusting the order and number of full refresh frames and various partial refresh frames, combinations of various partitions and display frequencies can be achieved.

[0148] For example, when the first display area A1 displays at a refresh rate f, the second display area A2 displays at a refresh rate f / 4, and the third display area A3 displays at a refresh rate f / 2, the combination of various display frames is as follows: Figure 18 As shown. See also Figure 18 For example, the first display area A1 corresponds to shift registers at levels 1 to (k-1), the second display area A2 corresponds to shift registers at levels k to (m-1), and the third display area A3 corresponds to shift registers at levels m to n, where i, k, m, and n are all positive integers and increase sequentially. For each row of sub-pixels in the first display area A1, data can be refreshed in each display frame. Figure 18 The waveform of the first-level scan signal GOUT1 is given as an example. It can be seen that the first-level scan signal GOUT1 contains a conduction pulse in each display frame. For each row of sub-pixels in the second display area A2, a hold frame interval of 3 can be set between two adjacent refresh frames. Figure 18 The waveform of the k-th level scan signal GOUTk is given as an example. It can be seen that the k-th level scan signal GOUTk contains a conduction pulse in display frames F1 and F5, that is, it only contains a conduction pulse in the 4i-3 display frames, and maintains a cutoff potential in other display frames. For each row of sub-pixels in the third display area A3, odd-numbered frames can be set as refresh frames and even-numbered frames as hold frames. Figure 18 The waveform of the m-th level scan signal GOUTm is given as an example. It can be seen that the m-th level scan signal GOUTm contains conduction pulses only in odd-numbered frames.

[0149] By repeating the driving process within a cycle of four display frames (F1 to F4), stable multi-frequency display in different display areas can be achieved, with a refresh rate of f for the first display area A1, f / 4 for the second display area A2, and f / 2 for the third sub-display area A3. Display frame F1 is a full refresh frame, while display frames F2-F4 are partial refresh frames.

[0150] If the partitioning positions between sub-display areas need to be adjusted, this can be achieved by adjusting the potential transition times of the frequency switching control signal SW0 and the first switch signal SW1 in various display frames. If the refresh rate of each display area needs to be adjusted, this can be achieved by controlling the order and number of various display frames in different cycles. Furthermore, by using different cycles to display at different time periods during the display process, a display scheme with dynamic refresh rate adjustment can be implemented.

[0151] Figure 19This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 19 For example, the display area AA of the display panel has multiple pixel circuits 20 arranged in an array, and the scan driving circuit 100 is disposed in the non-display area NAA of the display panel. The non-display area NAA of the display panel can be provided with a first potential signal line for providing a first potential signal VGH; a second potential signal line for providing a second potential signal VGL; a first clock signal line for providing a first initial clock signal CLK1; a second clock signal line for providing a second initial clock signal CLK2; a frequency switching control signal line for providing a frequency switching control signal SW0; and an input signal line for providing a first-stage input signal SIN1. The two clock terminals of each shift register 10 are alternately connected to the first clock signal line and the second clock signal line. That is, the first initial clock signal CLK1 can be used as the first clock signal SCK1 of the odd-stage shift register and the second clock signal SCK2 of the even-stage shift register; correspondingly, the second initial clock signal CLK2 can be used as the second clock signal SCK2 of the odd-stage shift register and the first clock signal SCK1 of the even-stage shift register.

[0152] The pixel circuit 20 can have any existing pixel circuit structure. Taking the 7T1C architecture pixel circuit as an example, in the scan drive circuit 100 provided in this embodiment of the invention, the scan signals output by each level of shift register can be used as the first control signal S1 required for the gate of the gate reset transistor and / or the second control signal S2 required for the gate of the threshold compensation transistor in the pixel circuit.

[0153] In one embodiment, optionally, two sets of scanning drive circuits 100 may be provided in the display panel, which are used to provide the first control signal S1 and the second control signal S2 required by each row of pixel circuits, respectively.

[0154] In another implementation, such as Figure 19 As shown, optionally, a set of scan drive circuits 100 can be provided in the display panel to provide a first control signal S1 and a second control signal S2 for each row of pixel circuits 20. Specifically, shift registers 10 of different levels can be connected to the same row of pixel circuits 20. The scan signal output by the previous level (one or several levels, which can be set according to actual needs) shift register 10 serves as the first control signal S1 for that row of pixel circuits 20, and the scan signal output by the subsequent level (one or several levels, which can be set according to actual needs) shift register 10 serves as the second control signal S2 for that row of pixel circuits 20. For example, as... Figure 19 The scanning signal output by the j-th level shift register 10 can be set as the second control signal S2 required by the (j-1)-th row pixel circuit 20, and as the first control signal S1 required by the j-th row pixel circuit 20.

[0155] Additionally, the display panel may include other driving circuits, such as control signals required to provide the gate of the data writing transistor in the pixel circuit 20, and control signals required to provide the gate of the light-emitting control transistor. Both the driving circuit for providing the control signals to the data writing transistor and the driving circuit for providing the control signals to the light-emitting control transistor can maintain a high-frequency output at all times.

[0156] It should be noted that the structures of the shift registers 10 given in the above embodiments are not intended to limit the present invention. In other embodiments, the shift registers 10 can be improved based on existing shift register circuits of any structure. For any shift register circuit, the original output module is used as a cascaded output module 120. On this basis, a set of scan output modules 140 is added, and an output control module 130 and its related structures are added between the first control terminal of the added scan output module 140 and one of the output terminals of the drive control module 110. The function of the shift registers 10 in the embodiments of the present invention can be realized.

[0157] It should also be noted that the scan drive circuit 100 provided in the above embodiments can be applied to LTPS pixel circuits, but this is not intended to limit the present invention. In other embodiments, replacing each shift register 10 with a long output low potential structure, for example by modifying the 10T3C architecture, can enable the scan drive circuit 100 to be applied to LTPO pixel circuits.

[0158] It should also be noted that the first terminal of each transistor involved in the above embodiments can be called the source or drain, and the corresponding second terminal can be called the drain or source. Since the structure of the transistors in the display panel is symmetrical, the source and drain of each transistor are not distinguished.

[0159] In summary, by adding an output control module 130 to the shift register 10, this embodiment of the invention can achieve the function of blocking / allowing the potential transmission of the first output terminal N1 (or the second output terminal N2) backward, thereby realizing the switching between high and low frequencies. Simultaneously, the stage transmission output module 120 serves as a high-frequency output unit, providing the input signal SIN required for normal startup of the next-stage shift register 10. The overall concept is simple, allowing for arbitrary switching of the refresh frequency from high to low and from low to high, making the solution easy to implement and promote.

[0160] This invention also provides a display device, including the scanning driving circuit provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 20For example, the display device may include a display panel and a driver chip 50. Both the scan drive circuit 100 and the pixel circuit 20 are disposed in the display panel. The scan drive circuit 100 provides scan signals to each row of pixel circuits 20 via each scan line LS. The driver chip 50 provides a first-stage input signal SIN1 to the first-stage shift register 10 in the scan drive circuit 100 via input signal lines, and provides data voltages to each column of pixel circuits 20 via each data line LD.

[0161] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0162] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning drive circuit, characterized in that, include: Multiple shift registers; The shift register includes: A drive control module, wherein the drive control module is used to control the potential of the first output terminal and the second output terminal of the drive control module according to the input signal of the shift register; An output control module, wherein the input terminal of the output control module is connected to the first output terminal or the second output terminal, and the control terminal of the output control module receives a frequency switching control signal; A scan output module, connected to the output terminal of the output control module, is used to control the output scan signal to the output terminal of the shift register in response to the potential of the output terminal of the output control module; wherein, the frequency switching control signal controls the frequency of the scan signal by controlling the potential of the output terminal of the output control module; The output control modules in each of the shift registers are all connected to the same frequency switching control signal; The frequency switching control signal maintains the on-state potential of the output control module in some display frames and performs a potential jump in some display frames, so that the scanning signals output by at least two shift registers have different frequencies, thereby realizing the segmented frequency display of the display device.

2. The scanning drive circuit according to claim 1, characterized in that, The input terminal of the output control module is connected to the first output terminal; the first control terminal of the scan output module is connected to the output terminal of the output control module, and the second control terminal of the scan output module is connected to the second output terminal; the potential of the output terminal of the output control module is used to control whether the scan output module outputs the on-state potential of the scan signal.

3. The scanning drive circuit according to claim 1, characterized in that, The output control module includes: a first transistor; the gate of the first transistor is electrically connected to the control terminal of the output control module, the first electrode of the first transistor is electrically connected to the input terminal of the output control module, and the second electrode of the first transistor is electrically connected to the output terminal of the output control module.

4. The scanning drive circuit according to claim 1, characterized in that, The shift register further includes a first switch module, which is electrically connected to the output terminal of the output control module, and is used to respond to the first switch signal, transmit the first potential signal to the output terminal of the output control module, and control the scan output module to stop outputting the on potential of the scan signal.

5. The scanning drive circuit according to claim 4, characterized in that, The output control module includes: a first transistor; the gate of the first transistor is electrically connected to the control terminal of the output control module, the first electrode of the first transistor is electrically connected to the input terminal of the output control module, and the second electrode of the first transistor is electrically connected to the output terminal of the output control module. The first switching module includes: a second transistor; the gate of the second transistor is connected to the first switching signal, the first terminal of the second transistor is connected to the first potential signal, and the second terminal of the second transistor is electrically connected to the output terminal of the output control module.

6. The scanning drive circuit according to claim 5, characterized in that, The first transistor and the second transistor have the same channel type, and the frequency switching control signal and the first switching signal are inverse signals to each other; Alternatively, the first transistor and the second transistor may have different channel types, and the frequency switching control signal may be multiplexed as the first switching signal.

7. The scanning drive circuit according to claim 1, characterized in that, The shift register further includes a second switch module, which is electrically connected to the output terminal of the output control module, and is used to respond to the second switch signal, transmit the second potential signal to the output terminal of the output control module, and control the scanning output module to output the on-potential of the scanning signal.

8. The scanning drive circuit according to claim 7, characterized in that, The second switching module includes a third transistor; the gate of the third transistor is connected to the second switching signal, the first terminal of the third transistor is connected to the second potential signal, and the second terminal of the third transistor is electrically connected to the output terminal of the output control module.

9. The scanning drive circuit according to claim 7, characterized in that, The input signals connected to this stage shift register are multiplexed into the second switching signals required by this stage shift register.

10. The scanning drive circuit according to claim 1, characterized in that, The shift register further includes a first protection module; the first protection module is connected between the output terminal of the output control module and the scan output module, and the control terminal of the first protection module is connected to a second potential signal.

11. The scanning drive circuit according to claim 10, characterized in that, The first protection module includes a fourth transistor; the gate of the fourth transistor is connected to a second potential signal, the first terminal of the fourth transistor is electrically connected to the output terminal of the output control module, and the second terminal of the fourth transistor is electrically connected to the scan output module.

12. The scanning drive circuit according to claim 1, characterized in that, The drive control module includes: An input unit, electrically connected to the first output terminal, is used to transmit the input signal to the first output terminal in response to a first clock signal; A potential control unit, electrically connected to the second output terminal, is used to transmit a second potential signal to the second output terminal in response to the first clock signal; The first node control unit is electrically connected to the first output terminal and the second output terminal respectively, and is used to transmit the first clock signal to the second output terminal in response to the potential of the first output terminal. The second node control unit is electrically connected to the first output terminal and the second output terminal respectively, and is used to transmit the first potential signal to the first output terminal in response to the second clock signal and the potential of the second output terminal.

13. The scanning drive circuit according to claim 1, characterized in that, The scan output module includes: The first output unit is electrically connected to the output terminal of the output control module and is used to respond to the potential conduction of the output terminal of the output control module. The second output unit is electrically connected to the second output terminal and is used to respond to the potential conduction of the second output terminal.

14. The scanning drive circuit according to claim 13, characterized in that, The first output unit includes a fifth transistor and a first capacitor; the gate of the fifth transistor is electrically connected to the output terminal of the output control module, the first terminal of the fifth transistor is connected to a second clock signal, and the second terminal of the fifth transistor serves as the output terminal of the scan output module; the first capacitor is connected between the gate and the second terminal of the fifth transistor. The second output unit includes a sixth transistor; the gate of the sixth transistor is electrically connected to the second output terminal, the first terminal of the sixth transistor is connected to a first potential signal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor.

15. The scanning drive circuit according to any one of claims 1-14, characterized in that, The multiple shift registers are cascaded; the scan signal serves as the input signal for the next-level shift register.

16. The scanning drive circuit according to any one of claims 1-14, characterized in that, The multiple shift registers are cascaded; each shift register further includes a stage output module, which is electrically connected to the first output terminal and the second output terminal respectively, and is used to output a stage transmission signal in response to the potential of the first output terminal and the second output terminal; the stage transmission signal serves as the input signal for the next stage shift register.

17. The scanning drive circuit according to claim 16, characterized in that, The first control terminal of the stage transmission output module is connected to the first output terminal, and the second control terminal of the stage transmission output module is connected to the second output terminal.

18. The scanning drive circuit according to claim 16, characterized in that, The shift register further includes: a second protection module, the first end of the second protection module being connected to the first output terminal, and the second end of the second protection module being connected to the first control terminal of the stage output module; The input terminal of the output control module is connected to either the first or second terminal of the second protection module.

19. The scanning drive circuit according to claim 16, characterized in that, The level transmission output module includes: The third output unit is electrically connected to the first output terminal and is used to respond to the potential conduction of the first output terminal; The fourth output unit is electrically connected to the second output terminal and is used to respond to the potential conduction of the second output terminal.

20. The scanning drive circuit according to claim 19, characterized in that, The third output unit includes a seventh transistor and a second capacitor; the gate of the seventh transistor is electrically connected to the first output terminal, the first terminal of the seventh transistor is connected to a second clock signal, and the second terminal of the seventh transistor serves as the output terminal of the stage transmission module. The second capacitor is connected between the gate and the second electrode of the seventh transistor; The fourth output unit includes an eighth transistor and a third capacitor; the gate of the eighth transistor is electrically connected to the second output terminal, the first terminal of the eighth transistor is connected to a first potential signal, and the second terminal of the eighth transistor is electrically connected to the second terminal of the seventh transistor; the third capacitor is connected between the gate and the first terminal of the eighth transistor.

21. The scanning drive circuit according to claim 20, characterized in that, The capacitance of the second capacitor is greater than that of the third capacitor.

22. A display device, characterized in that, include: The pixel circuit and the scanning drive circuit according to any one of claims 1-21.

Images