Display panel, driving method thereof, and display device

Abstract

The embodiment of the present application provides a display panel and its driving method, and a display device, including a first display area, wherein the first display area includes a plurality of first pixel circuits, the first pixel circuit includes a driving transistor, a data writing module, and a frequency control module, one end of the driving transistor is a data voltage storage end; the data writing module is electrically connected to the driving transistor and is used to write the data voltage into the data voltage storage end of the driving transistor; the frequency control module is electrically connected to the driving transistor and the data writing module, and is used to control the frequency at which the data writing module writes the data voltage into the data voltage storage end of the driving transistor. In the display panel provided by the embodiment of the present application, the change of the image refresh frequency in the first display area can be achieved by controlling the frequency of writing the data voltage into the gate of the driving transistor by the frequency control module in the first pixel circuit. Therefore, the position setting of the variable image refresh frequency region in the display panel is more flexible and easy to implement.

Description

Technical field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. [Background Technology]

[0002] How to further reduce the power consumption of display devices has always been a problem that technicians in the field of display technology need to think about.

[0003] One current solution is to downsample the display panel, reducing its display frequency when high-frequency display is not required. This solution relies primarily on reducing the frequency of the scan signal output by the shift register. This increases the design complexity of the shift register and only achieves overall frequency reduction of the display panel, making it inflexible.

[0004] Application Contents

[0005] In view of this, embodiments of the present application provide a display panel and a driving method thereof, as well as a display device to solve the above problems.

[0006] In a first aspect, an embodiment of the present application provides a display panel including a first display area, wherein the first display area includes a plurality of first pixel circuits, and the first pixel circuits include:

[0007] A driving transistor for generating a light-emitting driving current; one end of the driving transistor is a data voltage storage end;

[0008] a data writing module, electrically connected to the driving transistor and configured to write a data voltage into a data voltage storage terminal of the driving transistor;

[0009] A frequency control module is electrically connected to the driving transistor and the data writing module, and is used to control the frequency at which the data writing module writes the data voltage into the data voltage storage terminal of the driving transistor.

[0010] In an implementation of the first aspect, in the first display area, control terminals of frequency control modules included in at least some of the first pixel circuits are electrically connected to the same frequency control signal line.

[0011] In an implementation of the first aspect, in the first display area, control terminals of the frequency control modules included in all the first pixel circuits are electrically connected to the same frequency control signal line.

[0012] In an implementation of the first aspect, the first display area includes a first sub-display area and a second sub-display area, the plurality of first pixel circuits include a first type of pixel circuit and a second type of pixel circuit, the first type of pixel circuit is arranged in the first sub-display area, and the second type of pixel circuit is arranged in the second sub-display area;

[0013] The control ends of the frequency control modules respectively included in the first type pixel circuit and the second type pixel circuit are electrically connected to different frequency control signal lines.

[0014] In one implementation of the first aspect, the control end of the frequency control module included in each of the first-type pixel circuits is electrically connected to the same frequency control signal line, and the control end of the frequency control module included in each of the second-type pixel circuits is electrically connected to the same frequency control signal line.

[0015] In an implementation of the first aspect, the display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is configured to receive a first signal line, wherein a first signal is transmitted on the first signal line and the first signal is configured to control the frequency control module to be turned on;

[0016] The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit;

[0017] The control end of the first transistor is electrically connected to the first scan line, and the control end of the second transistor is electrically connected to the second scan line.

[0018] In an implementation of the first aspect, the display panel includes a first shift register, and the first shift register includes a plurality of cascaded shift register units;

[0019] The frequency control signal line electrically connected to the first type pixel circuit and the frequency control signal line electrically connected to the second type pixel circuit are respectively electrically connected to different shift register units in the first shift register.

[0020] In an implementation of the first aspect, the display panel includes a second shift register, and the second shift register includes a plurality of cascaded shift register units;

[0021] In the data writing module included in the first type of pixel circuit and the data writing module included in the second type of pixel circuit, gates of transistors with the same function are connected to different shift register units in the same second shift register.

[0022] In an implementation of the first aspect, the gate of the driving transistor is a data voltage storage terminal, and the frequency control module is electrically connected to the gate of the driving transistor;

[0023] The first pixel circuit further includes a storage capacitor electrically connected to the gate of the driving transistor.

[0024] In an implementation of the first aspect, the frequency control module includes a frequency control transistor, and the data writing module includes a data writing transistor and a threshold grabbing transistor;

[0025] The input end of the data writing transistor is connected to the data voltage line and the output end is electrically connected to the input end of the driving transistor, the input end of the threshold grabbing transistor is electrically connected to the output end of the driving transistor and the output end is electrically connected to the input end of the frequency control transistor, and the output end of the frequency control transistor is electrically connected to the gate of the driving transistor.

[0026] In an implementation of the first aspect, the frequency control module includes a frequency control transistor, and the data writing module includes a data writing transistor;

[0027] The input end of the data writing transistor is connected to the data voltage line and the output end is electrically connected to the input end of the driving transistor. The input end of the frequency control transistor is electrically connected to the output end of the driving transistor and the output end is electrically connected to the gate of the driving transistor.

[0028] In an implementation of the first aspect, the first pixel circuit further includes a first reset module, the first reset module being electrically connected to the input terminal of the frequency control transistor and configured to transmit a reset voltage to the gate of the driving transistor;

[0029] The frequency control transistor is configured to be turned on when the gate of the driving transistor receives a reset voltage and a data voltage.

[0030] In an implementation of the first aspect, the first reset module includes a first reset transistor, and an output end of the first reset transistor is electrically connected to an input end of the frequency control transistor;

[0031] Wherein, the first reset transistor includes a metal oxide semiconductor layer.

[0032] In an implementation of the first aspect, the display panel further includes a second display area, the second display area includes a second pixel circuit, and the second pixel circuit includes:

[0033] A driving transistor for generating a light-emitting driving current;

[0034] a data writing transistor having an input end connected to the data voltage line and an output end electrically connected to the input end of the driving transistor;

[0035] A threshold capture transistor has an input terminal electrically connected to the output terminal of the driving transistor and an output terminal electrically connected to the gate of the driving transistor.

[0036] In an implementation manner of the first aspect, the frequency control transistor and / or the threshold grabbing transistor both include a metal oxide semiconductor layer.

[0037] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel provided in the first aspect.

[0038] In a third aspect, an embodiment of the present application provides a method for driving a display panel, wherein the display panel includes a first display area, the first display area includes a plurality of first pixel circuits, and the first pixel circuits include:

[0039] A driving transistor for generating a light-emitting driving current; one end of the driving transistor is a data voltage storage end;

[0040] a data writing module, electrically connected to the driving transistor and configured to write a data voltage into a data voltage storage terminal of the driving transistor;

[0041] a frequency control module, the frequency control module being electrically connected to the driving transistor and the data writing module and configured to control a frequency at which the data writing module writes the data voltage into the data voltage storage terminal of the driving transistor;

[0042] The multiple display modes of the display panel include a first display mode and a second display mode, and the driving method includes:

[0043] The frequency control module included in at least part of the first pixel circuits is turned on at a frequency lower than the frequency in the second display mode.

[0044] In an implementation of the third aspect, the first display area includes a first sub-display area and a second sub-display area, the plurality of first pixel circuits include a first type of pixel circuit and a second type of pixel circuit, the first type of pixel circuit is arranged in the first sub-display area, and the second type of pixel circuit is arranged in the second sub-display area;

[0045] The control ends of the frequency control modules respectively included in the first type pixel circuit and the second type pixel circuit are electrically connected to different frequency control signal lines;

[0046] The driving method further includes:

[0047] At least in the first display mode and / or the second display mode, the frequency control signal lines electrically connected to the first type pixel circuit and the second type pixel circuit respectively transmit enable signals at different frequencies.

[0048] In an implementation of the third aspect, a control end of the frequency control module included in each of the first-type pixel circuits is electrically connected to the same frequency control signal line, and a control end of the frequency control module included in each of the second-type pixel circuits is electrically connected to the same frequency control signal line;

[0049] The driving method further includes:

[0050] The frequency control signal line electrically connected to the control terminal of the frequency control module included in the first type of pixel circuit transmits an enable signal during a period covering a period during which the data voltage storage terminals of the driving transistors in all the first type of pixel circuits receive data voltages;

[0051] The frequency control signal line electrically connected to the control terminal of the frequency control module included in the second type pixel circuit transmits an enable signal during a period when the data voltage storage terminals of the driving transistors in all the second type pixel circuits receive data voltages.

[0052] In an implementation of the third aspect, the display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is configured to receive a first signal line, wherein a first signal is transmitted on the first signal line and the first signal is configured to control the frequency control module to be turned on;

[0053] The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit;

[0054] Wherein, the control terminal of the first transistor is electrically connected to the first scan line, and the control terminal of the second transistor is electrically connected to the second scan line;

[0055] The driving method further includes:

[0056] In either the first display mode or the second display mode, a frequency at which the signal transmitted by the first scan line controls the first transistor to be turned on is different from a frequency at which the signal transmitted by the second scan line controls the second transistor to be turned on.

[0057] In an implementation of the third aspect, the display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is configured to receive a first signal line, wherein a first signal is transmitted on the first signal line and the first signal is configured to control the frequency control module to be turned on;

[0058] The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit;

[0059] Wherein, the control terminal of the first transistor is electrically connected to the first scan line, and the control terminal of the second transistor is electrically connected to the second scan line;

[0060] The driving method further includes:

[0061] In the first display mode and the second display mode, the frequency of the signal transmitted by the first scan line to control the opening of the first transistor is the same, the frequency of the signal transmitted by the second scan line to control the opening of the second transistor is the same, and the frequency of the first signal line transmitting the first signal in the first display mode and the second display mode is different.

[0062] In an implementation of the third aspect, the driving method includes:

[0063] The frequency at which the frequency control module included in at least some of the first pixel circuits is turned on in the first display mode is lower than the frequency at which it is turned on in the second display mode, and the frequency at which the data writing module included in those first pixel circuits is turned on in the first display mode is equal to or lower than the frequency at which it is turned on in the second display mode.

[0064] In an implementation of the third aspect, the first pixel circuit further includes a first reset module, the first reset module being electrically connected to the input terminal of the frequency control transistor and configured to transmit a reset voltage to the gate of the driving transistor;

[0065] The driving method further includes:

[0066] The frequency at which the frequency control module included in at least some of the first pixel circuits is turned on in the first display mode is lower than the frequency at which it is turned on in the second display mode, and the frequency at which the first reset module included in those first pixel circuits is turned on in the first display mode is equal to or lower than the frequency at which it is turned on in the second display mode.

[0067] In the display panel provided in the embodiments of the present application, the image refresh frequency in the first display area can be changed by controlling the frequency at which the data voltage is written to the gate of the drive transistor by the frequency control module in the first pixel circuit. This makes the location of the variable image refresh frequency region in the display panel more flexible and easier to implement.

Brief Description of the Drawings

[0068] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0069] Figure 1A A schematic diagram of a display panel provided by the prior art;

[0070] Figure 1B is a schematic diagram of a pixel circuit in the prior art;

[0071] Figure 1C for Figure 1B A timing diagram of a pixel circuit;

[0072] Figure 2 A schematic structural diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0073] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application;

[0074] Figure 4A A schematic diagram of a display panel provided in an embodiment of the present application;

[0075] Figure 4B An equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0076] Figure 4C for Figure 4B A timing diagram of a pixel circuit;

[0077] Figure 5 An equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0078] Figure 6 An equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0079] Figure 7 for Figure 6 The first pixel circuit shown is Figure 5 An operation timing diagram of the second pixel circuit shown;

[0080] Figure 8 A schematic diagram of a display panel provided in an embodiment of the present application;

[0081] Figure 9 for Figure 8 A timing diagram corresponding to the embodiment;

[0082] Figure 10 A schematic diagram of a display panel provided in an embodiment of the present application;

[0083] Figure 11 for Figure 10 A timing diagram corresponding to the embodiment;

[0084] Figure 12 A schematic diagram of a display panel provided in an embodiment of the present application;

[0085] Figure 13 for Figure 12 A timing diagram corresponding to the embodiment;

[0086] Figure 14 A schematic diagram of a display panel provided in an embodiment of the present application;

[0087] Figure 15 A schematic diagram of a display panel provided in an embodiment of the present application;

[0088] Figure 16 A schematic diagram of a display panel provided in an embodiment of the present application;

[0089] Figure 17 A schematic diagram of a display device provided in an embodiment of the present application;

[0090] Figure 18 A driving timing diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0091] Figure 19 A driving timing diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0092] Figure 20 A timing diagram of the operation of a display panel provided in an embodiment of the present application;

[0093] Figure 21 A timing diagram of the operation of a display panel provided in an embodiment of the present application;

[0094] Figure 22 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application;

[0095] Figure 23 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application;

[0096] Figure 24 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application;

[0097] Figure 25 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application. [Specific implementation method]

[0098] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0099] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0100] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0101] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0102] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0103] It should be understood that although the terms "first," "second," and "third" may be used to describe regions, etc., in the embodiments of the present application, these regions, etc. should not be limited to these terms. These terms are merely used to distinguish regions, etc. from each other. For example, without departing from the scope of the embodiments of the present application, a first region may also be referred to as a second region, and similarly, a second region may also be referred to as a first region.

[0104] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0105] Please refer to Figures 1A to 1C , Figure 1AA schematic diagram of a display panel provided by the prior art;

[0106] Figure 1B is a schematic diagram of a pixel circuit in the prior art; Figure 1C for Figure 1B The timing diagram of the pixel circuit is shown in FIG. Figure 1B and Figure 1C The display panel of the prior art changes the frequency by adding a hold frame. Specifically, in the t1 phase of the write frame, SN1 provides a valid level and provides an initialization signal to the gate of the driving transistor Td through RL1, so that the gate of the driving transistor is initialized. At the end of the t1 phase, SN2 provides a valid level, T4 and T2 are turned on at the same time, and the drain of the driving transistor is reset. In the t2 phase, SN2 and SP provide valid signals, and the data voltage is written to the gate of the driving transistor through T1, Td and T2, and the threshold is captured at the same time. In the T3 phase, EM provides a valid signal. Then enter the hold frame K. The duration of the hold frame K can be an integer multiple of the write frame time or an integer multiple of the EM period. For example, when the base frequency is 120Hz and the frame rate is 1 / 120s, the total time between writing one frame and writing the next is 1 / 60s, reducing the display frequency to 60Hz. When the frame rate is 1 / 60s, the total time between writing one frame and writing the next is 1 / 120s + 1 / 60s = 1 / 40s, reducing the display frequency to 40Hz. Existing technologies can reduce the frequency because, while holding frame K, SN1 and SN2 remain at an off level, causing the gate of the drive transistor to retain the signal of the current frame. This extends the refresh cycle, reduces the display frequency, and thus reduces power consumption. However, since SN1 and SN2 are both generated by the shift register circuit VSR, and the VSR circuit transmits signals in cascade, the entire display panel must have a uniform frequency. In many display device usage scenarios, this hinders further power consumption reduction. For example, the status bar displayed at the top of a mobile phone or the status bar at the bottom of a computer often displays a relatively fixed image. Therefore, a technology that can achieve different frequencies in multiple zones is urgently needed. The present application provides a technical solution that can achieve different frequencies in different areas of the same screen.

[0107] Figure 2 A schematic structural diagram of a first pixel circuit in a display panel provided in an embodiment of the present application;

[0108] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application.

[0109] The display panel 001 provided in the embodiment of the present application includes a first display area 01, which includes a plurality of first pixel circuits 10. The first pixel circuits 10 can provide a light-emitting driving current for the light-emitting devices in the display panel 001. The light-emitting devices can be organic light-emitting diodes (OLEDs), micro light-emitting diodes (Micro-LEDs), and sub-millimeter light-emitting diodes (Mini-LEDs).

[0110] like Figure 2 As shown, the first pixel circuit 10 includes a driving transistor Td, a data writing module 11 , and a frequency control module 12 .

[0111] Among them, one end of the driving transistor Td is the data voltage storage terminal 100, and the first pixel circuit 10 is used to generate a corresponding light-emitting driving current according to the data voltage stored in the data voltage storage terminal 100. The data writing module 11 can be electrically connected to the driving transistor Td and is used to write the data voltage into the data voltage storage terminal 100 of the driving transistor Td. The frequency control module 12 is electrically connected to the driving transistor Td and the data writing module 11, and is used to control the data writing module 11 to write the data voltage into the data voltage storage terminal 100 of the driving transistor Td. Figure 2 As shown, the data writing module 11 can be electrically connected to the data voltage storage terminal 100 of the driving transistor Td through the frequency control module 12, that is, when the frequency control module 12 is turned on, the data writing module 11 is electrically connected to the data voltage storage terminal 100 of the driving transistor Td through the turned-on frequency control module 12.

[0112] For example, Figure 2 As shown, the gate of the driving transistor Td is a data voltage storage terminal 100. When the data writing module 11 and the frequency control module 12 are turned on, the data voltage received at the input terminal of the data writing module 11 is transmitted to the gate of the driving transistor Td through the turned-on data writing module 11 and the frequency control module 12. It should be noted that the data voltage storage terminal 100 of the driving transistor Td can also be its input terminal or output terminal. For ease of description, the following description uses the data voltage storage terminal 100 of the driving transistor Td as its gate.

[0113] In the embodiment of the present application, the frequency control module 12 is used to control the frequency at which the data writing module 11 writes the data voltage into the data voltage storage terminal 100 of the driving transistor Td. That is, in the first display area 01, the frequency control module 12 controls the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the first pixel circuit 10 receives the data voltage to be locally variable, thereby making the local refresh frequency of the image displayed by the light-emitting device electrically connected to the first pixel circuit 10 variable.

[0114] It should be noted that the first pixel circuit 10 is disposed in the first display area 01. The first pixel circuit 10 can provide a light-emitting drive current to the light-emitting device disposed in the first display area 01, thereby enabling a variable local refresh rate for the image displayed in the first display area 01. Furthermore, the first pixel circuit 10 can also provide a light-emitting drive current to light-emitting devices disposed in other display areas outside the first display area 01, thereby enabling a variable refresh rate for the image displayed in these other display areas. For ease of understanding, the following description will take the example of the first pixel circuit 10 providing a light-emitting drive current to the light-emitting device disposed in the first display area 01.

[0115] In the embodiment of the present application, the display area of ​​the display panel 001 includes an area with a variable image refresh frequency, namely, the first display area 01.

[0116] In a technical solution of this embodiment, as shown in FIG1 , the display areas of the display panel 001 are all areas with a variable image refresh rate, that is, the display areas of the display panel 001 are all first display areas 01 . Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application. In another technical solution of this embodiment, as Figure 3 As shown, the display area of ​​the display panel 001 may also include a second display area 02, the second display area 02 includes a second pixel circuit 20, and the second pixel circuit 20 may not include the frequency control module 12. Then, the refresh frequency of the image displayed by the light-emitting device electrically connected to the second pixel circuit 20 is not controlled by the frequency control module 12.

[0117] If the second pixel circuit 20 provides a light-emitting driving current for the light-emitting devices in the second display area 02 , the refresh frequency of the image displayed in the second display area 02 cannot be adjusted by the frequency control module 12 .

[0118] In the display panel 001 provided in the embodiment of the present application, the image refresh frequency in the first display area 01 can be changed by controlling the frequency at which the data voltage is written to the gate of the driving transistor Td by the frequency control module 12 in the first pixel circuit 10. This makes the location of the variable image refresh frequency region in the display panel 001 more flexible and easier to implement.

[0119] In one embodiment of the present application, Figure 2 As shown, the gate of the driving transistor Td is its data voltage storage terminal 100 and the frequency control module 12 is electrically connected to the gate of the driving transistor Td. That is, the frequency control module 12 in the first pixel circuit 10 is used to control the frequency of writing the data voltage to the gate of the driving transistor Td. When the data voltage is written to the gate of the driving transistor Td, the light-emitting driving current generated by the driving transistor Td is no longer affected by the threshold voltage of the driving transistor Td.

[0120] In addition, if Figure 2 As shown, the first pixel circuit 10 further includes a storage capacitor CSt, which is electrically connected to the data voltage storage terminal 100 of the driving transistor Td and is used to maintain the potential of the data voltage storage terminal 100.

[0121] When the gate of the driving transistor Td serves as the data voltage storage terminal 100 , the storage capacitor CSt is electrically connected to the gate of the driving transistor Td to maintain the gate potential of the driving transistor Td.

[0122] For details, please refer to Figures 4A to 4C , Figure 4A A schematic diagram of a display panel provided in an embodiment of the present application; Figure 4B An equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application; Figure 4C for Figure 4B Timing diagram of the pixel circuit.

[0123] In some embodiments, as Figure 4B As shown, the frequency control module 12 includes a frequency control transistor T3 , and the data writing module 11 includes a data writing transistor T1 and a threshold grabbing transistor T2 .

[0124] The input of the data write transistor T1 is connected to the data voltage line DL, and the output of the data input transistor is electrically connected to the input of the drive transistor Td. The data voltage line DL transmits a data voltage to the data write transistor T1. The input of the threshold capture transistor T2 is electrically connected to the output of the drive transistor Td, and the output of the threshold capture transistor T2 is electrically connected to the input of the frequency control transistor T3. The output of the frequency control transistor T3 is electrically connected to the gate of the drive transistor Td. One plate of the storage capacitor CSt is electrically connected to the gate of the drive transistor Td, and the other plate is electrically connected to the first fixed potential signal line.

[0125] When a data voltage needs to be written to the gate of the driving transistor Td, the data writing transistor T1, the threshold grabbing transistor T2, and the frequency control transistor T3 are turned on, and the data voltage transmitted by the data voltage line DL is transmitted to the gate of the driving transistor Td. Therefore, even if the data writing transistor T1 and the threshold grabbing transistor T2 are turned on, if the frequency control transistor T3 is not turned on, the data voltage transmitted by the data voltage line DL cannot be transmitted to the gate of the driving transistor Td. Therefore, the turning-on frequency of the frequency control transistor T3 in the first pixel circuit 10 can affect the frequency at which the gate of the driving transistor Td receives the data voltage.

[0126] In this embodiment, when it is necessary to change the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the first pixel circuit 10 receives the data voltage, it is sufficient to change the turn-on frequency of the frequency control transistor T3, without making any special design for the turn-on frequencies of the data writing transistor T1 and the threshold grabbing transistor T2 included in the first pixel circuit 10. That is, there is no need to make any special design for the signals received by the scanning line S1 connected to the data writing transistor T1 and the scanning line S1' connected to the threshold grabbing transistor T2. That is, their inherent connection method can be maintained, which reduces the design difficulty of the display panel 001 and does not excessively increase power consumption.

[0127] The timing corresponding to the case where the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the first pixel circuit 10 receives the data voltage is less than the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the second pixel circuit 20 receives the data voltage. Figure 4C The timing shown is the operating timing of the first pixel circuit 10 or the second pixel circuit 20 located in a row.

[0128] The working process of this embodiment includes multiple writing frames W, each of which includes a reset phase t1, a data writing phase t2, and a light emitting phase t3. Here, two working cycles W1 and W2 including a hold frame K between the two writing frames are used as an example for description.

[0129] In any working cycle of the second pixel circuit 20, in the reset stage t1, the scan line S3 transmits an enable signal (high-level signal) to control the first reset transistor T4 to turn on, and the reset voltage on the first reset signal line RL1 is transmitted to the data voltage storage terminal 100 of the driving transistor Td; in the data writing stage t2, the scan line S1 transmits an enable signal (low-level signal) to control the data writing transistor T1 to turn on and the scan line S1' transmits an enable signal (high-level signal) to control the threshold capture transistor T2 to turn on, and the data voltage transmitted by the data voltage line DL is transmitted to the data voltage storage terminal 100 of the driving transistor Td; in the light-emitting stage t3, the light-emitting control signal line EM transmits an enable signal (low-level signal) to control the power supply voltage writing transistor T5 and the light-emitting control transistor T6 to turn on, and the driving transistor Td generates a light-emitting driving current.

[0130] The difference of the first pixel circuit 20 is that in the reset phase t1 and the data writing phase t2, the frequency control signal line SW transmits an enable signal (high level signal) to control the frequency control transistor T3 to turn on, so as to reset the gate of the driving transistor Td and write the data voltage respectively.

[0131] In the second writing frame W2, the second pixel circuit 20 is similar to the first pixel circuit 10, including a reset phase t1, a data writing phase t2, and a light-emitting phase t3. Therefore, the first writing frame W1 can be regarded as a data writing frame. In the first writing frame W1, the second pixel circuit 20 does not reset the gate of the driving transistor Td and does not write the data voltage to the gate of the driving transistor Td. Therefore, the second writing frame can be equivalent to a holding frame.

[0132] When the base frequency is 120 Hz and the writing time of frame W is 1 / 120 s, in the first writing frame W1, in the first display area 01, since the frequency control signal line SW is at the cutoff level, the frequency control transistor T3 is turned off, and the gate of the driving transistor Td is not written with the data voltage, and the voltage signal of the previous frame is still maintained. In the second display area 02, however, the frequency control transistor T3 is not provided, so the data signal is normally written to the second area 02. In the hold frame K, the data signal is written to both the first area 01 and the second area 02. In the second writing frame W2, since the frequency control transistor T3 in the first area 01 is turned on, the data signal is written to the gate of the driving transistor Td of the first pixel circuit 10. Therefore, the duration of the previous frame in the first area is 3*1 / 120=1 / 40 s, so the display frequency of the first area 01 is 40 Hz. The duration of the previous frame in the second area is 2*1 / 120 Hz, and the display frequency of the second area 02 is 60 Hz, thus achieving a unified display with different frequencies in different areas of the screen.

[0133] Figure 5 This is an equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application.

[0134] When the display panel 001 further includes a second display area 02, as shown in FIG. Figure 5 As shown, the second pixel circuit 20 provided in the second display area 02 may also include a driving transistor Td, a data writing transistor T1 and a threshold grabbing transistor T2. The driving transistor Td is also used to generate a light-emitting driving current.

[0135] The input terminal of the data write transistor T1 is connected to the data voltage line DL, and the output terminal of the data input transistor is electrically connected to the input terminal of the drive transistor Td. The data voltage line DL transmits the data voltage to the data write transistor T1. The input terminal of the threshold grabbing transistor T2 is electrically connected to the output terminal of the drive transistor Td, and the output terminal of the threshold grabbing transistor T2 is electrically connected to the gate of the drive transistor Td. One plate of the storage capacitor CSt is electrically connected to the gate of the drive transistor Td, and the other plate is electrically connected to the first fixed potential signal line.

[0136] When the gate of the driving transistor Td in the second pixel circuit 20 needs to receive the data voltage, after the data writing transistor T1 and the threshold grabbing transistor T2 are turned on, the data voltage transmitted by the data voltage line DL can be transmitted to the gate of the driving transistor Td.

[0137] As can be seen, the difference between the second pixel circuit 20 in the second display area 02 and the first pixel circuit 10 in the first display area 01 is that the frequency control transistor T3 is not provided in the second pixel circuit 20. However, the frequency at which the gate of the driving transistor Td in the first pixel circuit 10 receives the data voltage is controlled by the frequency control transistor T3. Therefore, the data writing transistor T1 included in the first pixel circuit 10 in the first display area and the second pixel circuit 20 in the second display area 02 can respectively adopt the same design, and the threshold grabbing transistor T2 included therein can also adopt the same design.

[0138] For example, the scan line S1 connected to the gate of the data-writing transistor T1 in the first pixel circuit 10 and the scan line S1 connected to the gate of the data-writing transistor T1 in the second pixel circuit 20 are electrically connected to the shift register unit in the same set of shift registers. For example, the scan line S1' connected to the gate of the threshold-grabbing transistor T2 in the first pixel circuit 10 and the scan line S1' connected to the gate of the threshold-grabbing transistor T2 in the second pixel circuit 20 are electrically connected to the shift register unit in the same set of shift registers. For example, the input end of the data-writing transistor T1 in the first pixel circuit 10 and the input end of the data-writing transistor T1 in the second pixel circuit 20 can be connected to the same data voltage line DL.

[0139] Figure 6 This is an equivalent circuit diagram of a first pixel circuit in a display panel provided in an embodiment of the present application.

[0140] In some embodiments, as Figure 6 As shown, the frequency control module 12 includes a frequency control transistor T3 , and the data writing module 11 includes a data writing transistor T1 .

[0141] The input terminal of the data write transistor T1 is connected to the data voltage line DL, and the output terminal of the data write transistor T1 is electrically connected to the input terminal of the drive transistor Td. The data voltage line DL transmits a data voltage to the data write transistor T1. The input terminal of the frequency control transistor T3 is electrically connected to the output terminal of the drive transistor Td, and the output terminal of the frequency control transistor T3 is electrically connected to the gate of the drive transistor Td. One plate of the storage capacitor CSt is electrically connected to the gate of the drive transistor Td, and the other plate is electrically connected to the first fixed potential signal line.

[0142] In the embodiment of the present application, the frequency of the electrical connection between the data writing module 11 and the data voltage storage terminal 100 of the driving transistor Td can be achieved by changing the activation frequency of the frequency control module 12, thereby changing the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the first pixel circuit 10 receives the data voltage. The activation frequency of the frequency control module 12 can be controlled by a signal transmitted by a frequency control signal line to which its control terminal is electrically connected.

[0143] When a data voltage needs to be written to the gate of the driving transistor Td, the data writing transistor T1 and the frequency control transistor T3 are turned on, and the data voltage transmitted by the data voltage line DL is transmitted to the gate of the driving transistor Td. Therefore, even if the data writing transistor T1 is turned on, when the frequency control transistor T3 is not turned on, the data voltage transmitted by the data voltage line DL cannot be transmitted to the gate of the driving transistor Td. Therefore, the turning-on frequency of the frequency control transistor T3 in the first pixel circuit 10 can affect the frequency at which the gate of the driving transistor Td receives the data voltage.

[0144] In this embodiment, in the first pixel circuit 10, the gate of the data writing transistor T1 and the gate of the frequency control transistor T3 are electrically connected to different scan lines, such as Figure 6 As shown, the data writing transistor T1 is connected to the scan line S1 and the gate of the frequency control transistor T3 is connected to the scan line SW. In at least some display modes, the frequency at which the scan line S1 transmits an enable signal to the data writing transistor T1 is different from the frequency at which the scan line SW transmits an enable signal to the frequency control transistor T3.

[0145] The display panel 001 provided in this embodiment includes a first pixel circuit 10 in which no additional threshold capture transistor T2 is provided. Instead, the frequency control transistor T3 is used to write the data voltage into the gate of the driving transistor Td to reduce the influence of the threshold voltage drift of the driving transistor Td on the generated light-emitting driving current.

[0146] When the display panel 001 further includes the second display area 02, the structure of the second pixel circuit 20 can still be the same as Figure 5 As shown, no further details are given here.

[0147] As can be seen, the data write transistors T1 included in the first pixel circuit 10 provided in the first display area 01 and the second pixel circuit 20 provided in the second display area 02 can also adopt the same design. For example, the scan line S1 connected to the gate of the data write transistor T1 in the first pixel circuit 10 and the scan line S1 connected to the gate of the data write transistor T1 in the second pixel circuit 20 are electrically connected to the shift register unit in the same shift register. For example, the input terminal of the data write transistor T1 in the first pixel circuit 10 and the input terminal of the data write transistor T1 in the second pixel circuit 20 can be connected to the same data voltage line DL.

[0148] In addition, if Figures 4A-6 As shown, the first pixel circuit 10 and the second pixel circuit 20 may further include a first reset module 13 , and the first reset module 13 is used to transmit a reset voltage to the gate of the driving transistor Td.

[0149] like Figure 4A and Figure 6 As shown, the first reset module 13 in the first pixel circuit 10 is electrically connected to the input end of the frequency control transistor T3. When the gate of the driving transistor Td included in the first pixel circuit 10 needs to receive a reset voltage, the first reset module 13 and the frequency control transistor T3 are turned on.

[0150] The first reset module 13 includes a first reset transistor T4, an input end of which is electrically connected to the first reset signal line RL1, and an output end of which is electrically connected to the input end of the frequency control transistor T3. When the gate of the driving transistor Td included in the first pixel circuit 10 needs to receive a reset voltage, the first reset transistor T4 and the frequency control transistor T3 are turned on, and the reset voltage on the first reset signal line RL1 is transmitted to the gate of the driving transistor Td.

[0151] The frequency control transistor T3 in the first pixel circuit 10 must be turned on when the gate of the driving transistor Td receives the reset voltage and the data voltage. It should be noted that although the turn-on frequency of the frequency control transistor T3 needs to take into account the frequencies at which the gate of the driving transistor in the first pixel circuit 10 receives the first reset voltage and the data voltage, the turn-on frequency of the frequency control transistor T3 still determines the frequency at which the gate of the driving transistor Td in the first pixel circuit 10 receives the data voltage.

[0152] The first reset module 13 in the second pixel circuit 20 is electrically connected to the gate of the driving transistor Td. When the gate of the driving transistor Td included in the first pixel circuit 10 needs to receive a reset voltage, the first reset module 13 is turned on.

[0153] The first reset module 13 includes a first reset transistor T4. An input terminal of the first reset transistor T4 is electrically connected to the first reset signal line RL1, and an output terminal of the first reset transistor T4 is electrically connected to the gate of the driving transistor Td. When the gate of the driving transistor Td needs to receive a reset voltage, the first reset transistor T4 turns on, and the reset voltage on the first reset signal line RL1 is transmitted to the gate of the driving transistor Td.

[0154] The first reset transistor T4 may be an N-channel transistor, and the semiconductor layer included therein may specifically be a metal oxide semiconductor layer.

[0155] Furthermore, if Figures 4A-6 As shown, the first pixel circuit 10 and the second pixel circuit 20 may further include a power supply voltage writing transistor T5 , a light emitting control transistor T6 and a second reset transistor T7 .

[0156] The power supply voltage writing transistor T5 has an input terminal that receives the first power supply voltage PVDD, and an output terminal that is electrically connected to the input terminal of the driving transistor Td. The light-emitting control transistor T6 has an input terminal that is electrically connected to the output terminal of the driving transistor Td, and an output terminal that is electrically connected to the light-emitting device EL. Furthermore, the gates of the power supply voltage writing transistor T5 and the gates of the light-emitting control transistor T6 can both be electrically connected to the light-emitting control signal line EM. One terminal of the light-emitting device EL is connected to the pixel circuit, and the other terminal can receive the second power supply voltage PVEE.

[0157] The second reset transistor T7 has an input electrically connected to the second reset signal line RL2, an output electrically connected to the light-emitting device EL, and a gate electrically connected to the scan line S3'. When the signal transmitted on the scan line S3' turns on the second reset transistor T7, it transmits the reset voltage on the second reset signal line RL2 to the light-emitting device EL.

[0158] Figures 4A-6 As shown, the gate of the first reset transistor T4 is electrically connected to the scan line S3 and the gate of the second reset transistor T7 is electrically connected to the scan line S3', that is, the gates of the first reset transistor T4 and the second reset transistor T7 can be connected to different scan lines. It should be noted that the gate of the first reset transistor T4 and the gate of the second reset transistor T7 can also be connected to the same scan line, or the gate of the second reset transistor T7 and the gate of the data writing transistor T1 can also be connected to the same scan line.

[0159] In some embodiments, the frequency control transistor T3 may be an N-channel transistor, and the semiconductor layer included therein may be a metal oxide semiconductor layer, which can effectively prevent leakage current from affecting the potential of the data voltage storage terminal 100 in the driving transistor Td.

[0160] In some embodiments, when the first pixel circuit 10 includes a threshold grabbing transistor T2, the threshold grabbing transistor T2 may also be an N-channel transistor, and the semiconductor layer included therein may specifically be a metal oxide semiconductor layer. Furthermore, when the second pixel circuit 20 includes a threshold grabbing transistor T2, the threshold grabbing transistor T2 may also be an N-channel transistor, and the semiconductor layer included therein may specifically be a metal oxide semiconductor layer.

[0161] Figure 7 for Figure 6 The first pixel circuit shown is Figure 5 A working timing diagram of the second pixel circuit is shown. Figure 8 The timing shown is the timing corresponding to the case where the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the first pixel circuit 10 receives the data voltage is less than the frequency at which the data voltage storage terminal 100 of the driving transistor Td in the second pixel circuit 20 receives the data voltage. Figure 8 The timing shown is the operating timing of the first pixel circuit 10 and the second pixel circuit 20 located in the same row.

[0162] like Figure 8 As shown, the working process of the second pixel circuit 20 includes multiple working cycles t0, each working cycle t0 includes a reset phase t1, a data writing phase t2 and a light emitting phase t3, and each working cycle t0 of the second pixel circuit 20 can be regarded as a data writing frame.

[0163] like Figure 7 As shown, the operation process of the first pixel circuit 10 includes a first operating cycle t01 and a second operating cycle t02. The first operating cycle t01 of the second pixel circuit 20 is the same as the operating cycle t0 of the first pixel circuit 10, including a reset phase t1, a data writing phase t2, and a light-emitting phase t3. Therefore, the first operating cycle t01 can be considered a data writing frame. The second operating cycle t02 of the second pixel circuit 20 includes a dummy reset phase t1', a dummy data writing phase t2', and a light-emitting phase t3. The dummy reset phase t1' does not reset the gate of the driving transistor Td, and the dummy data writing phase t2' does not write the data voltage to the gate of the driving transistor Td. Therefore, the second operating cycle t02 can be considered a data maintenance frame.

[0164] Please refer to Figure 7 , any working period t0 of the second pixel circuit 20 is Figure 7 Any working period t0 of the second pixel circuit 20 is the same as that shown, and will not be described again here.

[0165] Please continue to refer to Figure 7In the first working cycle t01 of the first pixel circuit 10, in the reset phase t1, the scan line S3 transmits an enable signal (high-level signal) to control the first reset transistor T4 to turn on and the frequency control signal line SW transmits an enable signal (high-level signal) to control the frequency control transistor T3 to turn on, and the reset voltage on the first reset signal line RL1 is transmitted to the data voltage storage terminal 100 of the driving transistor Td; in the data writing phase t2, the scan line S1 transmits an enable signal (low-level signal) to control the data writing transistor T1 to turn on and the frequency control signal line SW transmits an enable signal (high-level signal) to control the frequency control transistor T3 to turn on, and the data voltage transmitted by the data voltage line DL is transmitted to the data voltage storage terminal 100 of the driving transistor Td; in the light-emitting phase t3, the light-emitting control signal line EM transmits an enable signal (low-level signal) to control the power supply voltage writing transistor T5 and the light-emitting control transistor T6 to turn on, and the driving transistor Td generates a light-emitting driving current.

[0166] Please continue to refer to Figure 7 The difference between the second working cycle t02 of the first pixel circuit 20 and the first working cycle t01 is that in the dummy reset phase t1' and the dummy data writing phase t2', the frequency control signal line SW transmits a non-enable signal (low-level signal) to control the frequency control transistor T3 to turn off, and the data voltage storage terminal 100 of the driving transistor Td maintains its original data voltage potential.

[0167] Depend on Figure 7 It can be seen that part of the data writing frame of the second pixel circuit 20 corresponds to the data writing frame of the first pixel circuit 10 , and another part of the data writing frame of the second pixel circuit 20 corresponds to the data maintaining frame of the first pixel circuit 10 .

[0168] Figure 8 A schematic diagram of a display panel provided in an embodiment of the present application.

[0169] In some embodiments, the first display area 01 includes a first sub-display area 01A and a second sub-display area 01B; the plurality of first pixel circuits 10 include a first type of pixel circuit 10A and a second type of pixel circuit 10B, with the first type of pixel circuit 10A being disposed in the first sub-display area 01A and the second type of pixel circuit 10B being disposed in the second sub-display area 01B. Thus, the first pixel circuit 10 in the first sub-display area 01A is the first type of pixel circuit 10A, and the first pixel circuit 10 in the second sub-display area 01B is the second type of pixel circuit 10B.

[0170] Furthermore, the control terminals of the frequency control modules 12 included in the first type pixel circuit 10A and the second type pixel circuit 10B, respectively, are electrically connected to different frequency control signal lines SW. For example, the control terminal of the frequency control module 12 included in the first type pixel circuit 10A in the first sub-display area 01A is electrically connected to the frequency control signal line SW1, while the control terminal of the frequency control module 12 included in the second type pixel circuit 10B in the second sub-display area 01B is electrically connected to the control signal line SW2.

[0171] Although the frequency control signal line SW1 and the frequency control signal line SW2 can transmit enable signals of the same frequency in some display modes, so that the refresh frequencies of the images displayed in the first sub-display area 01A and the second sub-display area 01B are the same, the frequency control signal line SW1 and the frequency control signal line SW2 can also transmit enable signals of different frequencies in some display modes, so that the refresh frequencies of the images displayed in the first sub-display area 01A and the second sub-display area 01B are different. Therefore, the display area of ​​the display panel 001 includes multiple regions with variable refresh frequencies, and the refresh frequencies of the images displayed in the multiple regions with variable refresh frequencies can be different.

[0172] Please refer to further Figure 8 and Figure 9 The display panel of this embodiment includes a first display area 01, wherein the first display area includes five sub-display areas 01A, 01B, 01C, 01D and 01E, and the control signal lines of the frequency control module 12 in the first pixel circuit 10 corresponding to the five sub-display areas are SW1 to SW5 respectively. Please continue to refer to Figure 9 Here, we use a base frequency of 120Hz as an example, meaning each write frame lasts 1 / 120s. Here, only the frequency control module is used for frequency reduction, without using S3 or S1'. This means that for the shift register circuit, there are only write frames, not hold frames.

[0173] For the first sub-display area O1A, during the first write frame W1, the data signal is written to the gate of the drive transistor via the frequency control transistor T3. During the second and third write frames W2 and W3, the frequency control transistor is controlled by SW1 and turned off, allowing it to retain the data signal from the first write frame W1. This is equivalent to a hold frame. During the fourth write frame W4, the data signal is written to the gate of the drive transistor via the frequency control transistor T3. Therefore, the display frequency for the first sub-display area O1 is 40 Hz.

[0174] For the second sub-display area O1B, during the first write frame W1, the data signal is written to the gate of the drive transistor via the frequency control transistor T3. During the second write frame W2, the frequency control transistor is controlled by SW2 and turned off, allowing it to retain the data signal of the first write frame W1. This is equivalent to a hold frame. During the third write frame W3, the data signal is written to the gate of the drive transistor via the frequency control transistor T3. During the fourth write frame W4, the frequency control transistor is controlled by SW2 and turned off, allowing it to retain the data signal of the first write frame W3. This is equivalent to a hold frame. Therefore, the display frequency for the first sub-display area O1 is 60 Hz.

[0175] For the third sub-display area 01C and the fourth sub-display area 01D, data signals are written into the gate of the drive transistor via the frequency control transistor T3 during the first writing frame W1, the second writing frame W2, the third writing frame W3, and the fourth writing frame W4. Therefore, the display frequency for the first sub-display area 01 is 120 Hz.

[0176] For the fifth sub-display area 01E, during the first write frame W1, the data signal is written to the gate of the driving transistor through the frequency control transistor T3. In the second write frame W2, the third write frame W3, and the fourth write stage W4, the frequency control transistor is controlled by SW5 and cut off, so that it maintains the data signal of the first write frame W1. This is equivalent to holding the frame. During the fourth write frame W4, the data signal is written to the gate of the driving transistor through the frequency control transistor T3. Therefore, the display frequency for the first sub-display area 01 is 30Hz. Therefore, the present application can control the display frequency of different areas in the same display screen through the frequency control transistor.

[0177] Of course, in other embodiments of the present application, the frequency reduction of S3 and S1 ′ and the frequency reduction of the frequency control module of the present application may be adopted simultaneously.

[0178] In a technical solution corresponding to this embodiment, as Figure 10 and Figure 11 shown. Figure 10 A schematic diagram of a display panel provided in an embodiment of the present application; Figure 11 for Figure 10 A timing diagram corresponding to the embodiment;

[0179] The signal on the frequency control signal line SW1 to which the first type pixel circuit 10A is electrically connected and the signal on the frequency control signal line SW2 to which the second type pixel circuit 10B is electrically connected are both provided by the shift register.

[0180] Please refer to Figure 10 and Figure 11The display panel includes a first shift register VSR1, which includes a plurality of cascaded shift register units SR. The frequency control signal line SW1 electrically connected to the first type pixel circuit 10A and the frequency control signal line SW2 electrically connected to the second type pixel circuit 10B are respectively electrically connected to different shift register units SR in the first shift register VSR1.

[0181] In one implementation, when the frequency control modules 12 in the first pixel circuits 10 in the same row are connected to the same frequency control signal line SW and the frequency control modules 12 in the first pixel circuits 10 in different rows are connected to different frequency control signal lines SW, Figure 11 As shown, each frequency control signal line SW can be connected to a different shift register unit SR in the first shift register VSR1.

[0182] This implementation is suitable for, e.g. Figure 6 As shown in FIG. 1 , the frequency control transistor T3 in the first pixel circuit 10 is multiplexed as a threshold capture transistor. Figure 6 The frequency control transistor T3 in the first pixel circuit 10 shown is reused as a threshold capture transistor. By connecting the frequency control modules 12 in different rows of first pixel circuits 10 to different frequency control signal lines SW, the frequency control modules 12 included in the first pixel circuits 10 in the first display area 01 can be regionalized and turned on. When the first sub-display area 01A writes a data signal to the corresponding pixel circuit via the scanning signal lines S1-1 to S1-n, the frequency control signal line SW1 corresponding to the first sub-display area inputs a valid signal, causing the frequency control transistor to turn on and write the data signal. Similarly, when the frequency control transistor corresponding to the second sub-display area 01B is turned on, the data signal is written to the second sub-display area. Since the second sub-display area is scanned after the first sub-display area is scanned, the valid pulse of the frequency control signal SW2 of the second sub-display area 01B is after the frequency control signal SW1 of the first sub-display area 01A. Therefore, a shift register circuit can be used to output the frequency control signal.

[0183] In addition, when the first region requires multiple independently controlled sub-regions, and the sub-regions are evenly distributed, using a shift register circuit to output the frequency control signal can save the number of IC pins and reduce costs.

[0184] When the frequency control signals of multiple sub-display areas cascaded in the same shift register circuit require different control frequencies, the signal transmission can be stopped by pausing the clock signal, thereby reducing the frequency of the subsequent frequency control signal. For example, the frequency of SR2 can be made lower than that of SR1.

[0185] It should be noted that since the frequency control transistors of each sub-display area in the first display area are connected to the same control signal line. Figure 6 In the embodiment, it is necessary to wait until all sub-display areas have completed data writing before the frequency control transistors can be turned off and the light-emitting stage can be entered. Figure 11 As shown, the 1st to nth rows share a light-emitting control signal EM(1~n), and the n+1th to mth rows share a light-emitting control signal EM(n+1~m). The potential of the gate of the driving transistor Td will be changed due to early light emission.

[0186] The cascaded shift registers SR in the first shift register VSR1 output enable signals (high level signals) in sequence, such as Figure 11 As shown, when the shift register unit SR1 in the first shift register VSR1, which is electrically connected to the first pixel electrical connection 10 in the first display area 01A, outputs the enable signal first and the shift register unit SR2, which is electrically connected to the first pixel electrical connection 10 in the second display area 01B, outputs the enable signal later, by controlling the clock signal received by the first shift register VSR1, the frequency of the enable signal output by the shift register unit SR2 can be lower than the frequency of the enable signal output by the shift register unit SR1. Therefore, the display panel provided by this technical solution can realize top-bottom split-screen display, and the image display frequencies of the top-bottom split-screen can be different. Specifically, the image refresh frequency of the display area in the lower portion of the display panel is lower than the image refresh frequency of the display area in the upper portion.

[0187] Figure 12 A schematic diagram of a display panel provided in an embodiment of the present application is shown. Figure 13 for Figure 12 A timing diagram of an embodiment.

[0188] The display panel 001 of this embodiment further includes a multiplexer circuit DX, multiple output terminals of which can be electrically connected to different frequency control signal lines SW, and can provide different frequency control signal lines SW with enable signals of different frequencies and enable signals of the same frequency.

[0189] As shown in the figure, the multiplexer selection circuit DX includes a first transistor T01, a second transistor T02, a third transistor T03, a fourth transistor T04, and a first transistor T05. The input ends of T01 to T05 are all electrically connected to the first signal line IN. The first signal line IN transmits a first signal, which is a signal used to control the frequency control module 12 to turn on.

[0190] The output end of the first transistor T01 is electrically connected to the same control signal line SW1 as the first type pixel circuit 10A. That is, the first transistor T01 transmits a first signal to the control end of the frequency control module 12 in the first type pixel circuit 10A via the control signal line SW1. The output end of the second transistor T02 is electrically connected to the same control signal line SW2 as the second type pixel circuit 10B. That is, the second transistor T01 transmits a first signal to the control end of the frequency control module 12 in the first type pixel circuit 10A via the control signal line SW1. The same logic is used and will not be further described.

[0191] By configuring the multiplexer circuit DX to provide the first signal to the control terminal of the frequency control module 12 , that is, to provide an enable signal to the frequency control module 12 , the number of signal lines in the fan-shaped wiring area of ​​the display panel will not be excessively increased.

[0192] Please continue to refer to Figure 14 and Figure 15 The control terminal of the first transistor T01 is electrically connected to the first scan line L1, and the control terminal of the second transistor T02 is electrically connected to the second scan line L2. The signal transmitted by the first scan line L1 is used to control the on / off state of the first transistor T01, and the signal transmitted by the second scan line L2 is used to control the on / off state of the second transistor T02. The same logic is used and will not be further described.

[0193] In one embodiment of the present application, Figure 12 、 13 as well as Figure 8 and Figure 9 At the beginning of the first writing frame W1, when the first scan line L1 provides an effective level, the first signal line IN transmits a high level to the control signal line SW1, so that the first sub-display area 01A writes a data signal; when the second scan line L2 provides an effective level, the first signal line IN transmits a high level to the control signal line SW2, so that the second sub-display area 01B writes a data signal; when the third scan line L3 provides an effective level, the first signal line IN transmits a high level to the control signal line SW3, so that the third sub-area 01C writes a data signal; when the fourth scan line L4 provides an effective level, the first signal line IN transmits a high level to the control signal line SW4, so that the fourth sub-area 01D writes a data signal; when the fifth scan line L5 provides an effective level, the first signal line IN transmits a high level to the control signal line SW5, so that the fifth sub-area 01E writes a data signal;

[0194] At the beginning of the second writing frame W2, when the first scan line L1 provides an effective level, the first signal line IN transmits a low level to the control signal line SW1, so that the data signal is not written into the first sub-display area 01A; this is equivalent to the first sub-display area entering a hold frame, thereby causing frequency reduction; when the second scan line L2 provides an effective level, the first signal line IN transmits a low level to the control signal line SW2, so that the data signal is not written into the second sub-display area 01B; this is equivalent to the first sub-display area entering a hold frame, thereby causing frequency reduction; when the third scan line L3 provides an effective level, the first signal line IN transmits a high level to the control signal line SW3, so that the data signal is written into the third sub-area 01C; when the fourth scan line L4 provides an effective level, the first signal line IN transmits a high level to the control signal line SW4, so that the data signal is written into the fourth sub-area 01D; when the fifth scan line L5 provides an effective level, the first signal line IN transmits a high level to the control signal line SW5, so that the data signal is written into the fifth sub-area 01E;

[0195] The third writing frame W3 and the fourth writing frame W4 are not described in detail. Different voltage signals are input to the frequency control signal lines SW of different sub-display areas, so that different sub-display areas can realize different display frequencies.

[0196] To ensure that the potential on each frequency control signal line is maintained for a sufficiently long time, the parasitic capacitance on the frequency control signal line can be increased as much as possible. For example, the overlap area between the frequency control signal line and the fixed potential signal line can be increased. Furthermore, the transistors in the multiplexer circuit can be configured as metal oxide semiconductor transistors to reduce their leakage current.

[0197] In the previous embodiment, the first signal line IN needs to continuously jump between a high level and a low level to transmit the correct signal to the corresponding frequency control signal line. In addition, the frequency of the sub-display area can also be controlled by controlling the frequency at which the scan lines of the multiplexer circuit are turned on. Among them, the frequency at which the first transistor T01 outputs the first signal is the frequency at which the frequency control module 12 to which it is electrically connected is turned on, and the frequency at which the second transistor T02 outputs the enable signal is the frequency at which the frequency control module 12 to which it is electrically connected is turned on.

[0198] The frequency of the first signal output by the first transistor T01 is jointly determined by the signal transmitted on the first scan line L1 and the signal transmitted on the first signal line IN, and the frequency of the first signal output by the second transistor T01 is jointly determined by the signal transmitted on the second scan line L2 and the signal transmitted on the first signal line IN.

[0199] For example, when the first scan line L1 and the second scan line L2 transmit the same frequency of the enable signal, the first signal line IN transmits the enable signal at different frequencies when the first transistor T01 is turned on and when the second transistor T02 is turned on, so that the frequency of the first signal received on the frequency control signal SW1 and the frequency of the first signal received on the frequency control signal line SW2 can be different.

[0200] For example, when the frequencies of the enable signals transmitted by the first scan line L1 and the second scan line L2 are different, the first signal line IN transmits the enable signal when the first transistor T01 is turned on and when the second transistor T02 is turned on, so that the frequency of the first signal received on the frequency control signal SW1 and the frequency of the first signal received on the frequency control signal line SW2 can be different.

[0201] It should be noted that when the first pixel circuit is shown in FIG4 , after the frequency control transistor T3 is turned on and the data voltage is written to the gate of the driving transistor Td, the frequency control transistor T3 can remain in the on state, and after the threshold capture transistor T2 and the first reset transistor T1 are turned off, the first pixel circuit 10 can emit light normally. When the first pixel circuit is shown in FIG4 , after the frequency control transistor T3 is turned on and the data voltage is written to the gate of the driving transistor Td, the gate of the frequency control transistor T3 can also receive a disable signal to achieve a disabled state. In this case, the disable signal can still be provided by the multiplexer DX.

[0202] Figure 14 and Figure 15 The embodiment of the present invention is a more flexible distribution method of the sub-display areas in the first display area, which can display a partial picture and realize different sub-pixel frequencies in the same row.

[0203] Figure 16 A schematic diagram of a display panel provided in an embodiment of the present application.

[0204] like Figure 16 As shown, in some embodiments of the present application, the display panel 001 includes a second shift register VSR2, which includes a plurality of cascaded shift register units SR. In particular, the gates of transistors having the same function in the data writing module 11 included in the first type pixel circuit 10A and the data writing module 11 included in the second type pixel circuit 10B are connected to different shift register units SR in the same second shift register VSR2.

[0205] In this embodiment, the first type pixel circuit 10A and the second type pixel circuit 10B may both be pixel circuits with a frequency control module 12 added to a conventional pixel circuit, for example, the first pixel circuit 10 shown in FIG. 4 .

[0206] For example, Figure 16 As shown, the gates of the data writing transistor T1 in the data writing module 11 included in the first type pixel circuit 10A and the data writing transistor T1 in the data writing module 11 included in the second type pixel circuit 10B are connected to different shift register units SR in the same second shift register VSR2.

[0207] For example, Figure 16 As shown, the gates of the threshold grabbing transistor T2 in the data writing module 11 included in the first type pixel circuit 10A and the threshold grabbing transistor T2 in the data writing module 11 included in the second type pixel circuit 10B are connected to different shift register units SR in the same second shift register VSR2.

[0208] It should be noted that when the display panel 001 further includes the second display area 02 , the gates of transistors with the same function in the data writing modules 11 included in the first pixel circuit 10 and the second pixel circuit 20 are connected to different shift register units SR in the same second shift register VSR2 .

[0209] Figure 17 A schematic diagram of a display device provided in an embodiment of the present application.

[0210] The present application also provides a display device, such as Figure 17 As shown, the display device includes a display panel 001 as provided in any of the above embodiments. The display device provided in the embodiment of the present application can be a mobile phone. In addition, the display device provided in the embodiment of the present application can also be a display device such as a computer or a television.

[0211] In the display device provided by the embodiment of the present application, the image refresh frequency of at least a portion of the display area can be variable. Furthermore, the image refresh frequency in the first display area O1 can be varied by controlling the frequency at which the data voltage is written to the gate of the drive transistor Td by the frequency control module 12 in the first pixel circuit 10. This makes the location of the variable image refresh frequency region in the display device more flexible and easier to implement.

[0212] An embodiment of the present application further provides a method for driving a display panel, which is used to drive the display panel 001 provided by any one of the above embodiments.

[0213] Figure 1, Figure 3 and Figures 9-12 、 Figure 14-16 As shown, the display panel 001 includes a first display area 01 , and the first display area 01 includes a plurality of first pixel circuits 10 . The first pixel circuits 10 can provide light-emitting driving current for the light-emitting devices in the display panel 001 .

[0214] The first pixel circuit 10 includes a driving transistor Td, a data writing module 11, and a frequency control module 12. One terminal of the driving transistor Td serves as a data voltage storage terminal 100, and the first pixel circuit 10 is configured to generate a corresponding light-emitting driving current based on the data voltage stored in the data voltage storage terminal 100. The data writing module 11 can be electrically connected to the driving transistor Td and configured to write the data voltage into the data voltage storage terminal 100 of the driving transistor Td. The frequency control module 12 is electrically connected to the driving transistor Td and the data writing module 11 and configured to control the data writing module 11 to write the data voltage into the data voltage storage terminal 100 of the driving transistor Td. The data writing module 11 can be electrically connected to the data voltage storage terminal 100 of the driving transistor Td via the frequency control module 12. That is, when the frequency control module 12 is turned on, the data writing module 11 is electrically connected to the data voltage storage terminal 100 of the driving transistor Td via the turned-on frequency control module 12.

[0215] In the embodiment of the present application, the frequency control module 12 is used to control the frequency at which the data writing module 11 writes the data voltage into the data voltage storage terminal 100 of the driving transistor Td.

[0216] Figure 18 A driving timing diagram of a first pixel circuit in a display panel provided in an embodiment of the present application.

[0217] like Figure 18 As shown, the multiple display modes of the display panel 001 include a first display mode and a second display mode, wherein the image refresh frequency of at least a portion of the first display 01 in the first display mode is lower than the image refresh frequency in the second display mode.

[0218] The driving method provided by the embodiment of the present application includes that the frequency control module 12 included in at least part of the first pixel circuit 10 is turned on at a frequency lower than the frequency when it is turned on in the second display mode. Wherein, the control end of the frequency control module 12 in the first pixel circuit 10 is electrically connected to the frequency control signal line SW, such as Figure 18 As shown, the frequency control signal line SW transmits the enable signal to the frequency control module 12 at a frequency lower than the frequency of the enable signal transmitted to the frequency control module 12 in the second display mode, so that the frequency control module 12 included in the first pixel circuit 10 is turned on at a frequency lower than the turn-on frequency in the second display mode in the first display mode.

[0219] The frequency at which the data voltage storage terminal 100 of the driving transistor Td of the first pixel circuit 10 in the first display area 01 receives the data voltage is controlled by controlling the opening frequency of the frequency control module 12 , thereby making the image display frequency of the first display area 01 variable.

[0220] Figure 19 A driving timing diagram of a first pixel circuit in a display panel provided in an embodiment of the present application.

[0221] In some embodiments, as Figure 11-12 、 Figure 14-16 As shown, the first display area 01 includes a first sub-display area 01A and a second sub-display area 01B; the multiple first pixel circuits 10 include a first type of pixel circuit 10A and a second type of pixel circuit 10B, the first type of pixel circuit 10A is arranged in the first sub-display area 01A and the second type of pixel circuit 10B is arranged in the second sub-display area 01B.

[0222] Furthermore, the control terminals of the frequency control modules 12 included in the first type pixel circuit 10A and the second type pixel circuit 10B, respectively, are electrically connected to different frequency control signal lines SW. This description will be made using an example in which the control terminal of the frequency control module 12 included in the first type pixel circuit 10A is electrically connected to the frequency control signal line SW1, while the control terminal of the frequency control module 12 included in the second type pixel circuit 10B is electrically connected to the frequency control signal line SW2.

[0223] The driving method provided by the embodiment of the present application also includes that, at least in the first display mode and / or the second display mode, the frequency control signal lines SW electrically connected to the first type of pixel circuit and the second type of pixel circuit respectively transmit enable signals at different frequencies, that is, in at least one display mode, the frequency control signal line SW1 transmits the enable signal at a control end of the frequency control module 12 included in the first type of pixel circuit 10A, which is different from the frequency control signal line SW2 transmits the enable signal at a control end of the frequency control module 12 included in the second type of pixel circuit 10B.

[0224] like Figure 19 As shown, in the first display mode, the frequency of the enable signal transmitted by the frequency control signal line SW1 is different from the frequency of the enable signal transmitted by the frequency control signal line SW2, and thus the image refresh frequencies of the first sub-display area 01A and the second sub-display area 01B in the display panel 001 in the first display mode are different. In the second display mode, the frequency of the enable signal transmitted by the frequency control signal line SW1 is different from the frequency of the enable signal transmitted by the frequency control signal line SW2, and thus the image refresh frequencies of the first sub-display area 01A and the second sub-display area 01B in the display panel 001 in the second display mode are different.

[0225] In a technical solution corresponding to this embodiment, as Figure 14 and Figure 15As shown, the control terminals of the frequency control modules 12 included in each first-type pixel circuit 10A are electrically connected to the same frequency control signal line SW1, and the control terminals of the frequency control modules 12 included in each second-type pixel circuit 10B are electrically connected to the same frequency control signal line SW2. This can avoid excessively increasing the number of frequency control signal lines SW1.

[0226] The driving method provided in the embodiment of the present application further includes transmitting an enable signal on the frequency control signal line SW1 electrically connected to the control terminal of the frequency control module 12 included in the first-type pixel circuit 10A, during a period that covers a period during which the data voltage storage terminal 100 of the driving transistor Td in all the first-type pixel circuits 10A receives a data voltage. That is, when the data voltage storage terminal 100 of the driving transistor Td in any first-type pixel circuit 10A receives a data voltage, the enable signal transmitted on the frequency control signal line SW1 controls the frequency control modules 12 in all the first-type pixel circuits 10A to be in an on state.

[0227] Figure 20 This is a working timing diagram of a display panel provided in an embodiment of the present application.

[0228] like Figure 20 As shown, assuming that the scan lines S1 in the first sub-display area 01A that are electrically connected to the data writing transistors 11 in different first pixel circuits 10A are specifically S11, S12, ..., S1N, when the scan lines S11, S12, ..., S1N all transmit enable signals (low-level signals), the enable signal (high-level signal) transmitted on the frequency control signal line SW1.

[0229] The driving method provided in the embodiment of the present application further includes transmitting an enable signal on the frequency control signal line SW2 electrically connected to the control terminal of the frequency control module 12 included in the second-type pixel circuit 10B, during a period that covers a period during which the data voltage storage terminal 100 of the driving transistor Td in all the second-type pixel circuits 10B receives a data voltage. That is, when the data voltage storage terminal 100 of the driving transistor Td in any first-type pixel circuit 10A receives a data voltage, the enable signal transmitted on the frequency control signal line SW1 controls the frequency control modules 12 in all the first-type pixel circuits 10A to be in an on state.

[0230] like Figure 20 As shown, assuming that the scan lines S1 in the first sub-display area 01A that are electrically connected to the data writing transistors 11 in different first pixel circuits 10A are specifically S1N+1, S1N+2, ..., S1N+m, then when the scan lines S1N+1, S1N+2, ..., S1N+m all transmit enable signals (low-level signals), the enable signal (high-level signal) transmitted on the frequency control signal line SW2.

[0231] Figure 21 This is a working timing diagram of a display panel provided in an embodiment of the present application.

[0232] In one embodiment of the present application, the driving method provided in the embodiment of the present application also includes that the frequency control module 12 included in at least part of the first pixel circuit 10 is turned on at a frequency lower than the turn-on frequency in the second display mode, and the data writing module included in those first pixel circuits 10 is turned on at a frequency equal to or lower than the turn-on frequency in the second display mode.

[0233] That is, although the frequency control module 12 is turned on at different frequencies in the first display mode and the second display mode, the data writing module 11 is turned on at different frequencies in the first display mode and the second display mode. Figure 21 As shown, the scan line S1 connected to the data writing transistor T1 in the data writing module 11 transmits the enable signal at the same frequency in the first display mode and the second display mode; when the data writing module 11 also includes a threshold capture transistor T2, the scan line S1' connected to the threshold capture transistor T2 transmits the enable signal at the same frequency in the first display mode and the second display mode.

[0234] Then the gates of the data writing transistors T1 in different first pixel circuits 10 in different sub-display areas of the first display area 01 can be connected to the shift register units in the same second shift register VSR2, or the gates of the data writing transistors T1 in different first pixel circuits 10 in the first display area 01 and the second display area 02 can be connected to the shift register units in the same second shift register VSR2.

[0235] In addition, the gates of the threshold capture transistors T2 in different first pixel circuits 10 in different sub-display areas of the first display area 01 can be connected to the shift register units in the same second shift register VSR2, or the gates of the threshold capture transistors T2 in different first pixel circuits 10 in the first display area 01 and the second display area 02 can be connected to the shift register units in the same second shift register VSR2.

[0236] When the first pixel circuit 10 further includes a first reset module 13 , the first reset module 13 is electrically connected to the input terminal of the frequency control transistor 12 and is configured to transmit a reset voltage to the gate of the driving transistor Td.

[0237] At this time, the driving method of the display panel 001 also includes that the frequency control module 12 included in at least part of the first pixel circuit 10 is turned on at a frequency lower than the turn-on frequency in the second display mode, and the first reset module 13 included in those first pixel circuits 10 is turned on at a frequency equal to or lower than the turn-on frequency in the second display mode.

[0238] That is, although the frequency control module 12 has different opening frequencies in the first display mode and the second display mode, the first reset module 13 has different opening frequencies in the first display mode and the second display mode. Figure 21 As shown, the scan line S3 connected to the first reset transistor T4 in the first reset module 13 transmits the enable signal at the same frequency in the first display mode and the second display mode.

[0239] Then the gates of the first reset transistors T4 in different first pixel circuits 10 in different sub-display areas of the first display area 01 can be connected to the shift register unit in the same shift register, or the gates of the first reset transistors T4 in different first pixel circuits 10 in the first display area 01 and the second display area 02 can be connected to the shift register unit in the same shift register.

[0240] In some embodiments of the present application, Figure 13-15 As shown, the display panel 001 further includes a multiplexer circuit DX, multiple output terminals of the multiplexer circuit DX can be electrically connected to different frequency control signal lines SW respectively, and can provide different frequency control signal lines SW with enable signals of different frequencies and enable signals of the same frequency.

[0241] like Figure 13-15 As shown, the multiplexer circuit DX includes a first transistor T01 and a second transistor T02; the input end of the first transistor T01 and the input end of the second transistor T02 are both electrically connected to the first signal line IN, and the first signal line IN transmits a first signal, which is a signal for controlling the frequency control module 12 to start.

[0242] The output end of the first transistor T01 is electrically connected to the same frequency control signal line SW1 as the first type pixel circuit 10A, and the output end of the second transistor T02 is electrically connected to the same control signal line SW2 as the second type pixel circuit 10B. The control end of the first transistor T01 is electrically connected to the first scan line L1, and the control end of the second transistor T02 is electrically connected to the second scan line L2.

[0243] Figure 22 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application.

[0244] In a technical solution corresponding to this embodiment, in either the first display mode or the second display mode, the frequency at which the signal transmitted by the first scan line L1 controls the first transistor T01 to turn on is different from the frequency at which the signal transmitted by the second scan line L2 controls the second transistor T02 to turn on. That is, the frequency at which the first transistor T01 receives the enable signal (high-level signal) is different from the frequency at which the second transistor T02 receives the enable signal (high-level signal).

[0245] Furthermore, the frequency at which the first transistor T01 receives the enable signal (high-level signal) can be consistent with the frequency at which the frequency control signal line SW1 receives the enable signal, and the frequency at which the first transistor T01 receives the enable signal (high-level signal) can be consistent with the frequency at which the frequency control signal line SW1 receives the enable signal. That is, the frequency at which the enable signal is transmitted via the first scan line L1 and the second scan line L2 can control the frequency at which the frequency control signal line SW1 and the frequency control signal line SW2 receive the enable signal.

[0246] The first signal line IN may receive a constant first signal, or a first signal with a constant frequency.

[0247] Figure 23 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application.

[0248] In a technical solution corresponding to the present embodiment, in the display modes of the first display mode and the second display mode, the frequency of the signal transmitted by the first scan line L1 controlling the turning on of the first transistor T01 is the same, the frequency of the signal transmitted by the second scan line L2 controlling the turning on of the second transistor T02 is the same, and the frequency of the first signal line IN transmitting the first signal in the first display mode and the second display mode is different.

[0249] In this technical solution, since the first transistor T01 is turned on at the same frequency in the first display mode and the second display mode, the first signal line IN transmits a first signal at different frequencies in the first display mode and the second display mode, thereby enabling the frequency control signal line SW1 to transmit an enable signal with different frequencies in the first display mode and the second display mode. Since the second transistor T02 is turned on at the same frequency in the first display mode and the second display mode, the first signal line IN transmits a first signal at different frequencies in the first display mode and the second display mode, thereby enabling the frequency control signal line SW2 to transmit an enable signal with different frequencies in the first display mode and the second display mode.

[0250] Figure 24 This is a working timing diagram of the multi-way selection circuit in the embodiment of the present application. Figure 25 This is a working timing diagram of the multi-way selection circuit in an embodiment of the present application.

[0251] Combine Figure 4B 、 Figure 9 and Figure 24 and Figure 25 In another embodiment of the present application, the scan line S1' of the threshold capture transistor T2 can be as follows Figure 24 As shown in FIG, the output of the low-frequency sub-display area stops when it enters the "equivalent hold frame", thereby reducing power consumption. Figure 24 During the second write frame W2, the frequency control signal SW1 of the first sub-display area 01A is at a valid level, and the data signal is written to the first sub-display area 01. The frequency control signal SW2 of the second sub-display area 01B is at a cut-off level, and the data signal is not written to the second sub-display area, which is equivalent to a holding frame. At this time, the output of the shift register corresponding to S1' can be stopped, which can further reduce the power consumption of the shift register. Similarly, the frequency control signal SW3 of the third sub-display area 01C is at a cut-off level, and the data signal is not written to the third sub-display area, which is equivalent to a holding frame. At this time, the output of the shift register corresponding to S1' can be stopped, which can further reduce the power consumption of the shift register. However, during the third write frame W3, the frequency control signal SW1 of the first sub-display area 01A is at a valid level, and the data signal is written to the first sub-display area 01. The frequency control signal SW2 of the second sub-display area 01B is at a cut-off level, and the data signal is not written to the second sub-display area, which is equivalent to a holding frame. At this time, the output of the shift register corresponding to S1' can be stopped, which can further reduce the power consumption of the shift register. However, the frequency control signal SW3 of the third sub-display area 01C needs to output an active level to write the data signal to the third sub-display area 01C. However, at this time, S1' has already stopped in the second sub-display area 01B and can no longer generate the corresponding scan signal. Therefore, this embodiment is only applicable when the frequency is high in the first period and low in the second period.

[0252] In another embodiment, Figure 25 As shown, in any writing frame W, the scanning signal S1' of the threshold capture transistor T2 continues to output a signal, and the above situation will not occur. Moreover, because the frequency control transistor blocks the gate of the driving transistor and other nodes when it is turned off, the goal of reducing the frequency of the local display area of ​​the present application is achieved.

[0253] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device includes a first display area, wherein the first display area includes a plurality of first pixel circuits, and the first pixel circuits include: A driving transistor for generating a light-emitting driving current; one end of the driving transistor is a data voltage storage end; a data writing module, electrically connected to the driving transistor and configured to write a data voltage into a data voltage storage terminal of the driving transistor; a frequency control module, the frequency control module being electrically connected to the driving transistor and the data writing module and configured to control a frequency at which the data writing module writes the data voltage into the data voltage storage terminal of the driving transistor; The data writing module is electrically connected to the data voltage storage terminal of the driving transistor through the frequency control module. When the frequency control module is turned on, the data writing module is electrically connected to the data voltage storage terminal of the driving transistor through the turned-on frequency control module. The gate of the driving transistor is a data voltage storage terminal, and the frequency control module is electrically connected to the gate of the driving transistor; The first pixel circuit further includes a storage capacitor electrically connected to the gate of the driving transistor.

2. The display panel according to claim 1, wherein: In the first display area, control terminals of frequency control modules included in at least some of the first pixel circuits are electrically connected to the same frequency control signal line.

3. The display panel according to claim 2, wherein: In the first display area, control terminals of the frequency control modules included in all the first pixel circuits are electrically connected to the same frequency control signal line.

4. The display panel according to claim 2, wherein: The first display area includes a first sub-display area and a second sub-display area, the multiple first pixel circuits include a first type of pixel circuit and a second type of pixel circuit, the first type of pixel circuit is arranged in the first sub-display area and the second type of pixel circuit is arranged in the second sub-display area; the control ends of the frequency control modules respectively included in the first type of pixel circuit and the second type of pixel circuit are electrically connected to different frequency control signal lines.

5. The display panel according to claim 4, wherein: The control ends of the frequency control modules included in each of the first-type pixel circuits are electrically connected to the same frequency control signal line, and the control ends of the frequency control modules included in each of the second-type pixel circuits are electrically connected to the same frequency control signal line.

6. The display panel according to claim 5, wherein: The display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is used to receive a first signal line, the first signal line transmits a first signal and the first signal is used to control the frequency control module to turn on; The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit; The control end of the first transistor is electrically connected to the first scan line, and the control end of the second transistor is electrically connected to the second scan line.

7. The display panel according to claim 4, wherein: The display panel includes a first shift register, wherein the first shift register includes a plurality of cascaded shift register units; The frequency control signal line electrically connected to the first type pixel circuit and the frequency control signal line electrically connected to the second type pixel circuit are respectively electrically connected to different shift register units in the first shift register.

8. The display panel according to claim 4, wherein: The display panel includes a second shift register, and the second shift register includes a plurality of cascaded shift register units; In the data writing module included in the first type of pixel circuit and the data writing module included in the second type of pixel circuit, gates of transistors with the same function are connected to different shift register units in the same second shift register.

9. The display panel according to claim 1, wherein: The frequency control module includes a frequency control transistor, and the data writing module includes a data writing transistor and a threshold grabbing transistor; The input end of the data writing transistor is connected to the data voltage line and the output end is electrically connected to the input end of the driving transistor, the input end of the threshold grabbing transistor is electrically connected to the output end of the driving transistor and the output end is electrically connected to the input end of the frequency control transistor, and the output end of the frequency control transistor is electrically connected to the gate of the driving transistor.

10. The display panel according to claim 1, wherein The frequency control module includes a frequency control transistor, and the data writing module includes a data writing transistor; The input end of the data writing transistor is connected to the data voltage line and the output end is electrically connected to the input end of the driving transistor. The input end of the frequency control transistor is electrically connected to the output end of the driving transistor and the output end is electrically connected to the gate of the driving transistor.

11. The display panel according to claim 9 or 10, characterized in that: The first pixel circuit further includes a first reset module, the first reset module being electrically connected to the input terminal of the frequency control transistor and configured to transmit a reset voltage to the gate of the driving transistor; The frequency control transistor is configured to be turned on when the gate of the driving transistor receives a reset voltage and a data voltage.

12. The display panel according to claim 11, wherein: The first reset module includes a first reset transistor, wherein the output end of the first reset transistor is electrically connected to the input end of the frequency control transistor; Wherein, the first reset transistor includes a metal oxide semiconductor layer.

13. The display panel according to claim 9 or 10, characterized in that: The display panel further includes a second display area, the second display area includes a second pixel circuit, and the second pixel circuit includes: A driving transistor for generating a light-emitting driving current; a data writing transistor having an input end connected to the data voltage line and an output end electrically connected to the input end of the driving transistor; A threshold capture transistor has an input terminal electrically connected to the output terminal of the driving transistor and an output terminal electrically connected to the gate of the driving transistor.

14. The display panel according to claim 13, wherein: The frequency control transistor and / or the threshold grabbing transistor each include a metal oxide semiconductor layer.

15. A display device, characterized in that: Comprising the display panel according to any one of claims 1-14.

16. A method for driving a display panel, characterized in that: The display panel includes a first display area, the first display area includes a plurality of first pixel circuits, and the first pixel circuits include: A driving transistor for generating a light-emitting driving current; one end of the driving transistor is a data voltage storage end; a data writing module, electrically connected to the driving transistor and configured to write a data voltage into a data voltage storage terminal of the driving transistor; a frequency control module, the frequency control module being electrically connected to the driving transistor and the data writing module and configured to control a frequency at which the data writing module writes the data voltage into the data voltage storage terminal of the driving transistor; The data writing module is electrically connected to the data voltage storage terminal of the driving transistor through the frequency control module. When the frequency control module is turned on, the data writing module is electrically connected to the data voltage storage terminal of the driving transistor through the turned-on frequency control module. The gate of the driving transistor is a data voltage storage terminal, and the frequency control module is electrically connected to the gate of the driving transistor; The first pixel circuit further includes a storage capacitor electrically connected to the gate of the driving transistor; The multiple display modes of the display panel include a first display mode and a second display mode, and the driving method includes: The frequency control module included in at least part of the first pixel circuits is turned on at a frequency lower than the frequency in the second display mode.

17. The driving method according to claim 16, wherein: The first display area includes a first sub-display area and a second sub-display area, the plurality of first pixel circuits include a first type of pixel circuit and a second type of pixel circuit, the first type of pixel circuit is arranged in the first sub-display area and the second type of pixel circuit is arranged in the second sub-display area; The control ends of the frequency control modules respectively included in the first type pixel circuit and the second type pixel circuit are electrically connected to different frequency control signal lines; The driving method further includes: At least in the first display mode and / or the second display mode, the frequency control signal lines electrically connected to the first type pixel circuit and the second type pixel circuit respectively transmit enable signals at different frequencies.

18. The display panel according to claim 17, wherein: The control ends of the frequency control modules included in each of the first-type pixel circuits are electrically connected to the same frequency control signal line, and the control ends of the frequency control modules included in each of the second-type pixel circuits are electrically connected to the same frequency control signal line; The driving method further includes: The frequency control signal line electrically connected to the control terminal of the frequency control module included in the first type of pixel circuit transmits an enable signal during a period covering a period during which the data voltage storage terminals of the driving transistors in all the first type of pixel circuits receive data voltages; The frequency control signal line electrically connected to the control terminal of the frequency control module included in the second type pixel circuit transmits an enable signal during a period when the data voltage storage terminals of the driving transistors in all the second type pixel circuits receive data voltages.

19. The display panel according to claim 18, wherein: The display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is used to receive a first signal line, the first signal line transmits a first signal and the first signal is used to control the frequency control module to turn on; The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit; Wherein, the control terminal of the first transistor is electrically connected to the first scan line, and the control terminal of the second transistor is electrically connected to the second scan line; The driving method further includes: In either the first display mode or the second display mode, a frequency at which the signal transmitted by the first scan line controls the first transistor to be turned on is different from a frequency at which the signal transmitted by the second scan line controls the second transistor to be turned on.

20. The display panel according to claim 18, wherein The display panel further includes a first transistor and a second transistor; an input terminal of the first transistor is electrically connected to an input terminal of the second transistor and is used to receive a first signal line, the first signal line transmits a first signal and the first signal is used to control the frequency control module to turn on; The output end of the first transistor is electrically connected to the same frequency control signal line as the first type pixel circuit, and the output end of the second transistor is electrically connected to the same frequency control signal line as the second type pixel circuit; Wherein, the control terminal of the first transistor is electrically connected to the first scan line, and the control terminal of the second transistor is electrically connected to the second scan line; The driving method further includes: In the first display mode and the second display mode, the frequency of the signal transmitted by the first scan line to control the opening of the first transistor is the same, the frequency of the signal transmitted by the second scan line to control the opening of the second transistor is the same, and the frequency of the first signal line transmitting the first signal in the first display mode and the second display mode is different.

21. The driving method according to claim 16, wherein: The driving method includes: The frequency at which the frequency control module included in at least some of the first pixel circuits is turned on in the first display mode is lower than the frequency at which it is turned on in the second display mode, and the frequency at which the data writing module included in those first pixel circuits is turned on in the first display mode is equal to or lower than the frequency at which it is turned on in the second display mode.

22. The driving method according to claim 16, wherein: The first pixel circuit further includes a first reset module, the first reset module being electrically connected to an input terminal of the frequency control module and configured to transmit a reset voltage to a gate of the driving transistor; The driving method further includes: The frequency at which the frequency control module included in at least some of the first pixel circuits is turned on in the first display mode is lower than the frequency at which it is turned on in the second display mode, and the frequency at which the first reset module included in those first pixel circuits is turned on in the first display mode is equal to or lower than the frequency at which it is turned on in the second display mode.

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