Display panel and display device

Abstract

The present application provides a display panel and a display device. By setting a bias adjustment stage and inputting a bias adjustment signal to the source or drain of a driving transistor, the drain potential of the driving transistor is adjusted, the potential difference between the gate potential and the drain potential of the driving transistor is improved, and further, the degree of ion polarization inside the driving transistor is weakened, ensuring that the Id-Vg curve does not shift as much as possible and avoiding the shift of the threshold voltage of the driving transistor. Thereby, when the display panel switches from a driving mode with a high-frequency data refresh rate to a driving mode with a low-frequency data refresh rate, the problem of abnormal brightness is avoided, and further, the screen flickering phenomenon is avoided, improving the visual experience.

Description

[0001] This application is a divisional application of the application with the application date of September 13, 2021, the application number of 202111071013.4, and the invention title of "display panel and display device". Technical Field

[0002] The present invention relates to the field of display technologies, and more specifically, to a display panel and a display device. Background Art

[0003] The display panel adopts different refresh rates for display in different application scenarios. For example, a driving method with a higher refresh rate is used to drive the display of dynamic images (such as sports events or game scenarios) to ensure the smoothness of the display image; a driving method with a lower refresh rate is used to drive the display of slow-motion images or static images to reduce power consumption.

[0004] However, when the display panel directly switches from a high refresh rate to a low refresh rate, there is a problem of abnormal brightness of the first frame at the low refresh rate, that is, there will be a screen flickering phenomenon, which affects the visual experience. Summary of the Invention

[0005] In view of this, to solve the above problems, the present invention provides a display panel and a display device, and the technical solutions are as follows:

[0006] On the one hand, the present application provides a display panel, including:

[0007] A pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor, and the driving transistor is used to provide a driving current for the light-emitting element;

[0008] The working process of the pixel circuit includes a data writing stage and a bias adjustment stage. In the data writing stage, the gate of the driving transistor receives a data signal, and in the bias adjustment stage, the source or drain of the driving transistor receives a bias adjustment signal;

[0009] The frame refresh rate of the pixel circuit is F1, and the frame includes a data writing frame and a holding frame;

[0010] The data refresh rate of the pixel circuit includes a first data refresh rate F11 and a second data refresh rate F22, where F22 < F11 ≤ F1, where

[0011] After the data refresh frequency of the pixel circuit is switched from the first data refresh frequency F11 to the second data refresh frequency F22, a total of N11 bias adjustment stages are included in a second data refresh period, N11≥2. The first bias adjustment stage of the second data refresh period inputs a bias adjustment signal V11, and the i-th bias adjustment stage inputs a bias adjustment signal Vi, 1 < i ≤ N11; wherein,

[0012] V11≠Vi.

[0013] On the other hand, the present application provides another display panel, including:

[0014] A pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor, and the driving transistor is used to provide a driving current for the light-emitting element;

[0015] The working process of the pixel circuit includes a data writing stage and a bias adjustment stage. In the data writing stage, the gate of the driving transistor receives a data signal, and in the bias adjustment stage, the source or drain of the driving transistor receives a bias adjustment signal;

[0016] The frame refresh frequency of the pixel circuit is F1, and the frame includes a data writing frame and a holding frame;

[0017] The data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, wherein, F22 < F11 ≤ F1, wherein,

[0018] After the data refresh frequency of the pixel circuit is switched from the first data refresh frequency F11 to the second data refresh frequency F22, a total of N11 bias adjustment stages are included in a second data refresh period, N11≥2. The m-th bias adjustment stage of the second data refresh period inputs a bias adjustment signal Vm, and the n-th bias adjustment stage inputs a bias adjustment signal Vn, 1 ≤ m ≤ N11, 1 ≤ n ≤ N11, m < n; wherein,

[0019] Vm≠Vn.

[0020] On yet another aspect, the present application provides a display device, including the above-mentioned display panel.

[0021] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0022] A display panel provided by the present invention adjusts the drain potential of a driving transistor by setting a bias adjustment stage and inputting a bias adjustment signal to the source or drain of the driving transistor, so as to improve the potential difference between the gate potential and the drain potential of the driving transistor, and further cancel the problem of the bias between the gate potential and the drain potential caused by the driving transistor possibly operating in the non-saturation stage during the light-emitting stage, avoiding the shift of the Id-Vg curve of the driving transistor, and thus avoiding the shift of the threshold voltage of the driving transistor. Further, in the present application, when the data refresh frequency decreases from a high data refresh frequency to a low data refresh frequency, multiple bias adjustment stages can be set within the low data refresh cycle, and the bias adjustment signals of each bias adjustment stage can be different. That is to say, the bias adjustment signal is gradually changed to a fixed value in a gradually changing and transitional manner, so as to avoid the problem of abnormal brightness when the display panel switches from the driving mode with a high data refresh rate to the driving mode with a low data refresh rate, that is, to avoid the screen flicker phenomenon and improve the visual experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0024] Figure 1 It is a schematic diagram of the drift of the Id-Vg curve of a driving transistor;

[0025] Figure 2 It is a schematic circuit structure diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0026] Figure 3 It is a schematic circuit structure diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0027] Figure 4 It is a schematic circuit structure diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention;

[0028] Figure 5 It is a schematic circuit structure diagram of a pixel circuit in still another display panel provided by an embodiment of the present invention;

[0029] Figure 6 It is a schematic circuit structure diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention;

[0030] Figure 7 It is a schematic circuit structure diagram of a pixel circuit in still another display panel provided by an embodiment of the present invention;

[0031] Figure 8 Partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0032] Figure 9 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0033] Figure 10 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0034] Figure 11 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0035] Figure 12 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0036] Figure 13 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0037] Figure 14 Another circuit structure diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0038] Figure 15 Another circuit structure diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0039] Figure 16 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0040] Figure 17 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0041] Figure 18 Another partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention;

[0042] Figure 19 A structure diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0044] Based on the content described in the background art of this application, during the inventive process of this application, the inventors found that when a display panel using an organic self-luminous technology switches directly from a high refresh rate to a low refresh rate, there is a problem of abnormal brightness in the first frame of the low refresh rate, that is, there will be a screen flickering phenomenon, which affects the visual experience. Specifically: when the display panel switches from a driving method with a high-frequency data refresh rate to a driving method with a low-frequency data refresh rate, since the display panel is driven and displayed using a driving method with a high-frequency data refresh rate, within one data refresh cycle, the number of hold frames is zero or very small, and the gate of the driving transistor maintains the input of the data signal. That is to say, the gate potential of the driving transistor is refreshed relatively frequently. When the display panel is driven and displayed using a driving method with a low-frequency data refresh rate, within one data refresh cycle, the number of hold frames becomes relatively large, and within one data refresh cycle, the gate potential of the driving transistor remains unchanged for a long time. Moreover, when the pixel circuit in the display panel is in the light-emitting stage, the driving transistor may operate in a non-saturated state. For a PMOS-type driving transistor, it is possible that when the driving transistor is turned on, the gate potential is higher than the drain potential; for an NMOS-type driving transistor, it is possible that when the driving transistor is turned on, the gate potential is lower than the drain potential; maintaining this situation for a long time will cause the ions inside the driving transistor to be polarized, and then an internal built-in electric field is formed inside the driving transistor, resulting in a continuous shift of the threshold voltage of the driving transistor.

[0045] Reference Figure 1 , Figure 1 is a schematic diagram of the drift of the Id-Vg curve of a driving transistor. As Figure 1 shown, the Id-Vg curve shifts, which in turn causes the threshold voltage Vth of the driving transistor to also shift, resulting in unstable input signals of the driving transistor. Then, when the display panel switches from a driving method with a high-frequency data refresh rate to a driving method with a low-frequency data refresh rate, there will be a problem of abnormal brightness, that is, there will be a screen flickering phenomenon, which affects the visual experience.

[0046] To solve the above technical problems existing in the prior art, in this application, by setting a bias adjustment stage and inputting a bias adjustment signal to the source or drain of the driving transistor, the drain potential of the driving transistor is adjusted, the potential difference between the gate potential and the drain potential of the driving transistor is improved, and then the degree of ion polarization inside the driving transistor is weakened, the threshold voltage of the driving transistor is reduced, and it is ensured that the Id-Vg curve does not shift as much as possible. Then, when the display panel switches from a driving method with a high-frequency data refresh rate to a driving method with a low-frequency data refresh rate, there will be no problem of abnormal brightness, that is, there will be no screen flickering phenomenon, and the visual experience is improved.

[0047] However, the inventors found that during the driving stage of the high-frequency data refresh rate, the signal received by the driving transistor is mostly the data signal for most of the time. When switching to the low data refresh rate, when the first bias adjustment stage comes, during the first bias adjustment stage, the signal received by the driving transistor will suddenly change to the bias adjustment signal, resulting in a sudden change in the signal received by the driving transistor. Especially when the difference between the bias adjustment signal and the data signal is large, the sudden change is more obvious, which causes instability of the driving transistor, further affecting the driving current and ultimately the brightness of the light-emitting element.

[0048] Based on this, in the present application, multiple bias adjustment stages are set, and the bias adjustment signals of each bias adjustment stage are different. That is to say, the bias adjustment signal is gradually changed to a fixed value in a gradual manner as much as possible, so as to avoid the problem of abnormal brightness when the display panel switches from the driving mode of high-frequency data refresh rate to the driving mode of low-frequency data refresh rate. That is to say, it avoids the screen flickering phenomenon and improves the visual experience.

[0049] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Reference Figure 2 , Figure 2 is a schematic circuit diagram of a pixel circuit in a display panel provided by an embodiment of the present invention; reference Figure 3 , Figure 3 is another schematic circuit diagram of a pixel circuit in a display panel provided by an embodiment of the present invention.

[0051] The display panel includes: a pixel circuit 10 and a light-emitting element Q. The pixel circuit 10 is connected to a data signal line L1 and includes a driving transistor T0, and the driving transistor T0 is used to provide a driving current for the light-emitting element Q. Among them, the driving transistor T0 in the pixel circuit can be a PMOS-type driving transistor or an NMOS-type driving transistor, and the corresponding pixel circuit structures of the two are also different. The pixel circuit corresponding to the PMOS-type driving transistor and the pixel circuit corresponding to the NMOS-type driving transistor will be introduced separately below:

[0052] As Figure 2 shown, the pixel circuit with the driving transistor T0 being a PMOS-type driving transistor will be described.

[0053] The drain of the driving transistor T0 is coupled to the light-emitting element Q, and provides a driving current for the light-emitting element Q after the driving transistor T0 is turned on.

[0054] Optionally, as Figure 2As shown, the pixel circuit 10 further includes a data writing transistor T1, which is connected between the source of the driving transistor T0 and the data signal line L1. The source of the data writing transistor T1 is used to receive the data signal Vdata. The drain of the data writing transistor T1 is connected to the source of the driving transistor T0, and the gate of the data writing transistor T1 is used to receive the control signal S1. Among them, the control signal S1 received by the data writing transistor T1 is a pulse signal. The effective pulse of the control signal S1 controls the data writing transistor T1 to be in the on state to provide the data signal Vdata to the driving transistor T0; the ineffective pulse of the control signal S1 controls the data writing transistor T1 to be in the off state. Therefore, under the control of the control signal S1, the data writing transistor T1 selectively provides the data signal Vdata to the driving transistor T0.

[0055] Optionally, as Figure 2 As shown, the pixel circuit 10 further includes a compensation transistor T2 for compensating the threshold voltage of the driving transistor T0. The source of the compensation transistor T2 is connected to the gate of the driving transistor T0 to form a first node N1. The drain of the compensation transistor T2 is connected to the drain of the driving transistor T0, and the gate of the compensation transistor T2 is used to receive the control signal S2. Among them, the control signal S2 received by the compensation transistor T2 is a pulse signal. The effective pulse of the control signal S2 controls the compensation transistor T2 to be in the on state to compensate the threshold voltage of the driving transistor T0; the ineffective pulse of the control signal S2 controls the compensation transistor T2 to be in the off state. Therefore, under the control of the control signal S2, the compensation transistor T2 selectively compensates the threshold voltage of the driving transistor T0.

[0056] Optionally, as Figure 2 As shown, the pixel circuit 10 further includes a first transistor T3 and a second transistor T4. The first transistor T3 is connected between the first power signal terminal PVDD and the source of the driving transistor T0. The second transistor T4 is connected between the drain of the driving transistor T0 and the light emitting element Q to control whether the pixel circuit 10 is in the light emitting stage or the non-light emitting stage.

[0057] The cathode of the light emitting element Q is connected to the second power signal terminal PVEE.

[0058] The gates of the first transistor T3 and the second transistor T4 receive the control signal EM simultaneously. Under the control of the control signal EM, the second transistor T4 is in the on state or the off state. The control signal EM received by the gate of the second transistor T4 is a pulse signal. During the light-emitting stage, the control signal EM outputs an effective pulse to control the second transistor T4 to be in the on state, then the drive current provided by the drive transistor T0 flows into the light-emitting element Q to make it emit light. During the non-light-emitting stage, the control signal EM outputs an invalid pulse to control the second transistor T4 to be in the off state, then the light-emitting element Q does not emit light.

[0059] Optionally, as Figure 2 shown, the pixel circuit 10 further includes a third transistor T5. The source of the third transistor T5 receives the reset signal Vref, the drain of the third transistor T5 is connected to the gate of the drive transistor T0, and the gate of the third transistor T5 is used to receive the control signal S3. Among them, the control signal S3 received by the third transistor T5 is a pulse signal. The effective pulse of the control signal S3 controls the third transistor T5 to be in the on state, then the reset signal Vref is written into the gate of the drive transistor T0 through the third transistor T5 to reset the gate of the drive transistor T0. The invalid pulse of the control signal S3 controls the third transistor T5 to be in the off state.

[0060] Optionally, as Figure 2 shown, the pixel circuit 10 further includes a fourth transistor T6. The source of the fourth transistor T6 is used to receive the initialization signal Vini, the drain of the fourth transistor T6 is connected to the anode of the light-emitting element Q, and the gate of the fourth transistor T6 is used to receive the scan signal S4. Among them, the control signal S4 received by the fourth transistor T6 is a pulse signal. The effective pulse of the control signal S4 controls the fourth transistor T6 to be in the on state, then the initialization signal Vini is written into the anode of the light-emitting element Q through the fourth transistor T6 to initialize the light-emitting element Q. The invalid pulse of the control signal S4 controls the fifth transistor T6 to be in the off state.

[0061] Optionally, as Figure 2 shown, the pixel circuit further includes a storage capacitor C1. The first plate of the storage capacitor C1 is connected to the first power signal terminal PVDD, and the second plate of the storage capacitor C1 is connected to the first node N1.

[0062] As Figure 3 shown, the pixel circuit in which the drive transistor T0 is an NMOS type drive transistor is described.

[0063] The source of the drive transistor T0 is coupled to the light-emitting element Q, and provides a drive current for the light-emitting element Q after the drive transistor T0 is turned on.

[0064] Optionally, as Figure 3As shown, the pixel circuit 10 further includes a data writing transistor M1. The data writing transistor M1 is connected between the source of the driving transistor T0 and the data signal line L1. The source of the data writing transistor M1 is used to receive the data signal Vdata. The drain of the data writing transistor M1 is connected to the source of the driving transistor T0. The gate of the data writing transistor M1 is used to receive the control signal K1. Among them, the control signal K1 received by the data writing transistor M1 is a pulse signal. The effective pulse of the control signal K1 controls the data writing transistor M1 to be in the on state to provide the data signal Vdata to the driving transistor T0. The ineffective pulse of the control signal K1 controls the data writing transistor M1 to be in the off state. Therefore, under the control of the control signal K1, the data writing transistor M1 selectively provides the data signal Vdata to the driving transistor T0.

[0065] Optionally, as Figure 3 As shown, the pixel circuit 10 further includes a compensation transistor M2 for compensating the threshold voltage of the driving transistor T0. The source of the compensation transistor M2 is connected to the gate of the driving transistor T0 to form a first node N1. The drain of the compensation transistor M2 is connected to the drain of the driving transistor T0. The gate of the compensation transistor M2 is used to receive the control signal K2. Among them, the control signal K2 received by the compensation transistor M2 is a pulse signal. The effective pulse of the control signal K2 controls the compensation transistor M2 to be in the on state to compensate the threshold voltage of the driving transistor T0. The ineffective pulse of the control signal K2 controls the compensation transistor M2 to be in the off state. Therefore, under the control of the control signal K2, the compensation transistor M2 selectively compensates the threshold voltage of the driving transistor T0.

[0066] Optionally, as Figure 3 As shown, the pixel circuit 10 further includes a first transistor M3 and a second transistor M4. The first transistor M3 is connected between the first power signal terminal PVDD and the drain of the driving transistor T0. The second transistor M4 is connected between the source of the driving transistor T0 and the light-emitting element Q to control whether the pixel circuit 10 is in the light-emitting stage or the non-light-emitting stage.

[0067] The cathode of the light-emitting element Q is connected to the second power signal terminal PVEE.

[0068] The gates of the first transistor M3 and the second transistor M4 receive the control signal EM simultaneously. Under the control of the control signal EM, the second transistor M4 is in the on state or the off state; the control signal EM received by the gate of the second transistor M4 is a pulse signal. In the light-emitting stage, the control signal EM outputs an effective pulse to control the second transistor M4 to be in the on state, then the driving current provided by the driving transistor T0 flows into the light-emitting element Q to make it emit light; in the non-light-emitting stage, the control signal EM outputs an invalid pulse to control the second transistor M4 to be in the off state, then the light-emitting element Q does not emit light.

[0069] Optionally, as Figure 3 shown, the pixel circuit 10 further includes a third transistor M5; the source of the third transistor M5 is used to receive the initialization signal Vini, the drain of the third transistor M5 is connected to the anode of the light-emitting element Q, and the gate of the third transistor M5 is used to receive the scan signal K3. Among them, the control signal K3 received by the third transistor M5 is a pulse signal. The effective pulse of the control signal K3 controls the third transistor M5 to be in the on state, then the initialization signal Vini is written into the anode of the light-emitting element Q through the third transistor M5 to initialize the light-emitting element Q; the invalid pulse of the control signal K3 controls the third transistor M5 to be in the off state.

[0070] Optionally, as Figure 3 shown, the pixel circuit 10 further includes a storage capacitor C2. The first plate of the storage capacitor C2 is connected to the first node N1, and the second plate of the storage capacitor C2 is connected to the anode of the light-emitting unit Q.

[0071] Based on Figure 2 and Figure 3 the pixel circuit shown, optionally, the pixel circuit includes a data writing module. The data writing module can be Figure 2 the transistor T1 in Figure 3 or can be the transistor M1 in

[0072] The above method can avoid adding an additional bias adjustment module. By reusing the data writing module, the function of bias adjustment can be achieved. Its structure is simple, which is beneficial to simplifying the panel structure and improving the resolution of the display panel.

[0073] Reference Figures 4 - 7 , Figure 4 FIG. is a schematic circuit diagram of a pixel circuit in another display panel provided by an embodiment of the present invention. Figure 5 FIG. is a schematic circuit diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention. Figure 6 FIG. is a schematic circuit diagram of a pixel circuit in another display panel provided by an embodiment of the present invention. Figure 7 FIG. is a schematic circuit diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention, wherein Figure 2 , Figure 4 , Figure 5 in, the driving transistor is a PMOS transistor. Figure 4 and Figure 5 and Figure 2 The difference is that Figure 4 and Figure 5 in the pixel circuit shown, a bias adjustment module TR is added. Figure 3 , Figure 6 , Figure 7 in, the driving transistor is an NMOS transistor. Figure 6 and Figure 7 and Figure 3 The difference is that Figure 6 and Figure 7 in the pixel circuit shown, a bias adjustment module TR is added. Specifically, the pixel circuit includes a data writing module and a bias adjustment module TR. The data writing module is connected to the data signal line, and the bias adjustment module is connected to the bias adjustment signal line LR. The bias adjustment signal line LR is used to transmit the bias adjustment signal VR, and the bias adjustment module TR is controlled by the control signal SR; in the data writing stage, the data writing module is turned on, and the data signal line writes the data signal to the gate of the driving transistor T0; in the bias adjustment stage, the bias adjustment module TR is turned on, and the bias adjustment signal line LR writes the bias adjustment signal VR to the source or drain of the driving transistor T0.

[0074] Figure 4 and Figure 5 The difference is that Figure 4 in the pixel circuit, the bias adjustment module TR is connected to the drain of the driving transistor. Figure 5 in the pixel circuit, the bias adjustment module TR is connected to the source of the driving transistor. Figure 6 and Figure 7 The difference is that Figure 6 in the pixel circuit, the bias adjustment module TR is connected to the drain of the driving transistor.Figure 7 In the pixel circuit, the bias adjustment module TR is connected to the source of the driving transistor.

[0075] In the above structure, by additionally adding the bias adjustment module TR, it is beneficial to achieve separate control of the bias adjustment module TR and the data writing module, and the magnitude of the bias adjustment signal can also be set independently without being restricted by the data signal. When high display effect requirements are needed for the display panel at both high and low data refresh frequencies, the above structure is required to fully ensure good display effects at each data refresh frequency.

[0076] It should be noted that the above data writing module can be the aforementioned data writing transistor T1 or M1, and the bias adjustment module TR can be the bias adjustment transistor TR.

[0077] Optionally, referring to Figure 8 , Figure 8 is a partial timing diagram of the operation of a pixel circuit provided by an embodiment of the present invention. Figure 8 The shown timing diagram is Figure 2 or Figure 3 An optional timing diagram of the shown pixel circuit. For the sake of simplicity, the timing diagrams in this application only show the timing processes related to the core content of this application, and the timing processes of other transistors are omitted here. It should be clear that the operation process of the pixel circuit requires the cooperation of the timing processes of each transistor to be achieved.

[0078] As Figure 8 shown, the operation process of the pixel circuit 10 includes a data writing stage and a bias adjustment stage. In the data writing stage, the data signal line L1 writes a data signal Vdata to the gate of the driving transistor T0. In the bias adjustment stage, the data signal line L1 writes a bias adjustment signal to the source or drain of the driving transistor T0.

[0079] Specifically, as Figure 8 shown, for the pixel circuit based on the PMOS type driving transistor, in the data writing stage, the control signal S1 is in the effective pulse stage to control the data writing transistor T1 to be in the conducting state, and the data signal Vdata is written to the gate of the driving transistor T0 through the data signal line L1; in the bias adjustment stage, the control signal S1 is in the effective pulse stage to control the data writing transistor T1 to be in the conducting state, and the bias adjustment signal is written to the source of the driving transistor T0 through the data signal line L1.

[0080] Similarly, for the pixel circuit based on the NMOS type driving transistor, in the data writing stage, the control signal K1 is in the effective pulse stage to control the data writing transistor M1 to be in the conducting state, and the data signal Vdata is written to the gate of the driving transistor T0 through the data signal line L1; in the bias adjustment stage, the control signal K1 is in the effective pulse stage to control the data writing transistor T1 to be in the conducting state, and the bias adjustment signal is written to the source of the driving transistor T0 through the data signal line L1.

[0081] It should be noted that Figure 8 in [reference document] an example is given with the data writing transistor being a PMOS type transistor. In some other embodiments, the data writing transistor can also be an NMOS type transistor. At this time, when S1 or K1 jumps to a high-level signal, the data writing transistor is turned on, and when S1 or K1 jumps to a low-level signal, the data writing transistor is turned off.

[0082] Referring to Figure 9 , Figure 9 is a partial timing diagram of the operation of another pixel circuit provided by an embodiment of the present invention. Figure 9 The shown timing diagram is Figures 4 - 7 an optional timing diagram of the pixel circuit shown. Among them, in the data writing stage, the data writing transistor T1 or M1 is turned on, the bias adjustment module TR is turned off, the compensation transistor is turned on, and the data signal is written to the gate of the driving transistor T0; in the bias adjustment stage, the data writing transistor is turned off, the bias adjustment module TR is turned on, the compensation transistor is turned off, and the bias adjustment signal VR is written to the source or drain of the driving transistor T0. Figure 9 The shown is an example with the transistors included in the bias adjustment module TR being PMOS type transistors. In other embodiments, the transistors included in the bias adjustment module can be NMOS type transistors.

[0083] Exemplarily, the frame refresh frequency of the pixel circuit provided by the present application is F1. The frame includes a data writing frame and a holding frame. In the data writing frame, the data signal line L1 writes the data signal Vdata to the gate of the driving transistor T0. In the holding frame, the data signal line L1 does not write the data signal Vdata to the gate of the driving transistor T0.

[0084] Furthermore, the data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22. Among them, the frame refresh frequency F1, the first data refresh frequency F11, and the second data refresh frequency F22 satisfy: F22 < F11 ≤ F1.

[0085] Here, it should be noted that in the concept of frame refresh frequency, a frame is calculated based on the minimum period of a light-emitting stage, and a frame includes a data writing frame and a holding frame; in the concept of data refresh frequency, data refresh is calculated based on the minimum period of the written data signal. One data refresh cycle may include one data writing frame and several holding frames.

[0086] Reference Figure 10 , Figure 10 is a partial timing diagram of the operation of another pixel circuit provided by an embodiment of the present invention; after the data refresh frequency of the pixel circuit is switched from the first data refresh frequency F11 to the second data refresh frequency F22, a total of N11 bias adjustment stages are included in one second data refresh cycle, N11≥2. The bias adjustment signal V11 is input in the first bias adjustment stage of the second data refresh cycle, and the bias adjustment signal Vi is input in the i-th bias adjustment stage, 1<i≤N11; where

[0087] V11≠Vi.

[0088] That is to say, after the data refresh frequency of the pixel circuit is switched from the high-frequency data refresh frequency to the low-frequency data refresh frequency, the bias adjustment signal V11 in the first bias adjustment stage of the second data refresh cycle can be different from the bias adjustment signal Vi in the i-th bias adjustment stage. That is to say, try to make the bias adjustment signal gradually change to a fixed value in a gradual transition manner, so as to avoid the problem of abnormal brightness when the display panel is switched from the driving mode of high-frequency data refresh rate to the driving mode of low-frequency data refresh rate. That is to say, avoid the screen flicker phenomenon and improve the visual experience.

[0089] Figure 10 In, according to the different input methods of the bias adjustment signal in the pixel circuit, the control signal of the optional bias adjustment module can be any one of the three signals S1, K1, and SR in the aforementioned pixel circuit. Which specific signal to choose depends on the specific structure of the pixel circuit.

[0090] Optionally, in an embodiment of the present invention, the data signal written in the data writing frame within the second data refresh cycle is Vdata, where

[0091] |V11-Vdata|<|Vi-Vdata|.

[0092] Specifically, within the second data refresh cycle, |V11 - Vdata| < |Vi - Vdata| indicates that the bias adjustment signal V11 in the first bias adjustment stage of the second data refresh cycle is different from the bias adjustment signal Vi in the i-th bias adjustment stage, and the difference between the bias adjustment signal V11 in the first bias adjustment stage and Vdata is less than the difference between the bias adjustment signal Vi in the i-th bias adjustment stage and Vdata. That is to say, after the data refresh frequency of the pixel circuit switches from the high-frequency data refresh frequency to the low-frequency data refresh frequency, when the first bias adjustment stage arrives, in the first bias adjustment stage, the signal received by the driving transistor first changes from Vdata to a value with a smaller difference from Vdata, and then gradually changes to a value with a larger difference from Vdata. It does not directly jump to a bias adjustment signal with a large difference from Vdata, but gradually changes to a fixed value in a smooth transition manner, thus avoiding the problem of abnormal brightness in the display panel and improving the visual experience. Generally, taking the driving transistor T0 as a PMOS transistor as an example, the maximum value of Vdata is generally 4V - 5V, and the bias adjustment signal can be set to 6.5V - 7V. V11 and / or Vi can be between these two values, for example, greater than 5V and less than 6.5V, so as to achieve a smooth transition of the bias adjustment signal.

[0093] An example is given with a PMOS driving transistor for illustration:

[0094] When the driving transistor T0 is a PMOS driving transistor, the bias adjustment signal received by the driving transistor T0 needs to be greater than the data signal Vdata. That is to say, the driving transistor T0 needs to switch from the state of receiving the data signal Vdata to receiving a bias adjustment signal with a higher level. To ensure a smooth transition of this higher-level bias adjustment signal, |V11 - Vdata| < |Vi - Vdata| will exist.

[0095] An example is given with an NMOS driving transistor for illustration:

[0096] When the driving transistor T0 is an NMOS driving transistor, the bias adjustment signal received by the driving transistor T0 needs to be less than the data signal Vdata. That is to say, the driving transistor T0 needs to switch from the state of receiving the data signal Vdata to receiving a bias adjustment signal with a lower level. To ensure a smooth transition of this lower-level bias adjustment signal, |V11 - Vdata| < |Vi - Vdata| will also exist.

[0097] Optionally, in another embodiment of the present invention, the difference between the bias adjustment signals input during the i bias adjustment stages from the first bias adjustment stage to the i-th bias adjustment stage of the second data refresh cycle and Vdata increases in sequence.

[0098] Specifically, it is further ensured that the bias adjustment signal received by the driving transistor can smoothly transition to a fixed value, preventing the occurrence of sudden changes in the bias adjustment signal during the transition process.

[0099] That is to say, after the data refresh frequency of the pixel circuit switches from the high-frequency data refresh frequency to the low-frequency data refresh frequency, when the first bias adjustment stage arrives, in the first bias adjustment stage, the signal received by the driving transistor does not directly jump to the bias adjustment signal with the maximum value. Instead, through multiple bias adjustment stages, bias adjustment signals with sequentially increasing differences from Vdata are gradually input in multiple stages, and gradually change to a fixed value in a smooth transition manner, thereby avoiding the problem of abnormal brightness of the display panel and improving the visual experience.

[0100] Exemplarily, assuming that the bias adjustment stages within the second data refresh cycle include three in total, then the difference between the bias adjustment signal input in the first bias adjustment stage and Vdata is less than the difference between the bias adjustment signal input in the second bias adjustment stage and Vdata, and less than the difference between the bias adjustment signal input in the third bias adjustment stage and Vdata.

[0101] Optionally, in another embodiment of the present invention:

[0102] When the driving transistor is a PMOS transistor, V11 < Vi; or,

[0103] When the driving transistor is an NMOS transistor, V11 > Vi.

[0104] Specifically, based on the characteristics of the PMOS transistor, when it operates in the saturation state, the gate potential is low, and the source and drain potentials are high. However, when the pixel circuit in the display panel is in the light-emitting stage, the driving transistor operates in the non-saturation state. For a PMOS driving transistor, this will result in a situation where the gate potential is higher than the drain potential when the PMOS driving transistor is turned on; maintaining this situation for a long time will cause ionic polarization inside the driving transistor, and then an internal built-in electric field is formed inside the driving transistor, resulting in continuous offset of the threshold voltage of the driving transistor.

[0105] Based on this, in the present application, in order to prevent this situation from occurring, the drain potential of the PMOS-type driving transistor is raised by a bias adjustment signal during the bias adjustment stage. Therefore, the bias adjustment signal needs to be a high-level signal. At the same time, during the first bias adjustment stage, the bias adjustment signal can be relatively small, and through multiple bias adjustment stages, the bias adjustment signal gradually changes to a fixed high-level signal in a smooth transition manner, thereby also avoiding the problem of abnormal brightness when the display panel switches from a driving method with a high-frequency data refresh rate to a driving method with a low-frequency data refresh rate, that is, avoiding the screen flicker phenomenon and improving the visual experience.

[0106] Similarly, based on the characteristics of the NMOS-type transistor, when it operates in the saturation state, the gate potential is high, and the source potential and drain potential are low. However, when the pixel circuit in the display panel is in the light-emitting stage, the driving transistor operates in the non-saturation state. For the NMOS-type driving transistor, this will result in a situation where when the NMOS-type driving transistor is turned on, the gate potential is lower than the drain potential; maintaining this situation for a long time will cause the ions inside the driving transistor to be polarized, and then an internal built-in electric field is formed inside the driving transistor, resulting in continuous offset of the threshold voltage of the driving transistor.

[0107] Based on this, in the present application, in order to prevent this situation from occurring, the drain potential of the NMOS-type driving transistor is pulled down by a bias adjustment signal during the bias adjustment stage. Therefore, the bias adjustment signal needs to be a low-level signal. At the same time, during the first bias adjustment stage, the bias adjustment signal can be relatively large, and through multiple bias adjustment stages, the bias adjustment signal gradually changes to a fixed low-level signal in a smooth transition manner, thereby also avoiding the problem of abnormal brightness when the display panel switches from a driving method with a high-frequency data refresh rate to a driving method with a low-frequency data refresh rate, that is, avoiding the screen flicker phenomenon and improving the visual experience.

[0108] Optionally, in another embodiment of the present invention, the driving transistor is a PMOS-type transistor, and the bias adjustment signals input during the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle increase in sequence;

[0109] The driving transistor is an NMOS-type transistor, and the bias adjustment signals input during the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle decrease in sequence.

[0110] Specifically, it is further ensured that the bias adjustment signal received by the driving transistor can smoothly transition to a fixed value, preventing the bias adjustment signal from mutating during the transition process.

[0111] For a PMOS-type driving transistor, during the process of continuously increasing the bias adjustment signal, after the data refresh frequency of the pixel circuit switches from the high-frequency data refresh frequency to the low-frequency data refresh frequency, when the first bias adjustment stage comes, in the first bias adjustment stage, the signal received by the driving transistor does not directly jump to the maximum bias adjustment signal, but through multiple bias adjustment stages, successively increasing bias adjustment signals are gradually input in a multi-stage manner, and gradually change to a fixed high-level signal in a smooth transition manner, so as to avoid the problem of abnormal brightness in the display panel and improve the visual experience.

[0112] For an NMOS-type driving transistor, during the process of continuously decreasing the bias adjustment signal, after the data refresh frequency of the pixel circuit switches from the high-frequency data refresh frequency to the low-frequency data refresh frequency, when the first bias adjustment stage comes, in the first bias adjustment stage, the signal received by the driving transistor does not directly jump to the minimum bias adjustment signal, but through multiple bias adjustment stages, successively decreasing bias adjustment signals are gradually input in a multi-stage manner, and gradually change to a fixed low-level signal in a smooth transition manner, so as to avoid the problem of abnormal brightness in the display panel and improve the visual experience.

[0113] Optionally, in another embodiment of the present invention, the bias adjustment signals input in the (N - i + 1) bias adjustment stages between the i-th bias adjustment stage and the N-th bias adjustment stage of the second data refresh cycle are equal, and are a preset bias adjustment signal V0.

[0114] Specifically, within the second data refresh cycle, after the first bias adjustment stage to the i-th bias adjustment stage, the smoothly transitioning bias adjustment signal has changed to a fixed-value bias adjustment signal, that is, the preset bias adjustment signal V0.

[0115] During this smooth transition process, it is fully ensured that the signal received by the driving transistor will not mutate, thereby avoiding the problem of abnormal brightness in the display panel and improving the visual experience.

[0116] Then, it is sufficient that the bias adjustment signals input in the (N - i + 1) bias adjustment stages between the i-th bias adjustment stage and the N-th bias adjustment stage of the second data refresh cycle are equal, and are all the preset bias adjustment signal V0.

[0117] Optionally, in another embodiment of the present invention, the bias adjustment signals input in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle increase or decrease in an arithmetic progression.

[0118] Specifically, in order to further ensure that the bias adjustment signal received by the driving transistor can smoothly transition to a fixed value and prevent the bias adjustment signal from mutating during the transition process, in this application, by optimizing the way of the smooth transition of the bias adjustment signal, in the way of increasing or decreasing arithmetically, it is fully ensured that the signal received by the driving transistor is smoothly transitioning, ensuring that the signal received by the driving transistor does not mutate, thereby avoiding the problem of abnormal brightness of the display panel and improving the visual experience.

[0119] Optionally, in another embodiment of the present invention, among the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle, the difference between the bias adjustment signals input in adjacent bias adjustment stages gradually increases.

[0120] Specifically, between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle, the difference between the bias adjustment signals input in adjacent bias adjustment stages is gradually increased. Without the signal received by the driving transistor mutating, the bias adjustment signal received by the driving transistor reaches the preset bias adjustment signal V0 at a relatively fast speed.

[0121] Exemplarily, when the data signal Vdata is quite different from the preset bias adjustment signal V0, the difference between the bias adjustment signal input in the first bias adjustment stage and the bias adjustment signal input in the second bias adjustment stage can be relatively small first, and then the difference between the bias adjustment signals input in adjacent bias adjustment stages is gradually increased later.

[0122] That is to say, during the entire bias adjustment stage, the driving transistor is given an adaptation time in the early stage to avoid a large difference between the bias adjustment signals input in adjacent bias adjustment stages at the beginning, which may cause the state of the driving transistor to mutate. In the middle and late stages, the difference between the bias adjustment signals input in adjacent bias adjustment stages can be appropriately increased gradually, so that the bias adjustment signal received by the driving transistor reaches the preset bias adjustment signal V0 at a relatively fast speed.

[0123] Optionally, in another embodiment of the present invention, among the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle, the difference between the bias adjustment signals input in adjacent bias adjustment stages gradually decreases.

[0124] Specifically, when the data signal Vdata is already relatively close to the preset bias adjustment signal V0, the difference between the bias adjustment signals input in the first bias adjustment stage and those input in the second bias adjustment stage can be slightly larger, and then the difference between the bias adjustment signals input in adjacent bias adjustment stages is gradually reduced later.

[0125] Since the data signal Vdata is already relatively close to the preset bias adjustment signal V0 and has a small impact on the driving transistor, such a setting based on this will not cause too much impact on the driving transistor either.

[0126] Optionally, in another embodiment of the present invention, when the driving transistor is a PMOS transistor, the voltage of the bias adjustment signal is higher than the data signal Vdata written in the data writing frame during the second data refresh period.

[0127] When the driving transistor is an NMOS transistor, the voltage of the bias adjustment signal is lower than the data signal Vdata written in the data writing frame during the second data refresh period.

[0128] Specifically, based on the characteristics of the PMOS transistor, when it operates in the saturation state, the gate potential is low, and the source and drain potentials are high. However, when the pixel circuit in the display panel is in the light-emitting stage, the driving transistor operates in the non-saturation state. For a PMOS driving transistor, this will result in a situation where the gate potential is higher than the drain potential when the PMOS driving transistor is turned on; maintaining this situation for a long time will cause ionic polarization inside the driving transistor, and then an internal built-in electric field is formed inside the driving transistor, resulting in a continuous increase in the threshold voltage of the driving transistor.

[0129] Based on this, in this application, to prevent this situation from occurring, the voltage of the bias adjustment signal is made higher than the data signal Vdata written in the data writing frame during the second data refresh period, that is, the drain potential of the PMOS driving transistor is raised through the bias adjustment signal during the bias adjustment stage to improve the potential difference between the gate potential and the drain potential of the PMOS driving transistor, thereby weakening the degree of ionic polarization inside the driving transistor, reducing the threshold voltage of the driving transistor, ensuring that the Id-Vg curve does not shift as much as possible. Then, when the display panel switches from the driving mode with a high-frequency data refresh rate to the driving mode with a low-frequency data refresh rate, there will be no problem of abnormal brightness, that is, there will be no screen flickering phenomenon, improving the visual experience.

[0130] Similarly, based on the characteristics of NMOS transistors, when they operate in the saturation state, the gate potential is high, and the source and drain potentials are low. However, when the pixel circuit in the display panel is in the light-emitting stage, the driving transistor operates in the non-saturation state. For an NMOS driving transistor, this will cause the gate potential to be lower than the drain potential when the NMOS driving transistor is turned on; maintaining this situation for a long time will cause the ions inside the driving transistor to be polarized, and then an internal built-in electric field will be formed inside the driving transistor, resulting in a continuous increase in the threshold voltage of the driving transistor.

[0131] Based on this, in the present application, to prevent this situation from occurring, the voltage of the bias adjustment signal is made lower than the data signal Vdata written in the data write frame within the second data refresh period, that is, the drain potential of the NMOS driving transistor is pulled down by the bias adjustment signal during the bias adjustment stage, so as to improve the potential difference between the gate potential and the drain potential of the NMOS driving transistor, thereby weakening the degree of ion polarization inside the driving transistor, reducing the threshold voltage of the driving transistor, and ensuring that the Id-Vg curve does not shift as much as possible. Then, when the display panel switches from the driving method with a high-frequency data refresh rate to the driving method with a low-frequency data refresh rate, there will be no problem of abnormal brightness, that is, there will be no screen flickering phenomenon, improving the visual experience.

[0132] Optionally, in another embodiment of the present invention, refer to Figures 11 - 13 , Figure 11 which is a partial timing diagram of the operation of another pixel circuit provided by the embodiment of the present invention. Figure 12 is a partial timing diagram of the operation of another pixel circuit provided by the embodiment of the present invention. Figure 13 is a partial timing diagram of the operation of another pixel circuit provided by the embodiment of the present invention. Figure 11 For Figure 2 or Figure 3 the partial timing diagram corresponding to the pixel circuit shown. Figure 12 and Figure 13 For Figures 4 - 7 the partial timing diagram corresponding to the pixel circuit shown.

[0133] When the pixel circuit operates at the second data refresh frequency F22, one second data refresh period includes one data write frame and r hold frames, where r≥1.

[0134] This hold frame includes a bias adjustment stage.

[0135] Specifically, in the data writing frame, the data signal line L1 provides the data signal Vdata for the gate of the driving transistor T0, while in the holding frame, the data signal line L1 does not provide the data signal Vdata for the gate of the driving transistor T0. Therefore, in this application, the bias adjustment stage is placed in the holding frame. On the one hand, it can avoid the excessive duration of the data writing frame; on the other hand, as Figure 11 shown, since the bias adjustment signal needs to be transmitted through the data signal line L1, and the data signal Vdata needs to be transmitted on the data signal line L1 in the data writing frame, it will cause incompatibility between the data signal Vdata and the bias adjustment signal, while the data signal line L1 in the holding frame can be switched to transmit the bias adjustment signal. In other embodiments of this application, especially corresponding to Figures 4 - 7 shown pixel circuit, if the data writing frame can also set the bias adjustment stage, the data writing frame can also include the bias adjustment stage, that is, as Figure 13 shown, in the data writing frame, the SR signal can also control the bias adjustment module to turn on.

[0136] Furthermore, for the driving method of the display panel with a low-frequency data refresh rate, the number of its holding frames is relatively large, so the way of transmitting the bias adjustment signal can be set more flexibly.

[0137] Optionally, in another embodiment of the present invention, referring to Figure 14 , Figure 14 is a schematic circuit structure diagram of a pixel circuit in another display panel provided by an embodiment of the present invention; referring to Figure 15 , Figure 15 is a schematic circuit structure diagram of a pixel circuit in another display panel provided by an embodiment of the present invention.

[0138] The pixel circuit 10 includes a data writing module 11 and a compensation module 12. The data writing module 11 is connected between the data signal line L1 and the source of the driving transistor T0, and the compensation module 12 is connected between the gate and the drain of the driving transistor T0; wherein,

[0139] In the data writing frame, the data writing module 11 and the compensation module 12 are turned on, and the data signal line L1 writes the data signal Vdata into the gate of the driving transistor T0.

[0140] In the holding frame, the data writing module 11 is turned on, the compensation module 12 is turned off, and the data signal line L1 writes the bias adjustment signal into the source or drain of the driving transistor T0.

[0141] Specifically, as Figure 14 shown, for the pixel circuit based on the PMOS type driving transistor, referring to Figure 16 , Figure 16Another partial timing diagram of the operation of the pixel circuit provided by the embodiment of the present invention. In the data writing frame, the control signal S1 is in the active pulse stage to control the data writing transistor T1 to be in the on state, and the control signal S2 is in the active pulse stage to control the compensation transistor T2 to be in the on state. The data signal Vdata is written into the gate of the driving transistor T0 through the data signal line L1; in the holding frame, the control signal S1 is in the active pulse stage to control the data writing transistor T1 to be in the on state, and the control signal S2 is in the inactive pulse stage to control the compensation transistor to be in the off state. The bias adjustment signal is written into the source of the driving transistor T0 through the data signal line L1 to adjust the bias state of the driving transistor T0.

[0142] Similarly, for the pixel circuit based on the NMOS type driving transistor, referring to Figure 17 , Figure 17 Another partial timing diagram of the operation of the pixel circuit provided by the embodiment of the present invention. In the data writing frame, the control signal K1 is in the active pulse stage to control the data writing transistor M1 to be in the on state, and the control signal K2 is in the active pulse stage to control the compensation transistor M2 to be in the on state. The data signal Vdata is written into the gate of the driving transistor T0 through the data signal line L1; in the holding frame, the control signal K1 is in the active pulse stage to control the data writing transistor T1 to be in the on state, and the control signal K2 is in the inactive pulse stage to control the compensation transistor M2 to be in the off state. The bias adjustment signal is written into the source of the driving transistor T0 through the data signal line L1 to adjust the bias state of the driving transistor T0.

[0143] Optionally, in another embodiment of the present invention, within the second data refresh cycle, the first bias adjustment stage is located in the first holding frame, and the i-th bias adjustment stage is located in the i-th holding frame.

[0144] Specifically, in the case of having multiple holding frames, if one holding frame includes one bias adjustment stage, then the first bias adjustment stage is located within the first holding frame, which can ensure that after the data writing frame ends, the bias adjustment of the driving transistor can be realized within the first holding frame.

[0145] Or, within the second data refresh cycle, having multiple bias adjustment stages in one holding frame is also a way to realize the bias adjustment of the driving transistor.

[0146] Or, within the second data refresh cycle, in the case of having multiple holding frames, some holding frames have one or more bias adjustment stages, and some holding frames do not have bias adjustment stages, which is also a way to realize the bias adjustment of the driving transistor.

[0147] Alternatively, the first bias adjustment stage may also be located in the data writing frame, and the i-th bias adjustment stage is located in the (i - 1)-th holding frame.

[0148] Based on various bias adjustment methods, it can be reasonably selected according to the actual situation in practical applications, and it is not limited in the embodiments of the present invention.

[0149] Optionally, in another embodiment of the present invention, the data refresh frequency of the pixel circuit further includes a third data refresh frequency F33, where F33 < F22; wherein,

[0150] Reference Figure 18 , Figure 18 is a partial timing diagram of the operation of another pixel circuit provided by the embodiment of the present invention; after the data refresh frequency of the pixel circuit is switched from the first data refresh frequency F11 to the third data refresh frequency F33, a total of N12 bias adjustment stages are included in one third data refresh cycle, N12 ≥ 2. The bias adjustment signal V12 is input to the first bias adjustment stage of the third data refresh cycle, and the bias adjustment signal Vj is input to the j-th bias adjustment stage, 1 ≤ j ≤ N12; wherein,

[0151] V12 ≠ Vj.

[0152] Specifically, after the data refresh frequency of the pixel circuit is switched from the high-frequency data refresh frequency to the low-frequency data refresh frequency, the bias adjustment signal of the first bias adjustment stage of the third data refresh cycle may be different from the bias adjustment signal of the j-th bias adjustment stage. That is to say, try to make the bias adjustment signal gradually change to a fixed value in a smooth transition manner, so as to avoid the problem of abnormal brightness when the display panel is switched from the driving mode of high-frequency data refresh rate to the driving mode of low-frequency data refresh rate. That is to say, avoid the screen flickering phenomenon and improve the visual experience.

[0153] Optionally, in another embodiment of the present invention, the bias adjustment signals input to the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle increase or decrease in sequence, and the bias adjustment signals input to the (N11 - i + 1) bias adjustment stages between the i-th bias adjustment stage and the N11-th bias adjustment stage are equal.

[0154] The bias adjustment signals input to the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage of the third data refresh cycle increase or decrease in sequence, and the bias adjustment signals input to the (N12 - j + 1) bias adjustment stages between the j-th bias adjustment stage and the N12-th bias adjustment stage are equal; wherein,

[0155] i < j.

[0156] Specifically, in the data refresh frequency of the pixel circuit, the first data refresh frequency F11 is greater than the second data refresh frequency F22 which is greater than the third data refresh frequency F33. That is, the second data refresh frequency F22 is relatively higher than the third data refresh frequency F33, and the third data refresh frequency F33 is relatively lower than the second data refresh frequency F22.

[0157] Also, since the lower the frequency, the relatively more the number of holding frames will be within one data refresh cycle, the longer the duration for which the gate potential of the driving transistor remains unchanged within one data refresh cycle will be. This will cause the degree of ion polarization inside the driving transistor to increase, form a built-in electric field inside the driving transistor, lead to a continuous increase in the threshold voltage of the driving transistor, a serious shift in the Ig-Vg curve, and a more serious shift in the threshold voltage of the driving transistor.

[0158] Therefore, in the stage with a relatively lower data refresh frequency, more bias adjustment stages are adopted to gradually adjust the bias adjustment signal step by step to stabilize it to a certain fixed value, so as to alleviate the problem of a relatively large shift in the threshold voltage of the driving transistor to the greatest extent.

[0159] Exemplarily, in the second data refresh cycle, the bias adjustment signal is stabilized to a certain fixed value through 5 bias adjustment stages, and the input of this bias adjustment signal is maintained in subsequent bias adjustment stages.

[0160] In the third data refresh cycle, the bias adjustment signal is stabilized to a certain fixed value through 8 or 10 or more bias adjustment stages, and the input of this bias adjustment signal is maintained in subsequent bias adjustment stages.

[0161] Optionally, in another embodiment of the present invention, the bias adjustment signals input in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh cycle increase or decrease in an arithmetic progression of △V1.

[0162] The bias adjustment signals input in the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage of the third data refresh cycle increase or decrease in an arithmetic progression of △V2.

[0163] Among them, △V1 > △V2.

[0164] Specifically, in the data refresh frequency of the pixel circuit, the first data refresh frequency F11 is greater than the second data refresh frequency F22 which is greater than the third data refresh frequency F33. That is, the second data refresh frequency F22 is relatively higher than the third data refresh frequency F33, and the third data refresh frequency F33 is relatively lower than the second data refresh frequency F22.

[0165] Also, since the lower the frequency, the relatively more the number of holding frames within a data refresh period, the longer the duration during which the gate potential of the driving transistor remains unchanged within a data refresh period, which will lead to a more serious polarization of ions inside the driving transistor, forming a built-in electric field inside the driving transistor, resulting in a continuous increase in the threshold voltage of the driving transistor, a serious shift in the Ig-Vg curve, and a more serious shift in the threshold voltage of the driving transistor.

[0166] Therefore, when the bias adjustment signal adopts an arithmetic change method, in the stage with a relatively lower data refresh frequency, it is necessary to adopt a method with a more gentle arithmetic change trend (i.e., adopt △V2 smaller than △V1) to gradually adjust the bias adjustment signal to stabilize it to a certain fixed value, so as to alleviate the problem of a relatively large shift in the threshold voltage of the driving transistor to the greatest extent.

[0167] If △V2 is relatively large, it will cause the signal received by the driving transistor to have too large a span, easily leading to an unstable state of the driving transistor, unable to well adjust the threshold voltage of the driving transistor, and thus affecting the light-emitting state of the light-emitting element.

[0168] Optionally, in another embodiment of the present invention, among the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage in the second data refresh period, the difference between the bias adjustment signals input in two adjacent bias adjustment stages is greater than the difference between the bias adjustment signals input in two adjacent bias adjustment stages among the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage in the third data refresh period.

[0169] Specifically, in this embodiment of the present invention, it is not limited that the bias adjustment signal changes in an arithmetic manner, as long as it is ensured that the difference between the bias adjustment signals input in two adjacent bias adjustment stages in the third data refresh period is smaller than the difference between the bias adjustment signals input in two adjacent bias adjustment stages in the second data refresh period.

[0170] That is to say, the change amplitude of the bias adjustment signal in the third data refresh period is more gentle than that of the bias adjustment signal in the second data refresh period, so as to alleviate the problem of a relatively large shift in the threshold voltage of the driving transistor to the greatest extent.

[0171] It should be noted that the time length of the second data refresh period in this application is the reciprocal of the second data refresh frequency F22, and the time length of the third data refresh period is the reciprocal of the third data refresh frequency F33.

[0172] Optionally, in this embodiment, after switching from the first data refresh frequency F11 to the second data refresh frequency F22, the first data refresh cycle may include the N11 bias adjustment stages, or each of the first q data refresh cycles may include the N11 bias adjustment stages, where q≥1. In both cases, for other data refresh cycles, the bias adjustment stage may be set such that the bias adjustment signal of the first bias adjustment stage reaches a fixed value V0. Due to the transition of these data refresh cycles, the driving transistor can adapt to the operation at the second data refresh frequency, and thus, for other data refresh cycles, there is no need to set a smooth transition method. Of course, in other embodiments, when the display panel operates at the second data refresh frequency, all data refresh cycles may include the N11 bias adjustment stages to ensure the stability of the driving transistor. It can be selected according to the specific situation.

[0173] Optionally, on the other hand, an embodiment of the present application provides another display panel, where the display panel includes: a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor for providing a driving current for the light-emitting element. The operation process of the pixel circuit includes a data writing stage and a bias adjustment stage. In the data writing stage, the gate of the driving transistor receives a data signal, and in the bias adjustment stage, the source or drain of the driving transistor receives a bias adjustment signal. The frame refresh frequency of the pixel circuit is F1, and the frame includes a data writing frame and a holding frame. The data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, where F22<F11≤F1. After the data refresh frequency of the pixel circuit switches from the first data refresh frequency F11 to the second data refresh frequency F22, a second data refresh cycle includes a total of N11 bias adjustment stages, where N11≥2. In the m-th bias adjustment stage of the second data refresh cycle, a bias adjustment signal Vm is input, and in the n-th bias adjustment stage, a bias adjustment signal Vn is input, where 1≤m≤N11, 1≤n≤N11, and m<n. Among them,

[0174] Vm≠Vn.

[0175] In the present application, when switching from a high data refresh frequency to a low data refresh frequency, multiple bias adjustment stages are set in the low data refresh cycle. The bias adjustment signal in the m-th bias adjustment stage may be different from the bias adjustment signal in the n-th bias adjustment stage. That is to say, the bias adjustment signal is gradually changed to a fixed value in a smooth transition manner, so as to avoid the problem of abnormal brightness when the display panel switches from the driving mode of the high-frequency data refresh rate to the driving mode of the low-frequency data refresh rate, that is, to avoid the screen flicker phenomenon and improve the visual experience.

[0176] The difference between this embodiment and the foregoing embodiment is that it is not limited whether m and n are in the first bias adjustment stage. That is, in some cases, the bias adjustment signals of different bias adjustment stages can be set to be adjustable, so that specific bias adjustment signals can be set according to specific needs, all of which are within the scope of protection of this application.

[0177] Based on this, in this embodiment, the data signal written in the data write frame within the second data refresh period is Vdata, where |Vm - Vdata| < |Vn - Vdata|. Since m < n, setting |Vm - Vdata| < |Vn - Vdata| can make the bias adjustment signal gradually change to a fixed value in a smooth transition manner, so that the difference between the bias adjustment signal and Vdata gradually increases, and it will not cause signal mutation and have a greater impact on the driving transistor whose threshold voltage has already shifted.

[0178] In addition, in this embodiment,

[0179] the driving transistor is a PMOS transistor, and Vm < Vn; or,

[0180] the driving transistor is an NMOS transistor, and Vm > Vn.

[0181] Since m < n, the above setting can make the bias adjustment signal gradually change to a fixed value in a smooth transition manner, so that the bias adjustment signal gradually increases or gradually decreases, and it will not cause signal mutation and have a greater impact on the driving transistor whose threshold voltage has already shifted.

[0182] It should be noted that in this embodiment, only the definitions of m and n are different from those in the foregoing embodiment, and the pixel circuit and related timings are similar to those in the foregoing embodiment, which can be directly referred to the foregoing embodiment and will not be elaborated here.

[0183] Optionally, based on all the above embodiments of the present invention, in another embodiment of the present invention, a display device is further provided. Refer to Figure 19 , Figure 19 which is a schematic structural diagram of a display device provided by an embodiment of the present invention.

[0184] The display device includes any one of the display panels 200 provided by the above embodiments.

[0185] Since the display device provided by the embodiment of the present invention includes any one of the display panels provided by the above embodiments, this display device has the same or corresponding technical effects as the display panel provided by the above embodiments.

[0186] The display device may specifically be a mobile phone, a computer, and other electronic devices, etc.

[0187] The above has introduced in detail a display panel and a display device provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0188] It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements also includes the elements inherent to these processes, methods, articles or devices, or further includes the elements inherent to these processes, methods, articles or devices. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device that includes the said element.

[0189] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, Comprising: A pixel circuit and a light-emitting element, the pixel circuit including a driving transistor for providing a driving current to the light-emitting element; The operation process of the pixel circuit includes a data writing stage and a bias adjustment stage. In the data writing stage, the gate of the driving transistor receives a data signal. In the bias adjustment stage, the source or drain of the driving transistor receives a bias adjustment signal; The frame refresh frequency of the pixel circuit is F1, and the frame includes a data writing frame and a holding frame; The data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, where F22 < F11 ≤ F1, where After the data refresh frequency of the pixel circuit switches from the first data refresh frequency F11 to the second data refresh frequency F22, a total of N11 bias adjustment stages are included in one second data refresh period, N11 ≥ 2. The first bias adjustment stage of the second data refresh period inputs a bias adjustment signal V11, and the i-th bias adjustment stage inputs a bias adjustment signal Vi, 1 < i ≤ N11; where V11 ≠ Vi; The i-th bias adjustment stage is located in the holding frame; The data signal written in the data writing frame within the second data refresh period is Vdata, where |V11 - Vdata| < |Vi - Vdata|, or when the driving transistor is a PMOS transistor, the voltage of at least one of the bias adjustment signals is higher than the data signal Vdata written in the data writing frame within the second data refresh period; when the driving transistor is an NMOS transistor, the voltage of the bias adjustment signal is lower than the data signal Vdata written in the data writing frame within the second data refresh period.

2. The display panel according to claim 1, wherein The pixel circuit includes a data writing module connected to a data signal line; In the data writing stage, the data writing module is turned on, and the data signal line writes a data signal to the gate of the driving transistor; In the bias adjustment stage, the data writing module is turned on, and the data signal line writes a bias adjustment signal to the source or drain of the driving transistor.

3. The display panel according to claim 1, wherein The pixel circuit includes a data writing module and a bias adjustment module. The data writing module is connected to a data signal line, and the bias adjustment module is connected to a bias adjustment signal line; In the data writing stage, the data writing module is turned on, and the data signal line writes a data signal to the gate of the driving transistor; In the bias adjustment stage, the bias adjustment module is turned on, and the bias adjustment signal line writes a bias adjustment signal to the source or drain of the driving transistor.

4. The display panel according to claim 1, wherein The difference between the bias adjustment signals input in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period and Vdata increases in sequence.

5. The display panel according to claim 1, wherein the bias adjustment signals input in the (N - i + 1) bias adjustment stages between the i-th bias adjustment stage and the N-th bias adjustment stage of the second data refresh period are equal and are a preset bias adjustment signal V0.

6. The display panel according to claim 1, wherein in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period, the difference between the bias adjustment signals input in adjacent bias adjustment stages gradually increases.

7. The display panel according to claim 1, wherein in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period, the difference between the bias adjustment signals input in adjacent bias adjustment stages gradually decreases.

8. The display panel according to any one of claims 1, 6 or 7, wherein the first bias adjustment stage is located in the data writing frame.

9. The display panel according to claim 8, wherein in at least one of the second data refresh periods, the first bias adjustment stage is located after the data writing stage of the data writing frame.

10. The display panel according to any one of claims 1, 6 or 7, wherein the first bias adjustment stage is located in the data writing frame, and the i-th bias adjustment stage is located in the (i - 1)-th holding frame.

11. The display panel according to any one of claims 1, 6 or 7, wherein in the second data refresh period, there are multiple bias adjustment stages in one holding frame.

12. The display panel according to any one of claims 1, 6 or 7, wherein in at least one of the second data refresh periods, the first bias adjustment stage is located after the data writing stage of the data writing frame.

13. The display panel according to claim 1, wherein when the pixel circuit operates at the second data refresh frequency F22, one second data refresh period includes one data writing frame and r holding frames, r ≥ 1; the holding frame includes the bias adjustment stage.

14. The display panel according to claim 13, wherein in the second data refresh period, the first bias adjustment stage is located in the first holding frame, and the i-th bias adjustment stage is located in the i-th holding frame.

15. The display panel according to claim 1, wherein the data refresh frequency of the pixel circuit further includes a third data refresh frequency F33, F33 < F22; wherein, after the data refresh frequency of the pixel circuit is switched from the first data refresh frequency F11 to the third data refresh frequency F33, one third data refresh period altogether includes N12 bias adjustment stages, N12 ≥ 2, the first bias adjustment stage of the third data refresh period inputs a bias adjustment signal V12, and the j-th bias adjustment stage inputs a bias adjustment signal Vj, 1 ≤ j ≤ N12; wherein, V12 ≠ Vj.

16. The display panel according to claim 15, wherein the bias adjustment signals input in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period increase or decrease in sequence, and the bias adjustment signals input in the (N11 - i + 1) bias adjustment stages between the i-th bias adjustment stage and the N11-th bias adjustment stage are equal; the bias adjustment signals input in the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage of the third data refresh period increase or decrease in sequence, and the bias adjustment signals input in the (N12 - j + 1) bias adjustment stages between the j-th bias adjustment stage and the N12-th bias adjustment stage are equal; wherein, i < j.

17. The display panel according to claim 15, wherein the bias adjustment signals input in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period increase or decrease in sequence with an arithmetic difference of △V1; the bias adjustment signals input in the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage of the third data refresh period increase or decrease in sequence with an arithmetic difference of △V2; wherein, △V1 > △V2.

18. The display panel according to claim 15, wherein the difference between the bias adjustment signals input in two adjacent bias adjustment stages in the i bias adjustment stages between the first bias adjustment stage and the i-th bias adjustment stage of the second data refresh period is greater than the difference between the bias adjustment signals input in two adjacent bias adjustment stages in the j bias adjustment stages between the first bias adjustment stage and the j-th bias adjustment stage of the third data refresh period.

19. A display panel, characterized in that, Comprising: a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor, and the driving transistor is used to provide a driving current for the light-emitting element; the working process of the pixel circuit includes a data writing stage and a bias adjustment stage. In the data writing stage, the gate of the driving transistor receives a data signal, and in the bias adjustment stage, the source or drain of the driving transistor receives a bias adjustment signal; the frame refresh frequency of the pixel circuit is F1, and the frame includes a data writing frame and a holding frame; the data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, wherein, F22 < F11 ≤ F1, wherein, after the data refresh frequency of the pixel circuit switches from the first data refresh frequency F11 to the second data refresh frequency F22, a second data refresh period includes a total of N11 bias adjustment stages, N11 ≥ 2. The bias adjustment signal Vm is input in the m-th bias adjustment stage of the second data refresh period, and the bias adjustment signal Vn is input in the n-th bias adjustment stage, 1 ≤ m ≤ N11, 1 ≤ n ≤ N11, m < n; wherein, Vm ≠ Vn; The first bias adjustment stage is located in the data writing frame; or, the i-th bias adjustment stage is located in the holding frame, where 1 < i ≤ N11; or, there are multiple bias adjustment stages in one holding frame during the second data refresh period; or, during at least one of the second data refresh periods, the first bias adjustment stage is located after the data writing stage of the data writing frame.

20. The display panel according to claim 19, wherein When the first bias adjustment stage is located in the data writing frame, or when there are multiple bias adjustment stages in one holding frame during the second data refresh period, or when during at least one of the second data refresh periods, the first bias adjustment stage is located after the data writing stage of the data writing frame, or when m ≠ 1, the data signal written in the data writing frame during the second data refresh period is Vdata, where |Vm - Vdata| < |Vn - Vdata|.

21. The display panel according to claim 19, wherein the driving transistor is a PMOS transistor and Vm < Vn; or the driving transistor is an NMOS transistor and Vm > Vn.

22. A display device, characterized in that, It includes the display panel according to any one of claims 1 - 21.

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